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      1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the XCore implementation of the MRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "XCoreRegisterInfo.h"
     15 #include "XCoreMachineFunctionInfo.h"
     16 #include "XCore.h"
     17 #include "llvm/CodeGen/MachineInstrBuilder.h"
     18 #include "llvm/CodeGen/MachineFunction.h"
     19 #include "llvm/CodeGen/MachineFrameInfo.h"
     20 #include "llvm/CodeGen/MachineModuleInfo.h"
     21 #include "llvm/CodeGen/MachineRegisterInfo.h"
     22 #include "llvm/CodeGen/RegisterScavenging.h"
     23 #include "llvm/Target/TargetFrameLowering.h"
     24 #include "llvm/Target/TargetMachine.h"
     25 #include "llvm/Target/TargetOptions.h"
     26 #include "llvm/Target/TargetInstrInfo.h"
     27 #include "llvm/Type.h"
     28 #include "llvm/Function.h"
     29 #include "llvm/ADT/BitVector.h"
     30 #include "llvm/ADT/STLExtras.h"
     31 #include "llvm/Support/Debug.h"
     32 #include "llvm/Support/ErrorHandling.h"
     33 #include "llvm/Support/raw_ostream.h"
     34 
     35 #define GET_REGINFO_TARGET_DESC
     36 #include "XCoreGenRegisterInfo.inc"
     37 
     38 using namespace llvm;
     39 
     40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
     41   : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
     42 }
     43 
     44 // helper functions
     45 static inline bool isImmUs(unsigned val) {
     46   return val <= 11;
     47 }
     48 
     49 static inline bool isImmU6(unsigned val) {
     50   return val < (1 << 6);
     51 }
     52 
     53 static inline bool isImmU16(unsigned val) {
     54   return val < (1 << 16);
     55 }
     56 
     57 static const unsigned XCore_ArgRegs[] = {
     58   XCore::R0, XCore::R1, XCore::R2, XCore::R3
     59 };
     60 
     61 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
     62 {
     63   return XCore_ArgRegs;
     64 }
     65 
     66 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
     67 {
     68   return array_lengthof(XCore_ArgRegs);
     69 }
     70 
     71 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
     72   return MF.getMMI().hasDebugInfo() ||
     73     MF.getFunction()->needsUnwindTableEntry();
     74 }
     75 
     76 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
     77                                                                          const {
     78   static const unsigned CalleeSavedRegs[] = {
     79     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
     80     XCore::R8, XCore::R9, XCore::R10, XCore::LR,
     81     0
     82   };
     83   return CalleeSavedRegs;
     84 }
     85 
     86 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     87   BitVector Reserved(getNumRegs());
     88   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
     89 
     90   Reserved.set(XCore::CP);
     91   Reserved.set(XCore::DP);
     92   Reserved.set(XCore::SP);
     93   Reserved.set(XCore::LR);
     94   if (TFI->hasFP(MF)) {
     95     Reserved.set(XCore::R10);
     96   }
     97   return Reserved;
     98 }
     99 
    100 bool
    101 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
    102   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    103 
    104   // TODO can we estimate stack size?
    105   return TFI->hasFP(MF);
    106 }
    107 
    108 bool
    109 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
    110   return false;
    111 }
    112 
    113 // This function eliminates ADJCALLSTACKDOWN,
    114 // ADJCALLSTACKUP pseudo instructions
    115 void XCoreRegisterInfo::
    116 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
    117                               MachineBasicBlock::iterator I) const {
    118   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    119 
    120   if (!TFI->hasReservedCallFrame(MF)) {
    121     // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
    122     // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
    123     MachineInstr *Old = I;
    124     uint64_t Amount = Old->getOperand(0).getImm();
    125     if (Amount != 0) {
    126       // We need to keep the stack aligned properly.  To do this, we round the
    127       // amount of space needed for the outgoing arguments up to the next
    128       // alignment boundary.
    129       unsigned Align = TFI->getStackAlignment();
    130       Amount = (Amount+Align-1)/Align*Align;
    131 
    132       assert(Amount%4 == 0);
    133       Amount /= 4;
    134 
    135       bool isU6 = isImmU6(Amount);
    136       if (!isU6 && !isImmU16(Amount)) {
    137         // FIX could emit multiple instructions in this case.
    138 #ifndef NDEBUG
    139         errs() << "eliminateCallFramePseudoInstr size too big: "
    140                << Amount << "\n";
    141 #endif
    142         llvm_unreachable(0);
    143       }
    144 
    145       MachineInstr *New;
    146       if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
    147         int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
    148         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
    149           .addImm(Amount);
    150       } else {
    151         assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
    152         int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
    153         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
    154           .addImm(Amount);
    155       }
    156 
    157       // Replace the pseudo instruction with a new instruction...
    158       MBB.insert(I, New);
    159     }
    160   }
    161 
    162   MBB.erase(I);
    163 }
    164 
    165 void
    166 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
    167                                        int SPAdj, RegScavenger *RS) const {
    168   assert(SPAdj == 0 && "Unexpected");
    169   MachineInstr &MI = *II;
    170   DebugLoc dl = MI.getDebugLoc();
    171   unsigned i = 0;
    172 
    173   while (!MI.getOperand(i).isFI()) {
    174     ++i;
    175     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
    176   }
    177 
    178   MachineOperand &FrameOp = MI.getOperand(i);
    179   int FrameIndex = FrameOp.getIndex();
    180 
    181   MachineFunction &MF = *MI.getParent()->getParent();
    182   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    183   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
    184   int StackSize = MF.getFrameInfo()->getStackSize();
    185 
    186   #ifndef NDEBUG
    187   DEBUG(errs() << "\nFunction         : "
    188         << MF.getFunction()->getName() << "\n");
    189   DEBUG(errs() << "<--------->\n");
    190   DEBUG(MI.print(errs()));
    191   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
    192   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
    193   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
    194   #endif
    195 
    196   Offset += StackSize;
    197 
    198   unsigned FrameReg = getFrameRegister(MF);
    199 
    200   // Special handling of DBG_VALUE instructions.
    201   if (MI.isDebugValue()) {
    202     MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
    203     MI.getOperand(i+1).ChangeToImmediate(Offset);
    204     return;
    205   }
    206 
    207   // fold constant into offset.
    208   Offset += MI.getOperand(i + 1).getImm();
    209   MI.getOperand(i + 1).ChangeToImmediate(0);
    210 
    211   assert(Offset%4 == 0 && "Misaligned stack offset");
    212 
    213   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
    214 
    215   Offset/=4;
    216 
    217   bool FP = TFI->hasFP(MF);
    218 
    219   unsigned Reg = MI.getOperand(0).getReg();
    220   bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
    221 
    222   assert(XCore::GRRegsRegisterClass->contains(Reg) &&
    223          "Unexpected register operand");
    224 
    225   MachineBasicBlock &MBB = *MI.getParent();
    226 
    227   if (FP) {
    228     bool isUs = isImmUs(Offset);
    229 
    230     if (!isUs) {
    231       if (!RS)
    232         report_fatal_error("eliminateFrameIndex Frame size too big: " +
    233                            Twine(Offset));
    234       unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
    235                                                  SPAdj);
    236       loadConstant(MBB, II, ScratchReg, Offset, dl);
    237       switch (MI.getOpcode()) {
    238       case XCore::LDWFI:
    239         BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
    240               .addReg(FrameReg)
    241               .addReg(ScratchReg, RegState::Kill);
    242         break;
    243       case XCore::STWFI:
    244         BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
    245               .addReg(Reg, getKillRegState(isKill))
    246               .addReg(FrameReg)
    247               .addReg(ScratchReg, RegState::Kill);
    248         break;
    249       case XCore::LDAWFI:
    250         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
    251               .addReg(FrameReg)
    252               .addReg(ScratchReg, RegState::Kill);
    253         break;
    254       default:
    255         llvm_unreachable("Unexpected Opcode");
    256       }
    257     } else {
    258       switch (MI.getOpcode()) {
    259       case XCore::LDWFI:
    260         BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
    261               .addReg(FrameReg)
    262               .addImm(Offset);
    263         break;
    264       case XCore::STWFI:
    265         BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
    266               .addReg(Reg, getKillRegState(isKill))
    267               .addReg(FrameReg)
    268               .addImm(Offset);
    269         break;
    270       case XCore::LDAWFI:
    271         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
    272               .addReg(FrameReg)
    273               .addImm(Offset);
    274         break;
    275       default:
    276         llvm_unreachable("Unexpected Opcode");
    277       }
    278     }
    279   } else {
    280     bool isU6 = isImmU6(Offset);
    281     if (!isU6 && !isImmU16(Offset))
    282       report_fatal_error("eliminateFrameIndex Frame size too big: " +
    283                          Twine(Offset));
    284 
    285     switch (MI.getOpcode()) {
    286     int NewOpcode;
    287     case XCore::LDWFI:
    288       NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
    289       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
    290             .addImm(Offset);
    291       break;
    292     case XCore::STWFI:
    293       NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
    294       BuildMI(MBB, II, dl, TII.get(NewOpcode))
    295             .addReg(Reg, getKillRegState(isKill))
    296             .addImm(Offset);
    297       break;
    298     case XCore::LDAWFI:
    299       NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
    300       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
    301             .addImm(Offset);
    302       break;
    303     default:
    304       llvm_unreachable("Unexpected Opcode");
    305     }
    306   }
    307   // Erase old instruction.
    308   MBB.erase(II);
    309 }
    310 
    311 void XCoreRegisterInfo::
    312 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
    313             unsigned DstReg, int64_t Value, DebugLoc dl) const {
    314   // TODO use mkmsk if possible.
    315   if (!isImmU16(Value)) {
    316     // TODO use constant pool.
    317     report_fatal_error("loadConstant value too big " + Twine(Value));
    318   }
    319   int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
    320   BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
    321 }
    322 
    323 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    324   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    325 
    326   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
    327 }
    328