1 ; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=SOFT 2 ; RUN: llc < %s -mtriple=armv7-gnueabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -check-prefix=HARD 3 4 ; rdar://8984306 5 define float @test1(float %x, float %y) nounwind { 6 entry: 7 ; SOFT: test1: 8 ; SOFT: lsr r1, r1, #31 9 ; SOFT: bfi r0, r1, #31, #1 10 11 ; HARD: test1: 12 ; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000 13 ; HARD: vbsl [[REG1]], d 14 %0 = tail call float @copysignf(float %x, float %y) nounwind 15 ret float %0 16 } 17 18 define double @test2(double %x, double %y) nounwind { 19 entry: 20 ; SOFT: test2: 21 ; SOFT: lsr r2, r3, #31 22 ; SOFT: bfi r1, r2, #31, #1 23 24 ; HARD: test2: 25 ; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000 26 ; HARD: vshl.i64 [[REG2]], [[REG2]], #32 27 ; HARD: vbsl [[REG2]], d1, d0 28 %0 = tail call double @copysign(double %x, double %y) nounwind 29 ret double %0 30 } 31 32 define double @test3(double %x, double %y, double %z) nounwind { 33 entry: 34 ; SOFT: test3: 35 ; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000 36 ; SOFT: vshl.i64 [[REG3]], [[REG3]], #32 37 ; SOFT: vbsl [[REG3]], 38 %0 = fmul double %x, %y 39 %1 = tail call double @copysign(double %0, double %z) nounwind 40 ret double %1 41 } 42 43 ; rdar://9059537 44 define i32 @test4() ssp { 45 entry: 46 ; SOFT: test4: 47 ; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00 48 ; This S-reg must be the first sub-reg of the last D-reg on vbsl. 49 ; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]] 50 ; SOFT: vshr.u64 [[REG4]], [[REG4]], #32 51 ; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000 52 ; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}} 53 %call80 = tail call double @copysign(double 1.000000e+00, double undef) 54 %conv81 = fptrunc double %call80 to float 55 %tmp88 = bitcast float %conv81 to i32 56 ret i32 %tmp88 57 } 58 59 ; rdar://9287902 60 define float @test5() nounwind { 61 entry: 62 ; SOFT: test5: 63 ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000 64 ; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1 65 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32 66 ; SOFT: vbsl [[REG6]], [[REG7]], 67 %0 = tail call double (...)* @bar() nounwind 68 %1 = fptrunc double %0 to float 69 %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone 70 %3 = fadd float %1, %2 71 ret float %3 72 } 73 74 declare double @bar(...) 75 declare double @copysign(double, double) nounwind 76 declare float @copysignf(float, float) nounwind 77
