1 ; These are tests for SSE3 codegen. 2 3 ; RUN: llc < %s -march=x86-64 -mcpu=nocona -mtriple=i686-apple-darwin9 -O3 \ 4 ; RUN: | FileCheck %s --check-prefix=X64 5 6 ; Test for v8xi16 lowering where we extract the first element of the vector and 7 ; placed it in the second element of the result. 8 9 define void @t0(<8 x i16>* %dest, <8 x i16>* %old) nounwind { 10 entry: 11 %tmp3 = load <8 x i16>* %old 12 %tmp6 = shufflevector <8 x i16> %tmp3, 13 <8 x i16> < i16 0, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef >, 14 <8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef > 15 store <8 x i16> %tmp6, <8 x i16>* %dest 16 ret void 17 18 ; X64: t0: 19 ; X64: movddup (%rsi), %xmm0 20 ; X64: pshuflw $0, %xmm0, %xmm0 21 ; X64: xorl %eax, %eax 22 ; X64: pinsrw $0, %eax, %xmm0 23 ; X64: movdqa %xmm0, (%rdi) 24 ; X64: ret 25 } 26 27 define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind { 28 %tmp1 = load <8 x i16>* %A 29 %tmp2 = load <8 x i16>* %B 30 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > 31 ret <8 x i16> %tmp3 32 33 ; X64: t1: 34 ; X64: movl (%rsi), %eax 35 ; X64: movdqa (%rdi), %xmm0 36 ; X64: pinsrw $0, %eax, %xmm0 37 ; X64: ret 38 } 39 40 define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind { 41 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 > 42 ret <8 x i16> %tmp 43 ; X64: t2: 44 ; X64: pextrw $1, %xmm1, %eax 45 ; X64: pinsrw $0, %eax, %xmm0 46 ; X64: pinsrw $3, %eax, %xmm0 47 ; X64: ret 48 } 49 50 define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind { 51 %tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 > 52 ret <8 x i16> %tmp 53 ; X64: t3: 54 ; X64: pextrw $5, %xmm0, %eax 55 ; X64: pshuflw $44, %xmm0, %xmm0 56 ; X64: pshufhw $27, %xmm0, %xmm0 57 ; X64: pinsrw $3, %eax, %xmm0 58 ; X64: ret 59 } 60 61 define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { 62 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 > 63 ret <8 x i16> %tmp 64 ; X64: t4: 65 ; X64: pextrw $7, [[XMM0:%xmm[0-9]+]], %eax 66 ; X64: pshufhw $100, [[XMM0]], [[XMM1:%xmm[0-9]+]] 67 ; X64: pinsrw $1, %eax, [[XMM1]] 68 ; X64: pextrw $1, [[XMM0]], %eax 69 ; X64: pinsrw $4, %eax, %xmm0 70 ; X64: ret 71 } 72 73 define <8 x i16> @t5(<8 x i16> %A, <8 x i16> %B) nounwind { 74 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 0, i32 1, i32 10, i32 11, i32 2, i32 3 > 75 ret <8 x i16> %tmp 76 ; X64: t5: 77 ; X64: movlhps %xmm1, %xmm0 78 ; X64: pshufd $114, %xmm0, %xmm0 79 ; X64: ret 80 } 81 82 define <8 x i16> @t6(<8 x i16> %A, <8 x i16> %B) nounwind { 83 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > 84 ret <8 x i16> %tmp 85 ; X64: t6: 86 ; X64: movss %xmm1, %xmm0 87 ; X64: ret 88 } 89 90 define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind { 91 %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 > 92 ret <8 x i16> %tmp 93 ; X64: t7: 94 ; X64: pshuflw $-80, %xmm0, %xmm0 95 ; X64: pshufhw $-56, %xmm0, %xmm0 96 ; X64: ret 97 } 98 99 define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind { 100 %tmp = load <2 x i64>* %A 101 %tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16> 102 %tmp0 = extractelement <8 x i16> %tmp.upgrd.1, i32 0 103 %tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1 104 %tmp2 = extractelement <8 x i16> %tmp.upgrd.1, i32 2 105 %tmp3 = extractelement <8 x i16> %tmp.upgrd.1, i32 3 106 %tmp4 = extractelement <8 x i16> %tmp.upgrd.1, i32 4 107 %tmp5 = extractelement <8 x i16> %tmp.upgrd.1, i32 5 108 %tmp6 = extractelement <8 x i16> %tmp.upgrd.1, i32 6 109 %tmp7 = extractelement <8 x i16> %tmp.upgrd.1, i32 7 110 %tmp8 = insertelement <8 x i16> undef, i16 %tmp2, i32 0 111 %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 1 112 %tmp10 = insertelement <8 x i16> %tmp9, i16 %tmp0, i32 2 113 %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 3 114 %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp6, i32 4 115 %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 5 116 %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp4, i32 6 117 %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 7 118 %tmp15.upgrd.2 = bitcast <8 x i16> %tmp15 to <2 x i64> 119 store <2 x i64> %tmp15.upgrd.2, <2 x i64>* %res 120 ret void 121 ; X64: t8: 122 ; X64: pshuflw $-58, (%rsi), %xmm0 123 ; X64: pshufhw $-58, %xmm0, %xmm0 124 ; X64: movdqa %xmm0, (%rdi) 125 ; X64: ret 126 } 127 128 define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind { 129 %tmp = load <4 x float>* %r 130 %tmp.upgrd.3 = bitcast <2 x i32>* %A to double* 131 %tmp.upgrd.4 = load double* %tmp.upgrd.3 132 %tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0 133 %tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1 134 %tmp6 = bitcast <2 x double> %tmp5 to <4 x float> 135 %tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0 136 %tmp7 = extractelement <4 x float> %tmp, i32 1 137 %tmp8 = extractelement <4 x float> %tmp6, i32 0 138 %tmp9 = extractelement <4 x float> %tmp6, i32 1 139 %tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0 140 %tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1 141 %tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2 142 %tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3 143 store <4 x float> %tmp13, <4 x float>* %r 144 ret void 145 ; X64: t9: 146 ; X64: movaps (%rdi), %xmm0 147 ; X64: movhps (%rsi), %xmm0 148 ; X64: movaps %xmm0, (%rdi) 149 ; X64: ret 150 } 151 152 153 154 ; FIXME: This testcase produces icky code. It can be made much better! 155 ; PR2585 156 157 @g1 = external constant <4 x i32> 158 @g2 = external constant <4 x i16> 159 160 define internal void @t10() nounwind { 161 load <4 x i32>* @g1, align 16 162 bitcast <4 x i32> %1 to <8 x i16> 163 shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef > 164 bitcast <8 x i16> %3 to <2 x i64> 165 extractelement <2 x i64> %4, i32 0 166 bitcast i64 %5 to <4 x i16> 167 store <4 x i16> %6, <4 x i16>* @g2, align 8 168 ret void 169 ; X64: t10: 170 ; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax 171 ; X64: unpcklpd [[X1:%xmm[0-9]+]] 172 ; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]] 173 ; X64: pinsrw $2, %eax, [[X2]] 174 ; X64: pextrw $6, [[X0]], %eax 175 ; X64: pinsrw $3, %eax, [[X2]] 176 } 177 178 179 ; Pack various elements via shuffles. 180 define <8 x i16> @t11(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 181 entry: 182 %tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > 183 ret <8 x i16> %tmp7 184 185 ; X64: t11: 186 ; X64: movd %xmm1, %eax 187 ; X64: movlhps %xmm0, %xmm0 188 ; X64: pshuflw $1, %xmm0, %xmm0 189 ; X64: pinsrw $1, %eax, %xmm0 190 ; X64: ret 191 } 192 193 194 define <8 x i16> @t12(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 195 entry: 196 %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef > 197 ret <8 x i16> %tmp9 198 199 ; X64: t12: 200 ; X64: pextrw $3, %xmm1, %eax 201 ; X64: movlhps %xmm0, %xmm0 202 ; X64: pshufhw $3, %xmm0, %xmm0 203 ; X64: pinsrw $5, %eax, %xmm0 204 ; X64: ret 205 } 206 207 208 define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 209 entry: 210 %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef > 211 ret <8 x i16> %tmp9 212 ; X64: t13: 213 ; X64: punpcklqdq %xmm0, %xmm1 214 ; X64: pextrw $3, %xmm1, %eax 215 ; X64: pshufd $52, %xmm1, %xmm0 216 ; X64: pinsrw $4, %eax, %xmm0 217 ; X64: ret 218 } 219 220 221 define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 222 entry: 223 %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef > 224 ret <8 x i16> %tmp9 225 ; X64: t14: 226 ; X64: punpcklqdq %xmm0, %xmm1 227 ; X64: pshufhw $8, %xmm1, %xmm0 228 ; X64: ret 229 } 230 231 232 233 define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { 234 entry: 235 %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef > 236 ret <8 x i16> %tmp8 237 ; X64: t15: 238 ; X64: pextrw $7, %xmm0, %eax 239 ; X64: punpcklqdq %xmm1, %xmm0 240 ; X64: pshuflw $-128, %xmm0, %xmm0 241 ; X64: pinsrw $2, %eax, %xmm0 242 ; X64: ret 243 } 244 245 246 ; Test yonah where we convert a shuffle to pextrw and pinrsw 247 define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone { 248 entry: 249 %tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > 250 %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > 251 ret <16 x i8> %tmp9 252 ; X64: t16: 253 ; X64: pinsrw $0, %eax, [[X1:%xmm[0-9]+]] 254 ; X64: pextrw $8, [[X0:%xmm[0-9]+]], %eax 255 ; X64: pinsrw $1, %eax, [[X1]] 256 ; X64: pextrw $1, [[X1]], %ecx 257 ; X64: movd [[X1]], %edx 258 ; X64: pinsrw $0, %edx, %xmm 259 ; X64: pinsrw $1, %eax, %xmm 260 ; X64: ret 261 } 262 263 ; rdar://8520311 264 define <4 x i32> @t17() nounwind { 265 entry: 266 ; X64: t17: 267 ; X64: movddup (%rax), %xmm0 268 %tmp1 = load <4 x float>* undef, align 16 269 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3> 270 %tmp3 = load <4 x float>* undef, align 16 271 %tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> 272 %tmp5 = bitcast <4 x float> %tmp3 to <4 x i32> 273 %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> 274 %tmp7 = and <4 x i32> %tmp6, <i32 undef, i32 undef, i32 -1, i32 0> 275 ret <4 x i32> %tmp7 276 } 277
