1 2 /*---------------------------------------------------------------*/ 3 /*--- begin ir_defs.c ---*/ 4 /*---------------------------------------------------------------*/ 5 6 /* 7 This file is part of Valgrind, a dynamic binary instrumentation 8 framework. 9 10 Copyright (C) 2004-2015 OpenWorks LLP 11 info (at) open-works.net 12 13 This program is free software; you can redistribute it and/or 14 modify it under the terms of the GNU General Public License as 15 published by the Free Software Foundation; either version 2 of the 16 License, or (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, but 19 WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21 General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, write to the Free Software 25 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 26 02110-1301, USA. 27 28 The GNU General Public License is contained in the file COPYING. 29 30 Neither the names of the U.S. Department of Energy nor the 31 University of California nor the names of its contributors may be 32 used to endorse or promote products derived from this software 33 without prior written permission. 34 */ 35 36 #include "libvex_basictypes.h" 37 #include "libvex_ir.h" 38 #include "libvex.h" 39 40 #include "main_util.h" 41 42 43 /*---------------------------------------------------------------*/ 44 /*--- Printing the IR ---*/ 45 /*---------------------------------------------------------------*/ 46 47 void ppIRType ( IRType ty ) 48 { 49 switch (ty) { 50 case Ity_INVALID: vex_printf("Ity_INVALID"); break; 51 case Ity_I1: vex_printf( "I1"); break; 52 case Ity_I8: vex_printf( "I8"); break; 53 case Ity_I16: vex_printf( "I16"); break; 54 case Ity_I32: vex_printf( "I32"); break; 55 case Ity_I64: vex_printf( "I64"); break; 56 case Ity_I128: vex_printf( "I128"); break; 57 case Ity_F16: vex_printf( "F16"); break; 58 case Ity_F32: vex_printf( "F32"); break; 59 case Ity_F64: vex_printf( "F64"); break; 60 case Ity_F128: vex_printf( "F128"); break; 61 case Ity_D32: vex_printf( "D32"); break; 62 case Ity_D64: vex_printf( "D64"); break; 63 case Ity_D128: vex_printf( "D128"); break; 64 case Ity_V128: vex_printf( "V128"); break; 65 case Ity_V256: vex_printf( "V256"); break; 66 default: vex_printf("ty = 0x%x\n", (UInt)ty); 67 vpanic("ppIRType"); 68 } 69 } 70 71 void ppIRConst ( const IRConst* con ) 72 { 73 union { ULong i64; Double f64; UInt i32; Float f32; } u; 74 vassert(sizeof(ULong) == sizeof(Double)); 75 switch (con->tag) { 76 case Ico_U1: vex_printf( "%d:I1", con->Ico.U1 ? 1 : 0); break; 77 case Ico_U8: vex_printf( "0x%x:I8", (UInt)(con->Ico.U8)); break; 78 case Ico_U16: vex_printf( "0x%x:I16", (UInt)(con->Ico.U16)); break; 79 case Ico_U32: vex_printf( "0x%x:I32", (UInt)(con->Ico.U32)); break; 80 case Ico_U64: vex_printf( "0x%llx:I64", (ULong)(con->Ico.U64)); break; 81 case Ico_F32: u.f32 = con->Ico.F32; 82 vex_printf( "F32{0x%x}", u.i32); 83 break; 84 case Ico_F32i: vex_printf( "F32i{0x%x}", con->Ico.F32i); break; 85 case Ico_F64: u.f64 = con->Ico.F64; 86 vex_printf( "F64{0x%llx}", u.i64); 87 break; 88 case Ico_F64i: vex_printf( "F64i{0x%llx}", con->Ico.F64i); break; 89 case Ico_V128: vex_printf( "V128{0x%04x}", (UInt)(con->Ico.V128)); break; 90 case Ico_V256: vex_printf( "V256{0x%08x}", con->Ico.V256); break; 91 default: vpanic("ppIRConst"); 92 } 93 } 94 95 void ppIRCallee ( const IRCallee* ce ) 96 { 97 vex_printf("%s", ce->name); 98 if (ce->regparms > 0) 99 vex_printf("[rp=%d]", ce->regparms); 100 if (ce->mcx_mask > 0) 101 vex_printf("[mcx=0x%x]", ce->mcx_mask); 102 vex_printf("{%p}", (void*)ce->addr); 103 } 104 105 void ppIRRegArray ( const IRRegArray* arr ) 106 { 107 vex_printf("(%d:%dx", arr->base, arr->nElems); 108 ppIRType(arr->elemTy); 109 vex_printf(")"); 110 } 111 112 void ppIRTemp ( IRTemp tmp ) 113 { 114 if (tmp == IRTemp_INVALID) 115 vex_printf("IRTemp_INVALID"); 116 else 117 vex_printf( "t%u", tmp); 118 } 119 120 void ppIROp ( IROp op ) 121 { 122 const HChar* str = NULL; 123 IROp base; 124 switch (op) { 125 case Iop_Add8 ... Iop_Add64: 126 str = "Add"; base = Iop_Add8; break; 127 case Iop_Sub8 ... Iop_Sub64: 128 str = "Sub"; base = Iop_Sub8; break; 129 case Iop_Mul8 ... Iop_Mul64: 130 str = "Mul"; base = Iop_Mul8; break; 131 case Iop_Or8 ... Iop_Or64: 132 str = "Or"; base = Iop_Or8; break; 133 case Iop_And8 ... Iop_And64: 134 str = "And"; base = Iop_And8; break; 135 case Iop_Xor8 ... Iop_Xor64: 136 str = "Xor"; base = Iop_Xor8; break; 137 case Iop_Shl8 ... Iop_Shl64: 138 str = "Shl"; base = Iop_Shl8; break; 139 case Iop_Shr8 ... Iop_Shr64: 140 str = "Shr"; base = Iop_Shr8; break; 141 case Iop_Sar8 ... Iop_Sar64: 142 str = "Sar"; base = Iop_Sar8; break; 143 case Iop_CmpEQ8 ... Iop_CmpEQ64: 144 str = "CmpEQ"; base = Iop_CmpEQ8; break; 145 case Iop_CmpNE8 ... Iop_CmpNE64: 146 str = "CmpNE"; base = Iop_CmpNE8; break; 147 case Iop_CasCmpEQ8 ... Iop_CasCmpEQ64: 148 str = "CasCmpEQ"; base = Iop_CasCmpEQ8; break; 149 case Iop_CasCmpNE8 ... Iop_CasCmpNE64: 150 str = "CasCmpNE"; base = Iop_CasCmpNE8; break; 151 case Iop_ExpCmpNE8 ... Iop_ExpCmpNE64: 152 str = "ExpCmpNE"; base = Iop_ExpCmpNE8; break; 153 case Iop_Not8 ... Iop_Not64: 154 str = "Not"; base = Iop_Not8; break; 155 /* other cases must explicitly "return;" */ 156 case Iop_8Uto16: vex_printf("8Uto16"); return; 157 case Iop_8Uto32: vex_printf("8Uto32"); return; 158 case Iop_16Uto32: vex_printf("16Uto32"); return; 159 case Iop_8Sto16: vex_printf("8Sto16"); return; 160 case Iop_8Sto32: vex_printf("8Sto32"); return; 161 case Iop_16Sto32: vex_printf("16Sto32"); return; 162 case Iop_32Sto64: vex_printf("32Sto64"); return; 163 case Iop_32Uto64: vex_printf("32Uto64"); return; 164 case Iop_32to8: vex_printf("32to8"); return; 165 case Iop_16Uto64: vex_printf("16Uto64"); return; 166 case Iop_16Sto64: vex_printf("16Sto64"); return; 167 case Iop_8Uto64: vex_printf("8Uto64"); return; 168 case Iop_8Sto64: vex_printf("8Sto64"); return; 169 case Iop_64to16: vex_printf("64to16"); return; 170 case Iop_64to8: vex_printf("64to8"); return; 171 172 case Iop_Not1: vex_printf("Not1"); return; 173 case Iop_32to1: vex_printf("32to1"); return; 174 case Iop_64to1: vex_printf("64to1"); return; 175 case Iop_1Uto8: vex_printf("1Uto8"); return; 176 case Iop_1Uto32: vex_printf("1Uto32"); return; 177 case Iop_1Uto64: vex_printf("1Uto64"); return; 178 case Iop_1Sto8: vex_printf("1Sto8"); return; 179 case Iop_1Sto16: vex_printf("1Sto16"); return; 180 case Iop_1Sto32: vex_printf("1Sto32"); return; 181 case Iop_1Sto64: vex_printf("1Sto64"); return; 182 183 case Iop_MullS8: vex_printf("MullS8"); return; 184 case Iop_MullS16: vex_printf("MullS16"); return; 185 case Iop_MullS32: vex_printf("MullS32"); return; 186 case Iop_MullS64: vex_printf("MullS64"); return; 187 case Iop_MullU8: vex_printf("MullU8"); return; 188 case Iop_MullU16: vex_printf("MullU16"); return; 189 case Iop_MullU32: vex_printf("MullU32"); return; 190 case Iop_MullU64: vex_printf("MullU64"); return; 191 192 case Iop_Clz64: vex_printf("Clz64"); return; 193 case Iop_Clz32: vex_printf("Clz32"); return; 194 case Iop_Ctz64: vex_printf("Ctz64"); return; 195 case Iop_Ctz32: vex_printf("Ctz32"); return; 196 197 case Iop_CmpLT32S: vex_printf("CmpLT32S"); return; 198 case Iop_CmpLE32S: vex_printf("CmpLE32S"); return; 199 case Iop_CmpLT32U: vex_printf("CmpLT32U"); return; 200 case Iop_CmpLE32U: vex_printf("CmpLE32U"); return; 201 202 case Iop_CmpLT64S: vex_printf("CmpLT64S"); return; 203 case Iop_CmpLE64S: vex_printf("CmpLE64S"); return; 204 case Iop_CmpLT64U: vex_printf("CmpLT64U"); return; 205 case Iop_CmpLE64U: vex_printf("CmpLE64U"); return; 206 207 case Iop_CmpNEZ8: vex_printf("CmpNEZ8"); return; 208 case Iop_CmpNEZ16: vex_printf("CmpNEZ16"); return; 209 case Iop_CmpNEZ32: vex_printf("CmpNEZ32"); return; 210 case Iop_CmpNEZ64: vex_printf("CmpNEZ64"); return; 211 212 case Iop_CmpwNEZ32: vex_printf("CmpwNEZ32"); return; 213 case Iop_CmpwNEZ64: vex_printf("CmpwNEZ64"); return; 214 215 case Iop_Left8: vex_printf("Left8"); return; 216 case Iop_Left16: vex_printf("Left16"); return; 217 case Iop_Left32: vex_printf("Left32"); return; 218 case Iop_Left64: vex_printf("Left64"); return; 219 case Iop_Max32U: vex_printf("Max32U"); return; 220 221 case Iop_CmpORD32U: vex_printf("CmpORD32U"); return; 222 case Iop_CmpORD32S: vex_printf("CmpORD32S"); return; 223 224 case Iop_CmpORD64U: vex_printf("CmpORD64U"); return; 225 case Iop_CmpORD64S: vex_printf("CmpORD64S"); return; 226 227 case Iop_DivU32: vex_printf("DivU32"); return; 228 case Iop_DivS32: vex_printf("DivS32"); return; 229 case Iop_DivU64: vex_printf("DivU64"); return; 230 case Iop_DivS64: vex_printf("DivS64"); return; 231 case Iop_DivU64E: vex_printf("DivU64E"); return; 232 case Iop_DivS64E: vex_printf("DivS64E"); return; 233 case Iop_DivU32E: vex_printf("DivU32E"); return; 234 case Iop_DivS32E: vex_printf("DivS32E"); return; 235 236 case Iop_DivModU64to32: vex_printf("DivModU64to32"); return; 237 case Iop_DivModS64to32: vex_printf("DivModS64to32"); return; 238 239 case Iop_DivModU128to64: vex_printf("DivModU128to64"); return; 240 case Iop_DivModS128to64: vex_printf("DivModS128to64"); return; 241 242 case Iop_DivModS64to64: vex_printf("DivModS64to64"); return; 243 244 case Iop_16HIto8: vex_printf("16HIto8"); return; 245 case Iop_16to8: vex_printf("16to8"); return; 246 case Iop_8HLto16: vex_printf("8HLto16"); return; 247 248 case Iop_32HIto16: vex_printf("32HIto16"); return; 249 case Iop_32to16: vex_printf("32to16"); return; 250 case Iop_16HLto32: vex_printf("16HLto32"); return; 251 252 case Iop_64HIto32: vex_printf("64HIto32"); return; 253 case Iop_64to32: vex_printf("64to32"); return; 254 case Iop_32HLto64: vex_printf("32HLto64"); return; 255 256 case Iop_128HIto64: vex_printf("128HIto64"); return; 257 case Iop_128to64: vex_printf("128to64"); return; 258 case Iop_64HLto128: vex_printf("64HLto128"); return; 259 260 case Iop_CmpF32: vex_printf("CmpF32"); return; 261 case Iop_F32toI32S: vex_printf("F32toI32S"); return; 262 case Iop_F32toI64S: vex_printf("F32toI64S"); return; 263 case Iop_I32StoF32: vex_printf("I32StoF32"); return; 264 case Iop_I64StoF32: vex_printf("I64StoF32"); return; 265 266 case Iop_AddF64: vex_printf("AddF64"); return; 267 case Iop_SubF64: vex_printf("SubF64"); return; 268 case Iop_MulF64: vex_printf("MulF64"); return; 269 case Iop_DivF64: vex_printf("DivF64"); return; 270 case Iop_AddF64r32: vex_printf("AddF64r32"); return; 271 case Iop_SubF64r32: vex_printf("SubF64r32"); return; 272 case Iop_MulF64r32: vex_printf("MulF64r32"); return; 273 case Iop_DivF64r32: vex_printf("DivF64r32"); return; 274 case Iop_AddF32: vex_printf("AddF32"); return; 275 case Iop_SubF32: vex_printf("SubF32"); return; 276 case Iop_MulF32: vex_printf("MulF32"); return; 277 case Iop_DivF32: vex_printf("DivF32"); return; 278 279 /* 128 bit floating point */ 280 case Iop_AddF128: vex_printf("AddF128"); return; 281 case Iop_SubF128: vex_printf("SubF128"); return; 282 case Iop_MulF128: vex_printf("MulF128"); return; 283 case Iop_DivF128: vex_printf("DivF128"); return; 284 case Iop_AbsF128: vex_printf("AbsF128"); return; 285 case Iop_NegF128: vex_printf("NegF128"); return; 286 case Iop_SqrtF128: vex_printf("SqrtF128"); return; 287 case Iop_CmpF128: vex_printf("CmpF128"); return; 288 289 case Iop_F64HLtoF128: vex_printf("F64HLtoF128"); return; 290 case Iop_F128HItoF64: vex_printf("F128HItoF64"); return; 291 case Iop_F128LOtoF64: vex_printf("F128LOtoF64"); return; 292 case Iop_I32StoF128: vex_printf("I32StoF128"); return; 293 case Iop_I64StoF128: vex_printf("I64StoF128"); return; 294 case Iop_I32UtoF128: vex_printf("I32UtoF128"); return; 295 case Iop_I64UtoF128: vex_printf("I64UtoF128"); return; 296 case Iop_F128toI32S: vex_printf("F128toI32S"); return; 297 case Iop_F128toI64S: vex_printf("F128toI64S"); return; 298 case Iop_F128toI32U: vex_printf("F128toI32U"); return; 299 case Iop_F128toI64U: vex_printf("F128toI64U"); return; 300 case Iop_F32toF128: vex_printf("F32toF128"); return; 301 case Iop_F64toF128: vex_printf("F64toF128"); return; 302 case Iop_F128toF64: vex_printf("F128toF64"); return; 303 case Iop_F128toF32: vex_printf("F128toF32"); return; 304 305 /* s390 specific */ 306 case Iop_MAddF32: vex_printf("s390_MAddF32"); return; 307 case Iop_MSubF32: vex_printf("s390_MSubF32"); return; 308 309 case Iop_ScaleF64: vex_printf("ScaleF64"); return; 310 case Iop_AtanF64: vex_printf("AtanF64"); return; 311 case Iop_Yl2xF64: vex_printf("Yl2xF64"); return; 312 case Iop_Yl2xp1F64: vex_printf("Yl2xp1F64"); return; 313 case Iop_PRemF64: vex_printf("PRemF64"); return; 314 case Iop_PRemC3210F64: vex_printf("PRemC3210F64"); return; 315 case Iop_PRem1F64: vex_printf("PRem1F64"); return; 316 case Iop_PRem1C3210F64: vex_printf("PRem1C3210F64"); return; 317 case Iop_NegF64: vex_printf("NegF64"); return; 318 case Iop_AbsF64: vex_printf("AbsF64"); return; 319 case Iop_NegF32: vex_printf("NegF32"); return; 320 case Iop_AbsF32: vex_printf("AbsF32"); return; 321 case Iop_SqrtF64: vex_printf("SqrtF64"); return; 322 case Iop_SqrtF32: vex_printf("SqrtF32"); return; 323 case Iop_SinF64: vex_printf("SinF64"); return; 324 case Iop_CosF64: vex_printf("CosF64"); return; 325 case Iop_TanF64: vex_printf("TanF64"); return; 326 case Iop_2xm1F64: vex_printf("2xm1F64"); return; 327 328 case Iop_MAddF64: vex_printf("MAddF64"); return; 329 case Iop_MSubF64: vex_printf("MSubF64"); return; 330 case Iop_MAddF64r32: vex_printf("MAddF64r32"); return; 331 case Iop_MSubF64r32: vex_printf("MSubF64r32"); return; 332 333 case Iop_RSqrtEst5GoodF64: vex_printf("RSqrtEst5GoodF64"); return; 334 case Iop_RoundF64toF64_NEAREST: vex_printf("RoundF64toF64_NEAREST"); return; 335 case Iop_RoundF64toF64_NegINF: vex_printf("RoundF64toF64_NegINF"); return; 336 case Iop_RoundF64toF64_PosINF: vex_printf("RoundF64toF64_PosINF"); return; 337 case Iop_RoundF64toF64_ZERO: vex_printf("RoundF64toF64_ZERO"); return; 338 339 case Iop_TruncF64asF32: vex_printf("TruncF64asF32"); return; 340 341 case Iop_RecpExpF64: vex_printf("RecpExpF64"); return; 342 case Iop_RecpExpF32: vex_printf("RecpExpF32"); return; 343 344 case Iop_F16toF64: vex_printf("F16toF64"); return; 345 case Iop_F64toF16: vex_printf("F64toF16"); return; 346 case Iop_F16toF32: vex_printf("F16toF32"); return; 347 case Iop_F32toF16: vex_printf("F32toF16"); return; 348 349 case Iop_QAdd32S: vex_printf("QAdd32S"); return; 350 case Iop_QSub32S: vex_printf("QSub32S"); return; 351 case Iop_Add16x2: vex_printf("Add16x2"); return; 352 case Iop_Sub16x2: vex_printf("Sub16x2"); return; 353 case Iop_QAdd16Sx2: vex_printf("QAdd16Sx2"); return; 354 case Iop_QAdd16Ux2: vex_printf("QAdd16Ux2"); return; 355 case Iop_QSub16Sx2: vex_printf("QSub16Sx2"); return; 356 case Iop_QSub16Ux2: vex_printf("QSub16Ux2"); return; 357 case Iop_HAdd16Ux2: vex_printf("HAdd16Ux2"); return; 358 case Iop_HAdd16Sx2: vex_printf("HAdd16Sx2"); return; 359 case Iop_HSub16Ux2: vex_printf("HSub16Ux2"); return; 360 case Iop_HSub16Sx2: vex_printf("HSub16Sx2"); return; 361 362 case Iop_Add8x4: vex_printf("Add8x4"); return; 363 case Iop_Sub8x4: vex_printf("Sub8x4"); return; 364 case Iop_QAdd8Sx4: vex_printf("QAdd8Sx4"); return; 365 case Iop_QAdd8Ux4: vex_printf("QAdd8Ux4"); return; 366 case Iop_QSub8Sx4: vex_printf("QSub8Sx4"); return; 367 case Iop_QSub8Ux4: vex_printf("QSub8Ux4"); return; 368 case Iop_HAdd8Ux4: vex_printf("HAdd8Ux4"); return; 369 case Iop_HAdd8Sx4: vex_printf("HAdd8Sx4"); return; 370 case Iop_HSub8Ux4: vex_printf("HSub8Ux4"); return; 371 case Iop_HSub8Sx4: vex_printf("HSub8Sx4"); return; 372 case Iop_Sad8Ux4: vex_printf("Sad8Ux4"); return; 373 374 case Iop_CmpNEZ16x2: vex_printf("CmpNEZ16x2"); return; 375 case Iop_CmpNEZ8x4: vex_printf("CmpNEZ8x4"); return; 376 377 case Iop_CmpF64: vex_printf("CmpF64"); return; 378 379 case Iop_F64toI16S: vex_printf("F64toI16S"); return; 380 case Iop_F64toI32S: vex_printf("F64toI32S"); return; 381 case Iop_F64toI64S: vex_printf("F64toI64S"); return; 382 case Iop_F64toI64U: vex_printf("F64toI64U"); return; 383 case Iop_F32toI32U: vex_printf("F32toI32U"); return; 384 case Iop_F32toI64U: vex_printf("F32toI64U"); return; 385 386 case Iop_F64toI32U: vex_printf("F64toI32U"); return; 387 388 case Iop_I32StoF64: vex_printf("I32StoF64"); return; 389 case Iop_I64StoF64: vex_printf("I64StoF64"); return; 390 case Iop_I64UtoF64: vex_printf("I64UtoF64"); return; 391 case Iop_I32UtoF32: vex_printf("I32UtoF32"); return; 392 case Iop_I64UtoF32: vex_printf("I64UtoF32"); return; 393 394 case Iop_I32UtoF64: vex_printf("I32UtoF64"); return; 395 396 case Iop_F32toF64: vex_printf("F32toF64"); return; 397 case Iop_F64toF32: vex_printf("F64toF32"); return; 398 399 case Iop_RoundF128toInt: vex_printf("RoundF128toInt"); return; 400 case Iop_RoundF64toInt: vex_printf("RoundF64toInt"); return; 401 case Iop_RoundF32toInt: vex_printf("RoundF32toInt"); return; 402 case Iop_RoundF64toF32: vex_printf("RoundF64toF32"); return; 403 404 case Iop_ReinterpF64asI64: vex_printf("ReinterpF64asI64"); return; 405 case Iop_ReinterpI64asF64: vex_printf("ReinterpI64asF64"); return; 406 case Iop_ReinterpF32asI32: vex_printf("ReinterpF32asI32"); return; 407 case Iop_ReinterpI32asF32: vex_printf("ReinterpI32asF32"); return; 408 409 case Iop_I32UtoFx4: vex_printf("I32UtoFx4"); return; 410 case Iop_I32StoFx4: vex_printf("I32StoFx4"); return; 411 412 case Iop_F32toF16x4: vex_printf("F32toF16x4"); return; 413 case Iop_F16toF32x4: vex_printf("F16toF32x4"); return; 414 415 case Iop_RSqrtEst32Fx4: vex_printf("RSqrtEst32Fx4"); return; 416 case Iop_RSqrtEst32Ux4: vex_printf("RSqrtEst32Ux4"); return; 417 case Iop_RSqrtEst32Fx2: vex_printf("RSqrtEst32Fx2"); return; 418 case Iop_RSqrtEst32Ux2: vex_printf("RSqrtEst32Ux2"); return; 419 420 case Iop_QFtoI32Ux4_RZ: vex_printf("QFtoI32Ux4_RZ"); return; 421 case Iop_QFtoI32Sx4_RZ: vex_printf("QFtoI32Sx4_RZ"); return; 422 423 case Iop_FtoI32Ux4_RZ: vex_printf("FtoI32Ux4_RZ"); return; 424 case Iop_FtoI32Sx4_RZ: vex_printf("FtoI32Sx4_RZ"); return; 425 426 case Iop_I32UtoFx2: vex_printf("I32UtoFx2"); return; 427 case Iop_I32StoFx2: vex_printf("I32StoFx2"); return; 428 429 case Iop_FtoI32Ux2_RZ: vex_printf("FtoI32Ux2_RZ"); return; 430 case Iop_FtoI32Sx2_RZ: vex_printf("FtoI32Sx2_RZ"); return; 431 432 case Iop_RoundF32x4_RM: vex_printf("RoundF32x4_RM"); return; 433 case Iop_RoundF32x4_RP: vex_printf("RoundF32x4_RP"); return; 434 case Iop_RoundF32x4_RN: vex_printf("RoundF32x4_RN"); return; 435 case Iop_RoundF32x4_RZ: vex_printf("RoundF32x4_RZ"); return; 436 437 case Iop_Abs8x8: vex_printf("Abs8x8"); return; 438 case Iop_Abs16x4: vex_printf("Abs16x4"); return; 439 case Iop_Abs32x2: vex_printf("Abs32x2"); return; 440 case Iop_Add8x8: vex_printf("Add8x8"); return; 441 case Iop_Add16x4: vex_printf("Add16x4"); return; 442 case Iop_Add32x2: vex_printf("Add32x2"); return; 443 case Iop_QAdd8Ux8: vex_printf("QAdd8Ux8"); return; 444 case Iop_QAdd16Ux4: vex_printf("QAdd16Ux4"); return; 445 case Iop_QAdd32Ux2: vex_printf("QAdd32Ux2"); return; 446 case Iop_QAdd64Ux1: vex_printf("QAdd64Ux1"); return; 447 case Iop_QAdd8Sx8: vex_printf("QAdd8Sx8"); return; 448 case Iop_QAdd16Sx4: vex_printf("QAdd16Sx4"); return; 449 case Iop_QAdd32Sx2: vex_printf("QAdd32Sx2"); return; 450 case Iop_QAdd64Sx1: vex_printf("QAdd64Sx1"); return; 451 case Iop_PwAdd8x8: vex_printf("PwAdd8x8"); return; 452 case Iop_PwAdd16x4: vex_printf("PwAdd16x4"); return; 453 case Iop_PwAdd32x2: vex_printf("PwAdd32x2"); return; 454 case Iop_PwAdd32Fx2: vex_printf("PwAdd32Fx2"); return; 455 case Iop_PwAddL8Ux8: vex_printf("PwAddL8Ux8"); return; 456 case Iop_PwAddL16Ux4: vex_printf("PwAddL16Ux4"); return; 457 case Iop_PwAddL32Ux2: vex_printf("PwAddL32Ux2"); return; 458 case Iop_PwAddL8Sx8: vex_printf("PwAddL8Sx8"); return; 459 case Iop_PwAddL16Sx4: vex_printf("PwAddL16Sx4"); return; 460 case Iop_PwAddL32Sx2: vex_printf("PwAddL32Sx2"); return; 461 case Iop_Sub8x8: vex_printf("Sub8x8"); return; 462 case Iop_Sub16x4: vex_printf("Sub16x4"); return; 463 case Iop_Sub32x2: vex_printf("Sub32x2"); return; 464 case Iop_QSub8Ux8: vex_printf("QSub8Ux8"); return; 465 case Iop_QSub16Ux4: vex_printf("QSub16Ux4"); return; 466 case Iop_QSub32Ux2: vex_printf("QSub32Ux2"); return; 467 case Iop_QSub64Ux1: vex_printf("QSub64Ux1"); return; 468 case Iop_QSub8Sx8: vex_printf("QSub8Sx8"); return; 469 case Iop_QSub16Sx4: vex_printf("QSub16Sx4"); return; 470 case Iop_QSub32Sx2: vex_printf("QSub32Sx2"); return; 471 case Iop_QSub64Sx1: vex_printf("QSub64Sx1"); return; 472 case Iop_Mul8x8: vex_printf("Mul8x8"); return; 473 case Iop_Mul16x4: vex_printf("Mul16x4"); return; 474 case Iop_Mul32x2: vex_printf("Mul32x2"); return; 475 case Iop_Mul32Fx2: vex_printf("Mul32Fx2"); return; 476 case Iop_PolynomialMul8x8: vex_printf("PolynomialMul8x8"); return; 477 case Iop_MulHi16Ux4: vex_printf("MulHi16Ux4"); return; 478 case Iop_MulHi16Sx4: vex_printf("MulHi16Sx4"); return; 479 case Iop_QDMulHi16Sx4: vex_printf("QDMulHi16Sx4"); return; 480 case Iop_QDMulHi32Sx2: vex_printf("QDMulHi32Sx2"); return; 481 case Iop_QRDMulHi16Sx4: vex_printf("QRDMulHi16Sx4"); return; 482 case Iop_QRDMulHi32Sx2: vex_printf("QRDMulHi32Sx2"); return; 483 case Iop_QDMull16Sx4: vex_printf("QDMull16Sx4"); return; 484 case Iop_QDMull32Sx2: vex_printf("QDMull32Sx2"); return; 485 case Iop_Avg8Ux8: vex_printf("Avg8Ux8"); return; 486 case Iop_Avg16Ux4: vex_printf("Avg16Ux4"); return; 487 case Iop_Max8Sx8: vex_printf("Max8Sx8"); return; 488 case Iop_Max16Sx4: vex_printf("Max16Sx4"); return; 489 case Iop_Max32Sx2: vex_printf("Max32Sx2"); return; 490 case Iop_Max8Ux8: vex_printf("Max8Ux8"); return; 491 case Iop_Max16Ux4: vex_printf("Max16Ux4"); return; 492 case Iop_Max32Ux2: vex_printf("Max32Ux2"); return; 493 case Iop_Min8Sx8: vex_printf("Min8Sx8"); return; 494 case Iop_Min16Sx4: vex_printf("Min16Sx4"); return; 495 case Iop_Min32Sx2: vex_printf("Min32Sx2"); return; 496 case Iop_Min8Ux8: vex_printf("Min8Ux8"); return; 497 case Iop_Min16Ux4: vex_printf("Min16Ux4"); return; 498 case Iop_Min32Ux2: vex_printf("Min32Ux2"); return; 499 case Iop_PwMax8Sx8: vex_printf("PwMax8Sx8"); return; 500 case Iop_PwMax16Sx4: vex_printf("PwMax16Sx4"); return; 501 case Iop_PwMax32Sx2: vex_printf("PwMax32Sx2"); return; 502 case Iop_PwMax8Ux8: vex_printf("PwMax8Ux8"); return; 503 case Iop_PwMax16Ux4: vex_printf("PwMax16Ux4"); return; 504 case Iop_PwMax32Ux2: vex_printf("PwMax32Ux2"); return; 505 case Iop_PwMin8Sx8: vex_printf("PwMin8Sx8"); return; 506 case Iop_PwMin16Sx4: vex_printf("PwMin16Sx4"); return; 507 case Iop_PwMin32Sx2: vex_printf("PwMin32Sx2"); return; 508 case Iop_PwMin8Ux8: vex_printf("PwMin8Ux8"); return; 509 case Iop_PwMin16Ux4: vex_printf("PwMin16Ux4"); return; 510 case Iop_PwMin32Ux2: vex_printf("PwMin32Ux2"); return; 511 case Iop_CmpEQ8x8: vex_printf("CmpEQ8x8"); return; 512 case Iop_CmpEQ16x4: vex_printf("CmpEQ16x4"); return; 513 case Iop_CmpEQ32x2: vex_printf("CmpEQ32x2"); return; 514 case Iop_CmpGT8Ux8: vex_printf("CmpGT8Ux8"); return; 515 case Iop_CmpGT16Ux4: vex_printf("CmpGT16Ux4"); return; 516 case Iop_CmpGT32Ux2: vex_printf("CmpGT32Ux2"); return; 517 case Iop_CmpGT8Sx8: vex_printf("CmpGT8Sx8"); return; 518 case Iop_CmpGT16Sx4: vex_printf("CmpGT16Sx4"); return; 519 case Iop_CmpGT32Sx2: vex_printf("CmpGT32Sx2"); return; 520 case Iop_Cnt8x8: vex_printf("Cnt8x8"); return; 521 case Iop_Clz8x8: vex_printf("Clz8x8"); return; 522 case Iop_Clz16x4: vex_printf("Clz16x4"); return; 523 case Iop_Clz32x2: vex_printf("Clz32x2"); return; 524 case Iop_Cls8x8: vex_printf("Cls8x8"); return; 525 case Iop_Cls16x4: vex_printf("Cls16x4"); return; 526 case Iop_Cls32x2: vex_printf("Cls32x2"); return; 527 case Iop_ShlN8x8: vex_printf("ShlN8x8"); return; 528 case Iop_ShlN16x4: vex_printf("ShlN16x4"); return; 529 case Iop_ShlN32x2: vex_printf("ShlN32x2"); return; 530 case Iop_ShrN8x8: vex_printf("ShrN8x8"); return; 531 case Iop_ShrN16x4: vex_printf("ShrN16x4"); return; 532 case Iop_ShrN32x2: vex_printf("ShrN32x2"); return; 533 case Iop_SarN8x8: vex_printf("SarN8x8"); return; 534 case Iop_SarN16x4: vex_printf("SarN16x4"); return; 535 case Iop_SarN32x2: vex_printf("SarN32x2"); return; 536 case Iop_QNarrowBin16Sto8Ux8: vex_printf("QNarrowBin16Sto8Ux8"); return; 537 case Iop_QNarrowBin16Sto8Sx8: vex_printf("QNarrowBin16Sto8Sx8"); return; 538 case Iop_QNarrowBin32Sto16Sx4: vex_printf("QNarrowBin32Sto16Sx4"); return; 539 case Iop_QNarrowBin64Sto32Sx4: vex_printf("QNarrowBin64Sto32Sx4"); return; 540 case Iop_QNarrowBin64Uto32Ux4: vex_printf("QNarrowBin64Uto32Ux4"); return; 541 case Iop_NarrowBin16to8x8: vex_printf("NarrowBin16to8x8"); return; 542 case Iop_NarrowBin32to16x4: vex_printf("NarrowBin32to16x4"); return; 543 case Iop_NarrowBin64to32x4: vex_printf("NarrowBin64to32x4"); return; 544 case Iop_InterleaveHI8x8: vex_printf("InterleaveHI8x8"); return; 545 case Iop_InterleaveHI16x4: vex_printf("InterleaveHI16x4"); return; 546 case Iop_InterleaveHI32x2: vex_printf("InterleaveHI32x2"); return; 547 case Iop_InterleaveLO8x8: vex_printf("InterleaveLO8x8"); return; 548 case Iop_InterleaveLO16x4: vex_printf("InterleaveLO16x4"); return; 549 case Iop_InterleaveLO32x2: vex_printf("InterleaveLO32x2"); return; 550 case Iop_CatOddLanes8x8: vex_printf("CatOddLanes8x8"); return; 551 case Iop_CatOddLanes16x4: vex_printf("CatOddLanes16x4"); return; 552 case Iop_CatEvenLanes8x8: vex_printf("CatEvenLanes8x8"); return; 553 case Iop_CatEvenLanes16x4: vex_printf("CatEvenLanes16x4"); return; 554 case Iop_InterleaveOddLanes8x8: vex_printf("InterleaveOddLanes8x8"); return; 555 case Iop_InterleaveOddLanes16x4: vex_printf("InterleaveOddLanes16x4"); return; 556 case Iop_InterleaveEvenLanes8x8: vex_printf("InterleaveEvenLanes8x8"); return; 557 case Iop_InterleaveEvenLanes16x4: vex_printf("InterleaveEvenLanes16x4"); return; 558 case Iop_Shl8x8: vex_printf("Shl8x8"); return; 559 case Iop_Shl16x4: vex_printf("Shl16x4"); return; 560 case Iop_Shl32x2: vex_printf("Shl32x2"); return; 561 case Iop_Shr8x8: vex_printf("Shr8x8"); return; 562 case Iop_Shr16x4: vex_printf("Shr16x4"); return; 563 case Iop_Shr32x2: vex_printf("Shr32x2"); return; 564 case Iop_QShl8x8: vex_printf("QShl8x8"); return; 565 case Iop_QShl16x4: vex_printf("QShl16x4"); return; 566 case Iop_QShl32x2: vex_printf("QShl32x2"); return; 567 case Iop_QShl64x1: vex_printf("QShl64x1"); return; 568 case Iop_QSal8x8: vex_printf("QSal8x8"); return; 569 case Iop_QSal16x4: vex_printf("QSal16x4"); return; 570 case Iop_QSal32x2: vex_printf("QSal32x2"); return; 571 case Iop_QSal64x1: vex_printf("QSal64x1"); return; 572 case Iop_QShlNsatUU8x8: vex_printf("QShlNsatUU8x8"); return; 573 case Iop_QShlNsatUU16x4: vex_printf("QShlNsatUU16x4"); return; 574 case Iop_QShlNsatUU32x2: vex_printf("QShlNsatUU32x2"); return; 575 case Iop_QShlNsatUU64x1: vex_printf("QShlNsatUU64x1"); return; 576 case Iop_QShlNsatSU8x8: vex_printf("QShlNsatSU8x8"); return; 577 case Iop_QShlNsatSU16x4: vex_printf("QShlNsatSU16x4"); return; 578 case Iop_QShlNsatSU32x2: vex_printf("QShlNsatSU32x2"); return; 579 case Iop_QShlNsatSU64x1: vex_printf("QShlNsatSU64x1"); return; 580 case Iop_QShlNsatSS8x8: vex_printf("QShlNsatSS8x8"); return; 581 case Iop_QShlNsatSS16x4: vex_printf("QShlNsatSS16x4"); return; 582 case Iop_QShlNsatSS32x2: vex_printf("QShlNsatSS32x2"); return; 583 case Iop_QShlNsatSS64x1: vex_printf("QShlNsatSS64x1"); return; 584 case Iop_Sar8x8: vex_printf("Sar8x8"); return; 585 case Iop_Sar16x4: vex_printf("Sar16x4"); return; 586 case Iop_Sar32x2: vex_printf("Sar32x2"); return; 587 case Iop_Sal8x8: vex_printf("Sal8x8"); return; 588 case Iop_Sal16x4: vex_printf("Sal16x4"); return; 589 case Iop_Sal32x2: vex_printf("Sal32x2"); return; 590 case Iop_Sal64x1: vex_printf("Sal64x1"); return; 591 case Iop_Perm8x8: vex_printf("Perm8x8"); return; 592 case Iop_Reverse8sIn16_x4: vex_printf("Reverse8sIn16_x4"); return; 593 case Iop_Reverse8sIn32_x2: vex_printf("Reverse8sIn32_x2"); return; 594 case Iop_Reverse16sIn32_x2: vex_printf("Reverse16sIn32_x2"); return; 595 case Iop_Reverse8sIn64_x1: vex_printf("Reverse8sIn64_x1"); return; 596 case Iop_Reverse16sIn64_x1: vex_printf("Reverse16sIn64_x1"); return; 597 case Iop_Reverse32sIn64_x1: vex_printf("Reverse32sIn64_x1"); return; 598 case Iop_Abs32Fx2: vex_printf("Abs32Fx2"); return; 599 case Iop_GetMSBs8x8: vex_printf("GetMSBs8x8"); return; 600 case Iop_GetMSBs8x16: vex_printf("GetMSBs8x16"); return; 601 602 case Iop_CmpNEZ32x2: vex_printf("CmpNEZ32x2"); return; 603 case Iop_CmpNEZ16x4: vex_printf("CmpNEZ16x4"); return; 604 case Iop_CmpNEZ8x8: vex_printf("CmpNEZ8x8"); return; 605 606 case Iop_Add32Fx4: vex_printf("Add32Fx4"); return; 607 case Iop_Add32Fx2: vex_printf("Add32Fx2"); return; 608 case Iop_Add32F0x4: vex_printf("Add32F0x4"); return; 609 case Iop_Add64Fx2: vex_printf("Add64Fx2"); return; 610 case Iop_Add64F0x2: vex_printf("Add64F0x2"); return; 611 612 case Iop_Div32Fx4: vex_printf("Div32Fx4"); return; 613 case Iop_Div32F0x4: vex_printf("Div32F0x4"); return; 614 case Iop_Div64Fx2: vex_printf("Div64Fx2"); return; 615 case Iop_Div64F0x2: vex_printf("Div64F0x2"); return; 616 617 case Iop_Max32Fx8: vex_printf("Max32Fx8"); return; 618 case Iop_Max32Fx4: vex_printf("Max32Fx4"); return; 619 case Iop_Max32Fx2: vex_printf("Max32Fx2"); return; 620 case Iop_PwMax32Fx4: vex_printf("PwMax32Fx4"); return; 621 case Iop_PwMax32Fx2: vex_printf("PwMax32Fx2"); return; 622 case Iop_Max32F0x4: vex_printf("Max32F0x4"); return; 623 case Iop_Max64Fx4: vex_printf("Max64Fx4"); return; 624 case Iop_Max64Fx2: vex_printf("Max64Fx2"); return; 625 case Iop_Max64F0x2: vex_printf("Max64F0x2"); return; 626 627 case Iop_Min32Fx8: vex_printf("Min32Fx8"); return; 628 case Iop_Min32Fx4: vex_printf("Min32Fx4"); return; 629 case Iop_Min32Fx2: vex_printf("Min32Fx2"); return; 630 case Iop_PwMin32Fx4: vex_printf("PwMin32Fx4"); return; 631 case Iop_PwMin32Fx2: vex_printf("PwMin32Fx2"); return; 632 case Iop_Min32F0x4: vex_printf("Min32F0x4"); return; 633 case Iop_Min64Fx4: vex_printf("Min64Fx4"); return; 634 case Iop_Min64Fx2: vex_printf("Min64Fx2"); return; 635 case Iop_Min64F0x2: vex_printf("Min64F0x2"); return; 636 637 case Iop_Mul32Fx4: vex_printf("Mul32Fx4"); return; 638 case Iop_Mul32F0x4: vex_printf("Mul32F0x4"); return; 639 case Iop_Mul64Fx2: vex_printf("Mul64Fx2"); return; 640 case Iop_Mul64F0x2: vex_printf("Mul64F0x2"); return; 641 642 case Iop_RecipEst32Ux2: vex_printf("RecipEst32Ux2"); return; 643 case Iop_RecipEst32Fx2: vex_printf("RecipEst32Fx2"); return; 644 case Iop_RecipEst32Fx4: vex_printf("RecipEst32Fx4"); return; 645 case Iop_RecipEst32Fx8: vex_printf("RecipEst32Fx8"); return; 646 case Iop_RecipEst32Ux4: vex_printf("RecipEst32Ux4"); return; 647 case Iop_RecipEst32F0x4: vex_printf("RecipEst32F0x4"); return; 648 case Iop_RecipStep32Fx2: vex_printf("RecipStep32Fx2"); return; 649 case Iop_RecipStep32Fx4: vex_printf("RecipStep32Fx4"); return; 650 case Iop_RecipEst64Fx2: vex_printf("RecipEst64Fx2"); return; 651 case Iop_RecipStep64Fx2: vex_printf("RecipStep64Fx2"); return; 652 653 case Iop_Abs32Fx4: vex_printf("Abs32Fx4"); return; 654 case Iop_Abs64Fx2: vex_printf("Abs64Fx2"); return; 655 case Iop_RSqrtStep32Fx4: vex_printf("RSqrtStep32Fx4"); return; 656 case Iop_RSqrtStep64Fx2: vex_printf("RSqrtStep64Fx2"); return; 657 case Iop_RSqrtStep32Fx2: vex_printf("RSqrtStep32Fx2"); return; 658 case Iop_RSqrtEst64Fx2: vex_printf("RSqrtEst64Fx2"); return; 659 660 case Iop_RSqrtEst32F0x4: vex_printf("RSqrtEst32F0x4"); return; 661 case Iop_RSqrtEst32Fx8: vex_printf("RSqrtEst32Fx8"); return; 662 663 case Iop_Sqrt32Fx4: vex_printf("Sqrt32Fx4"); return; 664 case Iop_Sqrt32F0x4: vex_printf("Sqrt32F0x4"); return; 665 case Iop_Sqrt64Fx2: vex_printf("Sqrt64Fx2"); return; 666 case Iop_Sqrt64F0x2: vex_printf("Sqrt64F0x2"); return; 667 case Iop_Sqrt32Fx8: vex_printf("Sqrt32Fx8"); return; 668 case Iop_Sqrt64Fx4: vex_printf("Sqrt64Fx4"); return; 669 670 case Iop_Sub32Fx4: vex_printf("Sub32Fx4"); return; 671 case Iop_Sub32Fx2: vex_printf("Sub32Fx2"); return; 672 case Iop_Sub32F0x4: vex_printf("Sub32F0x4"); return; 673 case Iop_Sub64Fx2: vex_printf("Sub64Fx2"); return; 674 case Iop_Sub64F0x2: vex_printf("Sub64F0x2"); return; 675 676 case Iop_CmpEQ32Fx4: vex_printf("CmpEQ32Fx4"); return; 677 case Iop_CmpLT32Fx4: vex_printf("CmpLT32Fx4"); return; 678 case Iop_CmpLE32Fx4: vex_printf("CmpLE32Fx4"); return; 679 case Iop_CmpGT32Fx4: vex_printf("CmpGT32Fx4"); return; 680 case Iop_CmpGE32Fx4: vex_printf("CmpGE32Fx4"); return; 681 case Iop_CmpUN32Fx4: vex_printf("CmpUN32Fx4"); return; 682 case Iop_CmpEQ64Fx2: vex_printf("CmpEQ64Fx2"); return; 683 case Iop_CmpLT64Fx2: vex_printf("CmpLT64Fx2"); return; 684 case Iop_CmpLE64Fx2: vex_printf("CmpLE64Fx2"); return; 685 case Iop_CmpUN64Fx2: vex_printf("CmpUN64Fx2"); return; 686 case Iop_CmpGT32Fx2: vex_printf("CmpGT32Fx2"); return; 687 case Iop_CmpEQ32Fx2: vex_printf("CmpEQ32Fx2"); return; 688 case Iop_CmpGE32Fx2: vex_printf("CmpGE32Fx2"); return; 689 690 case Iop_CmpEQ32F0x4: vex_printf("CmpEQ32F0x4"); return; 691 case Iop_CmpLT32F0x4: vex_printf("CmpLT32F0x4"); return; 692 case Iop_CmpLE32F0x4: vex_printf("CmpLE32F0x4"); return; 693 case Iop_CmpUN32F0x4: vex_printf("CmpUN32F0x4"); return; 694 case Iop_CmpEQ64F0x2: vex_printf("CmpEQ64F0x2"); return; 695 case Iop_CmpLT64F0x2: vex_printf("CmpLT64F0x2"); return; 696 case Iop_CmpLE64F0x2: vex_printf("CmpLE64F0x2"); return; 697 case Iop_CmpUN64F0x2: vex_printf("CmpUN64F0x2"); return; 698 699 case Iop_Neg64Fx2: vex_printf("Neg64Fx2"); return; 700 case Iop_Neg32Fx4: vex_printf("Neg32Fx4"); return; 701 case Iop_Neg32Fx2: vex_printf("Neg32Fx2"); return; 702 703 case Iop_V128to64: vex_printf("V128to64"); return; 704 case Iop_V128HIto64: vex_printf("V128HIto64"); return; 705 case Iop_64HLtoV128: vex_printf("64HLtoV128"); return; 706 707 case Iop_64UtoV128: vex_printf("64UtoV128"); return; 708 case Iop_SetV128lo64: vex_printf("SetV128lo64"); return; 709 710 case Iop_ZeroHI64ofV128: vex_printf("ZeroHI64ofV128"); return; 711 case Iop_ZeroHI96ofV128: vex_printf("ZeroHI96ofV128"); return; 712 case Iop_ZeroHI112ofV128: vex_printf("ZeroHI112ofV128"); return; 713 case Iop_ZeroHI120ofV128: vex_printf("ZeroHI120ofV128"); return; 714 715 case Iop_32UtoV128: vex_printf("32UtoV128"); return; 716 case Iop_V128to32: vex_printf("V128to32"); return; 717 case Iop_SetV128lo32: vex_printf("SetV128lo32"); return; 718 719 case Iop_Dup8x16: vex_printf("Dup8x16"); return; 720 case Iop_Dup16x8: vex_printf("Dup16x8"); return; 721 case Iop_Dup32x4: vex_printf("Dup32x4"); return; 722 case Iop_Dup8x8: vex_printf("Dup8x8"); return; 723 case Iop_Dup16x4: vex_printf("Dup16x4"); return; 724 case Iop_Dup32x2: vex_printf("Dup32x2"); return; 725 726 case Iop_NotV128: vex_printf("NotV128"); return; 727 case Iop_AndV128: vex_printf("AndV128"); return; 728 case Iop_OrV128: vex_printf("OrV128"); return; 729 case Iop_XorV128: vex_printf("XorV128"); return; 730 731 case Iop_CmpNEZ8x16: vex_printf("CmpNEZ8x16"); return; 732 case Iop_CmpNEZ16x8: vex_printf("CmpNEZ16x8"); return; 733 case Iop_CmpNEZ32x4: vex_printf("CmpNEZ32x4"); return; 734 case Iop_CmpNEZ64x2: vex_printf("CmpNEZ64x2"); return; 735 736 case Iop_Abs8x16: vex_printf("Abs8x16"); return; 737 case Iop_Abs16x8: vex_printf("Abs16x8"); return; 738 case Iop_Abs32x4: vex_printf("Abs32x4"); return; 739 case Iop_Abs64x2: vex_printf("Abs64x2"); return; 740 741 case Iop_Add8x16: vex_printf("Add8x16"); return; 742 case Iop_Add16x8: vex_printf("Add16x8"); return; 743 case Iop_Add32x4: vex_printf("Add32x4"); return; 744 case Iop_Add64x2: vex_printf("Add64x2"); return; 745 case Iop_QAdd8Ux16: vex_printf("QAdd8Ux16"); return; 746 case Iop_QAdd16Ux8: vex_printf("QAdd16Ux8"); return; 747 case Iop_QAdd32Ux4: vex_printf("QAdd32Ux4"); return; 748 case Iop_QAdd8Sx16: vex_printf("QAdd8Sx16"); return; 749 case Iop_QAdd16Sx8: vex_printf("QAdd16Sx8"); return; 750 case Iop_QAdd32Sx4: vex_printf("QAdd32Sx4"); return; 751 case Iop_QAdd64Ux2: vex_printf("QAdd64Ux2"); return; 752 case Iop_QAdd64Sx2: vex_printf("QAdd64Sx2"); return; 753 754 case Iop_QAddExtUSsatSS8x16: vex_printf("QAddExtUSsatSS8x16"); return; 755 case Iop_QAddExtUSsatSS16x8: vex_printf("QAddExtUSsatSS16x8"); return; 756 case Iop_QAddExtUSsatSS32x4: vex_printf("QAddExtUSsatSS32x4"); return; 757 case Iop_QAddExtUSsatSS64x2: vex_printf("QAddExtUSsatSS64x2"); return; 758 case Iop_QAddExtSUsatUU8x16: vex_printf("QAddExtSUsatUU8x16"); return; 759 case Iop_QAddExtSUsatUU16x8: vex_printf("QAddExtSUsatUU16x8"); return; 760 case Iop_QAddExtSUsatUU32x4: vex_printf("QAddExtSUsatUU32x4"); return; 761 case Iop_QAddExtSUsatUU64x2: vex_printf("QAddExtSUsatUU64x2"); return; 762 763 case Iop_PwAdd8x16: vex_printf("PwAdd8x16"); return; 764 case Iop_PwAdd16x8: vex_printf("PwAdd16x8"); return; 765 case Iop_PwAdd32x4: vex_printf("PwAdd32x4"); return; 766 case Iop_PwAddL8Ux16: vex_printf("PwAddL8Ux16"); return; 767 case Iop_PwAddL16Ux8: vex_printf("PwAddL16Ux8"); return; 768 case Iop_PwAddL32Ux4: vex_printf("PwAddL32Ux4"); return; 769 case Iop_PwAddL8Sx16: vex_printf("PwAddL8Sx16"); return; 770 case Iop_PwAddL16Sx8: vex_printf("PwAddL16Sx8"); return; 771 case Iop_PwAddL32Sx4: vex_printf("PwAddL32Sx4"); return; 772 773 case Iop_Sub8x16: vex_printf("Sub8x16"); return; 774 case Iop_Sub16x8: vex_printf("Sub16x8"); return; 775 case Iop_Sub32x4: vex_printf("Sub32x4"); return; 776 case Iop_Sub64x2: vex_printf("Sub64x2"); return; 777 case Iop_QSub8Ux16: vex_printf("QSub8Ux16"); return; 778 case Iop_QSub16Ux8: vex_printf("QSub16Ux8"); return; 779 case Iop_QSub32Ux4: vex_printf("QSub32Ux4"); return; 780 case Iop_QSub8Sx16: vex_printf("QSub8Sx16"); return; 781 case Iop_QSub16Sx8: vex_printf("QSub16Sx8"); return; 782 case Iop_QSub32Sx4: vex_printf("QSub32Sx4"); return; 783 case Iop_QSub64Ux2: vex_printf("QSub64Ux2"); return; 784 case Iop_QSub64Sx2: vex_printf("QSub64Sx2"); return; 785 786 case Iop_Mul8x16: vex_printf("Mul8x16"); return; 787 case Iop_Mul16x8: vex_printf("Mul16x8"); return; 788 case Iop_Mul32x4: vex_printf("Mul32x4"); return; 789 case Iop_Mull8Ux8: vex_printf("Mull8Ux8"); return; 790 case Iop_Mull8Sx8: vex_printf("Mull8Sx8"); return; 791 case Iop_Mull16Ux4: vex_printf("Mull16Ux4"); return; 792 case Iop_Mull16Sx4: vex_printf("Mull16Sx4"); return; 793 case Iop_Mull32Ux2: vex_printf("Mull32Ux2"); return; 794 case Iop_Mull32Sx2: vex_printf("Mull32Sx2"); return; 795 case Iop_PolynomialMul8x16: vex_printf("PolynomialMul8x16"); return; 796 case Iop_PolynomialMull8x8: vex_printf("PolynomialMull8x8"); return; 797 case Iop_MulHi16Ux8: vex_printf("MulHi16Ux8"); return; 798 case Iop_MulHi32Ux4: vex_printf("MulHi32Ux4"); return; 799 case Iop_MulHi16Sx8: vex_printf("MulHi16Sx8"); return; 800 case Iop_MulHi32Sx4: vex_printf("MulHi32Sx4"); return; 801 case Iop_QDMulHi16Sx8: vex_printf("QDMulHi16Sx8"); return; 802 case Iop_QDMulHi32Sx4: vex_printf("QDMulHi32Sx4"); return; 803 case Iop_QRDMulHi16Sx8: vex_printf("QRDMulHi16Sx8"); return; 804 case Iop_QRDMulHi32Sx4: vex_printf("QRDMulHi32Sx4"); return; 805 806 case Iop_MullEven8Ux16: vex_printf("MullEven8Ux16"); return; 807 case Iop_MullEven16Ux8: vex_printf("MullEven16Ux8"); return; 808 case Iop_MullEven32Ux4: vex_printf("MullEven32Ux4"); return; 809 case Iop_MullEven8Sx16: vex_printf("MullEven8Sx16"); return; 810 case Iop_MullEven16Sx8: vex_printf("MullEven16Sx8"); return; 811 case Iop_MullEven32Sx4: vex_printf("MullEven32Sx4"); return; 812 813 case Iop_PolynomialMulAdd8x16: 814 vex_printf("PolynomialMulAdd8x16"); return; 815 case Iop_PolynomialMulAdd16x8: 816 vex_printf("PolynomialMulAdd16x8"); return; 817 case Iop_PolynomialMulAdd32x4: 818 vex_printf("PolynomialMulAdd32x4"); return; 819 case Iop_PolynomialMulAdd64x2: 820 vex_printf("PolynomialMulAdd64x2"); return; 821 822 case Iop_Avg8Ux16: vex_printf("Avg8Ux16"); return; 823 case Iop_Avg16Ux8: vex_printf("Avg16Ux8"); return; 824 case Iop_Avg32Ux4: vex_printf("Avg32Ux4"); return; 825 case Iop_Avg8Sx16: vex_printf("Avg8Sx16"); return; 826 case Iop_Avg16Sx8: vex_printf("Avg16Sx8"); return; 827 case Iop_Avg32Sx4: vex_printf("Avg32Sx4"); return; 828 829 case Iop_Max8Sx16: vex_printf("Max8Sx16"); return; 830 case Iop_Max16Sx8: vex_printf("Max16Sx8"); return; 831 case Iop_Max32Sx4: vex_printf("Max32Sx4"); return; 832 case Iop_Max64Sx2: vex_printf("Max64Sx2"); return; 833 case Iop_Max8Ux16: vex_printf("Max8Ux16"); return; 834 case Iop_Max16Ux8: vex_printf("Max16Ux8"); return; 835 case Iop_Max32Ux4: vex_printf("Max32Ux4"); return; 836 case Iop_Max64Ux2: vex_printf("Max64Ux2"); return; 837 838 case Iop_Min8Sx16: vex_printf("Min8Sx16"); return; 839 case Iop_Min16Sx8: vex_printf("Min16Sx8"); return; 840 case Iop_Min32Sx4: vex_printf("Min32Sx4"); return; 841 case Iop_Min64Sx2: vex_printf("Min64Sx2"); return; 842 case Iop_Min8Ux16: vex_printf("Min8Ux16"); return; 843 case Iop_Min16Ux8: vex_printf("Min16Ux8"); return; 844 case Iop_Min32Ux4: vex_printf("Min32Ux4"); return; 845 case Iop_Min64Ux2: vex_printf("Min64Ux2"); return; 846 847 case Iop_CmpEQ8x16: vex_printf("CmpEQ8x16"); return; 848 case Iop_CmpEQ16x8: vex_printf("CmpEQ16x8"); return; 849 case Iop_CmpEQ32x4: vex_printf("CmpEQ32x4"); return; 850 case Iop_CmpEQ64x2: vex_printf("CmpEQ64x2"); return; 851 case Iop_CmpGT8Sx16: vex_printf("CmpGT8Sx16"); return; 852 case Iop_CmpGT16Sx8: vex_printf("CmpGT16Sx8"); return; 853 case Iop_CmpGT32Sx4: vex_printf("CmpGT32Sx4"); return; 854 case Iop_CmpGT64Sx2: vex_printf("CmpGT64Sx2"); return; 855 case Iop_CmpGT8Ux16: vex_printf("CmpGT8Ux16"); return; 856 case Iop_CmpGT16Ux8: vex_printf("CmpGT16Ux8"); return; 857 case Iop_CmpGT32Ux4: vex_printf("CmpGT32Ux4"); return; 858 case Iop_CmpGT64Ux2: vex_printf("CmpGT64Ux2"); return; 859 860 case Iop_Cnt8x16: vex_printf("Cnt8x16"); return; 861 case Iop_Clz8x16: vex_printf("Clz8x16"); return; 862 case Iop_Clz16x8: vex_printf("Clz16x8"); return; 863 case Iop_Clz32x4: vex_printf("Clz32x4"); return; 864 case Iop_Clz64x2: vex_printf("Clz64x2"); return; 865 case Iop_Cls8x16: vex_printf("Cls8x16"); return; 866 case Iop_Cls16x8: vex_printf("Cls16x8"); return; 867 case Iop_Cls32x4: vex_printf("Cls32x4"); return; 868 869 case Iop_ShlV128: vex_printf("ShlV128"); return; 870 case Iop_ShrV128: vex_printf("ShrV128"); return; 871 872 case Iop_ShlN8x16: vex_printf("ShlN8x16"); return; 873 case Iop_ShlN16x8: vex_printf("ShlN16x8"); return; 874 case Iop_ShlN32x4: vex_printf("ShlN32x4"); return; 875 case Iop_ShlN64x2: vex_printf("ShlN64x2"); return; 876 case Iop_ShrN8x16: vex_printf("ShrN8x16"); return; 877 case Iop_ShrN16x8: vex_printf("ShrN16x8"); return; 878 case Iop_ShrN32x4: vex_printf("ShrN32x4"); return; 879 case Iop_ShrN64x2: vex_printf("ShrN64x2"); return; 880 case Iop_SarN8x16: vex_printf("SarN8x16"); return; 881 case Iop_SarN16x8: vex_printf("SarN16x8"); return; 882 case Iop_SarN32x4: vex_printf("SarN32x4"); return; 883 case Iop_SarN64x2: vex_printf("SarN64x2"); return; 884 885 case Iop_Shl8x16: vex_printf("Shl8x16"); return; 886 case Iop_Shl16x8: vex_printf("Shl16x8"); return; 887 case Iop_Shl32x4: vex_printf("Shl32x4"); return; 888 case Iop_Shl64x2: vex_printf("Shl64x2"); return; 889 case Iop_QSal8x16: vex_printf("QSal8x16"); return; 890 case Iop_QSal16x8: vex_printf("QSal16x8"); return; 891 case Iop_QSal32x4: vex_printf("QSal32x4"); return; 892 case Iop_QSal64x2: vex_printf("QSal64x2"); return; 893 case Iop_QShl8x16: vex_printf("QShl8x16"); return; 894 case Iop_QShl16x8: vex_printf("QShl16x8"); return; 895 case Iop_QShl32x4: vex_printf("QShl32x4"); return; 896 case Iop_QShl64x2: vex_printf("QShl64x2"); return; 897 case Iop_QShlNsatSS8x16: vex_printf("QShlNsatSS8x16"); return; 898 case Iop_QShlNsatSS16x8: vex_printf("QShlNsatSS16x8"); return; 899 case Iop_QShlNsatSS32x4: vex_printf("QShlNsatSS32x4"); return; 900 case Iop_QShlNsatSS64x2: vex_printf("QShlNsatSS64x2"); return; 901 case Iop_QShlNsatUU8x16: vex_printf("QShlNsatUU8x16"); return; 902 case Iop_QShlNsatUU16x8: vex_printf("QShlNsatUU16x8"); return; 903 case Iop_QShlNsatUU32x4: vex_printf("QShlNsatUU32x4"); return; 904 case Iop_QShlNsatUU64x2: vex_printf("QShlNsatUU64x2"); return; 905 case Iop_QShlNsatSU8x16: vex_printf("QShlNsatSU8x16"); return; 906 case Iop_QShlNsatSU16x8: vex_printf("QShlNsatSU16x8"); return; 907 case Iop_QShlNsatSU32x4: vex_printf("QShlNsatSU32x4"); return; 908 case Iop_QShlNsatSU64x2: vex_printf("QShlNsatSU64x2"); return; 909 case Iop_Shr8x16: vex_printf("Shr8x16"); return; 910 case Iop_Shr16x8: vex_printf("Shr16x8"); return; 911 case Iop_Shr32x4: vex_printf("Shr32x4"); return; 912 case Iop_Shr64x2: vex_printf("Shr64x2"); return; 913 case Iop_Sar8x16: vex_printf("Sar8x16"); return; 914 case Iop_Sar16x8: vex_printf("Sar16x8"); return; 915 case Iop_Sar32x4: vex_printf("Sar32x4"); return; 916 case Iop_Sar64x2: vex_printf("Sar64x2"); return; 917 case Iop_Sal8x16: vex_printf("Sal8x16"); return; 918 case Iop_Sal16x8: vex_printf("Sal16x8"); return; 919 case Iop_Sal32x4: vex_printf("Sal32x4"); return; 920 case Iop_Sal64x2: vex_printf("Sal64x2"); return; 921 case Iop_Rol8x16: vex_printf("Rol8x16"); return; 922 case Iop_Rol16x8: vex_printf("Rol16x8"); return; 923 case Iop_Rol32x4: vex_printf("Rol32x4"); return; 924 case Iop_Rol64x2: vex_printf("Rol64x2"); return; 925 926 case Iop_QandUQsh8x16: vex_printf("QandUQsh8x16"); return; 927 case Iop_QandUQsh16x8: vex_printf("QandUQsh16x8"); return; 928 case Iop_QandUQsh32x4: vex_printf("QandUQsh32x4"); return; 929 case Iop_QandUQsh64x2: vex_printf("QandUQsh64x2"); return; 930 case Iop_QandSQsh8x16: vex_printf("QandSQsh8x16"); return; 931 case Iop_QandSQsh16x8: vex_printf("QandSQsh16x8"); return; 932 case Iop_QandSQsh32x4: vex_printf("QandSQsh32x4"); return; 933 case Iop_QandSQsh64x2: vex_printf("QandSQsh64x2"); return; 934 case Iop_QandUQRsh8x16: vex_printf("QandUQRsh8x16"); return; 935 case Iop_QandUQRsh16x8: vex_printf("QandUQRsh16x8"); return; 936 case Iop_QandUQRsh32x4: vex_printf("QandUQRsh32x4"); return; 937 case Iop_QandUQRsh64x2: vex_printf("QandUQRsh64x2"); return; 938 case Iop_QandSQRsh8x16: vex_printf("QandSQRsh8x16"); return; 939 case Iop_QandSQRsh16x8: vex_printf("QandSQRsh16x8"); return; 940 case Iop_QandSQRsh32x4: vex_printf("QandSQRsh32x4"); return; 941 case Iop_QandSQRsh64x2: vex_printf("QandSQRsh64x2"); return; 942 943 case Iop_Sh8Sx16: vex_printf("Sh8Sx16"); return; 944 case Iop_Sh16Sx8: vex_printf("Sh16Sx8"); return; 945 case Iop_Sh32Sx4: vex_printf("Sh32Sx4"); return; 946 case Iop_Sh64Sx2: vex_printf("Sh64Sx2"); return; 947 case Iop_Sh8Ux16: vex_printf("Sh8Ux16"); return; 948 case Iop_Sh16Ux8: vex_printf("Sh16Ux8"); return; 949 case Iop_Sh32Ux4: vex_printf("Sh32Ux4"); return; 950 case Iop_Sh64Ux2: vex_printf("Sh64Ux2"); return; 951 case Iop_Rsh8Sx16: vex_printf("Rsh8Sx16"); return; 952 case Iop_Rsh16Sx8: vex_printf("Rsh16Sx8"); return; 953 case Iop_Rsh32Sx4: vex_printf("Rsh32Sx4"); return; 954 case Iop_Rsh64Sx2: vex_printf("Rsh64Sx2"); return; 955 case Iop_Rsh8Ux16: vex_printf("Rsh8Ux16"); return; 956 case Iop_Rsh16Ux8: vex_printf("Rsh16Ux8"); return; 957 case Iop_Rsh32Ux4: vex_printf("Rsh32Ux4"); return; 958 case Iop_Rsh64Ux2: vex_printf("Rsh64Ux2"); return; 959 960 case Iop_QandQShrNnarrow16Uto8Ux8: 961 vex_printf("QandQShrNnarrow16Uto8Ux8"); return; 962 case Iop_QandQShrNnarrow32Uto16Ux4: 963 vex_printf("QandQShrNnarrow32Uto16Ux4"); return; 964 case Iop_QandQShrNnarrow64Uto32Ux2: 965 vex_printf("QandQShrNnarrow64Uto32Ux2"); return; 966 case Iop_QandQSarNnarrow16Sto8Sx8: 967 vex_printf("QandQSarNnarrow16Sto8Sx8"); return; 968 case Iop_QandQSarNnarrow32Sto16Sx4: 969 vex_printf("QandQSarNnarrow32Sto16Sx4"); return; 970 case Iop_QandQSarNnarrow64Sto32Sx2: 971 vex_printf("QandQSarNnarrow64Sto32Sx2"); return; 972 case Iop_QandQSarNnarrow16Sto8Ux8: 973 vex_printf("QandQSarNnarrow16Sto8Ux8"); return; 974 case Iop_QandQSarNnarrow32Sto16Ux4: 975 vex_printf("QandQSarNnarrow32Sto16Ux4"); return; 976 case Iop_QandQSarNnarrow64Sto32Ux2: 977 vex_printf("QandQSarNnarrow64Sto32Ux2"); return; 978 case Iop_QandQRShrNnarrow16Uto8Ux8: 979 vex_printf("QandQRShrNnarrow16Uto8Ux8"); return; 980 case Iop_QandQRShrNnarrow32Uto16Ux4: 981 vex_printf("QandQRShrNnarrow32Uto16Ux4"); return; 982 case Iop_QandQRShrNnarrow64Uto32Ux2: 983 vex_printf("QandQRShrNnarrow64Uto32Ux2"); return; 984 case Iop_QandQRSarNnarrow16Sto8Sx8: 985 vex_printf("QandQRSarNnarrow16Sto8Sx8"); return; 986 case Iop_QandQRSarNnarrow32Sto16Sx4: 987 vex_printf("QandQRSarNnarrow32Sto16Sx4"); return; 988 case Iop_QandQRSarNnarrow64Sto32Sx2: 989 vex_printf("QandQRSarNnarrow64Sto32Sx2"); return; 990 case Iop_QandQRSarNnarrow16Sto8Ux8: 991 vex_printf("QandQRSarNnarrow16Sto8Ux8"); return; 992 case Iop_QandQRSarNnarrow32Sto16Ux4: 993 vex_printf("QandQRSarNnarrow32Sto16Ux4"); return; 994 case Iop_QandQRSarNnarrow64Sto32Ux2: 995 vex_printf("QandQRSarNnarrow64Sto32Ux2"); return; 996 997 case Iop_NarrowBin16to8x16: vex_printf("NarrowBin16to8x16"); return; 998 case Iop_NarrowBin32to16x8: vex_printf("NarrowBin32to16x8"); return; 999 case Iop_QNarrowBin16Uto8Ux16: vex_printf("QNarrowBin16Uto8Ux16"); return; 1000 case Iop_QNarrowBin32Sto16Ux8: vex_printf("QNarrowBin32Sto16Ux8"); return; 1001 case Iop_QNarrowBin16Sto8Ux16: vex_printf("QNarrowBin16Sto8Ux16"); return; 1002 case Iop_QNarrowBin32Uto16Ux8: vex_printf("QNarrowBin32Uto16Ux8"); return; 1003 case Iop_QNarrowBin16Sto8Sx16: vex_printf("QNarrowBin16Sto8Sx16"); return; 1004 case Iop_QNarrowBin32Sto16Sx8: vex_printf("QNarrowBin32Sto16Sx8"); return; 1005 case Iop_NarrowUn16to8x8: vex_printf("NarrowUn16to8x8"); return; 1006 case Iop_NarrowUn32to16x4: vex_printf("NarrowUn32to16x4"); return; 1007 case Iop_NarrowUn64to32x2: vex_printf("NarrowUn64to32x2"); return; 1008 case Iop_QNarrowUn16Uto8Ux8: vex_printf("QNarrowUn16Uto8Ux8"); return; 1009 case Iop_QNarrowUn32Uto16Ux4: vex_printf("QNarrowUn32Uto16Ux4"); return; 1010 case Iop_QNarrowUn64Uto32Ux2: vex_printf("QNarrowUn64Uto32Ux2"); return; 1011 case Iop_QNarrowUn16Sto8Sx8: vex_printf("QNarrowUn16Sto8Sx8"); return; 1012 case Iop_QNarrowUn32Sto16Sx4: vex_printf("QNarrowUn32Sto16Sx4"); return; 1013 case Iop_QNarrowUn64Sto32Sx2: vex_printf("QNarrowUn64Sto32Sx2"); return; 1014 case Iop_QNarrowUn16Sto8Ux8: vex_printf("QNarrowUn16Sto8Ux8"); return; 1015 case Iop_QNarrowUn32Sto16Ux4: vex_printf("QNarrowUn32Sto16Ux4"); return; 1016 case Iop_QNarrowUn64Sto32Ux2: vex_printf("QNarrowUn64Sto32Ux2"); return; 1017 case Iop_Widen8Uto16x8: vex_printf("Widen8Uto16x8"); return; 1018 case Iop_Widen16Uto32x4: vex_printf("Widen16Uto32x4"); return; 1019 case Iop_Widen32Uto64x2: vex_printf("Widen32Uto64x2"); return; 1020 case Iop_Widen8Sto16x8: vex_printf("Widen8Sto16x8"); return; 1021 case Iop_Widen16Sto32x4: vex_printf("Widen16Sto32x4"); return; 1022 case Iop_Widen32Sto64x2: vex_printf("Widen32Sto64x2"); return; 1023 1024 case Iop_InterleaveHI8x16: vex_printf("InterleaveHI8x16"); return; 1025 case Iop_InterleaveHI16x8: vex_printf("InterleaveHI16x8"); return; 1026 case Iop_InterleaveHI32x4: vex_printf("InterleaveHI32x4"); return; 1027 case Iop_InterleaveHI64x2: vex_printf("InterleaveHI64x2"); return; 1028 case Iop_InterleaveLO8x16: vex_printf("InterleaveLO8x16"); return; 1029 case Iop_InterleaveLO16x8: vex_printf("InterleaveLO16x8"); return; 1030 case Iop_InterleaveLO32x4: vex_printf("InterleaveLO32x4"); return; 1031 case Iop_InterleaveLO64x2: vex_printf("InterleaveLO64x2"); return; 1032 1033 case Iop_CatOddLanes8x16: vex_printf("CatOddLanes8x16"); return; 1034 case Iop_CatOddLanes16x8: vex_printf("CatOddLanes16x8"); return; 1035 case Iop_CatOddLanes32x4: vex_printf("CatOddLanes32x4"); return; 1036 case Iop_CatEvenLanes8x16: vex_printf("CatEvenLanes8x16"); return; 1037 case Iop_CatEvenLanes16x8: vex_printf("CatEvenLanes16x8"); return; 1038 case Iop_CatEvenLanes32x4: vex_printf("CatEvenLanes32x4"); return; 1039 1040 case Iop_InterleaveOddLanes8x16: vex_printf("InterleaveOddLanes8x16"); return; 1041 case Iop_InterleaveOddLanes16x8: vex_printf("InterleaveOddLanes16x8"); return; 1042 case Iop_InterleaveOddLanes32x4: vex_printf("InterleaveOddLanes32x4"); return; 1043 case Iop_InterleaveEvenLanes8x16: vex_printf("InterleaveEvenLanes8x16"); return; 1044 case Iop_InterleaveEvenLanes16x8: vex_printf("InterleaveEvenLanes16x8"); return; 1045 case Iop_InterleaveEvenLanes32x4: vex_printf("InterleaveEvenLanes32x4"); return; 1046 1047 case Iop_GetElem8x16: vex_printf("GetElem8x16"); return; 1048 case Iop_GetElem16x8: vex_printf("GetElem16x8"); return; 1049 case Iop_GetElem32x4: vex_printf("GetElem32x4"); return; 1050 case Iop_GetElem64x2: vex_printf("GetElem64x2"); return; 1051 1052 case Iop_GetElem8x8: vex_printf("GetElem8x8"); return; 1053 case Iop_GetElem16x4: vex_printf("GetElem16x4"); return; 1054 case Iop_GetElem32x2: vex_printf("GetElem32x2"); return; 1055 case Iop_SetElem8x8: vex_printf("SetElem8x8"); return; 1056 case Iop_SetElem16x4: vex_printf("SetElem16x4"); return; 1057 case Iop_SetElem32x2: vex_printf("SetElem32x2"); return; 1058 1059 case Iop_Slice64: vex_printf("Slice64"); return; 1060 case Iop_SliceV128: vex_printf("SliceV128"); return; 1061 1062 case Iop_Perm8x16: vex_printf("Perm8x16"); return; 1063 case Iop_Perm32x4: vex_printf("Perm32x4"); return; 1064 case Iop_Reverse8sIn16_x8: vex_printf("Reverse8sIn16_x8"); return; 1065 case Iop_Reverse8sIn32_x4: vex_printf("Reverse8sIn32_x4"); return; 1066 case Iop_Reverse16sIn32_x4: vex_printf("Reverse16sIn32_x4"); return; 1067 case Iop_Reverse8sIn64_x2: vex_printf("Reverse8sIn64_x2"); return; 1068 case Iop_Reverse16sIn64_x2: vex_printf("Reverse16sIn64_x2"); return; 1069 case Iop_Reverse32sIn64_x2: vex_printf("Reverse32sIn64_x2"); return; 1070 case Iop_Reverse1sIn8_x16: vex_printf("Reverse1sIn8_x16"); return; 1071 1072 case Iop_F32ToFixed32Ux4_RZ: vex_printf("F32ToFixed32Ux4_RZ"); return; 1073 case Iop_F32ToFixed32Sx4_RZ: vex_printf("F32ToFixed32Sx4_RZ"); return; 1074 case Iop_Fixed32UToF32x4_RN: vex_printf("Fixed32UToF32x4_RN"); return; 1075 case Iop_Fixed32SToF32x4_RN: vex_printf("Fixed32SToF32x4_RN"); return; 1076 case Iop_F32ToFixed32Ux2_RZ: vex_printf("F32ToFixed32Ux2_RZ"); return; 1077 case Iop_F32ToFixed32Sx2_RZ: vex_printf("F32ToFixed32Sx2_RZ"); return; 1078 case Iop_Fixed32UToF32x2_RN: vex_printf("Fixed32UToF32x2_RN"); return; 1079 case Iop_Fixed32SToF32x2_RN: vex_printf("Fixed32SToF32x2_RN"); return; 1080 1081 case Iop_D32toD64: vex_printf("D32toD64"); return; 1082 case Iop_D64toD32: vex_printf("D64toD32"); return; 1083 case Iop_AddD64: vex_printf("AddD64"); return; 1084 case Iop_SubD64: vex_printf("SubD64"); return; 1085 case Iop_MulD64: vex_printf("MulD64"); return; 1086 case Iop_DivD64: vex_printf("DivD64"); return; 1087 case Iop_ShlD64: vex_printf("ShlD64"); return; 1088 case Iop_ShrD64: vex_printf("ShrD64"); return; 1089 case Iop_D64toI32S: vex_printf("D64toI32S"); return; 1090 case Iop_D64toI32U: vex_printf("D64toI32U"); return; 1091 case Iop_D64toI64S: vex_printf("D64toI64S"); return; 1092 case Iop_D64toI64U: vex_printf("D64toI64U"); return; 1093 case Iop_I32StoD64: vex_printf("I32StoD64"); return; 1094 case Iop_I32UtoD64: vex_printf("I32UtoD64"); return; 1095 case Iop_I64StoD64: vex_printf("I64StoD64"); return; 1096 case Iop_I64UtoD64: vex_printf("I64UtoD64"); return; 1097 case Iop_I32StoD128: vex_printf("I32StoD128"); return; 1098 case Iop_I32UtoD128: vex_printf("I32UtoD128"); return; 1099 case Iop_I64StoD128: vex_printf("I64StoD128"); return; 1100 case Iop_I64UtoD128: vex_printf("I64UtoD128"); return; 1101 case Iop_D64toD128: vex_printf("D64toD128"); return; 1102 case Iop_D128toD64: vex_printf("D128toD64"); return; 1103 case Iop_D128toI32S: vex_printf("D128toI32S"); return; 1104 case Iop_D128toI32U: vex_printf("D128toI32U"); return; 1105 case Iop_D128toI64S: vex_printf("D128toI64S"); return; 1106 case Iop_D128toI64U: vex_printf("D128toI64U"); return; 1107 case Iop_F32toD32: vex_printf("F32toD32"); return; 1108 case Iop_F32toD64: vex_printf("F32toD64"); return; 1109 case Iop_F32toD128: vex_printf("F32toD128"); return; 1110 case Iop_F64toD32: vex_printf("F64toD32"); return; 1111 case Iop_F64toD64: vex_printf("F64toD64"); return; 1112 case Iop_F64toD128: vex_printf("F64toD128"); return; 1113 case Iop_F128toD32: vex_printf("F128toD32"); return; 1114 case Iop_F128toD64: vex_printf("F128toD64"); return; 1115 case Iop_F128toD128: vex_printf("F128toD128"); return; 1116 case Iop_D32toF32: vex_printf("D32toF32"); return; 1117 case Iop_D32toF64: vex_printf("D32toF64"); return; 1118 case Iop_D32toF128: vex_printf("D32toF128"); return; 1119 case Iop_D64toF32: vex_printf("D64toF32"); return; 1120 case Iop_D64toF64: vex_printf("D64toF64"); return; 1121 case Iop_D64toF128: vex_printf("D64toF128"); return; 1122 case Iop_D128toF32: vex_printf("D128toF32"); return; 1123 case Iop_D128toF64: vex_printf("D128toF64"); return; 1124 case Iop_D128toF128: vex_printf("D128toF128"); return; 1125 case Iop_AddD128: vex_printf("AddD128"); return; 1126 case Iop_SubD128: vex_printf("SubD128"); return; 1127 case Iop_MulD128: vex_printf("MulD128"); return; 1128 case Iop_DivD128: vex_printf("DivD128"); return; 1129 case Iop_ShlD128: vex_printf("ShlD128"); return; 1130 case Iop_ShrD128: vex_printf("ShrD128"); return; 1131 case Iop_RoundD64toInt: vex_printf("RoundD64toInt"); return; 1132 case Iop_RoundD128toInt: vex_printf("RoundD128toInt"); return; 1133 case Iop_QuantizeD64: vex_printf("QuantizeD64"); return; 1134 case Iop_QuantizeD128: vex_printf("QuantizeD128"); return; 1135 case Iop_ExtractExpD64: vex_printf("ExtractExpD64"); return; 1136 case Iop_ExtractExpD128: vex_printf("ExtractExpD128"); return; 1137 case Iop_ExtractSigD64: vex_printf("ExtractSigD64"); return; 1138 case Iop_ExtractSigD128: vex_printf("ExtractSigD128"); return; 1139 case Iop_InsertExpD64: vex_printf("InsertExpD64"); return; 1140 case Iop_InsertExpD128: vex_printf("InsertExpD128"); return; 1141 case Iop_CmpD64: vex_printf("CmpD64"); return; 1142 case Iop_CmpD128: vex_printf("CmpD128"); return; 1143 case Iop_CmpExpD64: vex_printf("CmpExpD64"); return; 1144 case Iop_CmpExpD128: vex_printf("CmpExpD128"); return; 1145 case Iop_D64HLtoD128: vex_printf("D64HLtoD128"); return; 1146 case Iop_D128HItoD64: vex_printf("D128HItoD64"); return; 1147 case Iop_D128LOtoD64: vex_printf("D128LOtoD64"); return; 1148 case Iop_SignificanceRoundD64: vex_printf("SignificanceRoundD64"); 1149 return; 1150 case Iop_SignificanceRoundD128: vex_printf("SignificanceRoundD128"); 1151 return; 1152 case Iop_ReinterpI64asD64: vex_printf("ReinterpI64asD64"); return; 1153 case Iop_ReinterpD64asI64: vex_printf("ReinterpD64asI64"); return; 1154 case Iop_V256to64_0: vex_printf("V256to64_0"); return; 1155 case Iop_V256to64_1: vex_printf("V256to64_1"); return; 1156 case Iop_V256to64_2: vex_printf("V256to64_2"); return; 1157 case Iop_V256to64_3: vex_printf("V256to64_3"); return; 1158 case Iop_64x4toV256: vex_printf("64x4toV256"); return; 1159 case Iop_V256toV128_0: vex_printf("V256toV128_0"); return; 1160 case Iop_V256toV128_1: vex_printf("V256toV128_1"); return; 1161 case Iop_V128HLtoV256: vex_printf("V128HLtoV256"); return; 1162 case Iop_DPBtoBCD: vex_printf("DPBtoBCD"); return; 1163 case Iop_BCDtoDPB: vex_printf("BCDtoDPB"); return; 1164 case Iop_Add64Fx4: vex_printf("Add64Fx4"); return; 1165 case Iop_Sub64Fx4: vex_printf("Sub64Fx4"); return; 1166 case Iop_Mul64Fx4: vex_printf("Mul64Fx4"); return; 1167 case Iop_Div64Fx4: vex_printf("Div64Fx4"); return; 1168 case Iop_Add32Fx8: vex_printf("Add32Fx8"); return; 1169 case Iop_Sub32Fx8: vex_printf("Sub32Fx8"); return; 1170 case Iop_Mul32Fx8: vex_printf("Mul32Fx8"); return; 1171 case Iop_Div32Fx8: vex_printf("Div32Fx8"); return; 1172 case Iop_AndV256: vex_printf("AndV256"); return; 1173 case Iop_OrV256: vex_printf("OrV256"); return; 1174 case Iop_XorV256: vex_printf("XorV256"); return; 1175 case Iop_NotV256: vex_printf("NotV256"); return; 1176 case Iop_CmpNEZ64x4: vex_printf("CmpNEZ64x4"); return; 1177 case Iop_CmpNEZ32x8: vex_printf("CmpNEZ32x8"); return; 1178 case Iop_CmpNEZ16x16: vex_printf("CmpNEZ16x16"); return; 1179 case Iop_CmpNEZ8x32: vex_printf("CmpNEZ8x32"); return; 1180 1181 case Iop_Add8x32: vex_printf("Add8x32"); return; 1182 case Iop_Add16x16: vex_printf("Add16x16"); return; 1183 case Iop_Add32x8: vex_printf("Add32x8"); return; 1184 case Iop_Add64x4: vex_printf("Add64x4"); return; 1185 case Iop_Sub8x32: vex_printf("Sub8x32"); return; 1186 case Iop_Sub16x16: vex_printf("Sub16x16"); return; 1187 case Iop_Sub32x8: vex_printf("Sub32x8"); return; 1188 case Iop_Sub64x4: vex_printf("Sub64x4"); return; 1189 case Iop_QAdd8Ux32: vex_printf("QAdd8Ux32"); return; 1190 case Iop_QAdd16Ux16: vex_printf("QAdd16Ux16"); return; 1191 case Iop_QAdd8Sx32: vex_printf("QAdd8Sx32"); return; 1192 case Iop_QAdd16Sx16: vex_printf("QAdd16Sx16"); return; 1193 case Iop_QSub8Ux32: vex_printf("QSub8Ux32"); return; 1194 case Iop_QSub16Ux16: vex_printf("QSub16Ux16"); return; 1195 case Iop_QSub8Sx32: vex_printf("QSub8Sx32"); return; 1196 case Iop_QSub16Sx16: vex_printf("QSub16Sx16"); return; 1197 1198 case Iop_Mul16x16: vex_printf("Mul16x16"); return; 1199 case Iop_Mul32x8: vex_printf("Mul32x8"); return; 1200 case Iop_MulHi16Ux16: vex_printf("MulHi16Ux16"); return; 1201 case Iop_MulHi16Sx16: vex_printf("MulHi16Sx16"); return; 1202 1203 case Iop_Avg8Ux32: vex_printf("Avg8Ux32"); return; 1204 case Iop_Avg16Ux16: vex_printf("Avg16Ux16"); return; 1205 1206 case Iop_Max8Sx32: vex_printf("Max8Sx32"); return; 1207 case Iop_Max16Sx16: vex_printf("Max16Sx16"); return; 1208 case Iop_Max32Sx8: vex_printf("Max32Sx8"); return; 1209 case Iop_Max8Ux32: vex_printf("Max8Ux32"); return; 1210 case Iop_Max16Ux16: vex_printf("Max16Ux16"); return; 1211 case Iop_Max32Ux8: vex_printf("Max32Ux8"); return; 1212 1213 case Iop_Min8Sx32: vex_printf("Min8Sx32"); return; 1214 case Iop_Min16Sx16: vex_printf("Min16Sx16"); return; 1215 case Iop_Min32Sx8: vex_printf("Min32Sx8"); return; 1216 case Iop_Min8Ux32: vex_printf("Min8Ux32"); return; 1217 case Iop_Min16Ux16: vex_printf("Min16Ux16"); return; 1218 case Iop_Min32Ux8: vex_printf("Min32Ux8"); return; 1219 1220 case Iop_CmpEQ8x32: vex_printf("CmpEQ8x32"); return; 1221 case Iop_CmpEQ16x16: vex_printf("CmpEQ16x16"); return; 1222 case Iop_CmpEQ32x8: vex_printf("CmpEQ32x8"); return; 1223 case Iop_CmpEQ64x4: vex_printf("CmpEQ64x4"); return; 1224 case Iop_CmpGT8Sx32: vex_printf("CmpGT8Sx32"); return; 1225 case Iop_CmpGT16Sx16: vex_printf("CmpGT16Sx16"); return; 1226 case Iop_CmpGT32Sx8: vex_printf("CmpGT32Sx8"); return; 1227 case Iop_CmpGT64Sx4: vex_printf("CmpGT64Sx4"); return; 1228 1229 case Iop_ShlN16x16: vex_printf("ShlN16x16"); return; 1230 case Iop_ShlN32x8: vex_printf("ShlN32x8"); return; 1231 case Iop_ShlN64x4: vex_printf("ShlN64x4"); return; 1232 case Iop_ShrN16x16: vex_printf("ShrN16x16"); return; 1233 case Iop_ShrN32x8: vex_printf("ShrN32x8"); return; 1234 case Iop_ShrN64x4: vex_printf("ShrN64x4"); return; 1235 case Iop_SarN16x16: vex_printf("SarN16x16"); return; 1236 case Iop_SarN32x8: vex_printf("SarN32x8"); return; 1237 1238 case Iop_Perm32x8: vex_printf("Perm32x8"); return; 1239 1240 case Iop_CipherV128: vex_printf("CipherV128"); return; 1241 case Iop_CipherLV128: vex_printf("CipherLV128"); return; 1242 case Iop_NCipherV128: vex_printf("NCipherV128"); return; 1243 case Iop_NCipherLV128: vex_printf("NCipherLV128"); return; 1244 case Iop_CipherSV128: vex_printf("CipherSV128"); return; 1245 1246 case Iop_SHA256: vex_printf("SHA256"); return; 1247 case Iop_SHA512: vex_printf("SHA512"); return; 1248 case Iop_BCDAdd: vex_printf("BCDAdd"); return; 1249 case Iop_BCDSub: vex_printf("BCDSub"); return; 1250 1251 case Iop_PwBitMtxXpose64x2: vex_printf("BitMatrixTranspose64x2"); return; 1252 1253 default: vpanic("ppIROp(1)"); 1254 } 1255 1256 vassert(str); 1257 switch (op - base) { 1258 case 0: vex_printf("%s",str); vex_printf("8"); break; 1259 case 1: vex_printf("%s",str); vex_printf("16"); break; 1260 case 2: vex_printf("%s",str); vex_printf("32"); break; 1261 case 3: vex_printf("%s",str); vex_printf("64"); break; 1262 default: vpanic("ppIROp(2)"); 1263 } 1264 } 1265 1266 void ppIRExpr ( const IRExpr* e ) 1267 { 1268 Int i; 1269 switch (e->tag) { 1270 case Iex_Binder: 1271 vex_printf("BIND-%d", e->Iex.Binder.binder); 1272 break; 1273 case Iex_Get: 1274 vex_printf( "GET:" ); 1275 ppIRType(e->Iex.Get.ty); 1276 vex_printf("(%d)", e->Iex.Get.offset); 1277 break; 1278 case Iex_GetI: 1279 vex_printf( "GETI" ); 1280 ppIRRegArray(e->Iex.GetI.descr); 1281 vex_printf("["); 1282 ppIRExpr(e->Iex.GetI.ix); 1283 vex_printf(",%d]", e->Iex.GetI.bias); 1284 break; 1285 case Iex_RdTmp: 1286 ppIRTemp(e->Iex.RdTmp.tmp); 1287 break; 1288 case Iex_Qop: { 1289 const IRQop *qop = e->Iex.Qop.details; 1290 ppIROp(qop->op); 1291 vex_printf( "(" ); 1292 ppIRExpr(qop->arg1); 1293 vex_printf( "," ); 1294 ppIRExpr(qop->arg2); 1295 vex_printf( "," ); 1296 ppIRExpr(qop->arg3); 1297 vex_printf( "," ); 1298 ppIRExpr(qop->arg4); 1299 vex_printf( ")" ); 1300 break; 1301 } 1302 case Iex_Triop: { 1303 const IRTriop *triop = e->Iex.Triop.details; 1304 ppIROp(triop->op); 1305 vex_printf( "(" ); 1306 ppIRExpr(triop->arg1); 1307 vex_printf( "," ); 1308 ppIRExpr(triop->arg2); 1309 vex_printf( "," ); 1310 ppIRExpr(triop->arg3); 1311 vex_printf( ")" ); 1312 break; 1313 } 1314 case Iex_Binop: 1315 ppIROp(e->Iex.Binop.op); 1316 vex_printf( "(" ); 1317 ppIRExpr(e->Iex.Binop.arg1); 1318 vex_printf( "," ); 1319 ppIRExpr(e->Iex.Binop.arg2); 1320 vex_printf( ")" ); 1321 break; 1322 case Iex_Unop: 1323 ppIROp(e->Iex.Unop.op); 1324 vex_printf( "(" ); 1325 ppIRExpr(e->Iex.Unop.arg); 1326 vex_printf( ")" ); 1327 break; 1328 case Iex_Load: 1329 vex_printf( "LD%s:", e->Iex.Load.end==Iend_LE ? "le" : "be" ); 1330 ppIRType(e->Iex.Load.ty); 1331 vex_printf( "(" ); 1332 ppIRExpr(e->Iex.Load.addr); 1333 vex_printf( ")" ); 1334 break; 1335 case Iex_Const: 1336 ppIRConst(e->Iex.Const.con); 1337 break; 1338 case Iex_CCall: 1339 ppIRCallee(e->Iex.CCall.cee); 1340 vex_printf("("); 1341 for (i = 0; e->Iex.CCall.args[i] != NULL; i++) { 1342 IRExpr* arg = e->Iex.CCall.args[i]; 1343 ppIRExpr(arg); 1344 1345 if (e->Iex.CCall.args[i+1] != NULL) { 1346 vex_printf(","); 1347 } 1348 } 1349 vex_printf("):"); 1350 ppIRType(e->Iex.CCall.retty); 1351 break; 1352 case Iex_ITE: 1353 vex_printf("ITE("); 1354 ppIRExpr(e->Iex.ITE.cond); 1355 vex_printf(","); 1356 ppIRExpr(e->Iex.ITE.iftrue); 1357 vex_printf(","); 1358 ppIRExpr(e->Iex.ITE.iffalse); 1359 vex_printf(")"); 1360 break; 1361 case Iex_VECRET: 1362 vex_printf("VECRET"); 1363 break; 1364 case Iex_BBPTR: 1365 vex_printf("BBPTR"); 1366 break; 1367 default: 1368 vpanic("ppIRExpr"); 1369 } 1370 } 1371 1372 void ppIREffect ( IREffect fx ) 1373 { 1374 switch (fx) { 1375 case Ifx_None: vex_printf("noFX"); return; 1376 case Ifx_Read: vex_printf("RdFX"); return; 1377 case Ifx_Write: vex_printf("WrFX"); return; 1378 case Ifx_Modify: vex_printf("MoFX"); return; 1379 default: vpanic("ppIREffect"); 1380 } 1381 } 1382 1383 void ppIRDirty ( const IRDirty* d ) 1384 { 1385 Int i; 1386 if (d->tmp != IRTemp_INVALID) { 1387 ppIRTemp(d->tmp); 1388 vex_printf(" = "); 1389 } 1390 vex_printf("DIRTY "); 1391 ppIRExpr(d->guard); 1392 if (d->mFx != Ifx_None) { 1393 vex_printf(" "); 1394 ppIREffect(d->mFx); 1395 vex_printf("-mem("); 1396 ppIRExpr(d->mAddr); 1397 vex_printf(",%d)", d->mSize); 1398 } 1399 for (i = 0; i < d->nFxState; i++) { 1400 vex_printf(" "); 1401 ppIREffect(d->fxState[i].fx); 1402 vex_printf("-gst(%u,%u", (UInt)d->fxState[i].offset, 1403 (UInt)d->fxState[i].size); 1404 if (d->fxState[i].nRepeats > 0) { 1405 vex_printf(",reps%u,step%u", (UInt)d->fxState[i].nRepeats, 1406 (UInt)d->fxState[i].repeatLen); 1407 } 1408 vex_printf(")"); 1409 } 1410 vex_printf(" ::: "); 1411 ppIRCallee(d->cee); 1412 vex_printf("("); 1413 for (i = 0; d->args[i] != NULL; i++) { 1414 IRExpr* arg = d->args[i]; 1415 ppIRExpr(arg); 1416 1417 if (d->args[i+1] != NULL) { 1418 vex_printf(","); 1419 } 1420 } 1421 vex_printf(")"); 1422 } 1423 1424 void ppIRCAS ( const IRCAS* cas ) 1425 { 1426 /* Print even structurally invalid constructions, as an aid to 1427 debugging. */ 1428 if (cas->oldHi != IRTemp_INVALID) { 1429 ppIRTemp(cas->oldHi); 1430 vex_printf(","); 1431 } 1432 ppIRTemp(cas->oldLo); 1433 vex_printf(" = CAS%s(", cas->end==Iend_LE ? "le" : "be" ); 1434 ppIRExpr(cas->addr); 1435 vex_printf("::"); 1436 if (cas->expdHi) { 1437 ppIRExpr(cas->expdHi); 1438 vex_printf(","); 1439 } 1440 ppIRExpr(cas->expdLo); 1441 vex_printf("->"); 1442 if (cas->dataHi) { 1443 ppIRExpr(cas->dataHi); 1444 vex_printf(","); 1445 } 1446 ppIRExpr(cas->dataLo); 1447 vex_printf(")"); 1448 } 1449 1450 void ppIRPutI ( const IRPutI* puti ) 1451 { 1452 vex_printf( "PUTI" ); 1453 ppIRRegArray(puti->descr); 1454 vex_printf("["); 1455 ppIRExpr(puti->ix); 1456 vex_printf(",%d] = ", puti->bias); 1457 ppIRExpr(puti->data); 1458 } 1459 1460 void ppIRStoreG ( const IRStoreG* sg ) 1461 { 1462 vex_printf("if ("); 1463 ppIRExpr(sg->guard); 1464 vex_printf(") { ST%s(", sg->end==Iend_LE ? "le" : "be"); 1465 ppIRExpr(sg->addr); 1466 vex_printf(") = "); 1467 ppIRExpr(sg->data); 1468 vex_printf(" }"); 1469 } 1470 1471 void ppIRLoadGOp ( IRLoadGOp cvt ) 1472 { 1473 switch (cvt) { 1474 case ILGop_INVALID: vex_printf("ILGop_INVALID"); break; 1475 case ILGop_IdentV128: vex_printf("IdentV128"); break; 1476 case ILGop_Ident64: vex_printf("Ident64"); break; 1477 case ILGop_Ident32: vex_printf("Ident32"); break; 1478 case ILGop_16Uto32: vex_printf("16Uto32"); break; 1479 case ILGop_16Sto32: vex_printf("16Sto32"); break; 1480 case ILGop_8Uto32: vex_printf("8Uto32"); break; 1481 case ILGop_8Sto32: vex_printf("8Sto32"); break; 1482 default: vpanic("ppIRLoadGOp"); 1483 } 1484 } 1485 1486 void ppIRLoadG ( const IRLoadG* lg ) 1487 { 1488 ppIRTemp(lg->dst); 1489 vex_printf(" = if-strict ("); 1490 ppIRExpr(lg->guard); 1491 vex_printf(") "); 1492 ppIRLoadGOp(lg->cvt); 1493 vex_printf("(LD%s(", lg->end==Iend_LE ? "le" : "be"); 1494 ppIRExpr(lg->addr); 1495 vex_printf(")) else "); 1496 ppIRExpr(lg->alt); 1497 } 1498 1499 void ppIRJumpKind ( IRJumpKind kind ) 1500 { 1501 switch (kind) { 1502 case Ijk_Boring: vex_printf("Boring"); break; 1503 case Ijk_Call: vex_printf("Call"); break; 1504 case Ijk_Ret: vex_printf("Return"); break; 1505 case Ijk_ClientReq: vex_printf("ClientReq"); break; 1506 case Ijk_Yield: vex_printf("Yield"); break; 1507 case Ijk_EmWarn: vex_printf("EmWarn"); break; 1508 case Ijk_EmFail: vex_printf("EmFail"); break; 1509 case Ijk_NoDecode: vex_printf("NoDecode"); break; 1510 case Ijk_MapFail: vex_printf("MapFail"); break; 1511 case Ijk_InvalICache: vex_printf("InvalICache"); break; 1512 case Ijk_FlushDCache: vex_printf("FlushDCache"); break; 1513 case Ijk_NoRedir: vex_printf("NoRedir"); break; 1514 case Ijk_SigILL: vex_printf("SigILL"); break; 1515 case Ijk_SigTRAP: vex_printf("SigTRAP"); break; 1516 case Ijk_SigSEGV: vex_printf("SigSEGV"); break; 1517 case Ijk_SigBUS: vex_printf("SigBUS"); break; 1518 case Ijk_SigFPE_IntDiv: vex_printf("SigFPE_IntDiv"); break; 1519 case Ijk_SigFPE_IntOvf: vex_printf("SigFPE_IntOvf"); break; 1520 case Ijk_Sys_syscall: vex_printf("Sys_syscall"); break; 1521 case Ijk_Sys_int32: vex_printf("Sys_int32"); break; 1522 case Ijk_Sys_int128: vex_printf("Sys_int128"); break; 1523 case Ijk_Sys_int129: vex_printf("Sys_int129"); break; 1524 case Ijk_Sys_int130: vex_printf("Sys_int130"); break; 1525 case Ijk_Sys_int145: vex_printf("Sys_int145"); break; 1526 case Ijk_Sys_int210: vex_printf("Sys_int210"); break; 1527 case Ijk_Sys_sysenter: vex_printf("Sys_sysenter"); break; 1528 default: vpanic("ppIRJumpKind"); 1529 } 1530 } 1531 1532 void ppIRMBusEvent ( IRMBusEvent event ) 1533 { 1534 switch (event) { 1535 case Imbe_Fence: 1536 vex_printf("Fence"); break; 1537 case Imbe_CancelReservation: 1538 vex_printf("CancelReservation"); break; 1539 default: 1540 vpanic("ppIRMBusEvent"); 1541 } 1542 } 1543 1544 void ppIRStmt ( const IRStmt* s ) 1545 { 1546 if (!s) { 1547 vex_printf("!!! IRStmt* which is NULL !!!"); 1548 return; 1549 } 1550 switch (s->tag) { 1551 case Ist_NoOp: 1552 vex_printf("IR-NoOp"); 1553 break; 1554 case Ist_IMark: 1555 vex_printf( "------ IMark(0x%lx, %u, %u) ------", 1556 s->Ist.IMark.addr, s->Ist.IMark.len, 1557 (UInt)s->Ist.IMark.delta); 1558 break; 1559 case Ist_AbiHint: 1560 vex_printf("====== AbiHint("); 1561 ppIRExpr(s->Ist.AbiHint.base); 1562 vex_printf(", %d, ", s->Ist.AbiHint.len); 1563 ppIRExpr(s->Ist.AbiHint.nia); 1564 vex_printf(") ======"); 1565 break; 1566 case Ist_Put: 1567 vex_printf( "PUT(%d) = ", s->Ist.Put.offset); 1568 ppIRExpr(s->Ist.Put.data); 1569 break; 1570 case Ist_PutI: 1571 ppIRPutI(s->Ist.PutI.details); 1572 break; 1573 case Ist_WrTmp: 1574 ppIRTemp(s->Ist.WrTmp.tmp); 1575 vex_printf( " = " ); 1576 ppIRExpr(s->Ist.WrTmp.data); 1577 break; 1578 case Ist_Store: 1579 vex_printf( "ST%s(", s->Ist.Store.end==Iend_LE ? "le" : "be" ); 1580 ppIRExpr(s->Ist.Store.addr); 1581 vex_printf( ") = "); 1582 ppIRExpr(s->Ist.Store.data); 1583 break; 1584 case Ist_StoreG: 1585 ppIRStoreG(s->Ist.StoreG.details); 1586 break; 1587 case Ist_LoadG: 1588 ppIRLoadG(s->Ist.LoadG.details); 1589 break; 1590 case Ist_CAS: 1591 ppIRCAS(s->Ist.CAS.details); 1592 break; 1593 case Ist_LLSC: 1594 if (s->Ist.LLSC.storedata == NULL) { 1595 ppIRTemp(s->Ist.LLSC.result); 1596 vex_printf(" = LD%s-Linked(", 1597 s->Ist.LLSC.end==Iend_LE ? "le" : "be"); 1598 ppIRExpr(s->Ist.LLSC.addr); 1599 vex_printf(")"); 1600 } else { 1601 ppIRTemp(s->Ist.LLSC.result); 1602 vex_printf(" = ( ST%s-Cond(", 1603 s->Ist.LLSC.end==Iend_LE ? "le" : "be"); 1604 ppIRExpr(s->Ist.LLSC.addr); 1605 vex_printf(") = "); 1606 ppIRExpr(s->Ist.LLSC.storedata); 1607 vex_printf(" )"); 1608 } 1609 break; 1610 case Ist_Dirty: 1611 ppIRDirty(s->Ist.Dirty.details); 1612 break; 1613 case Ist_MBE: 1614 vex_printf("IR-"); 1615 ppIRMBusEvent(s->Ist.MBE.event); 1616 break; 1617 case Ist_Exit: 1618 vex_printf( "if (" ); 1619 ppIRExpr(s->Ist.Exit.guard); 1620 vex_printf( ") { PUT(%d) = ", s->Ist.Exit.offsIP); 1621 ppIRConst(s->Ist.Exit.dst); 1622 vex_printf("; exit-"); 1623 ppIRJumpKind(s->Ist.Exit.jk); 1624 vex_printf(" } "); 1625 break; 1626 default: 1627 vpanic("ppIRStmt"); 1628 } 1629 } 1630 1631 void ppIRTypeEnv ( const IRTypeEnv* env ) 1632 { 1633 UInt i; 1634 for (i = 0; i < env->types_used; i++) { 1635 if (i % 8 == 0) 1636 vex_printf( " "); 1637 ppIRTemp(i); 1638 vex_printf( ":"); 1639 ppIRType(env->types[i]); 1640 if (i % 8 == 7) 1641 vex_printf( "\n"); 1642 else 1643 vex_printf( " "); 1644 } 1645 if (env->types_used > 0 && env->types_used % 8 != 7) 1646 vex_printf( "\n"); 1647 } 1648 1649 void ppIRSB ( const IRSB* bb ) 1650 { 1651 Int i; 1652 vex_printf("IRSB {\n"); 1653 ppIRTypeEnv(bb->tyenv); 1654 vex_printf("\n"); 1655 for (i = 0; i < bb->stmts_used; i++) { 1656 vex_printf( " "); 1657 ppIRStmt(bb->stmts[i]); 1658 vex_printf( "\n"); 1659 } 1660 vex_printf( " PUT(%d) = ", bb->offsIP ); 1661 ppIRExpr( bb->next ); 1662 vex_printf( "; exit-"); 1663 ppIRJumpKind(bb->jumpkind); 1664 vex_printf( "\n}\n"); 1665 } 1666 1667 1668 /*---------------------------------------------------------------*/ 1669 /*--- Constructors ---*/ 1670 /*---------------------------------------------------------------*/ 1671 1672 1673 /* Constructors -- IRConst */ 1674 1675 IRConst* IRConst_U1 ( Bool bit ) 1676 { 1677 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1678 c->tag = Ico_U1; 1679 c->Ico.U1 = bit; 1680 /* call me paranoid; I don't care :-) */ 1681 vassert(bit == False || bit == True); 1682 return c; 1683 } 1684 IRConst* IRConst_U8 ( UChar u8 ) 1685 { 1686 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1687 c->tag = Ico_U8; 1688 c->Ico.U8 = u8; 1689 return c; 1690 } 1691 IRConst* IRConst_U16 ( UShort u16 ) 1692 { 1693 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1694 c->tag = Ico_U16; 1695 c->Ico.U16 = u16; 1696 return c; 1697 } 1698 IRConst* IRConst_U32 ( UInt u32 ) 1699 { 1700 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1701 c->tag = Ico_U32; 1702 c->Ico.U32 = u32; 1703 return c; 1704 } 1705 IRConst* IRConst_U64 ( ULong u64 ) 1706 { 1707 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1708 c->tag = Ico_U64; 1709 c->Ico.U64 = u64; 1710 return c; 1711 } 1712 IRConst* IRConst_F32 ( Float f32 ) 1713 { 1714 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1715 c->tag = Ico_F32; 1716 c->Ico.F32 = f32; 1717 return c; 1718 } 1719 IRConst* IRConst_F32i ( UInt f32i ) 1720 { 1721 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1722 c->tag = Ico_F32i; 1723 c->Ico.F32i = f32i; 1724 return c; 1725 } 1726 IRConst* IRConst_F64 ( Double f64 ) 1727 { 1728 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1729 c->tag = Ico_F64; 1730 c->Ico.F64 = f64; 1731 return c; 1732 } 1733 IRConst* IRConst_F64i ( ULong f64i ) 1734 { 1735 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1736 c->tag = Ico_F64i; 1737 c->Ico.F64i = f64i; 1738 return c; 1739 } 1740 IRConst* IRConst_V128 ( UShort con ) 1741 { 1742 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1743 c->tag = Ico_V128; 1744 c->Ico.V128 = con; 1745 return c; 1746 } 1747 IRConst* IRConst_V256 ( UInt con ) 1748 { 1749 IRConst* c = LibVEX_Alloc_inline(sizeof(IRConst)); 1750 c->tag = Ico_V256; 1751 c->Ico.V256 = con; 1752 return c; 1753 } 1754 1755 /* Constructors -- IRCallee */ 1756 1757 IRCallee* mkIRCallee ( Int regparms, const HChar* name, void* addr ) 1758 { 1759 IRCallee* ce = LibVEX_Alloc_inline(sizeof(IRCallee)); 1760 ce->regparms = regparms; 1761 ce->name = name; 1762 ce->addr = addr; 1763 ce->mcx_mask = 0; 1764 vassert(regparms >= 0 && regparms <= 3); 1765 vassert(name != NULL); 1766 vassert(addr != 0); 1767 return ce; 1768 } 1769 1770 1771 /* Constructors -- IRRegArray */ 1772 1773 IRRegArray* mkIRRegArray ( Int base, IRType elemTy, Int nElems ) 1774 { 1775 IRRegArray* arr = LibVEX_Alloc_inline(sizeof(IRRegArray)); 1776 arr->base = base; 1777 arr->elemTy = elemTy; 1778 arr->nElems = nElems; 1779 vassert(!(arr->base < 0 || arr->base > 10000 /* somewhat arbitrary */)); 1780 vassert(!(arr->elemTy == Ity_I1)); 1781 vassert(!(arr->nElems <= 0 || arr->nElems > 500 /* somewhat arbitrary */)); 1782 return arr; 1783 } 1784 1785 1786 /* Constructors -- IRExpr */ 1787 1788 IRExpr* IRExpr_Binder ( Int binder ) { 1789 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1790 e->tag = Iex_Binder; 1791 e->Iex.Binder.binder = binder; 1792 return e; 1793 } 1794 IRExpr* IRExpr_Get ( Int off, IRType ty ) { 1795 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1796 e->tag = Iex_Get; 1797 e->Iex.Get.offset = off; 1798 e->Iex.Get.ty = ty; 1799 return e; 1800 } 1801 IRExpr* IRExpr_GetI ( IRRegArray* descr, IRExpr* ix, Int bias ) { 1802 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1803 e->tag = Iex_GetI; 1804 e->Iex.GetI.descr = descr; 1805 e->Iex.GetI.ix = ix; 1806 e->Iex.GetI.bias = bias; 1807 return e; 1808 } 1809 IRExpr* IRExpr_RdTmp ( IRTemp tmp ) { 1810 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1811 e->tag = Iex_RdTmp; 1812 e->Iex.RdTmp.tmp = tmp; 1813 return e; 1814 } 1815 IRExpr* IRExpr_Qop ( IROp op, IRExpr* arg1, IRExpr* arg2, 1816 IRExpr* arg3, IRExpr* arg4 ) { 1817 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1818 IRQop* qop = LibVEX_Alloc_inline(sizeof(IRQop)); 1819 qop->op = op; 1820 qop->arg1 = arg1; 1821 qop->arg2 = arg2; 1822 qop->arg3 = arg3; 1823 qop->arg4 = arg4; 1824 e->tag = Iex_Qop; 1825 e->Iex.Qop.details = qop; 1826 return e; 1827 } 1828 IRExpr* IRExpr_Triop ( IROp op, IRExpr* arg1, 1829 IRExpr* arg2, IRExpr* arg3 ) { 1830 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1831 IRTriop* triop = LibVEX_Alloc_inline(sizeof(IRTriop)); 1832 triop->op = op; 1833 triop->arg1 = arg1; 1834 triop->arg2 = arg2; 1835 triop->arg3 = arg3; 1836 e->tag = Iex_Triop; 1837 e->Iex.Triop.details = triop; 1838 return e; 1839 } 1840 IRExpr* IRExpr_Binop ( IROp op, IRExpr* arg1, IRExpr* arg2 ) { 1841 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1842 e->tag = Iex_Binop; 1843 e->Iex.Binop.op = op; 1844 e->Iex.Binop.arg1 = arg1; 1845 e->Iex.Binop.arg2 = arg2; 1846 return e; 1847 } 1848 IRExpr* IRExpr_Unop ( IROp op, IRExpr* arg ) { 1849 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1850 e->tag = Iex_Unop; 1851 e->Iex.Unop.op = op; 1852 e->Iex.Unop.arg = arg; 1853 return e; 1854 } 1855 IRExpr* IRExpr_Load ( IREndness end, IRType ty, IRExpr* addr ) { 1856 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1857 e->tag = Iex_Load; 1858 e->Iex.Load.end = end; 1859 e->Iex.Load.ty = ty; 1860 e->Iex.Load.addr = addr; 1861 vassert(end == Iend_LE || end == Iend_BE); 1862 return e; 1863 } 1864 IRExpr* IRExpr_Const ( IRConst* con ) { 1865 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1866 e->tag = Iex_Const; 1867 e->Iex.Const.con = con; 1868 return e; 1869 } 1870 IRExpr* IRExpr_CCall ( IRCallee* cee, IRType retty, IRExpr** args ) { 1871 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1872 e->tag = Iex_CCall; 1873 e->Iex.CCall.cee = cee; 1874 e->Iex.CCall.retty = retty; 1875 e->Iex.CCall.args = args; 1876 return e; 1877 } 1878 IRExpr* IRExpr_ITE ( IRExpr* cond, IRExpr* iftrue, IRExpr* iffalse ) { 1879 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1880 e->tag = Iex_ITE; 1881 e->Iex.ITE.cond = cond; 1882 e->Iex.ITE.iftrue = iftrue; 1883 e->Iex.ITE.iffalse = iffalse; 1884 return e; 1885 } 1886 IRExpr* IRExpr_VECRET ( void ) { 1887 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1888 e->tag = Iex_VECRET; 1889 return e; 1890 } 1891 IRExpr* IRExpr_BBPTR ( void ) { 1892 IRExpr* e = LibVEX_Alloc_inline(sizeof(IRExpr)); 1893 e->tag = Iex_BBPTR; 1894 return e; 1895 } 1896 1897 1898 /* Constructors for NULL-terminated IRExpr expression vectors, 1899 suitable for use as arg lists in clean/dirty helper calls. */ 1900 1901 IRExpr** mkIRExprVec_0 ( void ) { 1902 IRExpr** vec = LibVEX_Alloc_inline(1 * sizeof(IRExpr*)); 1903 vec[0] = NULL; 1904 return vec; 1905 } 1906 IRExpr** mkIRExprVec_1 ( IRExpr* arg1 ) { 1907 IRExpr** vec = LibVEX_Alloc_inline(2 * sizeof(IRExpr*)); 1908 vec[0] = arg1; 1909 vec[1] = NULL; 1910 return vec; 1911 } 1912 IRExpr** mkIRExprVec_2 ( IRExpr* arg1, IRExpr* arg2 ) { 1913 IRExpr** vec = LibVEX_Alloc_inline(3 * sizeof(IRExpr*)); 1914 vec[0] = arg1; 1915 vec[1] = arg2; 1916 vec[2] = NULL; 1917 return vec; 1918 } 1919 IRExpr** mkIRExprVec_3 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3 ) { 1920 IRExpr** vec = LibVEX_Alloc_inline(4 * sizeof(IRExpr*)); 1921 vec[0] = arg1; 1922 vec[1] = arg2; 1923 vec[2] = arg3; 1924 vec[3] = NULL; 1925 return vec; 1926 } 1927 IRExpr** mkIRExprVec_4 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3, 1928 IRExpr* arg4 ) { 1929 IRExpr** vec = LibVEX_Alloc_inline(5 * sizeof(IRExpr*)); 1930 vec[0] = arg1; 1931 vec[1] = arg2; 1932 vec[2] = arg3; 1933 vec[3] = arg4; 1934 vec[4] = NULL; 1935 return vec; 1936 } 1937 IRExpr** mkIRExprVec_5 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3, 1938 IRExpr* arg4, IRExpr* arg5 ) { 1939 IRExpr** vec = LibVEX_Alloc_inline(6 * sizeof(IRExpr*)); 1940 vec[0] = arg1; 1941 vec[1] = arg2; 1942 vec[2] = arg3; 1943 vec[3] = arg4; 1944 vec[4] = arg5; 1945 vec[5] = NULL; 1946 return vec; 1947 } 1948 IRExpr** mkIRExprVec_6 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3, 1949 IRExpr* arg4, IRExpr* arg5, IRExpr* arg6 ) { 1950 IRExpr** vec = LibVEX_Alloc_inline(7 * sizeof(IRExpr*)); 1951 vec[0] = arg1; 1952 vec[1] = arg2; 1953 vec[2] = arg3; 1954 vec[3] = arg4; 1955 vec[4] = arg5; 1956 vec[5] = arg6; 1957 vec[6] = NULL; 1958 return vec; 1959 } 1960 IRExpr** mkIRExprVec_7 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3, 1961 IRExpr* arg4, IRExpr* arg5, IRExpr* arg6, 1962 IRExpr* arg7 ) { 1963 IRExpr** vec = LibVEX_Alloc_inline(8 * sizeof(IRExpr*)); 1964 vec[0] = arg1; 1965 vec[1] = arg2; 1966 vec[2] = arg3; 1967 vec[3] = arg4; 1968 vec[4] = arg5; 1969 vec[5] = arg6; 1970 vec[6] = arg7; 1971 vec[7] = NULL; 1972 return vec; 1973 } 1974 IRExpr** mkIRExprVec_8 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3, 1975 IRExpr* arg4, IRExpr* arg5, IRExpr* arg6, 1976 IRExpr* arg7, IRExpr* arg8 ) { 1977 IRExpr** vec = LibVEX_Alloc_inline(9 * sizeof(IRExpr*)); 1978 vec[0] = arg1; 1979 vec[1] = arg2; 1980 vec[2] = arg3; 1981 vec[3] = arg4; 1982 vec[4] = arg5; 1983 vec[5] = arg6; 1984 vec[6] = arg7; 1985 vec[7] = arg8; 1986 vec[8] = NULL; 1987 return vec; 1988 } 1989 1990 1991 /* Constructors -- IRDirty */ 1992 1993 IRDirty* emptyIRDirty ( void ) { 1994 IRDirty* d = LibVEX_Alloc_inline(sizeof(IRDirty)); 1995 d->cee = NULL; 1996 d->guard = NULL; 1997 d->args = NULL; 1998 d->tmp = IRTemp_INVALID; 1999 d->mFx = Ifx_None; 2000 d->mAddr = NULL; 2001 d->mSize = 0; 2002 d->nFxState = 0; 2003 return d; 2004 } 2005 2006 2007 /* Constructors -- IRCAS */ 2008 2009 IRCAS* mkIRCAS ( IRTemp oldHi, IRTemp oldLo, 2010 IREndness end, IRExpr* addr, 2011 IRExpr* expdHi, IRExpr* expdLo, 2012 IRExpr* dataHi, IRExpr* dataLo ) { 2013 IRCAS* cas = LibVEX_Alloc_inline(sizeof(IRCAS)); 2014 cas->oldHi = oldHi; 2015 cas->oldLo = oldLo; 2016 cas->end = end; 2017 cas->addr = addr; 2018 cas->expdHi = expdHi; 2019 cas->expdLo = expdLo; 2020 cas->dataHi = dataHi; 2021 cas->dataLo = dataLo; 2022 return cas; 2023 } 2024 2025 2026 /* Constructors -- IRPutI */ 2027 2028 IRPutI* mkIRPutI ( IRRegArray* descr, IRExpr* ix, 2029 Int bias, IRExpr* data ) 2030 { 2031 IRPutI* puti = LibVEX_Alloc_inline(sizeof(IRPutI)); 2032 puti->descr = descr; 2033 puti->ix = ix; 2034 puti->bias = bias; 2035 puti->data = data; 2036 return puti; 2037 } 2038 2039 2040 /* Constructors -- IRStoreG and IRLoadG */ 2041 2042 IRStoreG* mkIRStoreG ( IREndness end, 2043 IRExpr* addr, IRExpr* data, IRExpr* guard ) 2044 { 2045 IRStoreG* sg = LibVEX_Alloc_inline(sizeof(IRStoreG)); 2046 sg->end = end; 2047 sg->addr = addr; 2048 sg->data = data; 2049 sg->guard = guard; 2050 return sg; 2051 } 2052 2053 IRLoadG* mkIRLoadG ( IREndness end, IRLoadGOp cvt, 2054 IRTemp dst, IRExpr* addr, IRExpr* alt, IRExpr* guard ) 2055 { 2056 IRLoadG* lg = LibVEX_Alloc_inline(sizeof(IRLoadG)); 2057 lg->end = end; 2058 lg->cvt = cvt; 2059 lg->dst = dst; 2060 lg->addr = addr; 2061 lg->alt = alt; 2062 lg->guard = guard; 2063 return lg; 2064 } 2065 2066 2067 /* Constructors -- IRStmt */ 2068 2069 IRStmt* IRStmt_NoOp ( void ) 2070 { 2071 /* Just use a single static closure. */ 2072 static IRStmt static_closure; 2073 static_closure.tag = Ist_NoOp; 2074 return &static_closure; 2075 } 2076 IRStmt* IRStmt_IMark ( Addr addr, UInt len, UChar delta ) { 2077 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2078 s->tag = Ist_IMark; 2079 s->Ist.IMark.addr = addr; 2080 s->Ist.IMark.len = len; 2081 s->Ist.IMark.delta = delta; 2082 return s; 2083 } 2084 IRStmt* IRStmt_AbiHint ( IRExpr* base, Int len, IRExpr* nia ) { 2085 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2086 s->tag = Ist_AbiHint; 2087 s->Ist.AbiHint.base = base; 2088 s->Ist.AbiHint.len = len; 2089 s->Ist.AbiHint.nia = nia; 2090 return s; 2091 } 2092 IRStmt* IRStmt_Put ( Int off, IRExpr* data ) { 2093 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2094 s->tag = Ist_Put; 2095 s->Ist.Put.offset = off; 2096 s->Ist.Put.data = data; 2097 return s; 2098 } 2099 IRStmt* IRStmt_PutI ( IRPutI* details ) { 2100 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2101 s->tag = Ist_PutI; 2102 s->Ist.PutI.details = details; 2103 return s; 2104 } 2105 IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data ) { 2106 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2107 s->tag = Ist_WrTmp; 2108 s->Ist.WrTmp.tmp = tmp; 2109 s->Ist.WrTmp.data = data; 2110 return s; 2111 } 2112 IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data ) { 2113 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2114 s->tag = Ist_Store; 2115 s->Ist.Store.end = end; 2116 s->Ist.Store.addr = addr; 2117 s->Ist.Store.data = data; 2118 vassert(end == Iend_LE || end == Iend_BE); 2119 return s; 2120 } 2121 IRStmt* IRStmt_StoreG ( IREndness end, IRExpr* addr, IRExpr* data, 2122 IRExpr* guard ) { 2123 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2124 s->tag = Ist_StoreG; 2125 s->Ist.StoreG.details = mkIRStoreG(end, addr, data, guard); 2126 vassert(end == Iend_LE || end == Iend_BE); 2127 return s; 2128 } 2129 IRStmt* IRStmt_LoadG ( IREndness end, IRLoadGOp cvt, IRTemp dst, 2130 IRExpr* addr, IRExpr* alt, IRExpr* guard ) { 2131 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2132 s->tag = Ist_LoadG; 2133 s->Ist.LoadG.details = mkIRLoadG(end, cvt, dst, addr, alt, guard); 2134 return s; 2135 } 2136 IRStmt* IRStmt_CAS ( IRCAS* cas ) { 2137 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2138 s->tag = Ist_CAS; 2139 s->Ist.CAS.details = cas; 2140 return s; 2141 } 2142 IRStmt* IRStmt_LLSC ( IREndness end, 2143 IRTemp result, IRExpr* addr, IRExpr* storedata ) { 2144 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2145 s->tag = Ist_LLSC; 2146 s->Ist.LLSC.end = end; 2147 s->Ist.LLSC.result = result; 2148 s->Ist.LLSC.addr = addr; 2149 s->Ist.LLSC.storedata = storedata; 2150 return s; 2151 } 2152 IRStmt* IRStmt_Dirty ( IRDirty* d ) 2153 { 2154 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2155 s->tag = Ist_Dirty; 2156 s->Ist.Dirty.details = d; 2157 return s; 2158 } 2159 IRStmt* IRStmt_MBE ( IRMBusEvent event ) 2160 { 2161 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2162 s->tag = Ist_MBE; 2163 s->Ist.MBE.event = event; 2164 return s; 2165 } 2166 IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst, 2167 Int offsIP ) { 2168 IRStmt* s = LibVEX_Alloc_inline(sizeof(IRStmt)); 2169 s->tag = Ist_Exit; 2170 s->Ist.Exit.guard = guard; 2171 s->Ist.Exit.jk = jk; 2172 s->Ist.Exit.dst = dst; 2173 s->Ist.Exit.offsIP = offsIP; 2174 return s; 2175 } 2176 2177 2178 /* Constructors -- IRTypeEnv */ 2179 2180 IRTypeEnv* emptyIRTypeEnv ( void ) 2181 { 2182 IRTypeEnv* env = LibVEX_Alloc_inline(sizeof(IRTypeEnv)); 2183 env->types = LibVEX_Alloc_inline(8 * sizeof(IRType)); 2184 env->types_size = 8; 2185 env->types_used = 0; 2186 return env; 2187 } 2188 2189 2190 /* Constructors -- IRSB */ 2191 2192 IRSB* emptyIRSB ( void ) 2193 { 2194 IRSB* bb = LibVEX_Alloc_inline(sizeof(IRSB)); 2195 bb->tyenv = emptyIRTypeEnv(); 2196 bb->stmts_used = 0; 2197 bb->stmts_size = 8; 2198 bb->stmts = LibVEX_Alloc_inline(bb->stmts_size * sizeof(IRStmt*)); 2199 bb->next = NULL; 2200 bb->jumpkind = Ijk_Boring; 2201 bb->offsIP = 0; 2202 return bb; 2203 } 2204 2205 2206 /*---------------------------------------------------------------*/ 2207 /*--- (Deep) copy constructors. These make complete copies ---*/ 2208 /*--- the original, which can be modified without affecting ---*/ 2209 /*--- the original. ---*/ 2210 /*---------------------------------------------------------------*/ 2211 2212 /* Copying IR Expr vectors (for call args). */ 2213 2214 /* Shallow copy of an IRExpr vector */ 2215 2216 IRExpr** shallowCopyIRExprVec ( IRExpr** vec ) 2217 { 2218 Int i; 2219 IRExpr** newvec; 2220 for (i = 0; vec[i]; i++) 2221 ; 2222 newvec = LibVEX_Alloc_inline((i+1)*sizeof(IRExpr*)); 2223 for (i = 0; vec[i]; i++) 2224 newvec[i] = vec[i]; 2225 newvec[i] = NULL; 2226 return newvec; 2227 } 2228 2229 /* Deep copy of an IRExpr vector */ 2230 2231 IRExpr** deepCopyIRExprVec ( IRExpr *const * vec ) 2232 { 2233 Int i; 2234 IRExpr** newvec; 2235 for (i = 0; vec[i]; i++) 2236 ; 2237 newvec = LibVEX_Alloc_inline((i+1)*sizeof(IRExpr*)); 2238 for (i = 0; vec[i]; i++) 2239 newvec[i] = deepCopyIRExpr(vec[i]); 2240 newvec[i] = NULL; 2241 return newvec; 2242 } 2243 2244 /* Deep copy constructors for all heap-allocated IR types follow. */ 2245 2246 IRConst* deepCopyIRConst ( const IRConst* c ) 2247 { 2248 switch (c->tag) { 2249 case Ico_U1: return IRConst_U1(c->Ico.U1); 2250 case Ico_U8: return IRConst_U8(c->Ico.U8); 2251 case Ico_U16: return IRConst_U16(c->Ico.U16); 2252 case Ico_U32: return IRConst_U32(c->Ico.U32); 2253 case Ico_U64: return IRConst_U64(c->Ico.U64); 2254 case Ico_F32: return IRConst_F32(c->Ico.F32); 2255 case Ico_F32i: return IRConst_F32i(c->Ico.F32i); 2256 case Ico_F64: return IRConst_F64(c->Ico.F64); 2257 case Ico_F64i: return IRConst_F64i(c->Ico.F64i); 2258 case Ico_V128: return IRConst_V128(c->Ico.V128); 2259 case Ico_V256: return IRConst_V256(c->Ico.V256); 2260 default: vpanic("deepCopyIRConst"); 2261 } 2262 } 2263 2264 IRCallee* deepCopyIRCallee ( const IRCallee* ce ) 2265 { 2266 IRCallee* ce2 = mkIRCallee(ce->regparms, ce->name, ce->addr); 2267 ce2->mcx_mask = ce->mcx_mask; 2268 return ce2; 2269 } 2270 2271 IRRegArray* deepCopyIRRegArray ( const IRRegArray* d ) 2272 { 2273 return mkIRRegArray(d->base, d->elemTy, d->nElems); 2274 } 2275 2276 IRExpr* deepCopyIRExpr ( const IRExpr* e ) 2277 { 2278 switch (e->tag) { 2279 case Iex_Get: 2280 return IRExpr_Get(e->Iex.Get.offset, e->Iex.Get.ty); 2281 case Iex_GetI: 2282 return IRExpr_GetI(deepCopyIRRegArray(e->Iex.GetI.descr), 2283 deepCopyIRExpr(e->Iex.GetI.ix), 2284 e->Iex.GetI.bias); 2285 case Iex_RdTmp: 2286 return IRExpr_RdTmp(e->Iex.RdTmp.tmp); 2287 case Iex_Qop: { 2288 const IRQop* qop = e->Iex.Qop.details; 2289 2290 return IRExpr_Qop(qop->op, 2291 deepCopyIRExpr(qop->arg1), 2292 deepCopyIRExpr(qop->arg2), 2293 deepCopyIRExpr(qop->arg3), 2294 deepCopyIRExpr(qop->arg4)); 2295 } 2296 case Iex_Triop: { 2297 const IRTriop *triop = e->Iex.Triop.details; 2298 2299 return IRExpr_Triop(triop->op, 2300 deepCopyIRExpr(triop->arg1), 2301 deepCopyIRExpr(triop->arg2), 2302 deepCopyIRExpr(triop->arg3)); 2303 } 2304 case Iex_Binop: 2305 return IRExpr_Binop(e->Iex.Binop.op, 2306 deepCopyIRExpr(e->Iex.Binop.arg1), 2307 deepCopyIRExpr(e->Iex.Binop.arg2)); 2308 case Iex_Unop: 2309 return IRExpr_Unop(e->Iex.Unop.op, 2310 deepCopyIRExpr(e->Iex.Unop.arg)); 2311 case Iex_Load: 2312 return IRExpr_Load(e->Iex.Load.end, 2313 e->Iex.Load.ty, 2314 deepCopyIRExpr(e->Iex.Load.addr)); 2315 case Iex_Const: 2316 return IRExpr_Const(deepCopyIRConst(e->Iex.Const.con)); 2317 case Iex_CCall: 2318 return IRExpr_CCall(deepCopyIRCallee(e->Iex.CCall.cee), 2319 e->Iex.CCall.retty, 2320 deepCopyIRExprVec(e->Iex.CCall.args)); 2321 2322 case Iex_ITE: 2323 return IRExpr_ITE(deepCopyIRExpr(e->Iex.ITE.cond), 2324 deepCopyIRExpr(e->Iex.ITE.iftrue), 2325 deepCopyIRExpr(e->Iex.ITE.iffalse)); 2326 case Iex_VECRET: 2327 return IRExpr_VECRET(); 2328 2329 case Iex_BBPTR: 2330 return IRExpr_BBPTR(); 2331 2332 case Iex_Binder: 2333 return IRExpr_Binder(e->Iex.Binder.binder); 2334 2335 default: 2336 vpanic("deepCopyIRExpr"); 2337 } 2338 } 2339 2340 IRDirty* deepCopyIRDirty ( const IRDirty* d ) 2341 { 2342 Int i; 2343 IRDirty* d2 = emptyIRDirty(); 2344 d2->cee = deepCopyIRCallee(d->cee); 2345 d2->guard = deepCopyIRExpr(d->guard); 2346 d2->args = deepCopyIRExprVec(d->args); 2347 d2->tmp = d->tmp; 2348 d2->mFx = d->mFx; 2349 d2->mAddr = d->mAddr==NULL ? NULL : deepCopyIRExpr(d->mAddr); 2350 d2->mSize = d->mSize; 2351 d2->nFxState = d->nFxState; 2352 for (i = 0; i < d2->nFxState; i++) 2353 d2->fxState[i] = d->fxState[i]; 2354 return d2; 2355 } 2356 2357 IRCAS* deepCopyIRCAS ( const IRCAS* cas ) 2358 { 2359 return mkIRCAS( cas->oldHi, cas->oldLo, cas->end, 2360 deepCopyIRExpr(cas->addr), 2361 cas->expdHi==NULL ? NULL : deepCopyIRExpr(cas->expdHi), 2362 deepCopyIRExpr(cas->expdLo), 2363 cas->dataHi==NULL ? NULL : deepCopyIRExpr(cas->dataHi), 2364 deepCopyIRExpr(cas->dataLo) ); 2365 } 2366 2367 IRPutI* deepCopyIRPutI ( const IRPutI * puti ) 2368 { 2369 return mkIRPutI( deepCopyIRRegArray(puti->descr), 2370 deepCopyIRExpr(puti->ix), 2371 puti->bias, 2372 deepCopyIRExpr(puti->data)); 2373 } 2374 2375 IRStmt* deepCopyIRStmt ( const IRStmt* s ) 2376 { 2377 switch (s->tag) { 2378 case Ist_NoOp: 2379 return IRStmt_NoOp(); 2380 case Ist_AbiHint: 2381 return IRStmt_AbiHint(deepCopyIRExpr(s->Ist.AbiHint.base), 2382 s->Ist.AbiHint.len, 2383 deepCopyIRExpr(s->Ist.AbiHint.nia)); 2384 case Ist_IMark: 2385 return IRStmt_IMark(s->Ist.IMark.addr, 2386 s->Ist.IMark.len, 2387 s->Ist.IMark.delta); 2388 case Ist_Put: 2389 return IRStmt_Put(s->Ist.Put.offset, 2390 deepCopyIRExpr(s->Ist.Put.data)); 2391 case Ist_PutI: 2392 return IRStmt_PutI(deepCopyIRPutI(s->Ist.PutI.details)); 2393 case Ist_WrTmp: 2394 return IRStmt_WrTmp(s->Ist.WrTmp.tmp, 2395 deepCopyIRExpr(s->Ist.WrTmp.data)); 2396 case Ist_Store: 2397 return IRStmt_Store(s->Ist.Store.end, 2398 deepCopyIRExpr(s->Ist.Store.addr), 2399 deepCopyIRExpr(s->Ist.Store.data)); 2400 case Ist_StoreG: { 2401 const IRStoreG* sg = s->Ist.StoreG.details; 2402 return IRStmt_StoreG(sg->end, 2403 deepCopyIRExpr(sg->addr), 2404 deepCopyIRExpr(sg->data), 2405 deepCopyIRExpr(sg->guard)); 2406 } 2407 case Ist_LoadG: { 2408 const IRLoadG* lg = s->Ist.LoadG.details; 2409 return IRStmt_LoadG(lg->end, lg->cvt, lg->dst, 2410 deepCopyIRExpr(lg->addr), 2411 deepCopyIRExpr(lg->alt), 2412 deepCopyIRExpr(lg->guard)); 2413 } 2414 case Ist_CAS: 2415 return IRStmt_CAS(deepCopyIRCAS(s->Ist.CAS.details)); 2416 case Ist_LLSC: 2417 return IRStmt_LLSC(s->Ist.LLSC.end, 2418 s->Ist.LLSC.result, 2419 deepCopyIRExpr(s->Ist.LLSC.addr), 2420 s->Ist.LLSC.storedata 2421 ? deepCopyIRExpr(s->Ist.LLSC.storedata) 2422 : NULL); 2423 case Ist_Dirty: 2424 return IRStmt_Dirty(deepCopyIRDirty(s->Ist.Dirty.details)); 2425 case Ist_MBE: 2426 return IRStmt_MBE(s->Ist.MBE.event); 2427 case Ist_Exit: 2428 return IRStmt_Exit(deepCopyIRExpr(s->Ist.Exit.guard), 2429 s->Ist.Exit.jk, 2430 deepCopyIRConst(s->Ist.Exit.dst), 2431 s->Ist.Exit.offsIP); 2432 default: 2433 vpanic("deepCopyIRStmt"); 2434 } 2435 } 2436 2437 IRTypeEnv* deepCopyIRTypeEnv ( const IRTypeEnv* src ) 2438 { 2439 Int i; 2440 IRTypeEnv* dst = LibVEX_Alloc_inline(sizeof(IRTypeEnv)); 2441 dst->types_size = src->types_size; 2442 dst->types_used = src->types_used; 2443 dst->types = LibVEX_Alloc_inline(dst->types_size * sizeof(IRType)); 2444 for (i = 0; i < src->types_used; i++) 2445 dst->types[i] = src->types[i]; 2446 return dst; 2447 } 2448 2449 IRSB* deepCopyIRSB ( const IRSB* bb ) 2450 { 2451 Int i; 2452 IRStmt** sts2; 2453 IRSB* bb2 = deepCopyIRSBExceptStmts(bb); 2454 bb2->stmts_used = bb2->stmts_size = bb->stmts_used; 2455 sts2 = LibVEX_Alloc_inline(bb2->stmts_used * sizeof(IRStmt*)); 2456 for (i = 0; i < bb2->stmts_used; i++) 2457 sts2[i] = deepCopyIRStmt(bb->stmts[i]); 2458 bb2->stmts = sts2; 2459 return bb2; 2460 } 2461 2462 IRSB* deepCopyIRSBExceptStmts ( const IRSB* bb ) 2463 { 2464 IRSB* bb2 = emptyIRSB(); 2465 bb2->tyenv = deepCopyIRTypeEnv(bb->tyenv); 2466 bb2->next = deepCopyIRExpr(bb->next); 2467 bb2->jumpkind = bb->jumpkind; 2468 bb2->offsIP = bb->offsIP; 2469 return bb2; 2470 } 2471 2472 2473 /*---------------------------------------------------------------*/ 2474 /*--- Primop types ---*/ 2475 /*---------------------------------------------------------------*/ 2476 2477 void typeOfPrimop ( IROp op, 2478 /*OUTs*/ 2479 IRType* t_dst, 2480 IRType* t_arg1, IRType* t_arg2, 2481 IRType* t_arg3, IRType* t_arg4 ) 2482 { 2483 # define UNARY(_ta1,_td) \ 2484 *t_dst = (_td); *t_arg1 = (_ta1); break 2485 # define BINARY(_ta1,_ta2,_td) \ 2486 *t_dst = (_td); *t_arg1 = (_ta1); *t_arg2 = (_ta2); break 2487 # define TERNARY(_ta1,_ta2,_ta3,_td) \ 2488 *t_dst = (_td); *t_arg1 = (_ta1); \ 2489 *t_arg2 = (_ta2); *t_arg3 = (_ta3); break 2490 # define QUATERNARY(_ta1,_ta2,_ta3,_ta4,_td) \ 2491 *t_dst = (_td); *t_arg1 = (_ta1); \ 2492 *t_arg2 = (_ta2); *t_arg3 = (_ta3); \ 2493 *t_arg4 = (_ta4); break 2494 # define COMPARISON(_ta) \ 2495 *t_dst = Ity_I1; *t_arg1 = *t_arg2 = (_ta); break; 2496 # define UNARY_COMPARISON(_ta) \ 2497 *t_dst = Ity_I1; *t_arg1 = (_ta); break; 2498 2499 /* Rounding mode values are always Ity_I32, encoded as per 2500 IRRoundingMode */ 2501 const IRType ity_RMode = Ity_I32; 2502 2503 *t_dst = Ity_INVALID; 2504 *t_arg1 = Ity_INVALID; 2505 *t_arg2 = Ity_INVALID; 2506 *t_arg3 = Ity_INVALID; 2507 *t_arg4 = Ity_INVALID; 2508 switch (op) { 2509 case Iop_Add8: case Iop_Sub8: case Iop_Mul8: 2510 case Iop_Or8: case Iop_And8: case Iop_Xor8: 2511 BINARY(Ity_I8,Ity_I8, Ity_I8); 2512 2513 case Iop_Add16: case Iop_Sub16: case Iop_Mul16: 2514 case Iop_Or16: case Iop_And16: case Iop_Xor16: 2515 BINARY(Ity_I16,Ity_I16, Ity_I16); 2516 2517 case Iop_CmpORD32U: 2518 case Iop_CmpORD32S: 2519 case Iop_Add32: case Iop_Sub32: case Iop_Mul32: 2520 case Iop_Or32: case Iop_And32: case Iop_Xor32: 2521 case Iop_Max32U: 2522 case Iop_QAdd32S: case Iop_QSub32S: 2523 case Iop_Add16x2: case Iop_Sub16x2: 2524 case Iop_QAdd16Sx2: case Iop_QAdd16Ux2: 2525 case Iop_QSub16Sx2: case Iop_QSub16Ux2: 2526 case Iop_HAdd16Ux2: case Iop_HAdd16Sx2: 2527 case Iop_HSub16Ux2: case Iop_HSub16Sx2: 2528 case Iop_Add8x4: case Iop_Sub8x4: 2529 case Iop_QAdd8Sx4: case Iop_QAdd8Ux4: 2530 case Iop_QSub8Sx4: case Iop_QSub8Ux4: 2531 case Iop_HAdd8Ux4: case Iop_HAdd8Sx4: 2532 case Iop_HSub8Ux4: case Iop_HSub8Sx4: 2533 case Iop_Sad8Ux4: 2534 BINARY(Ity_I32,Ity_I32, Ity_I32); 2535 2536 case Iop_Add64: case Iop_Sub64: case Iop_Mul64: 2537 case Iop_Or64: case Iop_And64: case Iop_Xor64: 2538 case Iop_CmpORD64U: 2539 case Iop_CmpORD64S: 2540 case Iop_Avg8Ux8: case Iop_Avg16Ux4: 2541 case Iop_Add8x8: case Iop_Add16x4: case Iop_Add32x2: 2542 case Iop_Add32Fx2: case Iop_Sub32Fx2: 2543 case Iop_CmpEQ8x8: case Iop_CmpEQ16x4: case Iop_CmpEQ32x2: 2544 case Iop_CmpGT8Sx8: case Iop_CmpGT16Sx4: case Iop_CmpGT32Sx2: 2545 case Iop_CmpGT8Ux8: case Iop_CmpGT16Ux4: case Iop_CmpGT32Ux2: 2546 case Iop_CmpGT32Fx2: case Iop_CmpEQ32Fx2: case Iop_CmpGE32Fx2: 2547 case Iop_InterleaveHI8x8: case Iop_InterleaveLO8x8: 2548 case Iop_InterleaveHI16x4: case Iop_InterleaveLO16x4: 2549 case Iop_InterleaveHI32x2: case Iop_InterleaveLO32x2: 2550 case Iop_CatOddLanes8x8: case Iop_CatEvenLanes8x8: 2551 case Iop_CatOddLanes16x4: case Iop_CatEvenLanes16x4: 2552 case Iop_InterleaveOddLanes8x8: case Iop_InterleaveEvenLanes8x8: 2553 case Iop_InterleaveOddLanes16x4: case Iop_InterleaveEvenLanes16x4: 2554 case Iop_Perm8x8: 2555 case Iop_Max8Ux8: case Iop_Max16Ux4: case Iop_Max32Ux2: 2556 case Iop_Max8Sx8: case Iop_Max16Sx4: case Iop_Max32Sx2: 2557 case Iop_Max32Fx2: case Iop_Min32Fx2: 2558 case Iop_PwMax32Fx2: case Iop_PwMin32Fx2: 2559 case Iop_Min8Ux8: case Iop_Min16Ux4: case Iop_Min32Ux2: 2560 case Iop_Min8Sx8: case Iop_Min16Sx4: case Iop_Min32Sx2: 2561 case Iop_PwMax8Ux8: case Iop_PwMax16Ux4: case Iop_PwMax32Ux2: 2562 case Iop_PwMax8Sx8: case Iop_PwMax16Sx4: case Iop_PwMax32Sx2: 2563 case Iop_PwMin8Ux8: case Iop_PwMin16Ux4: case Iop_PwMin32Ux2: 2564 case Iop_PwMin8Sx8: case Iop_PwMin16Sx4: case Iop_PwMin32Sx2: 2565 case Iop_Mul8x8: case Iop_Mul16x4: case Iop_Mul32x2: 2566 case Iop_Mul32Fx2: 2567 case Iop_PolynomialMul8x8: 2568 case Iop_MulHi16Sx4: case Iop_MulHi16Ux4: 2569 case Iop_QDMulHi16Sx4: case Iop_QDMulHi32Sx2: 2570 case Iop_QRDMulHi16Sx4: case Iop_QRDMulHi32Sx2: 2571 case Iop_QAdd8Sx8: case Iop_QAdd16Sx4: 2572 case Iop_QAdd32Sx2: case Iop_QAdd64Sx1: 2573 case Iop_QAdd8Ux8: case Iop_QAdd16Ux4: 2574 case Iop_QAdd32Ux2: case Iop_QAdd64Ux1: 2575 case Iop_PwAdd8x8: case Iop_PwAdd16x4: case Iop_PwAdd32x2: 2576 case Iop_PwAdd32Fx2: 2577 case Iop_QNarrowBin32Sto16Sx4: 2578 case Iop_QNarrowBin16Sto8Sx8: case Iop_QNarrowBin16Sto8Ux8: 2579 case Iop_NarrowBin16to8x8: case Iop_NarrowBin32to16x4: 2580 case Iop_Sub8x8: case Iop_Sub16x4: case Iop_Sub32x2: 2581 case Iop_QSub8Sx8: case Iop_QSub16Sx4: 2582 case Iop_QSub32Sx2: case Iop_QSub64Sx1: 2583 case Iop_QSub8Ux8: case Iop_QSub16Ux4: 2584 case Iop_QSub32Ux2: case Iop_QSub64Ux1: 2585 case Iop_Shl8x8: case Iop_Shl16x4: case Iop_Shl32x2: 2586 case Iop_Shr8x8: case Iop_Shr16x4: case Iop_Shr32x2: 2587 case Iop_Sar8x8: case Iop_Sar16x4: case Iop_Sar32x2: 2588 case Iop_Sal8x8: case Iop_Sal16x4: case Iop_Sal32x2: case Iop_Sal64x1: 2589 case Iop_QShl8x8: case Iop_QShl16x4: case Iop_QShl32x2: case Iop_QShl64x1: 2590 case Iop_QSal8x8: case Iop_QSal16x4: case Iop_QSal32x2: case Iop_QSal64x1: 2591 case Iop_RecipStep32Fx2: 2592 case Iop_RSqrtStep32Fx2: 2593 BINARY(Ity_I64,Ity_I64, Ity_I64); 2594 2595 case Iop_ShlN32x2: case Iop_ShlN16x4: case Iop_ShlN8x8: 2596 case Iop_ShrN32x2: case Iop_ShrN16x4: case Iop_ShrN8x8: 2597 case Iop_SarN32x2: case Iop_SarN16x4: case Iop_SarN8x8: 2598 case Iop_QShlNsatUU8x8: case Iop_QShlNsatUU16x4: 2599 case Iop_QShlNsatUU32x2: case Iop_QShlNsatUU64x1: 2600 case Iop_QShlNsatSU8x8: case Iop_QShlNsatSU16x4: 2601 case Iop_QShlNsatSU32x2: case Iop_QShlNsatSU64x1: 2602 case Iop_QShlNsatSS8x8: case Iop_QShlNsatSS16x4: 2603 case Iop_QShlNsatSS32x2: case Iop_QShlNsatSS64x1: 2604 BINARY(Ity_I64,Ity_I8, Ity_I64); 2605 2606 case Iop_Shl8: case Iop_Shr8: case Iop_Sar8: 2607 BINARY(Ity_I8,Ity_I8, Ity_I8); 2608 case Iop_Shl16: case Iop_Shr16: case Iop_Sar16: 2609 BINARY(Ity_I16,Ity_I8, Ity_I16); 2610 case Iop_Shl32: case Iop_Shr32: case Iop_Sar32: 2611 BINARY(Ity_I32,Ity_I8, Ity_I32); 2612 case Iop_Shl64: case Iop_Shr64: case Iop_Sar64: 2613 BINARY(Ity_I64,Ity_I8, Ity_I64); 2614 2615 case Iop_Not8: 2616 UNARY(Ity_I8, Ity_I8); 2617 case Iop_Not16: 2618 UNARY(Ity_I16, Ity_I16); 2619 case Iop_Not32: 2620 case Iop_CmpNEZ16x2: case Iop_CmpNEZ8x4: 2621 UNARY(Ity_I32, Ity_I32); 2622 2623 case Iop_Not64: 2624 case Iop_CmpNEZ32x2: case Iop_CmpNEZ16x4: case Iop_CmpNEZ8x8: 2625 case Iop_Cnt8x8: 2626 case Iop_Clz8x8: case Iop_Clz16x4: case Iop_Clz32x2: 2627 case Iop_Cls8x8: case Iop_Cls16x4: case Iop_Cls32x2: 2628 case Iop_PwAddL8Ux8: case Iop_PwAddL16Ux4: case Iop_PwAddL32Ux2: 2629 case Iop_PwAddL8Sx8: case Iop_PwAddL16Sx4: case Iop_PwAddL32Sx2: 2630 case Iop_Reverse8sIn64_x1: case Iop_Reverse16sIn64_x1: 2631 case Iop_Reverse32sIn64_x1: 2632 case Iop_Reverse8sIn32_x2: case Iop_Reverse16sIn32_x2: 2633 case Iop_Reverse8sIn16_x4: 2634 case Iop_FtoI32Sx2_RZ: case Iop_FtoI32Ux2_RZ: 2635 case Iop_I32StoFx2: case Iop_I32UtoFx2: 2636 case Iop_RecipEst32Ux2: case Iop_RecipEst32Fx2: 2637 case Iop_Abs32Fx2: 2638 case Iop_RSqrtEst32Fx2: 2639 case Iop_RSqrtEst32Ux2: 2640 case Iop_Neg32Fx2: 2641 case Iop_Abs8x8: case Iop_Abs16x4: case Iop_Abs32x2: 2642 UNARY(Ity_I64, Ity_I64); 2643 2644 case Iop_CmpEQ8: case Iop_CmpNE8: 2645 case Iop_CasCmpEQ8: case Iop_CasCmpNE8: case Iop_ExpCmpNE8: 2646 COMPARISON(Ity_I8); 2647 case Iop_CmpEQ16: case Iop_CmpNE16: 2648 case Iop_CasCmpEQ16: case Iop_CasCmpNE16: case Iop_ExpCmpNE16: 2649 COMPARISON(Ity_I16); 2650 case Iop_CmpEQ32: case Iop_CmpNE32: 2651 case Iop_CasCmpEQ32: case Iop_CasCmpNE32: case Iop_ExpCmpNE32: 2652 case Iop_CmpLT32S: case Iop_CmpLE32S: 2653 case Iop_CmpLT32U: case Iop_CmpLE32U: 2654 COMPARISON(Ity_I32); 2655 case Iop_CmpEQ64: case Iop_CmpNE64: 2656 case Iop_CasCmpEQ64: case Iop_CasCmpNE64: case Iop_ExpCmpNE64: 2657 case Iop_CmpLT64S: case Iop_CmpLE64S: 2658 case Iop_CmpLT64U: case Iop_CmpLE64U: 2659 COMPARISON(Ity_I64); 2660 2661 case Iop_CmpNEZ8: UNARY_COMPARISON(Ity_I8); 2662 case Iop_CmpNEZ16: UNARY_COMPARISON(Ity_I16); 2663 case Iop_CmpNEZ32: UNARY_COMPARISON(Ity_I32); 2664 case Iop_CmpNEZ64: UNARY_COMPARISON(Ity_I64); 2665 2666 case Iop_Left8: UNARY(Ity_I8, Ity_I8); 2667 case Iop_Left16: UNARY(Ity_I16,Ity_I16); 2668 case Iop_CmpwNEZ32: case Iop_Left32: UNARY(Ity_I32,Ity_I32); 2669 case Iop_CmpwNEZ64: case Iop_Left64: UNARY(Ity_I64,Ity_I64); 2670 2671 case Iop_GetMSBs8x8: UNARY(Ity_I64, Ity_I8); 2672 case Iop_GetMSBs8x16: UNARY(Ity_V128, Ity_I16); 2673 2674 case Iop_MullU8: case Iop_MullS8: 2675 BINARY(Ity_I8,Ity_I8, Ity_I16); 2676 case Iop_MullU16: case Iop_MullS16: 2677 BINARY(Ity_I16,Ity_I16, Ity_I32); 2678 case Iop_MullU32: case Iop_MullS32: 2679 BINARY(Ity_I32,Ity_I32, Ity_I64); 2680 case Iop_MullU64: case Iop_MullS64: 2681 BINARY(Ity_I64,Ity_I64, Ity_I128); 2682 2683 case Iop_Clz32: case Iop_Ctz32: 2684 UNARY(Ity_I32, Ity_I32); 2685 2686 case Iop_Clz64: case Iop_Ctz64: 2687 UNARY(Ity_I64, Ity_I64); 2688 2689 case Iop_DivU32: case Iop_DivS32: case Iop_DivU32E: case Iop_DivS32E: 2690 BINARY(Ity_I32,Ity_I32, Ity_I32); 2691 2692 case Iop_DivU64: case Iop_DivS64: case Iop_DivS64E: case Iop_DivU64E: 2693 BINARY(Ity_I64,Ity_I64, Ity_I64); 2694 2695 case Iop_DivModU64to32: case Iop_DivModS64to32: 2696 BINARY(Ity_I64,Ity_I32, Ity_I64); 2697 2698 case Iop_DivModU128to64: case Iop_DivModS128to64: 2699 BINARY(Ity_I128,Ity_I64, Ity_I128); 2700 2701 case Iop_DivModS64to64: 2702 BINARY(Ity_I64,Ity_I64, Ity_I128); 2703 2704 case Iop_16HIto8: case Iop_16to8: 2705 UNARY(Ity_I16, Ity_I8); 2706 case Iop_8HLto16: 2707 BINARY(Ity_I8,Ity_I8, Ity_I16); 2708 2709 case Iop_32HIto16: case Iop_32to16: 2710 UNARY(Ity_I32, Ity_I16); 2711 case Iop_16HLto32: 2712 BINARY(Ity_I16,Ity_I16, Ity_I32); 2713 2714 case Iop_64HIto32: case Iop_64to32: 2715 UNARY(Ity_I64, Ity_I32); 2716 case Iop_32HLto64: 2717 BINARY(Ity_I32,Ity_I32, Ity_I64); 2718 2719 case Iop_128HIto64: case Iop_128to64: 2720 UNARY(Ity_I128, Ity_I64); 2721 case Iop_64HLto128: 2722 BINARY(Ity_I64,Ity_I64, Ity_I128); 2723 2724 case Iop_Not1: UNARY(Ity_I1, Ity_I1); 2725 case Iop_1Uto8: UNARY(Ity_I1, Ity_I8); 2726 case Iop_1Sto8: UNARY(Ity_I1, Ity_I8); 2727 case Iop_1Sto16: UNARY(Ity_I1, Ity_I16); 2728 case Iop_1Uto32: case Iop_1Sto32: UNARY(Ity_I1, Ity_I32); 2729 case Iop_1Sto64: case Iop_1Uto64: UNARY(Ity_I1, Ity_I64); 2730 case Iop_32to1: UNARY(Ity_I32, Ity_I1); 2731 case Iop_64to1: UNARY(Ity_I64, Ity_I1); 2732 2733 case Iop_8Uto32: case Iop_8Sto32: 2734 UNARY(Ity_I8, Ity_I32); 2735 2736 case Iop_8Uto16: case Iop_8Sto16: 2737 UNARY(Ity_I8, Ity_I16); 2738 2739 case Iop_16Uto32: case Iop_16Sto32: 2740 UNARY(Ity_I16, Ity_I32); 2741 2742 case Iop_32Sto64: case Iop_32Uto64: 2743 UNARY(Ity_I32, Ity_I64); 2744 2745 case Iop_8Uto64: case Iop_8Sto64: 2746 UNARY(Ity_I8, Ity_I64); 2747 2748 case Iop_16Uto64: case Iop_16Sto64: 2749 UNARY(Ity_I16, Ity_I64); 2750 case Iop_64to16: 2751 UNARY(Ity_I64, Ity_I16); 2752 2753 case Iop_32to8: UNARY(Ity_I32, Ity_I8); 2754 case Iop_64to8: UNARY(Ity_I64, Ity_I8); 2755 2756 case Iop_AddF64: case Iop_SubF64: 2757 case Iop_MulF64: case Iop_DivF64: 2758 case Iop_AddF64r32: case Iop_SubF64r32: 2759 case Iop_MulF64r32: case Iop_DivF64r32: 2760 TERNARY(ity_RMode,Ity_F64,Ity_F64, Ity_F64); 2761 2762 case Iop_AddF32: case Iop_SubF32: 2763 case Iop_MulF32: case Iop_DivF32: 2764 TERNARY(ity_RMode,Ity_F32,Ity_F32, Ity_F32); 2765 2766 case Iop_NegF64: case Iop_AbsF64: 2767 UNARY(Ity_F64, Ity_F64); 2768 2769 case Iop_NegF32: case Iop_AbsF32: 2770 UNARY(Ity_F32, Ity_F32); 2771 2772 case Iop_SqrtF64: 2773 case Iop_RecpExpF64: 2774 BINARY(ity_RMode,Ity_F64, Ity_F64); 2775 2776 case Iop_SqrtF32: 2777 case Iop_RoundF32toInt: 2778 case Iop_RecpExpF32: 2779 BINARY(ity_RMode,Ity_F32, Ity_F32); 2780 2781 case Iop_CmpF32: 2782 BINARY(Ity_F32,Ity_F32, Ity_I32); 2783 2784 case Iop_CmpF64: 2785 BINARY(Ity_F64,Ity_F64, Ity_I32); 2786 2787 case Iop_CmpF128: 2788 BINARY(Ity_F128,Ity_F128, Ity_I32); 2789 2790 case Iop_F64toI16S: BINARY(ity_RMode,Ity_F64, Ity_I16); 2791 case Iop_F64toI32S: BINARY(ity_RMode,Ity_F64, Ity_I32); 2792 case Iop_F64toI64S: case Iop_F64toI64U: 2793 BINARY(ity_RMode,Ity_F64, Ity_I64); 2794 2795 case Iop_F64toI32U: BINARY(ity_RMode,Ity_F64, Ity_I32); 2796 2797 case Iop_I32StoF64: UNARY(Ity_I32, Ity_F64); 2798 case Iop_I64StoF64: BINARY(ity_RMode,Ity_I64, Ity_F64); 2799 case Iop_I64UtoF64: BINARY(ity_RMode,Ity_I64, Ity_F64); 2800 case Iop_I64UtoF32: BINARY(ity_RMode,Ity_I64, Ity_F32); 2801 2802 case Iop_I32UtoF64: UNARY(Ity_I32, Ity_F64); 2803 2804 case Iop_F32toI32S: BINARY(ity_RMode,Ity_F32, Ity_I32); 2805 case Iop_F32toI64S: BINARY(ity_RMode,Ity_F32, Ity_I64); 2806 case Iop_F32toI32U: BINARY(ity_RMode,Ity_F32, Ity_I32); 2807 case Iop_F32toI64U: BINARY(ity_RMode,Ity_F32, Ity_I64); 2808 2809 case Iop_I32UtoF32: BINARY(ity_RMode,Ity_I32, Ity_F32); 2810 case Iop_I32StoF32: BINARY(ity_RMode,Ity_I32, Ity_F32); 2811 case Iop_I64StoF32: BINARY(ity_RMode,Ity_I64, Ity_F32); 2812 2813 case Iop_F32toF64: UNARY(Ity_F32, Ity_F64); 2814 case Iop_F16toF64: UNARY(Ity_F16, Ity_F64); 2815 case Iop_F16toF32: UNARY(Ity_F16, Ity_F32); 2816 2817 case Iop_F64toF32: BINARY(ity_RMode,Ity_F64, Ity_F32); 2818 case Iop_F64toF16: BINARY(ity_RMode,Ity_F64, Ity_F16); 2819 case Iop_F32toF16: BINARY(ity_RMode,Ity_F32, Ity_F16); 2820 2821 case Iop_ReinterpI64asF64: UNARY(Ity_I64, Ity_F64); 2822 case Iop_ReinterpF64asI64: UNARY(Ity_F64, Ity_I64); 2823 case Iop_ReinterpI32asF32: UNARY(Ity_I32, Ity_F32); 2824 case Iop_ReinterpF32asI32: UNARY(Ity_F32, Ity_I32); 2825 2826 case Iop_AtanF64: case Iop_Yl2xF64: case Iop_Yl2xp1F64: 2827 case Iop_ScaleF64: case Iop_PRemF64: case Iop_PRem1F64: 2828 TERNARY(ity_RMode,Ity_F64,Ity_F64, Ity_F64); 2829 2830 case Iop_PRemC3210F64: case Iop_PRem1C3210F64: 2831 TERNARY(ity_RMode,Ity_F64,Ity_F64, Ity_I32); 2832 2833 case Iop_SinF64: case Iop_CosF64: case Iop_TanF64: 2834 case Iop_2xm1F64: 2835 case Iop_RoundF64toInt: BINARY(ity_RMode,Ity_F64, Ity_F64); 2836 2837 case Iop_MAddF64: case Iop_MSubF64: 2838 case Iop_MAddF64r32: case Iop_MSubF64r32: 2839 QUATERNARY(ity_RMode,Ity_F64,Ity_F64,Ity_F64, Ity_F64); 2840 2841 case Iop_RSqrtEst5GoodF64: 2842 case Iop_RoundF64toF64_NEAREST: case Iop_RoundF64toF64_NegINF: 2843 case Iop_RoundF64toF64_PosINF: case Iop_RoundF64toF64_ZERO: 2844 UNARY(Ity_F64, Ity_F64); 2845 case Iop_RoundF64toF32: 2846 BINARY(ity_RMode,Ity_F64, Ity_F64); 2847 case Iop_TruncF64asF32: 2848 UNARY(Ity_F64, Ity_F32); 2849 2850 case Iop_I32UtoFx4: 2851 case Iop_I32StoFx4: 2852 case Iop_QFtoI32Ux4_RZ: 2853 case Iop_QFtoI32Sx4_RZ: 2854 case Iop_FtoI32Ux4_RZ: 2855 case Iop_FtoI32Sx4_RZ: 2856 case Iop_RoundF32x4_RM: 2857 case Iop_RoundF32x4_RP: 2858 case Iop_RoundF32x4_RN: 2859 case Iop_RoundF32x4_RZ: 2860 case Iop_Abs64Fx2: case Iop_Abs32Fx4: 2861 case Iop_RSqrtEst32Fx4: 2862 case Iop_RSqrtEst32Ux4: 2863 UNARY(Ity_V128, Ity_V128); 2864 2865 case Iop_Sqrt64Fx2: 2866 case Iop_Sqrt32Fx4: 2867 BINARY(ity_RMode,Ity_V128, Ity_V128); 2868 2869 case Iop_64HLtoV128: 2870 BINARY(Ity_I64,Ity_I64, Ity_V128); 2871 2872 case Iop_V128to64: case Iop_V128HIto64: 2873 case Iop_NarrowUn16to8x8: 2874 case Iop_NarrowUn32to16x4: 2875 case Iop_NarrowUn64to32x2: 2876 case Iop_QNarrowUn16Uto8Ux8: 2877 case Iop_QNarrowUn32Uto16Ux4: 2878 case Iop_QNarrowUn64Uto32Ux2: 2879 case Iop_QNarrowUn16Sto8Sx8: 2880 case Iop_QNarrowUn32Sto16Sx4: 2881 case Iop_QNarrowUn64Sto32Sx2: 2882 case Iop_QNarrowUn16Sto8Ux8: 2883 case Iop_QNarrowUn32Sto16Ux4: 2884 case Iop_QNarrowUn64Sto32Ux2: 2885 case Iop_F32toF16x4: 2886 UNARY(Ity_V128, Ity_I64); 2887 2888 case Iop_Widen8Uto16x8: 2889 case Iop_Widen16Uto32x4: 2890 case Iop_Widen32Uto64x2: 2891 case Iop_Widen8Sto16x8: 2892 case Iop_Widen16Sto32x4: 2893 case Iop_Widen32Sto64x2: 2894 case Iop_F16toF32x4: 2895 UNARY(Ity_I64, Ity_V128); 2896 2897 case Iop_V128to32: UNARY(Ity_V128, Ity_I32); 2898 case Iop_32UtoV128: UNARY(Ity_I32, Ity_V128); 2899 case Iop_64UtoV128: UNARY(Ity_I64, Ity_V128); 2900 case Iop_SetV128lo32: BINARY(Ity_V128,Ity_I32, Ity_V128); 2901 case Iop_SetV128lo64: BINARY(Ity_V128,Ity_I64, Ity_V128); 2902 2903 case Iop_Dup8x16: UNARY(Ity_I8, Ity_V128); 2904 case Iop_Dup16x8: UNARY(Ity_I16, Ity_V128); 2905 case Iop_Dup32x4: UNARY(Ity_I32, Ity_V128); 2906 case Iop_Dup8x8: UNARY(Ity_I8, Ity_I64); 2907 case Iop_Dup16x4: UNARY(Ity_I16, Ity_I64); 2908 case Iop_Dup32x2: UNARY(Ity_I32, Ity_I64); 2909 2910 case Iop_CmpEQ32Fx4: case Iop_CmpLT32Fx4: 2911 case Iop_CmpEQ64Fx2: case Iop_CmpLT64Fx2: 2912 case Iop_CmpLE32Fx4: case Iop_CmpUN32Fx4: 2913 case Iop_CmpLE64Fx2: case Iop_CmpUN64Fx2: 2914 case Iop_CmpGT32Fx4: case Iop_CmpGE32Fx4: 2915 case Iop_CmpEQ32F0x4: case Iop_CmpLT32F0x4: 2916 case Iop_CmpEQ64F0x2: case Iop_CmpLT64F0x2: 2917 case Iop_CmpLE32F0x4: case Iop_CmpUN32F0x4: 2918 case Iop_CmpLE64F0x2: case Iop_CmpUN64F0x2: 2919 case Iop_Add32F0x4: 2920 case Iop_Add64F0x2: 2921 case Iop_Div32F0x4: 2922 case Iop_Div64F0x2: 2923 case Iop_Max32Fx4: case Iop_Max32F0x4: 2924 case Iop_PwMax32Fx4: case Iop_PwMin32Fx4: 2925 case Iop_Max64Fx2: case Iop_Max64F0x2: 2926 case Iop_Min32Fx4: case Iop_Min32F0x4: 2927 case Iop_Min64Fx2: case Iop_Min64F0x2: 2928 case Iop_Mul32F0x4: 2929 case Iop_Mul64F0x2: 2930 case Iop_Sub32F0x4: 2931 case Iop_Sub64F0x2: 2932 case Iop_AndV128: case Iop_OrV128: case Iop_XorV128: 2933 case Iop_Add8x16: case Iop_Add16x8: 2934 case Iop_Add32x4: case Iop_Add64x2: 2935 case Iop_QAdd8Ux16: case Iop_QAdd16Ux8: 2936 case Iop_QAdd32Ux4: case Iop_QAdd64Ux2: 2937 case Iop_QAdd8Sx16: case Iop_QAdd16Sx8: 2938 case Iop_QAdd32Sx4: case Iop_QAdd64Sx2: 2939 case Iop_QAddExtUSsatSS8x16: case Iop_QAddExtUSsatSS16x8: 2940 case Iop_QAddExtUSsatSS32x4: case Iop_QAddExtUSsatSS64x2: 2941 case Iop_QAddExtSUsatUU8x16: case Iop_QAddExtSUsatUU16x8: 2942 case Iop_QAddExtSUsatUU32x4: case Iop_QAddExtSUsatUU64x2: 2943 case Iop_PwAdd8x16: case Iop_PwAdd16x8: case Iop_PwAdd32x4: 2944 case Iop_Sub8x16: case Iop_Sub16x8: 2945 case Iop_Sub32x4: case Iop_Sub64x2: 2946 case Iop_QSub8Ux16: case Iop_QSub16Ux8: 2947 case Iop_QSub32Ux4: case Iop_QSub64Ux2: 2948 case Iop_QSub8Sx16: case Iop_QSub16Sx8: 2949 case Iop_QSub32Sx4: case Iop_QSub64Sx2: 2950 case Iop_Mul8x16: case Iop_Mul16x8: case Iop_Mul32x4: 2951 case Iop_PolynomialMul8x16: 2952 case Iop_PolynomialMulAdd8x16: case Iop_PolynomialMulAdd16x8: 2953 case Iop_PolynomialMulAdd32x4: case Iop_PolynomialMulAdd64x2: 2954 case Iop_MulHi16Ux8: case Iop_MulHi32Ux4: 2955 case Iop_MulHi16Sx8: case Iop_MulHi32Sx4: 2956 case Iop_QDMulHi16Sx8: case Iop_QDMulHi32Sx4: 2957 case Iop_QRDMulHi16Sx8: case Iop_QRDMulHi32Sx4: 2958 case Iop_MullEven8Ux16: case Iop_MullEven16Ux8: case Iop_MullEven32Ux4: 2959 case Iop_MullEven8Sx16: case Iop_MullEven16Sx8: case Iop_MullEven32Sx4: 2960 case Iop_Avg8Ux16: case Iop_Avg16Ux8: case Iop_Avg32Ux4: 2961 case Iop_Avg8Sx16: case Iop_Avg16Sx8: case Iop_Avg32Sx4: 2962 case Iop_Max8Sx16: case Iop_Max16Sx8: case Iop_Max32Sx4: 2963 case Iop_Max64Sx2: 2964 case Iop_Max8Ux16: case Iop_Max16Ux8: case Iop_Max32Ux4: 2965 case Iop_Max64Ux2: 2966 case Iop_Min8Sx16: case Iop_Min16Sx8: case Iop_Min32Sx4: 2967 case Iop_Min64Sx2: 2968 case Iop_Min8Ux16: case Iop_Min16Ux8: case Iop_Min32Ux4: 2969 case Iop_Min64Ux2: 2970 case Iop_CmpEQ8x16: case Iop_CmpEQ16x8: case Iop_CmpEQ32x4: 2971 case Iop_CmpEQ64x2: 2972 case Iop_CmpGT8Sx16: case Iop_CmpGT16Sx8: case Iop_CmpGT32Sx4: 2973 case Iop_CmpGT64Sx2: 2974 case Iop_CmpGT8Ux16: case Iop_CmpGT16Ux8: case Iop_CmpGT32Ux4: 2975 case Iop_CmpGT64Ux2: 2976 case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4: case Iop_Shl64x2: 2977 case Iop_QShl8x16: case Iop_QShl16x8: 2978 case Iop_QShl32x4: case Iop_QShl64x2: 2979 case Iop_QSal8x16: case Iop_QSal16x8: 2980 case Iop_QSal32x4: case Iop_QSal64x2: 2981 case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4: case Iop_Shr64x2: 2982 case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4: case Iop_Sar64x2: 2983 case Iop_Sal8x16: case Iop_Sal16x8: case Iop_Sal32x4: case Iop_Sal64x2: 2984 case Iop_Rol8x16: case Iop_Rol16x8: case Iop_Rol32x4:case Iop_Rol64x2: 2985 case Iop_QNarrowBin16Sto8Ux16: case Iop_QNarrowBin32Sto16Ux8: 2986 case Iop_QNarrowBin16Sto8Sx16: case Iop_QNarrowBin32Sto16Sx8: 2987 case Iop_QNarrowBin16Uto8Ux16: case Iop_QNarrowBin32Uto16Ux8: 2988 case Iop_QNarrowBin64Sto32Sx4: case Iop_QNarrowBin64Uto32Ux4: 2989 case Iop_NarrowBin16to8x16: case Iop_NarrowBin32to16x8: 2990 case Iop_NarrowBin64to32x4: 2991 case Iop_InterleaveHI8x16: case Iop_InterleaveHI16x8: 2992 case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2: 2993 case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8: 2994 case Iop_InterleaveLO32x4: case Iop_InterleaveLO64x2: 2995 case Iop_CatOddLanes8x16: case Iop_CatEvenLanes8x16: 2996 case Iop_CatOddLanes16x8: case Iop_CatEvenLanes16x8: 2997 case Iop_CatOddLanes32x4: case Iop_CatEvenLanes32x4: 2998 case Iop_InterleaveOddLanes8x16: case Iop_InterleaveEvenLanes8x16: 2999 case Iop_InterleaveOddLanes16x8: case Iop_InterleaveEvenLanes16x8: 3000 case Iop_InterleaveOddLanes32x4: case Iop_InterleaveEvenLanes32x4: 3001 case Iop_Perm8x16: case Iop_Perm32x4: 3002 case Iop_RecipStep32Fx4: case Iop_RecipStep64Fx2: 3003 case Iop_RSqrtStep32Fx4: case Iop_RSqrtStep64Fx2: 3004 case Iop_CipherV128: 3005 case Iop_CipherLV128: 3006 case Iop_NCipherV128: 3007 case Iop_NCipherLV128: 3008 case Iop_Sh8Sx16: case Iop_Sh16Sx8: 3009 case Iop_Sh32Sx4: case Iop_Sh64Sx2: 3010 case Iop_Sh8Ux16: case Iop_Sh16Ux8: 3011 case Iop_Sh32Ux4: case Iop_Sh64Ux2: 3012 case Iop_Rsh8Sx16: case Iop_Rsh16Sx8: 3013 case Iop_Rsh32Sx4: case Iop_Rsh64Sx2: 3014 case Iop_Rsh8Ux16: case Iop_Rsh16Ux8: 3015 case Iop_Rsh32Ux4: case Iop_Rsh64Ux2: 3016 BINARY(Ity_V128,Ity_V128, Ity_V128); 3017 3018 case Iop_PolynomialMull8x8: 3019 case Iop_Mull8Ux8: case Iop_Mull8Sx8: 3020 case Iop_Mull16Ux4: case Iop_Mull16Sx4: 3021 case Iop_Mull32Ux2: case Iop_Mull32Sx2: 3022 BINARY(Ity_I64, Ity_I64, Ity_V128); 3023 3024 case Iop_NotV128: 3025 case Iop_RecipEst32Fx4: case Iop_RecipEst32F0x4: 3026 case Iop_RecipEst64Fx2: case Iop_RSqrtEst64Fx2: 3027 case Iop_RecipEst32Ux4: 3028 case Iop_RSqrtEst32F0x4: 3029 case Iop_Sqrt32F0x4: 3030 case Iop_Sqrt64F0x2: 3031 case Iop_CmpNEZ8x16: case Iop_CmpNEZ16x8: 3032 case Iop_CmpNEZ32x4: case Iop_CmpNEZ64x2: 3033 case Iop_Cnt8x16: 3034 case Iop_Clz8x16: case Iop_Clz16x8: case Iop_Clz32x4: case Iop_Clz64x2: 3035 case Iop_Cls8x16: case Iop_Cls16x8: case Iop_Cls32x4: 3036 case Iop_PwAddL8Ux16: case Iop_PwAddL16Ux8: case Iop_PwAddL32Ux4: 3037 case Iop_PwAddL8Sx16: case Iop_PwAddL16Sx8: case Iop_PwAddL32Sx4: 3038 case Iop_Reverse8sIn64_x2: case Iop_Reverse16sIn64_x2: 3039 case Iop_Reverse32sIn64_x2: 3040 case Iop_Reverse8sIn32_x4: case Iop_Reverse16sIn32_x4: 3041 case Iop_Reverse8sIn16_x8: 3042 case Iop_Reverse1sIn8_x16: 3043 case Iop_Neg64Fx2: case Iop_Neg32Fx4: 3044 case Iop_Abs8x16: case Iop_Abs16x8: case Iop_Abs32x4: case Iop_Abs64x2: 3045 case Iop_CipherSV128: 3046 case Iop_PwBitMtxXpose64x2: 3047 case Iop_ZeroHI64ofV128: case Iop_ZeroHI96ofV128: 3048 case Iop_ZeroHI112ofV128: case Iop_ZeroHI120ofV128: 3049 UNARY(Ity_V128, Ity_V128); 3050 3051 case Iop_ShlV128: case Iop_ShrV128: 3052 case Iop_ShlN8x16: case Iop_ShlN16x8: 3053 case Iop_ShlN32x4: case Iop_ShlN64x2: 3054 case Iop_ShrN8x16: case Iop_ShrN16x8: 3055 case Iop_ShrN32x4: case Iop_ShrN64x2: 3056 case Iop_SarN8x16: case Iop_SarN16x8: 3057 case Iop_SarN32x4: case Iop_SarN64x2: 3058 case Iop_QShlNsatUU8x16: case Iop_QShlNsatUU16x8: 3059 case Iop_QShlNsatUU32x4: case Iop_QShlNsatUU64x2: 3060 case Iop_QShlNsatSU8x16: case Iop_QShlNsatSU16x8: 3061 case Iop_QShlNsatSU32x4: case Iop_QShlNsatSU64x2: 3062 case Iop_QShlNsatSS8x16: case Iop_QShlNsatSS16x8: 3063 case Iop_QShlNsatSS32x4: case Iop_QShlNsatSS64x2: 3064 case Iop_SHA256: case Iop_SHA512: 3065 case Iop_QandQShrNnarrow16Uto8Ux8: 3066 case Iop_QandQShrNnarrow32Uto16Ux4: 3067 case Iop_QandQShrNnarrow64Uto32Ux2: 3068 case Iop_QandQSarNnarrow16Sto8Sx8: 3069 case Iop_QandQSarNnarrow32Sto16Sx4: 3070 case Iop_QandQSarNnarrow64Sto32Sx2: 3071 case Iop_QandQSarNnarrow16Sto8Ux8: 3072 case Iop_QandQSarNnarrow32Sto16Ux4: 3073 case Iop_QandQSarNnarrow64Sto32Ux2: 3074 case Iop_QandQRShrNnarrow16Uto8Ux8: 3075 case Iop_QandQRShrNnarrow32Uto16Ux4: 3076 case Iop_QandQRShrNnarrow64Uto32Ux2: 3077 case Iop_QandQRSarNnarrow16Sto8Sx8: 3078 case Iop_QandQRSarNnarrow32Sto16Sx4: 3079 case Iop_QandQRSarNnarrow64Sto32Sx2: 3080 case Iop_QandQRSarNnarrow16Sto8Ux8: 3081 case Iop_QandQRSarNnarrow32Sto16Ux4: 3082 case Iop_QandQRSarNnarrow64Sto32Ux2: 3083 BINARY(Ity_V128,Ity_I8, Ity_V128); 3084 3085 case Iop_F32ToFixed32Ux4_RZ: 3086 case Iop_F32ToFixed32Sx4_RZ: 3087 case Iop_Fixed32UToF32x4_RN: 3088 case Iop_Fixed32SToF32x4_RN: 3089 BINARY(Ity_V128, Ity_I8, Ity_V128); 3090 3091 case Iop_F32ToFixed32Ux2_RZ: 3092 case Iop_F32ToFixed32Sx2_RZ: 3093 case Iop_Fixed32UToF32x2_RN: 3094 case Iop_Fixed32SToF32x2_RN: 3095 BINARY(Ity_I64, Ity_I8, Ity_I64); 3096 3097 case Iop_GetElem8x16: 3098 BINARY(Ity_V128, Ity_I8, Ity_I8); 3099 case Iop_GetElem16x8: 3100 BINARY(Ity_V128, Ity_I8, Ity_I16); 3101 case Iop_GetElem32x4: 3102 BINARY(Ity_V128, Ity_I8, Ity_I32); 3103 case Iop_GetElem64x2: 3104 BINARY(Ity_V128, Ity_I8, Ity_I64); 3105 case Iop_GetElem8x8: 3106 BINARY(Ity_I64, Ity_I8, Ity_I8); 3107 case Iop_GetElem16x4: 3108 BINARY(Ity_I64, Ity_I8, Ity_I16); 3109 case Iop_GetElem32x2: 3110 BINARY(Ity_I64, Ity_I8, Ity_I32); 3111 case Iop_SetElem8x8: 3112 TERNARY(Ity_I64, Ity_I8, Ity_I8, Ity_I64); 3113 case Iop_SetElem16x4: 3114 TERNARY(Ity_I64, Ity_I8, Ity_I16, Ity_I64); 3115 case Iop_SetElem32x2: 3116 TERNARY(Ity_I64, Ity_I8, Ity_I32, Ity_I64); 3117 3118 case Iop_Slice64: 3119 TERNARY(Ity_I64, Ity_I64, Ity_I8, Ity_I64); 3120 case Iop_SliceV128: 3121 TERNARY(Ity_V128, Ity_V128, Ity_I8, Ity_V128); 3122 3123 case Iop_BCDAdd: 3124 case Iop_BCDSub: 3125 TERNARY(Ity_V128,Ity_V128, Ity_I8, Ity_V128); 3126 case Iop_QDMull16Sx4: case Iop_QDMull32Sx2: 3127 BINARY(Ity_I64, Ity_I64, Ity_V128); 3128 3129 /* s390 specific */ 3130 case Iop_MAddF32: 3131 case Iop_MSubF32: 3132 QUATERNARY(ity_RMode,Ity_F32,Ity_F32,Ity_F32, Ity_F32); 3133 3134 case Iop_F64HLtoF128: 3135 BINARY(Ity_F64,Ity_F64, Ity_F128); 3136 3137 case Iop_F128HItoF64: 3138 case Iop_F128LOtoF64: 3139 UNARY(Ity_F128, Ity_F64); 3140 3141 case Iop_AddF128: 3142 case Iop_SubF128: 3143 case Iop_MulF128: 3144 case Iop_DivF128: 3145 TERNARY(ity_RMode,Ity_F128,Ity_F128, Ity_F128); 3146 3147 case Iop_Add64Fx2: case Iop_Sub64Fx2: 3148 case Iop_Mul64Fx2: case Iop_Div64Fx2: 3149 case Iop_Add32Fx4: case Iop_Sub32Fx4: 3150 case Iop_Mul32Fx4: case Iop_Div32Fx4: 3151 TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128); 3152 3153 case Iop_Add64Fx4: case Iop_Sub64Fx4: 3154 case Iop_Mul64Fx4: case Iop_Div64Fx4: 3155 case Iop_Add32Fx8: case Iop_Sub32Fx8: 3156 case Iop_Mul32Fx8: case Iop_Div32Fx8: 3157 TERNARY(ity_RMode,Ity_V256,Ity_V256, Ity_V256); 3158 3159 case Iop_NegF128: 3160 case Iop_AbsF128: 3161 UNARY(Ity_F128, Ity_F128); 3162 3163 case Iop_SqrtF128: 3164 case Iop_RoundF128toInt: 3165 BINARY(ity_RMode,Ity_F128, Ity_F128); 3166 3167 case Iop_I32StoF128: UNARY(Ity_I32, Ity_F128); 3168 case Iop_I64StoF128: UNARY(Ity_I64, Ity_F128); 3169 3170 case Iop_I32UtoF128: UNARY(Ity_I32, Ity_F128); 3171 case Iop_I64UtoF128: UNARY(Ity_I64, Ity_F128); 3172 3173 case Iop_F128toI32S: BINARY(ity_RMode,Ity_F128, Ity_I32); 3174 case Iop_F128toI64S: BINARY(ity_RMode,Ity_F128, Ity_I64); 3175 3176 case Iop_F128toI32U: BINARY(ity_RMode,Ity_F128, Ity_I32); 3177 case Iop_F128toI64U: BINARY(ity_RMode,Ity_F128, Ity_I64); 3178 3179 case Iop_F32toF128: UNARY(Ity_F32, Ity_F128); 3180 case Iop_F64toF128: UNARY(Ity_F64, Ity_F128); 3181 3182 case Iop_F128toF32: BINARY(ity_RMode,Ity_F128, Ity_F32); 3183 case Iop_F128toF64: BINARY(ity_RMode,Ity_F128, Ity_F64); 3184 3185 case Iop_D32toD64: 3186 UNARY(Ity_D32, Ity_D64); 3187 3188 case Iop_ExtractExpD64: 3189 UNARY(Ity_D64, Ity_I64); 3190 3191 case Iop_ExtractSigD64: 3192 UNARY(Ity_D64, Ity_I64); 3193 3194 case Iop_InsertExpD64: 3195 BINARY(Ity_I64,Ity_D64, Ity_D64); 3196 3197 case Iop_ExtractExpD128: 3198 UNARY(Ity_D128, Ity_I64); 3199 3200 case Iop_ExtractSigD128: 3201 UNARY(Ity_D128, Ity_I64); 3202 3203 case Iop_InsertExpD128: 3204 BINARY(Ity_I64,Ity_D128, Ity_D128); 3205 3206 case Iop_D64toD128: 3207 UNARY(Ity_D64, Ity_D128); 3208 3209 case Iop_ReinterpD64asI64: 3210 UNARY(Ity_D64, Ity_I64); 3211 3212 case Iop_ReinterpI64asD64: 3213 UNARY(Ity_I64, Ity_D64); 3214 3215 case Iop_RoundD64toInt: 3216 BINARY(ity_RMode,Ity_D64, Ity_D64); 3217 3218 case Iop_RoundD128toInt: 3219 BINARY(ity_RMode,Ity_D128, Ity_D128); 3220 3221 case Iop_I32StoD128: 3222 case Iop_I32UtoD128: 3223 UNARY(Ity_I32, Ity_D128); 3224 3225 case Iop_I64StoD128: 3226 UNARY(Ity_I64, Ity_D128); 3227 3228 case Iop_I64UtoD128: 3229 UNARY(Ity_I64, Ity_D128); 3230 3231 case Iop_DPBtoBCD: 3232 case Iop_BCDtoDPB: 3233 UNARY(Ity_I64, Ity_I64); 3234 3235 case Iop_D128HItoD64: 3236 case Iop_D128LOtoD64: 3237 UNARY(Ity_D128, Ity_D64); 3238 3239 case Iop_D128toI64S: 3240 BINARY(ity_RMode, Ity_D128, Ity_I64); 3241 3242 case Iop_D128toI64U: 3243 BINARY(ity_RMode, Ity_D128, Ity_I64); 3244 3245 case Iop_D128toI32S: 3246 case Iop_D128toI32U: 3247 BINARY(ity_RMode, Ity_D128, Ity_I32); 3248 3249 case Iop_D64HLtoD128: 3250 BINARY(Ity_D64, Ity_D64, Ity_D128); 3251 3252 case Iop_ShlD64: 3253 case Iop_ShrD64: 3254 BINARY(Ity_D64, Ity_I8, Ity_D64 ); 3255 3256 case Iop_D64toD32: 3257 BINARY(ity_RMode, Ity_D64, Ity_D32); 3258 3259 case Iop_D64toI32S: 3260 case Iop_D64toI32U: 3261 BINARY(ity_RMode, Ity_D64, Ity_I32); 3262 3263 case Iop_D64toI64S: 3264 BINARY(ity_RMode, Ity_D64, Ity_I64); 3265 3266 case Iop_D64toI64U: 3267 BINARY(ity_RMode, Ity_D64, Ity_I64); 3268 3269 case Iop_I32StoD64: 3270 case Iop_I32UtoD64: 3271 UNARY(Ity_I32, Ity_D64); 3272 3273 case Iop_I64StoD64: 3274 BINARY(ity_RMode, Ity_I64, Ity_D64); 3275 3276 case Iop_I64UtoD64: 3277 BINARY(ity_RMode, Ity_I64, Ity_D64); 3278 3279 case Iop_F32toD32: 3280 BINARY(ity_RMode, Ity_F32, Ity_D32); 3281 3282 case Iop_F32toD64: 3283 BINARY(ity_RMode, Ity_F32, Ity_D64); 3284 3285 case Iop_F32toD128: 3286 BINARY(ity_RMode, Ity_F32, Ity_D128); 3287 3288 case Iop_F64toD32: 3289 BINARY(ity_RMode, Ity_F64, Ity_D32); 3290 3291 case Iop_F64toD64: 3292 BINARY(ity_RMode, Ity_F64, Ity_D64); 3293 3294 case Iop_F64toD128: 3295 BINARY(ity_RMode, Ity_F64, Ity_D128); 3296 3297 case Iop_F128toD32: 3298 BINARY(ity_RMode, Ity_F128, Ity_D32); 3299 3300 case Iop_F128toD64: 3301 BINARY(ity_RMode, Ity_F128, Ity_D64); 3302 3303 case Iop_F128toD128: 3304 BINARY(ity_RMode, Ity_F128, Ity_D128); 3305 3306 case Iop_D32toF32: 3307 BINARY(ity_RMode, Ity_D32, Ity_F32); 3308 3309 case Iop_D32toF64: 3310 BINARY(ity_RMode, Ity_D32, Ity_F64); 3311 3312 case Iop_D32toF128: 3313 BINARY(ity_RMode, Ity_D32, Ity_F128); 3314 3315 case Iop_D64toF32: 3316 BINARY(ity_RMode, Ity_D64, Ity_F32); 3317 3318 case Iop_D64toF64: 3319 BINARY(ity_RMode, Ity_D64, Ity_F64); 3320 3321 case Iop_D64toF128: 3322 BINARY(ity_RMode, Ity_D64, Ity_F128); 3323 3324 case Iop_D128toF32: 3325 BINARY(ity_RMode, Ity_D128, Ity_F32); 3326 3327 case Iop_D128toF64: 3328 BINARY(ity_RMode, Ity_D128, Ity_F64); 3329 3330 case Iop_D128toF128: 3331 BINARY(ity_RMode, Ity_D128, Ity_F128); 3332 3333 case Iop_CmpD64: 3334 case Iop_CmpExpD64: 3335 BINARY(Ity_D64,Ity_D64, Ity_I32); 3336 3337 case Iop_CmpD128: 3338 case Iop_CmpExpD128: 3339 BINARY(Ity_D128,Ity_D128, Ity_I32); 3340 3341 case Iop_QuantizeD64: 3342 TERNARY(ity_RMode,Ity_D64,Ity_D64, Ity_D64); 3343 3344 case Iop_SignificanceRoundD64: 3345 TERNARY(ity_RMode, Ity_I8,Ity_D64, Ity_D64); 3346 3347 case Iop_QuantizeD128: 3348 TERNARY(ity_RMode,Ity_D128,Ity_D128, Ity_D128); 3349 3350 case Iop_SignificanceRoundD128: 3351 TERNARY(ity_RMode, Ity_I8,Ity_D128, Ity_D128); 3352 3353 case Iop_ShlD128: 3354 case Iop_ShrD128: 3355 BINARY(Ity_D128, Ity_I8, Ity_D128 ); 3356 3357 case Iop_AddD64: 3358 case Iop_SubD64: 3359 case Iop_MulD64: 3360 case Iop_DivD64: 3361 TERNARY( ity_RMode, Ity_D64, Ity_D64, Ity_D64 ); 3362 3363 case Iop_D128toD64: 3364 BINARY( ity_RMode, Ity_D128, Ity_D64 ); 3365 3366 case Iop_AddD128: 3367 case Iop_SubD128: 3368 case Iop_MulD128: 3369 case Iop_DivD128: 3370 TERNARY(ity_RMode,Ity_D128,Ity_D128, Ity_D128); 3371 3372 case Iop_V256to64_0: case Iop_V256to64_1: 3373 case Iop_V256to64_2: case Iop_V256to64_3: 3374 UNARY(Ity_V256, Ity_I64); 3375 3376 case Iop_64x4toV256: 3377 QUATERNARY(Ity_I64, Ity_I64, Ity_I64, Ity_I64, Ity_V256); 3378 3379 case Iop_AndV256: case Iop_OrV256: 3380 case Iop_XorV256: 3381 case Iop_Max32Fx8: case Iop_Min32Fx8: 3382 case Iop_Max64Fx4: case Iop_Min64Fx4: 3383 case Iop_Add8x32: case Iop_Add16x16: 3384 case Iop_Add32x8: case Iop_Add64x4: 3385 case Iop_Sub8x32: case Iop_Sub16x16: 3386 case Iop_Sub32x8: case Iop_Sub64x4: 3387 case Iop_Mul16x16: case Iop_Mul32x8: 3388 case Iop_MulHi16Ux16: case Iop_MulHi16Sx16: 3389 case Iop_Avg8Ux32: case Iop_Avg16Ux16: 3390 case Iop_Max8Sx32: case Iop_Max16Sx16: case Iop_Max32Sx8: 3391 case Iop_Max8Ux32: case Iop_Max16Ux16: case Iop_Max32Ux8: 3392 case Iop_Min8Sx32: case Iop_Min16Sx16: case Iop_Min32Sx8: 3393 case Iop_Min8Ux32: case Iop_Min16Ux16: case Iop_Min32Ux8: 3394 case Iop_CmpEQ8x32: case Iop_CmpEQ16x16: 3395 case Iop_CmpEQ32x8: case Iop_CmpEQ64x4: 3396 case Iop_CmpGT8Sx32: case Iop_CmpGT16Sx16: 3397 case Iop_CmpGT32Sx8: case Iop_CmpGT64Sx4: 3398 case Iop_QAdd8Ux32: case Iop_QAdd16Ux16: 3399 case Iop_QAdd8Sx32: case Iop_QAdd16Sx16: 3400 case Iop_QSub8Ux32: case Iop_QSub16Ux16: 3401 case Iop_QSub8Sx32: case Iop_QSub16Sx16: 3402 case Iop_Perm32x8: 3403 BINARY(Ity_V256,Ity_V256, Ity_V256); 3404 3405 case Iop_V256toV128_1: case Iop_V256toV128_0: 3406 UNARY(Ity_V256, Ity_V128); 3407 3408 case Iop_QandUQsh8x16: case Iop_QandUQsh16x8: 3409 case Iop_QandUQsh32x4: case Iop_QandUQsh64x2: 3410 case Iop_QandSQsh8x16: case Iop_QandSQsh16x8: 3411 case Iop_QandSQsh32x4: case Iop_QandSQsh64x2: 3412 case Iop_QandUQRsh8x16: case Iop_QandUQRsh16x8: 3413 case Iop_QandUQRsh32x4: case Iop_QandUQRsh64x2: 3414 case Iop_QandSQRsh8x16: case Iop_QandSQRsh16x8: 3415 case Iop_QandSQRsh32x4: case Iop_QandSQRsh64x2: 3416 case Iop_V128HLtoV256: 3417 BINARY(Ity_V128,Ity_V128, Ity_V256); 3418 3419 case Iop_NotV256: 3420 case Iop_RSqrtEst32Fx8: 3421 case Iop_Sqrt32Fx8: 3422 case Iop_Sqrt64Fx4: 3423 case Iop_RecipEst32Fx8: 3424 case Iop_CmpNEZ8x32: case Iop_CmpNEZ16x16: 3425 case Iop_CmpNEZ64x4: case Iop_CmpNEZ32x8: 3426 UNARY(Ity_V256, Ity_V256); 3427 3428 case Iop_ShlN16x16: case Iop_ShlN32x8: 3429 case Iop_ShlN64x4: 3430 case Iop_ShrN16x16: case Iop_ShrN32x8: 3431 case Iop_ShrN64x4: 3432 case Iop_SarN16x16: case Iop_SarN32x8: 3433 BINARY(Ity_V256,Ity_I8, Ity_V256); 3434 3435 default: 3436 ppIROp(op); 3437 vpanic("typeOfPrimop"); 3438 } 3439 # undef UNARY 3440 # undef BINARY 3441 # undef TERNARY 3442 # undef COMPARISON 3443 # undef UNARY_COMPARISON 3444 } 3445 3446 3447 /*---------------------------------------------------------------*/ 3448 /*--- Helper functions for the IR -- IR Basic Blocks ---*/ 3449 /*---------------------------------------------------------------*/ 3450 3451 void addStmtToIRSB ( IRSB* bb, IRStmt* st ) 3452 { 3453 Int i; 3454 if (bb->stmts_used == bb->stmts_size) { 3455 IRStmt** stmts2 = LibVEX_Alloc_inline(2 * bb->stmts_size * sizeof(IRStmt*)); 3456 for (i = 0; i < bb->stmts_size; i++) 3457 stmts2[i] = bb->stmts[i]; 3458 bb->stmts = stmts2; 3459 bb->stmts_size *= 2; 3460 } 3461 vassert(bb->stmts_used < bb->stmts_size); 3462 bb->stmts[bb->stmts_used] = st; 3463 bb->stmts_used++; 3464 } 3465 3466 3467 /*---------------------------------------------------------------*/ 3468 /*--- Helper functions for the IR -- IR Type Environments ---*/ 3469 /*---------------------------------------------------------------*/ 3470 3471 /* Allocate a new IRTemp, given its type. */ 3472 3473 IRTemp newIRTemp ( IRTypeEnv* env, IRType ty ) 3474 { 3475 vassert(env); 3476 vassert(env->types_used >= 0); 3477 vassert(env->types_size >= 0); 3478 vassert(env->types_used <= env->types_size); 3479 if (env->types_used < env->types_size) { 3480 env->types[env->types_used] = ty; 3481 return env->types_used++; 3482 } else { 3483 Int i; 3484 Int new_size = env->types_size==0 ? 8 : 2*env->types_size; 3485 IRType* new_types 3486 = LibVEX_Alloc_inline(new_size * sizeof(IRType)); 3487 for (i = 0; i < env->types_used; i++) 3488 new_types[i] = env->types[i]; 3489 env->types = new_types; 3490 env->types_size = new_size; 3491 return newIRTemp(env, ty); 3492 } 3493 } 3494 3495 3496 /*---------------------------------------------------------------*/ 3497 /*--- Helper functions for the IR -- finding types of exprs ---*/ 3498 /*---------------------------------------------------------------*/ 3499 3500 inline 3501 IRType typeOfIRTemp ( const IRTypeEnv* env, IRTemp tmp ) 3502 { 3503 vassert(tmp >= 0); 3504 vassert(tmp < env->types_used); 3505 return env->types[tmp]; 3506 } 3507 3508 IRType typeOfIRConst ( const IRConst* con ) 3509 { 3510 switch (con->tag) { 3511 case Ico_U1: return Ity_I1; 3512 case Ico_U8: return Ity_I8; 3513 case Ico_U16: return Ity_I16; 3514 case Ico_U32: return Ity_I32; 3515 case Ico_U64: return Ity_I64; 3516 case Ico_F32: return Ity_F32; 3517 case Ico_F32i: return Ity_F32; 3518 case Ico_F64: return Ity_F64; 3519 case Ico_F64i: return Ity_F64; 3520 case Ico_V128: return Ity_V128; 3521 case Ico_V256: return Ity_V256; 3522 default: vpanic("typeOfIRConst"); 3523 } 3524 } 3525 3526 void typeOfIRLoadGOp ( IRLoadGOp cvt, 3527 /*OUT*/IRType* t_res, /*OUT*/IRType* t_arg ) 3528 { 3529 switch (cvt) { 3530 case ILGop_IdentV128: 3531 *t_res = Ity_V128; *t_arg = Ity_V128; break; 3532 case ILGop_Ident64: 3533 *t_res = Ity_I64; *t_arg = Ity_I64; break; 3534 case ILGop_Ident32: 3535 *t_res = Ity_I32; *t_arg = Ity_I32; break; 3536 case ILGop_16Uto32: case ILGop_16Sto32: 3537 *t_res = Ity_I32; *t_arg = Ity_I16; break; 3538 case ILGop_8Uto32: case ILGop_8Sto32: 3539 *t_res = Ity_I32; *t_arg = Ity_I8; break; 3540 default: 3541 vpanic("typeOfIRLoadGOp"); 3542 } 3543 } 3544 3545 IRType typeOfIRExpr ( const IRTypeEnv* tyenv, const IRExpr* e ) 3546 { 3547 IRType t_dst, t_arg1, t_arg2, t_arg3, t_arg4; 3548 start: 3549 switch (e->tag) { 3550 case Iex_Load: 3551 return e->Iex.Load.ty; 3552 case Iex_Get: 3553 return e->Iex.Get.ty; 3554 case Iex_GetI: 3555 return e->Iex.GetI.descr->elemTy; 3556 case Iex_RdTmp: 3557 return typeOfIRTemp(tyenv, e->Iex.RdTmp.tmp); 3558 case Iex_Const: 3559 return typeOfIRConst(e->Iex.Const.con); 3560 case Iex_Qop: 3561 typeOfPrimop(e->Iex.Qop.details->op, 3562 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 3563 return t_dst; 3564 case Iex_Triop: 3565 typeOfPrimop(e->Iex.Triop.details->op, 3566 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 3567 return t_dst; 3568 case Iex_Binop: 3569 typeOfPrimop(e->Iex.Binop.op, 3570 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 3571 return t_dst; 3572 case Iex_Unop: 3573 typeOfPrimop(e->Iex.Unop.op, 3574 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 3575 return t_dst; 3576 case Iex_CCall: 3577 return e->Iex.CCall.retty; 3578 case Iex_ITE: 3579 e = e->Iex.ITE.iffalse; 3580 goto start; 3581 /* return typeOfIRExpr(tyenv, e->Iex.ITE.iffalse); */ 3582 case Iex_Binder: 3583 vpanic("typeOfIRExpr: Binder is not a valid expression"); 3584 case Iex_VECRET: 3585 vpanic("typeOfIRExpr: VECRET is not a valid expression"); 3586 case Iex_BBPTR: 3587 vpanic("typeOfIRExpr: BBPTR is not a valid expression"); 3588 default: 3589 ppIRExpr(e); 3590 vpanic("typeOfIRExpr"); 3591 } 3592 } 3593 3594 /* Is this any value actually in the enumeration 'IRType' ? */ 3595 Bool isPlausibleIRType ( IRType ty ) 3596 { 3597 switch (ty) { 3598 case Ity_INVALID: case Ity_I1: 3599 case Ity_I8: case Ity_I16: case Ity_I32: 3600 case Ity_I64: case Ity_I128: 3601 case Ity_F16: case Ity_F32: case Ity_F64: case Ity_F128: 3602 case Ity_D32: case Ity_D64: case Ity_D128: 3603 case Ity_V128: case Ity_V256: 3604 return True; 3605 default: 3606 return False; 3607 } 3608 } 3609 3610 3611 /*---------------------------------------------------------------*/ 3612 /*--- Sanity checking -- FLATNESS ---*/ 3613 /*---------------------------------------------------------------*/ 3614 3615 /* Check that the canonical flatness constraints hold on an 3616 IRStmt. The only place where any expression is allowed to be 3617 non-atomic is the RHS of IRStmt_Tmp. */ 3618 3619 /* Relies on: 3620 inline static Bool isAtom ( IRExpr* e ) { 3621 return e->tag == Iex_RdTmp || e->tag == Iex_Const; 3622 } 3623 */ 3624 3625 static inline Bool isIRAtom_or_VECRET_or_BBPTR ( const IRExpr* e ) 3626 { 3627 if (isIRAtom(e)) { 3628 return True; 3629 } 3630 3631 return UNLIKELY(is_IRExpr_VECRET_or_BBPTR(e)); 3632 } 3633 3634 Bool isFlatIRStmt ( const IRStmt* st ) 3635 { 3636 Int i; 3637 const IRExpr* e; 3638 const IRQop* qop; 3639 const IRTriop* triop; 3640 3641 switch (st->tag) { 3642 case Ist_AbiHint: 3643 return isIRAtom(st->Ist.AbiHint.base) 3644 && isIRAtom(st->Ist.AbiHint.nia); 3645 case Ist_Put: 3646 return isIRAtom(st->Ist.Put.data); 3647 case Ist_PutI: { 3648 const IRPutI *puti = st->Ist.PutI.details; 3649 return toBool( isIRAtom(puti->ix) 3650 && isIRAtom(puti->data) ); 3651 } 3652 case Ist_WrTmp: 3653 /* This is the only interesting case. The RHS can be any 3654 expression, *but* all its subexpressions *must* be 3655 atoms. */ 3656 e = st->Ist.WrTmp.data; 3657 switch (e->tag) { 3658 case Iex_Binder: return True; 3659 case Iex_Get: return True; 3660 case Iex_GetI: return isIRAtom(e->Iex.GetI.ix); 3661 case Iex_RdTmp: return True; 3662 case Iex_Qop: qop = e->Iex.Qop.details; 3663 return toBool( 3664 isIRAtom(qop->arg1) 3665 && isIRAtom(qop->arg2) 3666 && isIRAtom(qop->arg3) 3667 && isIRAtom(qop->arg4)); 3668 case Iex_Triop: triop = e->Iex.Triop.details; 3669 return toBool( 3670 isIRAtom(triop->arg1) 3671 && isIRAtom(triop->arg2) 3672 && isIRAtom(triop->arg3)); 3673 case Iex_Binop: return toBool( 3674 isIRAtom(e->Iex.Binop.arg1) 3675 && isIRAtom(e->Iex.Binop.arg2)); 3676 case Iex_Unop: return isIRAtom(e->Iex.Unop.arg); 3677 case Iex_Load: return isIRAtom(e->Iex.Load.addr); 3678 case Iex_Const: return True; 3679 case Iex_CCall: for (i = 0; e->Iex.CCall.args[i]; i++) 3680 if (!isIRAtom(e->Iex.CCall.args[i])) 3681 return False; 3682 return True; 3683 case Iex_ITE: return toBool ( 3684 isIRAtom(e->Iex.ITE.cond) 3685 && isIRAtom(e->Iex.ITE.iftrue) 3686 && isIRAtom(e->Iex.ITE.iffalse)); 3687 default: vpanic("isFlatIRStmt(e)"); 3688 } 3689 /*notreached*/ 3690 vassert(0); 3691 case Ist_Store: 3692 return toBool( isIRAtom(st->Ist.Store.addr) 3693 && isIRAtom(st->Ist.Store.data) ); 3694 case Ist_StoreG: { 3695 const IRStoreG* sg = st->Ist.StoreG.details; 3696 return toBool( isIRAtom(sg->addr) 3697 && isIRAtom(sg->data) && isIRAtom(sg->guard) ); 3698 } 3699 case Ist_LoadG: { 3700 const IRLoadG* lg = st->Ist.LoadG.details; 3701 return toBool( isIRAtom(lg->addr) 3702 && isIRAtom(lg->alt) && isIRAtom(lg->guard) ); 3703 } 3704 case Ist_CAS: { 3705 const IRCAS* cas = st->Ist.CAS.details; 3706 return toBool( isIRAtom(cas->addr) 3707 && (cas->expdHi ? isIRAtom(cas->expdHi) : True) 3708 && isIRAtom(cas->expdLo) 3709 && (cas->dataHi ? isIRAtom(cas->dataHi) : True) 3710 && isIRAtom(cas->dataLo) ); 3711 } 3712 case Ist_LLSC: 3713 return toBool( isIRAtom(st->Ist.LLSC.addr) 3714 && (st->Ist.LLSC.storedata 3715 ? isIRAtom(st->Ist.LLSC.storedata) : True) ); 3716 case Ist_Dirty: { 3717 const IRDirty* di = st->Ist.Dirty.details; 3718 if (!isIRAtom(di->guard)) 3719 return False; 3720 for (i = 0; di->args[i]; i++) 3721 if (!isIRAtom_or_VECRET_or_BBPTR(di->args[i])) 3722 return False; 3723 if (di->mAddr && !isIRAtom(di->mAddr)) 3724 return False; 3725 return True; 3726 } 3727 case Ist_NoOp: 3728 case Ist_IMark: 3729 case Ist_MBE: 3730 return True; 3731 case Ist_Exit: 3732 return isIRAtom(st->Ist.Exit.guard); 3733 default: 3734 vpanic("isFlatIRStmt(st)"); 3735 } 3736 } 3737 3738 3739 /*---------------------------------------------------------------*/ 3740 /*--- Sanity checking ---*/ 3741 /*---------------------------------------------------------------*/ 3742 3743 /* Checks: 3744 3745 Everything is type-consistent. No ill-typed anything. 3746 The target address at the end of the BB is a 32- or 64- 3747 bit expression, depending on the guest's word size. 3748 3749 Each temp is assigned only once, before its uses. 3750 */ 3751 3752 static inline Int countArgs ( IRExpr** args ) 3753 { 3754 Int i; 3755 for (i = 0; args[i]; i++) 3756 ; 3757 return i; 3758 } 3759 3760 static 3761 __attribute((noreturn)) 3762 void sanityCheckFail ( const IRSB* bb, const IRStmt* stmt, const HChar* what ) 3763 { 3764 vex_printf("\nIR SANITY CHECK FAILURE\n\n"); 3765 ppIRSB(bb); 3766 if (stmt) { 3767 vex_printf("\nIN STATEMENT:\n\n"); 3768 ppIRStmt(stmt); 3769 } 3770 vex_printf("\n\nERROR = %s\n\n", what ); 3771 vpanic("sanityCheckFail: exiting due to bad IR"); 3772 } 3773 3774 static Bool saneIRRegArray ( const IRRegArray* arr ) 3775 { 3776 if (arr->base < 0 || arr->base > 10000 /* somewhat arbitrary */) 3777 return False; 3778 if (arr->elemTy == Ity_I1) 3779 return False; 3780 if (arr->nElems <= 0 || arr->nElems > 500 /* somewhat arbitrary */) 3781 return False; 3782 return True; 3783 } 3784 3785 static Bool saneIRCallee ( const IRCallee* cee ) 3786 { 3787 if (cee->name == NULL) 3788 return False; 3789 if (cee->addr == 0) 3790 return False; 3791 if (cee->regparms < 0 || cee->regparms > 3) 3792 return False; 3793 return True; 3794 } 3795 3796 static Bool saneIRConst ( const IRConst* con ) 3797 { 3798 switch (con->tag) { 3799 case Ico_U1: 3800 return toBool( con->Ico.U1 == True || con->Ico.U1 == False ); 3801 default: 3802 /* Is there anything we can meaningfully check? I don't 3803 think so. */ 3804 return True; 3805 } 3806 } 3807 3808 /* Traverse a Stmt/Expr, inspecting IRTemp uses. Report any out of 3809 range ones. Report any which are read and for which the current 3810 def_count is zero. */ 3811 3812 static 3813 void useBeforeDef_Temp ( const IRSB* bb, const IRStmt* stmt, IRTemp tmp, 3814 Int* def_counts ) 3815 { 3816 if (tmp < 0 || tmp >= bb->tyenv->types_used) 3817 sanityCheckFail(bb,stmt, "out of range Temp in IRExpr"); 3818 if (def_counts[tmp] < 1) 3819 sanityCheckFail(bb,stmt, "IRTemp use before def in IRExpr"); 3820 } 3821 3822 static 3823 void useBeforeDef_Expr ( const IRSB* bb, const IRStmt* stmt, 3824 const IRExpr* expr, Int* def_counts ) 3825 { 3826 Int i; 3827 switch (expr->tag) { 3828 case Iex_Get: 3829 break; 3830 case Iex_GetI: 3831 useBeforeDef_Expr(bb,stmt,expr->Iex.GetI.ix,def_counts); 3832 break; 3833 case Iex_RdTmp: 3834 useBeforeDef_Temp(bb,stmt,expr->Iex.RdTmp.tmp,def_counts); 3835 break; 3836 case Iex_Qop: { 3837 const IRQop* qop = expr->Iex.Qop.details; 3838 useBeforeDef_Expr(bb,stmt,qop->arg1,def_counts); 3839 useBeforeDef_Expr(bb,stmt,qop->arg2,def_counts); 3840 useBeforeDef_Expr(bb,stmt,qop->arg3,def_counts); 3841 useBeforeDef_Expr(bb,stmt,qop->arg4,def_counts); 3842 break; 3843 } 3844 case Iex_Triop: { 3845 const IRTriop* triop = expr->Iex.Triop.details; 3846 useBeforeDef_Expr(bb,stmt,triop->arg1,def_counts); 3847 useBeforeDef_Expr(bb,stmt,triop->arg2,def_counts); 3848 useBeforeDef_Expr(bb,stmt,triop->arg3,def_counts); 3849 break; 3850 } 3851 case Iex_Binop: 3852 useBeforeDef_Expr(bb,stmt,expr->Iex.Binop.arg1,def_counts); 3853 useBeforeDef_Expr(bb,stmt,expr->Iex.Binop.arg2,def_counts); 3854 break; 3855 case Iex_Unop: 3856 useBeforeDef_Expr(bb,stmt,expr->Iex.Unop.arg,def_counts); 3857 break; 3858 case Iex_Load: 3859 useBeforeDef_Expr(bb,stmt,expr->Iex.Load.addr,def_counts); 3860 break; 3861 case Iex_Const: 3862 break; 3863 case Iex_CCall: 3864 for (i = 0; expr->Iex.CCall.args[i]; i++) { 3865 const IRExpr* arg = expr->Iex.CCall.args[i]; 3866 if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg))) { 3867 /* These aren't allowed in CCall lists. Let's detect 3868 and throw them out here, though, rather than 3869 segfaulting a bit later on. */ 3870 sanityCheckFail(bb,stmt, "IRExprP__* value in CCall arg list"); 3871 } else { 3872 useBeforeDef_Expr(bb,stmt,arg,def_counts); 3873 } 3874 } 3875 break; 3876 case Iex_ITE: 3877 useBeforeDef_Expr(bb,stmt,expr->Iex.ITE.cond,def_counts); 3878 useBeforeDef_Expr(bb,stmt,expr->Iex.ITE.iftrue,def_counts); 3879 useBeforeDef_Expr(bb,stmt,expr->Iex.ITE.iffalse,def_counts); 3880 break; 3881 default: 3882 vpanic("useBeforeDef_Expr"); 3883 } 3884 } 3885 3886 static 3887 void useBeforeDef_Stmt ( const IRSB* bb, const IRStmt* stmt, Int* def_counts ) 3888 { 3889 Int i; 3890 const IRDirty* d; 3891 const IRCAS* cas; 3892 const IRPutI* puti; 3893 const IRLoadG* lg; 3894 const IRStoreG* sg; 3895 switch (stmt->tag) { 3896 case Ist_IMark: 3897 break; 3898 case Ist_AbiHint: 3899 useBeforeDef_Expr(bb,stmt,stmt->Ist.AbiHint.base,def_counts); 3900 useBeforeDef_Expr(bb,stmt,stmt->Ist.AbiHint.nia,def_counts); 3901 break; 3902 case Ist_Put: 3903 useBeforeDef_Expr(bb,stmt,stmt->Ist.Put.data,def_counts); 3904 break; 3905 case Ist_PutI: 3906 puti = stmt->Ist.PutI.details; 3907 useBeforeDef_Expr(bb,stmt,puti->ix,def_counts); 3908 useBeforeDef_Expr(bb,stmt,puti->data,def_counts); 3909 break; 3910 case Ist_WrTmp: 3911 useBeforeDef_Expr(bb,stmt,stmt->Ist.WrTmp.data,def_counts); 3912 break; 3913 case Ist_Store: 3914 useBeforeDef_Expr(bb,stmt,stmt->Ist.Store.addr,def_counts); 3915 useBeforeDef_Expr(bb,stmt,stmt->Ist.Store.data,def_counts); 3916 break; 3917 case Ist_StoreG: 3918 sg = stmt->Ist.StoreG.details; 3919 useBeforeDef_Expr(bb,stmt,sg->addr,def_counts); 3920 useBeforeDef_Expr(bb,stmt,sg->data,def_counts); 3921 useBeforeDef_Expr(bb,stmt,sg->guard,def_counts); 3922 break; 3923 case Ist_LoadG: 3924 lg = stmt->Ist.LoadG.details; 3925 useBeforeDef_Expr(bb,stmt,lg->addr,def_counts); 3926 useBeforeDef_Expr(bb,stmt,lg->alt,def_counts); 3927 useBeforeDef_Expr(bb,stmt,lg->guard,def_counts); 3928 break; 3929 case Ist_CAS: 3930 cas = stmt->Ist.CAS.details; 3931 useBeforeDef_Expr(bb,stmt,cas->addr,def_counts); 3932 if (cas->expdHi) 3933 useBeforeDef_Expr(bb,stmt,cas->expdHi,def_counts); 3934 useBeforeDef_Expr(bb,stmt,cas->expdLo,def_counts); 3935 if (cas->dataHi) 3936 useBeforeDef_Expr(bb,stmt,cas->dataHi,def_counts); 3937 useBeforeDef_Expr(bb,stmt,cas->dataLo,def_counts); 3938 break; 3939 case Ist_LLSC: 3940 useBeforeDef_Expr(bb,stmt,stmt->Ist.LLSC.addr,def_counts); 3941 if (stmt->Ist.LLSC.storedata != NULL) 3942 useBeforeDef_Expr(bb,stmt,stmt->Ist.LLSC.storedata,def_counts); 3943 break; 3944 case Ist_Dirty: 3945 d = stmt->Ist.Dirty.details; 3946 for (i = 0; d->args[i] != NULL; i++) { 3947 IRExpr* arg = d->args[i]; 3948 if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg))) { 3949 /* This is ensured by isFlatIRStmt */ 3950 ; 3951 } else { 3952 useBeforeDef_Expr(bb,stmt,arg,def_counts); 3953 } 3954 } 3955 if (d->mFx != Ifx_None) 3956 useBeforeDef_Expr(bb,stmt,d->mAddr,def_counts); 3957 break; 3958 case Ist_NoOp: 3959 case Ist_MBE: 3960 break; 3961 case Ist_Exit: 3962 useBeforeDef_Expr(bb,stmt,stmt->Ist.Exit.guard,def_counts); 3963 break; 3964 default: 3965 vpanic("useBeforeDef_Stmt"); 3966 } 3967 } 3968 3969 static 3970 void tcExpr ( const IRSB* bb, const IRStmt* stmt, const IRExpr* expr, 3971 IRType gWordTy ) 3972 { 3973 Int i; 3974 IRType t_dst, t_arg1, t_arg2, t_arg3, t_arg4; 3975 const IRTypeEnv* tyenv = bb->tyenv; 3976 switch (expr->tag) { 3977 case Iex_Get: 3978 case Iex_RdTmp: 3979 break; 3980 case Iex_GetI: 3981 tcExpr(bb,stmt, expr->Iex.GetI.ix, gWordTy ); 3982 if (typeOfIRExpr(tyenv,expr->Iex.GetI.ix) != Ity_I32) 3983 sanityCheckFail(bb,stmt,"IRExpr.GetI.ix: not :: Ity_I32"); 3984 if (!saneIRRegArray(expr->Iex.GetI.descr)) 3985 sanityCheckFail(bb,stmt,"IRExpr.GetI.descr: invalid descr"); 3986 break; 3987 case Iex_Qop: { 3988 IRType ttarg1, ttarg2, ttarg3, ttarg4; 3989 const IRQop* qop = expr->Iex.Qop.details; 3990 tcExpr(bb,stmt, qop->arg1, gWordTy ); 3991 tcExpr(bb,stmt, qop->arg2, gWordTy ); 3992 tcExpr(bb,stmt, qop->arg3, gWordTy ); 3993 tcExpr(bb,stmt, qop->arg4, gWordTy ); 3994 typeOfPrimop(qop->op, 3995 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 3996 if (t_arg1 == Ity_INVALID || t_arg2 == Ity_INVALID 3997 || t_arg3 == Ity_INVALID || t_arg4 == Ity_INVALID) { 3998 vex_printf(" op name: " ); 3999 ppIROp(qop->op); 4000 vex_printf("\n"); 4001 sanityCheckFail(bb,stmt, 4002 "Iex.Qop: wrong arity op\n" 4003 "... name of op precedes BB printout\n"); 4004 } 4005 ttarg1 = typeOfIRExpr(tyenv, qop->arg1); 4006 ttarg2 = typeOfIRExpr(tyenv, qop->arg2); 4007 ttarg3 = typeOfIRExpr(tyenv, qop->arg3); 4008 ttarg4 = typeOfIRExpr(tyenv, qop->arg4); 4009 if (t_arg1 != ttarg1 || t_arg2 != ttarg2 4010 || t_arg3 != ttarg3 || t_arg4 != ttarg4) { 4011 vex_printf(" op name: "); 4012 ppIROp(qop->op); 4013 vex_printf("\n"); 4014 vex_printf(" op type is ("); 4015 ppIRType(t_arg1); 4016 vex_printf(","); 4017 ppIRType(t_arg2); 4018 vex_printf(","); 4019 ppIRType(t_arg3); 4020 vex_printf(","); 4021 ppIRType(t_arg4); 4022 vex_printf(") -> "); 4023 ppIRType (t_dst); 4024 vex_printf("\narg tys are ("); 4025 ppIRType(ttarg1); 4026 vex_printf(","); 4027 ppIRType(ttarg2); 4028 vex_printf(","); 4029 ppIRType(ttarg3); 4030 vex_printf(","); 4031 ppIRType(ttarg4); 4032 vex_printf(")\n"); 4033 sanityCheckFail(bb,stmt, 4034 "Iex.Qop: arg tys don't match op tys\n" 4035 "... additional details precede BB printout\n"); 4036 } 4037 break; 4038 } 4039 case Iex_Triop: { 4040 IRType ttarg1, ttarg2, ttarg3; 4041 const IRTriop *triop = expr->Iex.Triop.details; 4042 tcExpr(bb,stmt, triop->arg1, gWordTy ); 4043 tcExpr(bb,stmt, triop->arg2, gWordTy ); 4044 tcExpr(bb,stmt, triop->arg3, gWordTy ); 4045 typeOfPrimop(triop->op, 4046 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 4047 if (t_arg1 == Ity_INVALID || t_arg2 == Ity_INVALID 4048 || t_arg3 == Ity_INVALID || t_arg4 != Ity_INVALID) { 4049 vex_printf(" op name: " ); 4050 ppIROp(triop->op); 4051 vex_printf("\n"); 4052 sanityCheckFail(bb,stmt, 4053 "Iex.Triop: wrong arity op\n" 4054 "... name of op precedes BB printout\n"); 4055 } 4056 ttarg1 = typeOfIRExpr(tyenv, triop->arg1); 4057 ttarg2 = typeOfIRExpr(tyenv, triop->arg2); 4058 ttarg3 = typeOfIRExpr(tyenv, triop->arg3); 4059 if (t_arg1 != ttarg1 || t_arg2 != ttarg2 || t_arg3 != ttarg3) { 4060 vex_printf(" op name: "); 4061 ppIROp(triop->op); 4062 vex_printf("\n"); 4063 vex_printf(" op type is ("); 4064 ppIRType(t_arg1); 4065 vex_printf(","); 4066 ppIRType(t_arg2); 4067 vex_printf(","); 4068 ppIRType(t_arg3); 4069 vex_printf(") -> "); 4070 ppIRType (t_dst); 4071 vex_printf("\narg tys are ("); 4072 ppIRType(ttarg1); 4073 vex_printf(","); 4074 ppIRType(ttarg2); 4075 vex_printf(","); 4076 ppIRType(ttarg3); 4077 vex_printf(")\n"); 4078 sanityCheckFail(bb,stmt, 4079 "Iex.Triop: arg tys don't match op tys\n" 4080 "... additional details precede BB printout\n"); 4081 } 4082 break; 4083 } 4084 case Iex_Binop: { 4085 IRType ttarg1, ttarg2; 4086 tcExpr(bb,stmt, expr->Iex.Binop.arg1, gWordTy ); 4087 tcExpr(bb,stmt, expr->Iex.Binop.arg2, gWordTy ); 4088 typeOfPrimop(expr->Iex.Binop.op, 4089 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 4090 if (t_arg1 == Ity_INVALID || t_arg2 == Ity_INVALID 4091 || t_arg3 != Ity_INVALID || t_arg4 != Ity_INVALID) { 4092 vex_printf(" op name: " ); 4093 ppIROp(expr->Iex.Binop.op); 4094 vex_printf("\n"); 4095 sanityCheckFail(bb,stmt, 4096 "Iex.Binop: wrong arity op\n" 4097 "... name of op precedes BB printout\n"); 4098 } 4099 ttarg1 = typeOfIRExpr(tyenv, expr->Iex.Binop.arg1); 4100 ttarg2 = typeOfIRExpr(tyenv, expr->Iex.Binop.arg2); 4101 if (t_arg1 != ttarg1 || t_arg2 != ttarg2) { 4102 vex_printf(" op name: "); 4103 ppIROp(expr->Iex.Binop.op); 4104 vex_printf("\n"); 4105 vex_printf(" op type is ("); 4106 ppIRType(t_arg1); 4107 vex_printf(","); 4108 ppIRType(t_arg2); 4109 vex_printf(") -> "); 4110 ppIRType (t_dst); 4111 vex_printf("\narg tys are ("); 4112 ppIRType(ttarg1); 4113 vex_printf(","); 4114 ppIRType(ttarg2); 4115 vex_printf(")\n"); 4116 sanityCheckFail(bb,stmt, 4117 "Iex.Binop: arg tys don't match op tys\n" 4118 "... additional details precede BB printout\n"); 4119 } 4120 break; 4121 } 4122 case Iex_Unop: 4123 tcExpr(bb,stmt, expr->Iex.Unop.arg, gWordTy ); 4124 typeOfPrimop(expr->Iex.Unop.op, 4125 &t_dst, &t_arg1, &t_arg2, &t_arg3, &t_arg4); 4126 if (t_arg1 == Ity_INVALID || t_arg2 != Ity_INVALID 4127 || t_arg3 != Ity_INVALID || t_arg4 != Ity_INVALID) 4128 sanityCheckFail(bb,stmt,"Iex.Unop: wrong arity op"); 4129 if (t_arg1 != typeOfIRExpr(tyenv, expr->Iex.Unop.arg)) 4130 sanityCheckFail(bb,stmt,"Iex.Unop: arg ty doesn't match op ty"); 4131 break; 4132 case Iex_Load: 4133 tcExpr(bb,stmt, expr->Iex.Load.addr, gWordTy); 4134 if (typeOfIRExpr(tyenv, expr->Iex.Load.addr) != gWordTy) 4135 sanityCheckFail(bb,stmt,"Iex.Load.addr: not :: guest word type"); 4136 if (expr->Iex.Load.end != Iend_LE && expr->Iex.Load.end != Iend_BE) 4137 sanityCheckFail(bb,stmt,"Iex.Load.end: bogus endianness"); 4138 break; 4139 case Iex_CCall: 4140 if (!saneIRCallee(expr->Iex.CCall.cee)) 4141 sanityCheckFail(bb,stmt,"Iex.CCall.cee: bad IRCallee"); 4142 if (expr->Iex.CCall.cee->regparms > countArgs(expr->Iex.CCall.args)) 4143 sanityCheckFail(bb,stmt,"Iex.CCall.cee: #regparms > #args"); 4144 for (i = 0; expr->Iex.CCall.args[i]; i++) { 4145 if (i >= 32) 4146 sanityCheckFail(bb,stmt,"Iex.CCall: > 32 args"); 4147 IRExpr* arg = expr->Iex.CCall.args[i]; 4148 if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(arg))) 4149 sanityCheckFail(bb,stmt,"Iex.CCall.args: is VECRET/BBPTR"); 4150 tcExpr(bb,stmt, arg, gWordTy); 4151 } 4152 if (expr->Iex.CCall.retty == Ity_I1) 4153 sanityCheckFail(bb,stmt,"Iex.CCall.retty: cannot return :: Ity_I1"); 4154 for (i = 0; expr->Iex.CCall.args[i]; i++) 4155 if (typeOfIRExpr(tyenv, expr->Iex.CCall.args[i]) == Ity_I1) 4156 sanityCheckFail(bb,stmt,"Iex.CCall.arg: arg :: Ity_I1"); 4157 break; 4158 case Iex_Const: 4159 if (!saneIRConst(expr->Iex.Const.con)) 4160 sanityCheckFail(bb,stmt,"Iex.Const.con: invalid const"); 4161 break; 4162 case Iex_ITE: 4163 tcExpr(bb,stmt, expr->Iex.ITE.cond, gWordTy); 4164 tcExpr(bb,stmt, expr->Iex.ITE.iftrue, gWordTy); 4165 tcExpr(bb,stmt, expr->Iex.ITE.iffalse, gWordTy); 4166 if (typeOfIRExpr(tyenv, expr->Iex.ITE.cond) != Ity_I1) 4167 sanityCheckFail(bb,stmt,"Iex.ITE.cond: cond :: Ity_I1"); 4168 if (typeOfIRExpr(tyenv, expr->Iex.ITE.iftrue) 4169 != typeOfIRExpr(tyenv, expr->Iex.ITE.iffalse)) 4170 sanityCheckFail(bb,stmt,"Iex.ITE: iftrue/iffalse mismatch"); 4171 break; 4172 default: 4173 vpanic("tcExpr"); 4174 } 4175 } 4176 4177 4178 static 4179 void tcStmt ( const IRSB* bb, const IRStmt* stmt, IRType gWordTy ) 4180 { 4181 Int i; 4182 IRType tyExpd, tyData; 4183 const IRTypeEnv* tyenv = bb->tyenv; 4184 switch (stmt->tag) { 4185 case Ist_IMark: 4186 /* Somewhat heuristic, but rule out totally implausible 4187 instruction sizes and deltas. */ 4188 if (stmt->Ist.IMark.len > 24) 4189 sanityCheckFail(bb,stmt,"IRStmt.IMark.len: implausible"); 4190 if (stmt->Ist.IMark.delta > 1) 4191 sanityCheckFail(bb,stmt,"IRStmt.IMark.delta: implausible"); 4192 break; 4193 case Ist_AbiHint: 4194 if (typeOfIRExpr(tyenv, stmt->Ist.AbiHint.base) != gWordTy) 4195 sanityCheckFail(bb,stmt,"IRStmt.AbiHint.base: " 4196 "not :: guest word type"); 4197 if (typeOfIRExpr(tyenv, stmt->Ist.AbiHint.nia) != gWordTy) 4198 sanityCheckFail(bb,stmt,"IRStmt.AbiHint.nia: " 4199 "not :: guest word type"); 4200 break; 4201 case Ist_Put: 4202 tcExpr( bb, stmt, stmt->Ist.Put.data, gWordTy ); 4203 if (typeOfIRExpr(tyenv,stmt->Ist.Put.data) == Ity_I1) 4204 sanityCheckFail(bb,stmt,"IRStmt.Put.data: cannot Put :: Ity_I1"); 4205 break; 4206 case Ist_PutI:{ 4207 const IRPutI* puti = stmt->Ist.PutI.details; 4208 tcExpr( bb, stmt, puti->data, gWordTy ); 4209 tcExpr( bb, stmt, puti->ix, gWordTy ); 4210 if (typeOfIRExpr(tyenv,puti->data) == Ity_I1) 4211 sanityCheckFail(bb,stmt,"IRStmt.PutI.data: cannot PutI :: Ity_I1"); 4212 if (typeOfIRExpr(tyenv,puti->data) 4213 != puti->descr->elemTy) 4214 sanityCheckFail(bb,stmt,"IRStmt.PutI.data: data ty != elem ty"); 4215 if (typeOfIRExpr(tyenv,puti->ix) != Ity_I32) 4216 sanityCheckFail(bb,stmt,"IRStmt.PutI.ix: not :: Ity_I32"); 4217 if (!saneIRRegArray(puti->descr)) 4218 sanityCheckFail(bb,stmt,"IRStmt.PutI.descr: invalid descr"); 4219 break; 4220 } 4221 case Ist_WrTmp: 4222 tcExpr( bb, stmt, stmt->Ist.WrTmp.data, gWordTy ); 4223 if (typeOfIRTemp(tyenv, stmt->Ist.WrTmp.tmp) 4224 != typeOfIRExpr(tyenv, stmt->Ist.WrTmp.data)) 4225 sanityCheckFail(bb,stmt, 4226 "IRStmt.Put.Tmp: tmp and expr do not match"); 4227 break; 4228 case Ist_Store: 4229 tcExpr( bb, stmt, stmt->Ist.Store.addr, gWordTy ); 4230 tcExpr( bb, stmt, stmt->Ist.Store.data, gWordTy ); 4231 if (typeOfIRExpr(tyenv, stmt->Ist.Store.addr) != gWordTy) 4232 sanityCheckFail(bb,stmt, 4233 "IRStmt.Store.addr: not :: guest word type"); 4234 if (typeOfIRExpr(tyenv, stmt->Ist.Store.data) == Ity_I1) 4235 sanityCheckFail(bb,stmt, 4236 "IRStmt.Store.data: cannot Store :: Ity_I1"); 4237 if (stmt->Ist.Store.end != Iend_LE && stmt->Ist.Store.end != Iend_BE) 4238 sanityCheckFail(bb,stmt,"Ist.Store.end: bogus endianness"); 4239 break; 4240 case Ist_StoreG: { 4241 const IRStoreG* sg = stmt->Ist.StoreG.details; 4242 tcExpr( bb, stmt, sg->addr, gWordTy ); 4243 tcExpr( bb, stmt, sg->data, gWordTy ); 4244 tcExpr( bb, stmt, sg->guard, gWordTy ); 4245 if (typeOfIRExpr(tyenv, sg->addr) != gWordTy) 4246 sanityCheckFail(bb,stmt,"IRStmtG...addr: not :: guest word type"); 4247 if (typeOfIRExpr(tyenv, sg->data) == Ity_I1) 4248 sanityCheckFail(bb,stmt,"IRStmtG...data: cannot Store :: Ity_I1"); 4249 if (typeOfIRExpr(tyenv, sg->guard) != Ity_I1) 4250 sanityCheckFail(bb,stmt,"IRStmtG...guard: not :: Ity_I1"); 4251 if (sg->end != Iend_LE && sg->end != Iend_BE) 4252 sanityCheckFail(bb,stmt,"IRStmtG...end: bogus endianness"); 4253 break; 4254 } 4255 case Ist_LoadG: { 4256 const IRLoadG* lg = stmt->Ist.LoadG.details; 4257 tcExpr( bb, stmt, lg->addr, gWordTy ); 4258 tcExpr( bb, stmt, lg->alt, gWordTy ); 4259 tcExpr( bb, stmt, lg->guard, gWordTy ); 4260 if (typeOfIRExpr(tyenv, lg->guard) != Ity_I1) 4261 sanityCheckFail(bb,stmt,"IRStmt.LoadG.guard: not :: Ity_I1"); 4262 if (typeOfIRExpr(tyenv, lg->addr) != gWordTy) 4263 sanityCheckFail(bb,stmt,"IRStmt.LoadG.addr: not " 4264 ":: guest word type"); 4265 if (typeOfIRExpr(tyenv, lg->alt) != typeOfIRTemp(tyenv, lg->dst)) 4266 sanityCheckFail(bb,stmt,"IRStmt.LoadG: dst/alt type mismatch"); 4267 IRTemp cvtRes = Ity_INVALID, cvtArg = Ity_INVALID; 4268 typeOfIRLoadGOp(lg->cvt, &cvtRes, &cvtArg); 4269 if (cvtRes != typeOfIRTemp(tyenv, lg->dst)) 4270 sanityCheckFail(bb,stmt,"IRStmt.LoadG: dst/loaded type mismatch"); 4271 break; 4272 } 4273 case Ist_CAS: { 4274 const IRCAS* cas = stmt->Ist.CAS.details; 4275 /* make sure it's definitely either a CAS or a DCAS */ 4276 if (cas->oldHi == IRTemp_INVALID 4277 && cas->expdHi == NULL && cas->dataHi == NULL) { 4278 /* fine; it's a single cas */ 4279 } 4280 else 4281 if (cas->oldHi != IRTemp_INVALID 4282 && cas->expdHi != NULL && cas->dataHi != NULL) { 4283 /* fine; it's a double cas */ 4284 } 4285 else { 4286 /* it's some el-mutanto hybrid */ 4287 goto bad_cas; 4288 } 4289 /* check the address type */ 4290 tcExpr( bb, stmt, cas->addr, gWordTy ); 4291 if (typeOfIRExpr(tyenv, cas->addr) != gWordTy) goto bad_cas; 4292 /* check types on the {old,expd,data}Lo components agree */ 4293 tyExpd = typeOfIRExpr(tyenv, cas->expdLo); 4294 tyData = typeOfIRExpr(tyenv, cas->dataLo); 4295 if (tyExpd != tyData) goto bad_cas; 4296 if (tyExpd != typeOfIRTemp(tyenv, cas->oldLo)) 4297 goto bad_cas; 4298 /* check the base element type is sane */ 4299 if (tyExpd == Ity_I8 || tyExpd == Ity_I16 || tyExpd == Ity_I32 4300 || (gWordTy == Ity_I64 && tyExpd == Ity_I64)) { 4301 /* fine */ 4302 } else { 4303 goto bad_cas; 4304 } 4305 /* If it's a DCAS, check types on the {old,expd,data}Hi 4306 components too */ 4307 if (cas->oldHi != IRTemp_INVALID) { 4308 tyExpd = typeOfIRExpr(tyenv, cas->expdHi); 4309 tyData = typeOfIRExpr(tyenv, cas->dataHi); 4310 if (tyExpd != tyData) goto bad_cas; 4311 if (tyExpd != typeOfIRTemp(tyenv, cas->oldHi)) 4312 goto bad_cas; 4313 /* and finally check that oldLo and oldHi have the same 4314 type. This forces equivalence amongst all 6 types. */ 4315 if (typeOfIRTemp(tyenv, cas->oldHi) 4316 != typeOfIRTemp(tyenv, cas->oldLo)) 4317 goto bad_cas; 4318 } 4319 break; 4320 bad_cas: 4321 sanityCheckFail(bb,stmt,"IRStmt.CAS: ill-formed"); 4322 break; 4323 } 4324 case Ist_LLSC: { 4325 IRType tyRes; 4326 if (typeOfIRExpr(tyenv, stmt->Ist.LLSC.addr) != gWordTy) 4327 sanityCheckFail(bb,stmt,"IRStmt.LLSC.addr: not :: guest word type"); 4328 if (stmt->Ist.LLSC.end != Iend_LE && stmt->Ist.LLSC.end != Iend_BE) 4329 sanityCheckFail(bb,stmt,"Ist.LLSC.end: bogus endianness"); 4330 tyRes = typeOfIRTemp(tyenv, stmt->Ist.LLSC.result); 4331 if (stmt->Ist.LLSC.storedata == NULL) { 4332 /* it's a LL */ 4333 if (tyRes != Ity_I64 && tyRes != Ity_I32 4334 && tyRes != Ity_I16 && tyRes != Ity_I8) 4335 sanityCheckFail(bb,stmt,"Ist.LLSC(LL).result :: bogus"); 4336 } else { 4337 /* it's a SC */ 4338 if (tyRes != Ity_I1) 4339 sanityCheckFail(bb,stmt,"Ist.LLSC(SC).result: not :: Ity_I1"); 4340 tyData = typeOfIRExpr(tyenv, stmt->Ist.LLSC.storedata); 4341 if (tyData != Ity_I64 && tyData != Ity_I32 4342 && tyData != Ity_I16 && tyData != Ity_I8) 4343 sanityCheckFail(bb,stmt, 4344 "Ist.LLSC(SC).result :: storedata bogus"); 4345 } 4346 break; 4347 } 4348 case Ist_Dirty: { 4349 /* Mostly check for various kinds of ill-formed dirty calls. */ 4350 const IRDirty* d = stmt->Ist.Dirty.details; 4351 if (d->cee == NULL) goto bad_dirty; 4352 if (!saneIRCallee(d->cee)) goto bad_dirty; 4353 if (d->cee->regparms > countArgs(d->args)) goto bad_dirty; 4354 if (d->mFx == Ifx_None) { 4355 if (d->mAddr != NULL || d->mSize != 0) 4356 goto bad_dirty; 4357 } else { 4358 if (d->mAddr == NULL || d->mSize == 0) 4359 goto bad_dirty; 4360 } 4361 if (d->nFxState < 0 || d->nFxState > VEX_N_FXSTATE) 4362 goto bad_dirty; 4363 for (i = 0; i < d->nFxState; i++) { 4364 if (d->fxState[i].fx == Ifx_None) goto bad_dirty; 4365 if (d->fxState[i].size <= 0) goto bad_dirty; 4366 if (d->fxState[i].nRepeats == 0) { 4367 if (d->fxState[i].repeatLen != 0) goto bad_dirty; 4368 } else { 4369 if (d->fxState[i].repeatLen <= d->fxState[i].size) 4370 goto bad_dirty; 4371 /* the % is safe because of the .size check above */ 4372 if ((d->fxState[i].repeatLen % d->fxState[i].size) != 0) 4373 goto bad_dirty; 4374 } 4375 } 4376 /* check guard */ 4377 if (d->guard == NULL) goto bad_dirty; 4378 tcExpr( bb, stmt, d->guard, gWordTy ); 4379 if (typeOfIRExpr(tyenv, d->guard) != Ity_I1) 4380 sanityCheckFail(bb,stmt,"IRStmt.Dirty.guard not :: Ity_I1"); 4381 /* check types, minimally */ 4382 IRType retTy = Ity_INVALID; 4383 if (d->tmp != IRTemp_INVALID) { 4384 retTy = typeOfIRTemp(tyenv, d->tmp); 4385 if (retTy == Ity_I1) 4386 sanityCheckFail(bb,stmt,"IRStmt.Dirty.dst :: Ity_I1"); 4387 } 4388 UInt nVECRETs = 0, nBBPTRs = 0; 4389 for (i = 0; d->args[i] != NULL; i++) { 4390 if (i >= 32) 4391 sanityCheckFail(bb,stmt,"IRStmt.Dirty: > 32 args"); 4392 const IRExpr* arg = d->args[i]; 4393 if (UNLIKELY(arg->tag == Iex_VECRET)) { 4394 nVECRETs++; 4395 } else if (UNLIKELY(arg->tag == Iex_BBPTR)) { 4396 nBBPTRs++; 4397 } else { 4398 if (typeOfIRExpr(tyenv, arg) == Ity_I1) 4399 sanityCheckFail(bb,stmt,"IRStmt.Dirty.arg[i] :: Ity_I1"); 4400 } 4401 if (nBBPTRs > 1) { 4402 sanityCheckFail(bb,stmt,"IRStmt.Dirty.args: > 1 BBPTR arg"); 4403 } 4404 if (nVECRETs == 1) { 4405 /* Fn must return V128 or V256. */ 4406 if (retTy != Ity_V128 && retTy != Ity_V256) 4407 sanityCheckFail(bb,stmt, 4408 "IRStmt.Dirty.args: VECRET present, " 4409 "but fn does not return V128 or V256"); 4410 } else if (nVECRETs == 0) { 4411 /* Fn must not return V128 or V256 */ 4412 if (retTy == Ity_V128 || retTy == Ity_V256) 4413 sanityCheckFail(bb,stmt, 4414 "IRStmt.Dirty.args: VECRET not present, " 4415 "but fn returns V128 or V256"); 4416 } else { 4417 sanityCheckFail(bb,stmt, 4418 "IRStmt.Dirty.args: > 1 VECRET present"); 4419 } 4420 } 4421 if (nBBPTRs > 1) { 4422 sanityCheckFail(bb,stmt, 4423 "IRStmt.Dirty.args: > 1 BBPTR present"); 4424 } 4425 /* If you ask for the baseblock pointer, you have to make 4426 some declaration about access to the guest state too. */ 4427 if (d->nFxState == 0 && nBBPTRs != 0) { 4428 sanityCheckFail(bb,stmt, 4429 "IRStmt.Dirty.args: BBPTR requested, " 4430 "but no fxState declared"); 4431 } 4432 break; 4433 bad_dirty: 4434 sanityCheckFail(bb,stmt,"IRStmt.Dirty: ill-formed"); 4435 break; 4436 } 4437 case Ist_NoOp: 4438 break; 4439 case Ist_MBE: 4440 switch (stmt->Ist.MBE.event) { 4441 case Imbe_Fence: case Imbe_CancelReservation: 4442 break; 4443 default: sanityCheckFail(bb,stmt,"IRStmt.MBE.event: unknown"); 4444 break; 4445 } 4446 break; 4447 case Ist_Exit: 4448 tcExpr( bb, stmt, stmt->Ist.Exit.guard, gWordTy ); 4449 if (typeOfIRExpr(tyenv,stmt->Ist.Exit.guard) != Ity_I1) 4450 sanityCheckFail(bb,stmt,"IRStmt.Exit.guard: not :: Ity_I1"); 4451 if (!saneIRConst(stmt->Ist.Exit.dst)) 4452 sanityCheckFail(bb,stmt,"IRStmt.Exit.dst: bad dst"); 4453 if (typeOfIRConst(stmt->Ist.Exit.dst) != gWordTy) 4454 sanityCheckFail(bb,stmt,"IRStmt.Exit.dst: not :: guest word type"); 4455 /* because it would intersect with host_EvC_* */ 4456 if (stmt->Ist.Exit.offsIP < 16) 4457 sanityCheckFail(bb,stmt,"IRStmt.Exit.offsIP: too low"); 4458 break; 4459 default: 4460 vpanic("tcStmt"); 4461 } 4462 } 4463 4464 void sanityCheckIRSB ( const IRSB* bb, const HChar* caller, 4465 Bool require_flat, IRType guest_word_size ) 4466 { 4467 Int i; 4468 Int n_temps = bb->tyenv->types_used; 4469 Int* def_counts = LibVEX_Alloc_inline(n_temps * sizeof(Int)); 4470 4471 if (0) 4472 vex_printf("sanityCheck: %s\n", caller); 4473 4474 vassert(guest_word_size == Ity_I32 4475 || guest_word_size == Ity_I64); 4476 4477 if (bb->stmts_used < 0 || bb->stmts_size < 8 4478 || bb->stmts_used > bb->stmts_size) 4479 /* this BB is so strange we can't even print it */ 4480 vpanic("sanityCheckIRSB: stmts array limits wierd"); 4481 4482 /* Ensure each temp has a plausible type. */ 4483 for (i = 0; i < n_temps; i++) { 4484 IRType ty = typeOfIRTemp(bb->tyenv,(IRTemp)i); 4485 if (!isPlausibleIRType(ty)) { 4486 vex_printf("Temp t%d declared with implausible type 0x%x\n", 4487 i, (UInt)ty); 4488 sanityCheckFail(bb,NULL,"Temp declared with implausible type"); 4489 } 4490 } 4491 4492 const IRStmt* stmt; 4493 4494 /* Check for flatness, if required. */ 4495 if (require_flat) { 4496 for (i = 0; i < bb->stmts_used; i++) { 4497 stmt = bb->stmts[i]; 4498 if (!stmt) 4499 sanityCheckFail(bb, stmt, "IRStmt: is NULL"); 4500 if (!isFlatIRStmt(stmt)) 4501 sanityCheckFail(bb, stmt, "IRStmt: is not flat"); 4502 } 4503 if (!isIRAtom(bb->next)) 4504 sanityCheckFail(bb, NULL, "bb->next is not an atom"); 4505 } 4506 4507 /* Count the defs of each temp. Only one def is allowed. 4508 Also, check that each used temp has already been defd. */ 4509 4510 for (i = 0; i < n_temps; i++) 4511 def_counts[i] = 0; 4512 4513 for (i = 0; i < bb->stmts_used; i++) { 4514 stmt = bb->stmts[i]; 4515 /* Check any temps used by this statement. */ 4516 useBeforeDef_Stmt(bb,stmt,def_counts); 4517 4518 /* Now make note of any temps defd by this statement. */ 4519 switch (stmt->tag) { 4520 case Ist_WrTmp: 4521 if (stmt->Ist.WrTmp.tmp < 0 || stmt->Ist.WrTmp.tmp >= n_temps) 4522 sanityCheckFail(bb, stmt, 4523 "IRStmt.Tmp: destination tmp is out of range"); 4524 def_counts[stmt->Ist.WrTmp.tmp]++; 4525 if (def_counts[stmt->Ist.WrTmp.tmp] > 1) 4526 sanityCheckFail(bb, stmt, 4527 "IRStmt.Tmp: destination tmp is assigned more than once"); 4528 break; 4529 case Ist_LoadG: { 4530 const IRLoadG* lg = stmt->Ist.LoadG.details; 4531 if (lg->dst < 0 || lg->dst >= n_temps) 4532 sanityCheckFail(bb, stmt, 4533 "IRStmt.LoadG: destination tmp is out of range"); 4534 def_counts[lg->dst]++; 4535 if (def_counts[lg->dst] > 1) 4536 sanityCheckFail(bb, stmt, 4537 "IRStmt.LoadG: destination tmp is assigned more than once"); 4538 break; 4539 } 4540 case Ist_Dirty: { 4541 const IRDirty* d = stmt->Ist.Dirty.details; 4542 if (d->tmp != IRTemp_INVALID) { 4543 if (d->tmp < 0 || d->tmp >= n_temps) 4544 sanityCheckFail(bb, stmt, 4545 "IRStmt.Dirty: destination tmp is out of range"); 4546 def_counts[d->tmp]++; 4547 if (def_counts[d->tmp] > 1) 4548 sanityCheckFail(bb, stmt, 4549 "IRStmt.Dirty: destination tmp is assigned more than once"); 4550 } 4551 break; 4552 } 4553 case Ist_CAS: { 4554 const IRCAS* cas = stmt->Ist.CAS.details; 4555 if (cas->oldHi != IRTemp_INVALID) { 4556 if (cas->oldHi < 0 || cas->oldHi >= n_temps) 4557 sanityCheckFail(bb, stmt, 4558 "IRStmt.CAS: destination tmpHi is out of range"); 4559 def_counts[cas->oldHi]++; 4560 if (def_counts[cas->oldHi] > 1) 4561 sanityCheckFail(bb, stmt, 4562 "IRStmt.CAS: destination tmpHi is assigned more than once"); 4563 } 4564 if (cas->oldLo < 0 || cas->oldLo >= n_temps) 4565 sanityCheckFail(bb, stmt, 4566 "IRStmt.CAS: destination tmpLo is out of range"); 4567 def_counts[cas->oldLo]++; 4568 if (def_counts[cas->oldLo] > 1) 4569 sanityCheckFail(bb, stmt, 4570 "IRStmt.CAS: destination tmpLo is assigned more than once"); 4571 break; 4572 } 4573 case Ist_LLSC: 4574 if (stmt->Ist.LLSC.result < 0 || stmt->Ist.LLSC.result >= n_temps) 4575 sanityCheckFail(bb, stmt, 4576 "IRStmt.LLSC: destination tmp is out of range"); 4577 def_counts[stmt->Ist.LLSC.result]++; 4578 if (def_counts[stmt->Ist.LLSC.result] > 1) 4579 sanityCheckFail(bb, stmt, 4580 "IRStmt.LLSC: destination tmp is assigned more than once"); 4581 break; 4582 default: 4583 /* explicitly handle the rest, so as to keep gcc quiet */ 4584 break; 4585 } 4586 } 4587 4588 /* Typecheck everything. */ 4589 for (i = 0; i < bb->stmts_used; i++) 4590 if (bb->stmts[i]) 4591 tcStmt( bb, bb->stmts[i], guest_word_size ); 4592 if (typeOfIRExpr(bb->tyenv,bb->next) != guest_word_size) 4593 sanityCheckFail(bb, NULL, "bb->next field has wrong type"); 4594 /* because it would intersect with host_EvC_* */ 4595 if (bb->offsIP < 16) 4596 sanityCheckFail(bb, NULL, "bb->offsIP: too low"); 4597 } 4598 4599 /*---------------------------------------------------------------*/ 4600 /*--- Misc helper functions ---*/ 4601 /*---------------------------------------------------------------*/ 4602 4603 Bool eqIRConst ( const IRConst* c1, const IRConst* c2 ) 4604 { 4605 if (c1->tag != c2->tag) 4606 return False; 4607 4608 switch (c1->tag) { 4609 case Ico_U1: return toBool( (1 & c1->Ico.U1) == (1 & c2->Ico.U1) ); 4610 case Ico_U8: return toBool( c1->Ico.U8 == c2->Ico.U8 ); 4611 case Ico_U16: return toBool( c1->Ico.U16 == c2->Ico.U16 ); 4612 case Ico_U32: return toBool( c1->Ico.U32 == c2->Ico.U32 ); 4613 case Ico_U64: return toBool( c1->Ico.U64 == c2->Ico.U64 ); 4614 case Ico_F32: return toBool( c1->Ico.F32 == c2->Ico.F32 ); 4615 case Ico_F32i: return toBool( c1->Ico.F32i == c2->Ico.F32i ); 4616 case Ico_F64: return toBool( c1->Ico.F64 == c2->Ico.F64 ); 4617 case Ico_F64i: return toBool( c1->Ico.F64i == c2->Ico.F64i ); 4618 case Ico_V128: return toBool( c1->Ico.V128 == c2->Ico.V128 ); 4619 case Ico_V256: return toBool( c1->Ico.V256 == c2->Ico.V256 ); 4620 default: vpanic("eqIRConst"); 4621 } 4622 } 4623 4624 Bool eqIRRegArray ( const IRRegArray* descr1, const IRRegArray* descr2 ) 4625 { 4626 return toBool( descr1->base == descr2->base 4627 && descr1->elemTy == descr2->elemTy 4628 && descr1->nElems == descr2->nElems ); 4629 } 4630 4631 Int sizeofIRType ( IRType ty ) 4632 { 4633 switch (ty) { 4634 case Ity_I8: return 1; 4635 case Ity_I16: return 2; 4636 case Ity_I32: return 4; 4637 case Ity_I64: return 8; 4638 case Ity_I128: return 16; 4639 case Ity_F16: return 2; 4640 case Ity_F32: return 4; 4641 case Ity_F64: return 8; 4642 case Ity_F128: return 16; 4643 case Ity_D32: return 4; 4644 case Ity_D64: return 8; 4645 case Ity_D128: return 16; 4646 case Ity_V128: return 16; 4647 case Ity_V256: return 32; 4648 default: vex_printf("\n"); ppIRType(ty); vex_printf("\n"); 4649 vpanic("sizeofIRType"); 4650 } 4651 } 4652 4653 IRType integerIRTypeOfSize ( Int szB ) 4654 { 4655 switch (szB) { 4656 case 8: return Ity_I64; 4657 case 4: return Ity_I32; 4658 case 2: return Ity_I16; 4659 case 1: return Ity_I8; 4660 default: vpanic("integerIRTypeOfSize"); 4661 } 4662 } 4663 4664 IRExpr* mkIRExpr_HWord ( HWord hw ) 4665 { 4666 vassert(sizeof(void*) == sizeof(HWord)); 4667 if (sizeof(HWord) == 4) 4668 return IRExpr_Const(IRConst_U32((UInt)hw)); 4669 if (sizeof(HWord) == 8) 4670 return IRExpr_Const(IRConst_U64((ULong)hw)); 4671 vpanic("mkIRExpr_HWord"); 4672 } 4673 4674 IRDirty* unsafeIRDirty_0_N ( Int regparms, const HChar* name, void* addr, 4675 IRExpr** args ) 4676 { 4677 IRDirty* d = emptyIRDirty(); 4678 d->cee = mkIRCallee ( regparms, name, addr ); 4679 d->guard = IRExpr_Const(IRConst_U1(True)); 4680 d->args = args; 4681 return d; 4682 } 4683 4684 IRDirty* unsafeIRDirty_1_N ( IRTemp dst, 4685 Int regparms, const HChar* name, void* addr, 4686 IRExpr** args ) 4687 { 4688 IRDirty* d = emptyIRDirty(); 4689 d->cee = mkIRCallee ( regparms, name, addr ); 4690 d->guard = IRExpr_Const(IRConst_U1(True)); 4691 d->args = args; 4692 d->tmp = dst; 4693 return d; 4694 } 4695 4696 IRExpr* mkIRExprCCall ( IRType retty, 4697 Int regparms, const HChar* name, void* addr, 4698 IRExpr** args ) 4699 { 4700 return IRExpr_CCall ( mkIRCallee ( regparms, name, addr ), 4701 retty, args ); 4702 } 4703 4704 Bool eqIRAtom ( const IRExpr* a1, const IRExpr* a2 ) 4705 { 4706 vassert(isIRAtom(a1)); 4707 vassert(isIRAtom(a2)); 4708 if (a1->tag == Iex_RdTmp && a2->tag == Iex_RdTmp) 4709 return toBool(a1->Iex.RdTmp.tmp == a2->Iex.RdTmp.tmp); 4710 if (a1->tag == Iex_Const && a2->tag == Iex_Const) 4711 return eqIRConst(a1->Iex.Const.con, a2->Iex.Const.con); 4712 return False; 4713 } 4714 4715 /*---------------------------------------------------------------*/ 4716 /*--- end ir_defs.c ---*/ 4717 /*---------------------------------------------------------------*/ 4718
