1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 { 28 "mnemonics" : [ 29 "Cmn", // CMN{<c>}{<q>} <Rn>, #<const> ; A1 30 "Cmp", // CMP{<c>}{<q>} <Rn>, #<const> ; A1 31 "Mov", // MOV{<c>}{<q>} <Rd>, #<const> ; A1 32 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; A1 33 "Mvn", // MVN{<c>}{<q>} <Rd>, #<const> ; A1 34 "Mvns", // MVNS{<c>}{<q>} <Rd>, #<const> ; A1 35 "Teq", // TEQ{<c>}{<q>} <Rn>, #<const> ; A1 36 "Tst" // TST{<c>}{<q>} <Rn>, #<const> ; A1 37 ], 38 "description" : { 39 "operands": [ 40 { 41 "name": "cond", 42 "type": "Condition" 43 }, 44 { 45 "name": "rd", 46 "type": "AllRegisters" 47 }, 48 { 49 "name": "op", 50 "wrapper": "Operand", 51 "operands": [ 52 { 53 "name": "immediate", 54 "type": "A32ModifiedImmediate" 55 } 56 ] 57 } 58 ], 59 "inputs": [ 60 { 61 "name": "apsr", 62 "type": "NZCV" 63 }, 64 { 65 "name": "rd", 66 "type": "Register" 67 } 68 ] 69 }, 70 "test-files": [ 71 { 72 "name": "cannot-use-pc", 73 "type": "assembler", 74 "mnemonics": [ 75 "Mov", // MOV{<c>}{<q>} <Rd>, #<const> ; A1 76 "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; A1 77 "Mvn", // MVN{<c>}{<q>} <Rd>, #<const> ; A1 78 "Mvns" // MVNS{<c>}{<q>} <Rd>, #<const> ; A1 79 ], 80 "test-cases": [ 81 { 82 "name": "Operands", 83 "operands": [ 84 "cond", "rd", "immediate" 85 ], 86 "operand-filter": "rd != 'r15'", 87 "operand-limit": 500 88 } 89 ] 90 }, 91 { 92 "name": "can-use-pc", 93 "type": "assembler", 94 "mnemonics": [ 95 "Cmn", // CMN{<c>}{<q>} <Rn>, #<const> ; A1 96 "Cmp", // CMP{<c>}{<q>} <Rn>, #<const> ; A1 97 "Teq", // TEQ{<c>}{<q>} <Rn>, #<const> ; A1 98 "Tst" // TST{<c>}{<q>} <Rn>, #<const> ; A1 99 ], 100 "test-cases": [ 101 { 102 "name": "Operands", 103 "operands": [ 104 "cond", "rd", "immediate" 105 ], 106 "operand-limit": 500 107 } 108 ] 109 }, 110 { 111 "type": "simulator", 112 "test-cases": [ 113 { 114 "name": "Condition", 115 "operands": [ 116 "cond" 117 ], 118 "inputs": [ 119 "apsr" 120 ] 121 }, 122 { 123 "name": "ModifiedImmediate", 124 "operands": [ 125 "immediate" 126 ], 127 "inputs": [ 128 "rd" 129 ] 130 } 131 ] 132 } 133 ] 134 } 135
