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      1 // Copyright 2016, VIXL authors
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 // Test description for instructions of the following form:
     28 //   MNEMONIC{<c>}.W <Rd>, #<imm16>
     29 
     30 {
     31   "mnemonics" : [
     32     "Mov",  // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
     33     "Movt", // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
     34     "Movw"  // MOVW{<c>}{<q>} <Rd>, #<imm16> ; T3
     35   ],
     36   "description" : {
     37     "operands": [
     38       {
     39         "name": "cond",
     40         "type": "Condition"
     41       },
     42       {
     43         "name": "rd",
     44         "type": "AllRegistersButPC"
     45       },
     46       {
     47         "name": "op",
     48         "wrapper": "Operand",
     49         "operands": [
     50           {
     51             "name": "immediate",
     52             "type": "Imm16"
     53           }
     54         ]
     55       }
     56     ],
     57     "inputs": [
     58       {
     59         "name": "apsr",
     60         "type": "NZCV"
     61       },
     62       {
     63         "name": "rd",
     64         "type": "Register"
     65       }
     66     ]
     67   },
     68   "test-files": [
     69     {
     70       "type": "assembler",
     71       "test-cases": [
     72         {
     73           "name": "Operands",
     74           "operands": [
     75             "cond", "rd", "immediate"
     76           ],
     77           "operand-filter": "cond == 'al'"
     78         }
     79       ]
     80     },
     81     {
     82       "type": "simulator",
     83       "mnemonics" : [
     84         "Mov",  // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
     85         "Movt"  // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
     86       ],
     87       "test-cases": [
     88         {
     89           "name": "Condition",
     90           "operands": [
     91             "cond"
     92           ],
     93           "inputs": [
     94             "apsr"
     95           ]
     96         },
     97         {
     98           "name": "ModifiedImmediate",
     99           "operands": [
    100             "immediate"
    101           ],
    102           "inputs": [
    103             "rd"
    104           ]
    105         }
    106       ]
    107     }
    108   ]
    109 }
    110