1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 { 28 "mnemonics" : [ 29 "Cmn", // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 30 "Cmp", // CMP{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 31 "Mov", // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 32 "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 33 "Mvn", // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 34 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1 35 "Teq", // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 36 "Tst" // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1 37 ], 38 "description" : { 39 "operands": [ 40 { 41 "name": "cond", 42 "type": "Condition" 43 }, 44 { 45 "name": "rd", 46 "type": "AllRegistersButPC" 47 }, 48 { 49 "name": "op", 50 "wrapper": "Operand", 51 "operands": [ 52 { 53 "name": "rn", 54 "type": "AllRegistersButPC" 55 }, 56 { 57 "name": "shift", 58 "type": "Shift1To32" 59 }, 60 { 61 "name": "amount", 62 "type": "ShiftAmount1To32" 63 } 64 ] 65 } 66 ], 67 "inputs": [ 68 { 69 "name": "apsr", 70 "type": "NZCV" 71 }, 72 { 73 "name": "rd", 74 "type": "Register" 75 }, 76 { 77 "name": "rn", 78 "type": "Register" 79 } 80 ] 81 }, 82 "test-files": [ 83 { 84 "type": "assembler", 85 "test-cases": [ 86 { 87 "name": "Operands", 88 "operands": [ 89 "cond", "rd", "rn", "shift", "amount" 90 ], 91 "operand-limit": 500 92 } 93 ] 94 }, 95 { 96 "type": "simulator", 97 "test-cases": [ 98 { 99 "name": "Condition", 100 "operands": [ 101 "cond" 102 ], 103 "inputs": [ 104 "apsr" 105 ] 106 }, 107 // Test combinations of registers values with rd == rn. 108 { 109 "name": "RdIsRn", 110 "operands": [ 111 "rd", "rn" 112 ], 113 "inputs": [ 114 "rd", "rn" 115 ], 116 "operand-filter": "rd == rn", 117 "input-filter": "rd == rn" 118 }, 119 // Test combinations of registers values. 120 { 121 "name": "RdIsNotRn", 122 "operands": [ 123 "rd", "rn" 124 ], 125 "inputs": [ 126 "rd", "rn" 127 ], 128 "operand-filter": "rd != rn", 129 "operand-limit": 10, 130 "input-limit": 200 131 }, 132 // Test combinations of shift types and register values. 133 { 134 "name": "ShiftTypes", 135 "operands": [ 136 "shift", "amount" 137 ], 138 "inputs": [ 139 "rn" 140 ] 141 } 142 ] 143 } 144 ] 145 } 146
