1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following form: 28 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ASR <Rs> 29 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSL <Rs> 30 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSR <Rs> 31 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, ROR <Rs> 32 // MNEMONIC{<c>}.W <Rd>, <Rm>, <shift> <Rs> 33 34 { 35 "mnemonics": [ 36 "Mov", // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1 37 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1 38 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1 39 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1 40 // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2 41 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1 42 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1 43 // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1 44 // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1 45 // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2 46 ], 47 "description" : { 48 "operands": [ 49 { 50 "name": "cond", 51 "type": "Condition" 52 }, 53 { 54 "name": "rd", 55 "type": "AllRegistersButPC" 56 }, 57 { 58 "name": "op", 59 "wrapper": "Operand", 60 "operands": [ 61 { 62 "name": "rn", 63 "type": "AllRegistersButPC" 64 }, 65 { 66 "name": "shift", 67 "type": "Shift" 68 }, 69 { 70 "name": "rs", 71 "type": "AllRegistersButPC" 72 } 73 ] 74 } 75 ], 76 "inputs": [ 77 { 78 "name": "apsr", 79 "type": "NZCV" 80 }, 81 { 82 "name": "rd", 83 "type": "Register" 84 }, 85 { 86 "name": "rn", 87 "type": "Register" 88 }, 89 { 90 "name": "rs", 91 "type": "RegisterShift" 92 } 93 ] 94 }, 95 "test-files": [ 96 { 97 "type": "assembler", 98 "test-cases": [ 99 { 100 "name": "Unconditionnal", 101 "operands": [ 102 "cond", "rd", "rn", "shift", "rs" 103 ], 104 "operand-filter": "cond == 'al'", 105 "operand-limit": 1000 106 } 107 ] 108 }, 109 { 110 "name": "narrow-out-it-block", 111 "type": "assembler", 112 "mnemonics" : [ 113 "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1 114 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1 115 // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1 116 // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1 117 ], 118 "test-cases": [ 119 { 120 "name": "OutITBlock", 121 "operands": [ 122 "cond", "rd", "rn", "shift", "rs" 123 ], 124 "operand-filter": "cond == 'al' and rd == rn and register_is_low(rd) and register_is_low(rs)" 125 } 126 ] 127 }, 128 { 129 "name": "in-it-block", 130 "type": "assembler", 131 "mnemonics" : [ 132 "Mov" // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1 133 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1 134 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1 135 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1 136 ], 137 "test-cases": [ 138 { 139 "name": "InITBlock", 140 "operands": [ 141 "cond", "rd", "rn", "shift", "rs" 142 ], 143 // Generate an extra IT instruction. 144 "in-it-block": "{cond}", 145 "operand-filter": "cond != 'al' and rd == rn and register_is_low(rd) and register_is_low(rs)", 146 "operand-limit": 1000 147 } 148 ] 149 }, 150 { 151 "type": "simulator", 152 "test-cases": [ 153 { 154 "name": "Condition", 155 "operands": [ 156 "cond" 157 ], 158 "inputs": [ 159 "apsr" 160 ] 161 }, 162 // Test combinations of registers values with rd == rn. 163 { 164 "name": "RdIsRn", 165 "operands": [ 166 "rd", "rn" 167 ], 168 "inputs": [ 169 "rd", "rn" 170 ], 171 "operand-filter": "rd == rn", 172 "input-filter": "rd == rn" 173 }, 174 // Test combinations of registers values with rd != rn. 175 { 176 "name": "RdIsNotRn", 177 "operands": [ 178 "rd", "rn" 179 ], 180 "inputs": [ 181 "rd", "rn" 182 ], 183 "operand-filter": "rd != rn", 184 "operand-limit": 10, 185 "input-limit": 200 186 }, 187 // Test combinations of shift types and register values. 188 { 189 "name": "ShiftTypes", 190 "operands": [ 191 "rn", "shift", "rs" 192 ], 193 "inputs": [ 194 "rn", "rs" 195 ], 196 // Make sure the registers are different. 197 "operand-filter": "rn == 'r1' and rs == 'r2'" 198 } 199 ] 200 } 201 ] 202 } 203
