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      1 // Copyright 2016, VIXL authors
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 {
     28   "mnemonics" : [
     29     "Clz",   // CLZ{<c>}{<q>} <Rd>, <Rm> ; A1
     30     "Rbit",  // RBIT{<c>}{<q>} <Rd>, <Rm> ; A1
     31     "Rev",   // REV{<c>}{<q>} <Rd>, <Rm> ; A1
     32     "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; A1
     33     "Revsh", // REVSH{<c>}{<q>} <Rd>, <Rm> ; A1
     34     "Rrx",   // RRX{<c>}{<q>} {<Rd>}, <Rm> ; A1
     35     "Rrxs"   // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; A1
     36   ],
     37   "description" : {
     38     "operands": [
     39       {
     40         "name": "cond",
     41         "type": "Condition"
     42       },
     43       {
     44         "name": "rd",
     45         "type": "AllRegistersButPC"
     46       },
     47       {
     48         "name": "rn",
     49         "type": "AllRegistersButPC"
     50       }
     51     ],
     52     "inputs": [
     53       {
     54         "name": "apsr",
     55         "type": "NZCV"
     56       },
     57       {
     58         "name": "rd",
     59         "type": "Register"
     60       },
     61       {
     62         "name": "rn",
     63         "type": "Register"
     64       }
     65     ]
     66   },
     67   "test-files": [
     68     {
     69       "type": "assembler",
     70       "test-cases": [
     71         {
     72           "name": "Operands",
     73           "operands": [
     74             "cond", "rd", "rn"
     75           ],
     76           "operand-limit": 500
     77         }
     78       ]
     79     },
     80     {
     81       "type": "macro-assembler",
     82       "test-cases": [
     83         {
     84           "name": "Operands",
     85           "operands": [
     86             "cond", "rd", "rn"
     87           ],
     88           "operand-limit": 500
     89         }
     90       ]
     91     },
     92     {
     93       "type": "simulator",
     94       "test-cases": [
     95         {
     96           "name": "Condition",
     97           "operands": [
     98             "cond"
     99           ],
    100           "inputs": [
    101             "apsr"
    102           ]
    103         },
    104         // Test combinations of registers values with rd == rn.
    105         {
    106           "name": "RdIsRn",
    107           "operands": [
    108             "rd", "rn"
    109           ],
    110           "inputs": [
    111             "rd", "rn"
    112           ],
    113           "operand-filter": "rd == rn",
    114           "input-filter": "rd == rn"
    115         },
    116         // Test combinations of registers values with rd != rn.
    117         {
    118           "name": "RdIsNotRn",
    119           "operands": [
    120             "rd", "rn"
    121           ],
    122           "inputs": [
    123             "rd", "rn"
    124           ],
    125           "operand-filter": "rd != rn",
    126           "operand-limit": 10,
    127           "input-filter": "rd != rn"
    128         }
    129       ]
    130     }
    131   ]
    132 }
    133