1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following form: 28 // MNEMONIC{<c>} <Rd>, <Rn>, <Rm>, ROR #<amount> 29 30 { 31 "mnemonics": [ 32 "Sxtab", // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 33 "Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 34 "Sxtah", // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 35 "Uxtab", // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 36 "Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 37 "Uxtah" // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1 38 ], 39 "description": { 40 "operands": [ 41 { 42 "name": "cond", 43 "type": "Condition" 44 }, 45 { 46 "name": "rd", 47 "type": "AllRegistersButPC" 48 }, 49 { 50 "name": "rn", 51 "type": "AllRegistersButPC" 52 }, 53 { 54 "name": "op", 55 "wrapper": "Operand", 56 "operands": [ 57 { 58 "name": "rm", 59 "type": "AllRegistersButPC" 60 }, 61 { 62 "name": "ror", 63 "type": "ShiftROR" 64 }, 65 { 66 "name": "amount", 67 "type": "ShiftRotationAmountX8" 68 } 69 ] 70 } 71 ], 72 "inputs": [ 73 { 74 "name": "apsr", 75 "type": "NZCV" 76 }, 77 { 78 "name": "rd", 79 "type": "Register" 80 }, 81 { 82 "name": "rn", 83 "type": "Register" 84 }, 85 { 86 "name": "rm", 87 "type": "Register" 88 } 89 ] 90 }, 91 "test-files": [ 92 { 93 "type": "assembler", 94 "test-cases": [ 95 { 96 "name": "Operands", 97 "operands": [ 98 "cond", "rd", "rn", "rm", "ror", "amount" 99 ], 100 "operand-limit": 1000 101 } 102 ] 103 }, 104 { 105 "type": "simulator", 106 "test-cases": [ 107 { 108 "name": "Condition", 109 "operands": [ 110 "cond" 111 ], 112 "inputs": [ 113 "apsr" 114 ] 115 }, 116 // Test combinations of registers values with rd == rn. 117 { 118 "name": "RdIsRn", 119 "operands": [ 120 "rd", "rn", "rm" 121 ], 122 "inputs": [ 123 "rd", "rn", "rm" 124 ], 125 "operand-filter": "rd == rn and rn != rm", 126 "operand-limit": 10, 127 "input-filter": "rd == rn", 128 "input-limit": 200 129 }, 130 // Test combinations of registers values with rd == rm. 131 { 132 "name": "RdIsRm", 133 "operands": [ 134 "rd", "rn", "rm" 135 ], 136 "inputs": [ 137 "rd", "rn", "rm" 138 ], 139 "operand-filter": "rd == rm and rn != rm", 140 "operand-limit": 10, 141 "input-filter": "rd == rm", 142 "input-limit": 200 143 }, 144 // Test combinations of registers values. 145 { 146 "name": "RdIsNotRnIsNotRm", 147 "operands": [ 148 "rd", "rn", "rm" 149 ], 150 "inputs": [ 151 "rd", "rn", "rm" 152 ], 153 "operand-filter": "rd != rn != rm", 154 "operand-limit": 10, 155 "input-limit": 200 156 }, 157 // Test combinations of rotation amounts. 158 { 159 "name": "Rotations", 160 "operands": [ 161 "rd", "rn", "rm", "ror", "amount" 162 ], 163 "inputs": [ 164 "rm" 165 ], 166 // Specify exactly what registers to use in this test to make sure 167 // that they are different. It makes the execution trace more 168 // understandable. 169 "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r2'" 170 } 171 ] 172 } 173 ] 174 } 175
