1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 { 28 "mnemonics": [ 29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 31 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 32 // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 33 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 34 // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 35 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 36 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 38 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 39 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 40 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 41 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 42 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 43 "Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 44 "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 45 "Rsc", // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 46 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 47 "Sbc", // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 48 "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 49 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 50 // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 51 "Subs" // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1 52 // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1 53 ], 54 "description": { 55 "operands": [ 56 { 57 "name": "cond", 58 "type": "Condition" 59 }, 60 { 61 "name": "rd", 62 "type": "AllRegistersButPC" 63 }, 64 { 65 "name": "rn", 66 "type": "AllRegistersButPC" 67 }, 68 { 69 "name": "op", 70 "wrapper": "Operand", 71 "operands": [ 72 { 73 "name": "rm", 74 "type": "AllRegistersButPC" 75 }, 76 { 77 "name": "shift", 78 "type": "Shift1To31" 79 }, 80 { 81 "name": "amount", 82 "type": "ShiftAmount1To31" 83 } 84 ] 85 } 86 ], 87 "inputs": [ 88 { 89 "name": "apsr", 90 "type": "NZCV" 91 }, 92 { 93 "name": "rd", 94 "type": "Register" 95 }, 96 { 97 "name": "rn", 98 "type": "Register" 99 }, 100 { 101 "name": "rm", 102 "type": "Register" 103 } 104 ] 105 }, 106 "test-files": [ 107 { 108 "type": "assembler", 109 "test-cases": [ 110 { 111 "name": "Operands", 112 "operands": [ 113 "cond", "rd", "rn", "rm", "shift", "amount" 114 ], 115 "operand-limit": 500 116 } 117 ] 118 }, 119 { 120 "type": "simulator", 121 "test-cases": [ 122 { 123 "name": "Condition", 124 "operands": [ 125 "cond" 126 ], 127 "inputs": [ 128 "apsr" 129 ] 130 }, 131 // Test combinations of registers values with rd == rn. 132 { 133 "name": "RdIsRn", 134 "operands": [ 135 "rd", "rn", "rm" 136 ], 137 "inputs": [ 138 "rd", "rn", "rm" 139 ], 140 "operand-filter": "rd == rn and rn != rm", 141 "operand-limit": 10, 142 "input-filter": "rd == rn", 143 "input-limit": 200 144 }, 145 // Test combinations of registers values with rd == rm. 146 { 147 "name": "RdIsRm", 148 "operands": [ 149 "rd", "rn", "rm" 150 ], 151 "inputs": [ 152 "rd", "rn", "rm" 153 ], 154 "operand-filter": "rd == rm and rn != rm", 155 "operand-limit": 10, 156 "input-filter": "rd == rm", 157 "input-limit": 200 158 }, 159 // Test combinations of registers values. 160 { 161 "name": "RdIsNotRnIsNotRm", 162 "operands": [ 163 "rd", "rn", "rm" 164 ], 165 "inputs": [ 166 "rd", "rn", "rm" 167 ], 168 "operand-filter": "rd != rn != rm", 169 "operand-limit": 10, 170 "input-limit": 200 171 }, 172 // Test combinations of shift types and shift amounts. 173 { 174 "name": "ShiftTypes", 175 "operands": [ 176 "rm", "shift", "amount" 177 ], 178 "inputs": [ 179 "rm" 180 ], 181 "operand-filter": "rm == 'r1'" 182 } 183 ] 184 } 185 ] 186 } 187
