1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following form: 28 // MNEMONIC{<c>}.N <Rd>, <Rm> 29 // MNEMONIC{<c>}.W <Rd>, <Rm> 30 31 { 32 "mnemonics" : [ 33 "Clz", // CLZ{<c>}{<q>} <Rd>, <Rm> ; T1 34 "Rbit", // RBIT{<c>}{<q>} <Rd>, <Rm> ; T1 35 "Rev", // REV{<c>}{<q>} <Rd>, <Rm> ; T1 36 // REV{<c>}{<q>} <Rd>, <Rm> ; T2 37 "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; T1 38 // REV16{<c>}{<q>} <Rd>, <Rm> ; T2 39 "Revsh", // REVSH{<c>}{<q>} <Rd>, <Rm> ; T1 40 // REVSH{<c>}{<q>} <Rd>, <Rm> ; T2 41 "Rrx", // RRX{<c>}{<q>} {<Rd>}, <Rm> ; T3 42 "Rrxs" // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; T3 43 ], 44 "description" : { 45 "operands": [ 46 { 47 "name": "cond", 48 "type": "Condition" 49 }, 50 { 51 "name": "rd", 52 "type": "AllRegistersButPC" 53 }, 54 { 55 "name": "rn", 56 "type": "AllRegistersButPC" 57 } 58 ], 59 "inputs": [ 60 { 61 "name": "apsr", 62 "type": "NZCV" 63 }, 64 { 65 "name": "rd", 66 "type": "Register" 67 }, 68 { 69 "name": "rn", 70 "type": "Register" 71 } 72 ] 73 }, 74 "test-files": [ 75 { 76 "type": "assembler", 77 "test-cases": [ 78 { 79 "name": "Unconditional", 80 "operands": [ 81 "cond", "rd", "rn" 82 ], 83 "operand-filter": "cond == 'al'" 84 } 85 ] 86 }, 87 { 88 "type": "macro-assembler", 89 "test-cases": [ 90 { 91 "name": "Operands", 92 "operands": [ 93 "cond", "rd", "rn" 94 ], 95 "operand-limit": 500 96 } 97 ] 98 }, 99 { 100 "type": "simulator", 101 "test-cases": [ 102 { 103 "name": "Condition", 104 "operands": [ 105 "cond" 106 ], 107 "inputs": [ 108 "apsr" 109 ] 110 }, 111 // Test combinations of registers values with rd == rn. 112 { 113 "name": "RdIsRn", 114 "operands": [ 115 "rd", "rn" 116 ], 117 "inputs": [ 118 "rd", "rn" 119 ], 120 "operand-filter": "rd == rn", 121 "input-filter": "rd == rn" 122 }, 123 // Test combinations of registers values with rd != rn. 124 { 125 "name": "RdIsNotRn", 126 "operands": [ 127 "rd", "rn" 128 ], 129 "inputs": [ 130 "rd", "rn" 131 ], 132 "operand-filter": "rd != rn", 133 "operand-limit": 10, 134 "input-filter": "rd != rn" 135 } 136 ] 137 } 138 ] 139 } 140
