1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for instructions of the following forms: 28 // MNEMONIC{<c>}.N <Rd>, <Rn>, #0 29 // MNEMONIC{<c>}.N <Rd>, <Rn>, #<imm3> 30 // MNEMONIC{<c>}.N <Rdn>, <Rdn>, #<imm8> 31 32 { 33 "mnemonics" : [ 34 "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 35 // ADD<c>{<q>} <Rdn>, #<imm8> ; T2 36 // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 37 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1 38 // ADDS{<q>} <Rdn>, #<imm8> ; T2 39 // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 40 "Rsb", // RSB<c>{<q>} {<Rd>}, <Rn>, #0 ; T1 41 "Rsbs", // RSBS{<q>} {<Rd>}, <Rn>, #0 ; T1 42 "Sub", // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 43 // SUB<c>{<q>} <Rdn>, #<imm8> ; T2 44 // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 45 "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1 46 // SUBS{<q>} <Rdn>, #<imm8> ; T2 47 // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 48 ], 49 "description" : { 50 "operands": [ 51 { 52 "name": "cond", 53 "type": "Condition" 54 }, 55 { 56 "name": "rd", 57 "type": "LowRegisters" 58 }, 59 { 60 "name": "rn", 61 "type": "LowRegisters" 62 }, 63 { 64 "name": "op", 65 "wrapper": "Operand", 66 "operands": [ 67 { 68 "name": "immediate", 69 "type": "OffsetLowerThan256" 70 } 71 ] 72 } 73 ], 74 "inputs": [ 75 { 76 "name": "apsr", 77 "type": "NZCV" 78 }, 79 { 80 "name": "rd", 81 "type": "Register" 82 }, 83 { 84 "name": "rn", 85 "type": "Register" 86 } 87 ] 88 }, 89 "test-files": [ 90 { 91 "type": "simulator", 92 "test-cases": [ 93 { 94 "name": "RdIsRn", 95 "operands": [ 96 "cond", "rd", "rn", "immediate" 97 ], 98 "inputs": [ 99 "apsr", "rd", "rn" 100 ], 101 "operand-filter": "rd == rn", 102 "operand-limit": 20, 103 "input-filter": "rd == rn", 104 "input-limit": 300 105 }, 106 { 107 "name": "RdIsNotRn", 108 "operands": [ 109 "cond", "rd", "rn", "immediate" 110 ], 111 "inputs": [ 112 "apsr", "rd", "rn" 113 ], 114 "operand-filter": "rd != rn", 115 "operand-limit": 20, 116 "input-limit": 300 117 }, 118 { 119 "name": "Immediate", 120 "operands": [ 121 "cond", "immediate" 122 ], 123 "inputs": [ 124 "apsr", "rn" 125 ], 126 "operand-limit": 20, 127 "input-limit": 300 128 } 129 ] 130 }, 131 // Test encodings with an 8 bit immediate and identical rn and rd. 132 { 133 "name": "imm8", 134 "type": "assembler", 135 "mnemonics" : [ 136 "Adds", // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 137 "Subs" // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 138 ], 139 "test-cases": [ 140 { 141 "name": "OutItBlock", 142 "operands": [ 143 "cond", "rd", "rn", "immediate" 144 ], 145 "operand-filter": "cond == 'al' and rd == rn" 146 } 147 ] 148 }, 149 { 150 "name": "imm8-in-it-block", 151 "type": "assembler", 152 "mnemonics" : [ 153 "Add", // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 154 "Sub" // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2 155 ], 156 "test-cases": [ 157 { 158 "name": "InITBlock", 159 "operands": [ 160 "cond", "rd", "rn", "immediate" 161 ], 162 // Generate an extra IT instruction. 163 "in-it-block": "{cond}", 164 "operand-filter": "cond != 'al' and rd == rn", 165 "operand-limit": 1000 166 } 167 ] 168 }, 169 // Test encodings with a 3 bit immediate and different rn and rd. 170 { 171 "name": "imm3", 172 "type": "assembler", 173 "mnemonics" : [ 174 "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1 175 "Subs" // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1 176 ], 177 "test-cases": [ 178 { 179 "name": "OutITBlock", 180 "operands": [ 181 "cond", "rd", "rn", "immediate" 182 ], 183 "operand-filter": "cond == 'al' and int(immediate) <= 7" 184 } 185 ] 186 }, 187 { 188 "name": "imm3-in-it-block", 189 "type": "assembler", 190 "mnemonics" : [ 191 "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 192 "Sub" // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 193 ], 194 "test-cases": [ 195 { 196 "name": "InITBlock", 197 "operands": [ 198 "cond", "rd", "rn", "immediate" 199 ], 200 // Generate an extra IT instruction. 201 "in-it-block": "{cond}", 202 "operand-filter": "cond != 'al' and int(immediate) <= 7", 203 "operand-limit": 1000 204 } 205 ] 206 }, 207 // Test special cases for Rsb and Rsbs where there is a special 208 // encoding when the immediate is zero. 209 { 210 "name": "zero", 211 "type": "assembler", 212 "mnemonics" : [ 213 "Rsbs" // RSBS{<q>} {<Rd>}, <Rn>, #0 ; T1 214 ], 215 "test-cases": [ 216 { 217 "name": "OutITBlock", 218 "operands": [ 219 "cond", "rd", "rn", "immediate" 220 ], 221 "operand-filter": "cond == 'al' and int(immediate) == 0" 222 } 223 ] 224 }, 225 { 226 "name": "zero-in-it-block", 227 "type": "assembler", 228 "mnemonics" : [ 229 "Rsb" // RSB<c>{<q>} {<Rd>}, <Rn>, #0 ; T1 230 ], 231 "test-cases": [ 232 { 233 "name": "InITBlock", 234 "operands": [ 235 "cond", "rd", "rn", "immediate" 236 ], 237 // Generate an extra IT instruction. 238 "in-it-block": "{cond}", 239 "operand-filter": "cond != 'al' and int(immediate) == 0" 240 } 241 ] 242 } 243 ] 244 } 245
