1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 // Test description for the MULS instruction with the following operands: 28 // MNEMONIC{<c>}.N <Rdm>, <Rn>, <Rdm> 29 30 { 31 "mnemonics": [ 32 "Mul", // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1 33 "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1 34 ], 35 "description": { 36 "operands": [ 37 { 38 "name": "cond", 39 "type": "Condition" 40 }, 41 { 42 "name": "rd", 43 "type": "LowRegisters" 44 }, 45 { 46 "name": "rn", 47 "type": "LowRegisters" 48 }, 49 { 50 "name": "rm", 51 "type": "LowRegisters" 52 } 53 ], 54 "inputs": [ 55 { 56 "name": "apsr", 57 "type": "NZCV" 58 }, 59 { 60 "name": "rd", 61 "type": "Register" 62 }, 63 { 64 "name": "rn", 65 "type": "Register" 66 }, 67 { 68 "name": "rm", 69 "type": "Register" 70 } 71 ] 72 }, 73 "test-files": [ 74 { 75 "type": "assembler", 76 "mnemonics": [ 77 "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1 78 ], 79 "test-cases": [ 80 { 81 "name": "OutItBlock", 82 "operands": [ 83 "cond", "rd", "rn", "rm" 84 ], 85 "operand-filter": "cond == 'al' and rd == rm" 86 } 87 ] 88 }, 89 { 90 "name": "in-it-block", 91 "type": "assembler", 92 "mnemonics": [ 93 "Mul" // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1 94 ], 95 "test-cases": [ 96 { 97 "name": "InITBlock", 98 "operands": [ 99 "cond", "rd", "rn", "rm" 100 ], 101 // Generate an extra IT instruction. 102 "in-it-block": "{cond}", 103 "operand-filter": "cond != 'al' and rd == rm" 104 } 105 ] 106 }, 107 { 108 "type": "simulator", 109 "test-cases": [ 110 { 111 "name": "Condition", 112 "operands": [ 113 "cond" 114 ], 115 "inputs": [ 116 "apsr" 117 ] 118 }, 119 { 120 "name": "Unconditional", 121 "operands": [ 122 "cond", "rd", "rn", "rm" 123 ], 124 "inputs": [ 125 "cond", "rd", "rn", "rm" 126 ], 127 "operand-filter": "cond == 'al' and rd == rm", 128 "operand-limit": 20, 129 "input-filter": "rd == rm", 130 "input-limit": 500 131 } 132 ] 133 } 134 ] 135 } 136
