1 #ifndef _ASM_X86_PROCESSOR_FLAGS_H 2 #define _ASM_X86_PROCESSOR_FLAGS_H 3 /* Various flags defined: can be included from assembler. */ 4 5 /* 6 * EFLAGS bits 7 */ 8 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 9 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 10 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ 11 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 12 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 13 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 14 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 15 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 16 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 17 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 18 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 19 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 20 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 21 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 22 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 23 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 24 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 25 26 /* 27 * Basic CPU control in CR0 28 */ 29 #define X86_CR0_PE 0x00000001 /* Protection Enable */ 30 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ 31 #define X86_CR0_EM 0x00000004 /* Emulation */ 32 #define X86_CR0_TS 0x00000008 /* Task Switched */ 33 #define X86_CR0_ET 0x00000010 /* Extension Type */ 34 #define X86_CR0_NE 0x00000020 /* Numeric Error */ 35 #define X86_CR0_WP 0x00010000 /* Write Protect */ 36 #define X86_CR0_AM 0x00040000 /* Alignment Mask */ 37 #define X86_CR0_NW 0x20000000 /* Not Write-through */ 38 #define X86_CR0_CD 0x40000000 /* Cache Disable */ 39 #define X86_CR0_PG 0x80000000 /* Paging */ 40 41 /* 42 * Paging options in CR3 43 */ 44 #define X86_CR3_PWT 0x00000008 /* Page Write Through */ 45 #define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ 46 47 /* 48 * Intel CPU features in CR4 49 */ 50 #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ 51 #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ 52 #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ 53 #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ 54 #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ 55 #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ 56 #define X86_CR4_MCE 0x00000040 /* Machine check enable */ 57 #define X86_CR4_PGE 0x00000080 /* enable global pages */ 58 #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ 59 #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 60 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 61 #define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ 62 #define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 63 64 /* 65 * x86-64 Task Priority Register, CR8 66 */ 67 #define X86_CR8_TPR 0x0000000F /* task priority register */ 68 69 /* 70 * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> 71 */ 72 73 /* 74 * NSC/Cyrix CPU configuration register indexes 75 */ 76 #define CX86_PCR0 0x20 77 #define CX86_GCR 0xb8 78 #define CX86_CCR0 0xc0 79 #define CX86_CCR1 0xc1 80 #define CX86_CCR2 0xc2 81 #define CX86_CCR3 0xc3 82 #define CX86_CCR4 0xe8 83 #define CX86_CCR5 0xe9 84 #define CX86_CCR6 0xea 85 #define CX86_CCR7 0xeb 86 #define CX86_PCR1 0xf0 87 #define CX86_DIR0 0xfe 88 #define CX86_DIR1 0xff 89 #define CX86_ARR_BASE 0xc4 90 #define CX86_RCR_BASE 0xdc 91 92 93 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */ 94
