1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright 1995-1997 C H Forsyth (forsyth (a] terzarima.net) 5 // Portions Copyright 1997-1999 Vita Nuova Limited 6 // Portions Copyright 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright 2004,2006 Bruce Ellis 8 // Portions Copyright 2005-2007 C H Forsyth (forsyth (a] terzarima.net) 9 // Revisions Copyright 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "encoding/binary" 35 "fmt" 36 "log" 37 "sort" 38 ) 39 40 // Instruction layout. 41 42 const ( 43 funcAlign = 8 44 ) 45 46 const ( 47 r0iszero = 1 48 ) 49 50 type Optab struct { 51 as obj.As // Opcode 52 a1 uint8 53 a2 uint8 54 a3 uint8 55 a4 uint8 56 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 57 size int8 58 param int16 59 } 60 61 var optab = []Optab{ 62 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 63 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 64 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 65 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 66 /* move register */ 67 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 68 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 69 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 70 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 71 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 72 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 73 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 74 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 75 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 76 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 77 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 78 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 79 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 80 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 81 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 82 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 83 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 84 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 85 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 86 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 87 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 88 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 89 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 90 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 91 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 92 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 93 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 94 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 95 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 96 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 97 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 98 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 99 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 100 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 101 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 102 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 103 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 104 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 105 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 106 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 107 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 108 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 109 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 110 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 111 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 112 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 113 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 114 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 115 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 116 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 117 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 118 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 119 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 120 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 121 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 122 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 124 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 125 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 126 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 127 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 128 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 129 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 130 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 131 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 132 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 133 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 134 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 135 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 136 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 137 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 138 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 139 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 140 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 141 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 142 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 143 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 144 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 145 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 146 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 147 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 148 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 149 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 150 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 151 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 152 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 153 154 /* store, short offset */ 155 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 156 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 157 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 158 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 159 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 160 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 161 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 162 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 163 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 164 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 165 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 166 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 167 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 168 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 169 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 170 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 171 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 172 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 173 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 174 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 175 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 176 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 177 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 178 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 179 180 /* load, short offset */ 181 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 182 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 183 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 184 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 185 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 186 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 187 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 188 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 189 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 190 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 191 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 192 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 193 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 194 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 195 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 196 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 197 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 198 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 200 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 201 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 202 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 203 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 204 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 205 206 /* store, long offset */ 207 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 208 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 209 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 210 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 211 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 212 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 213 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 214 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 215 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 216 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 217 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 218 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 219 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 220 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 221 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 222 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 223 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 224 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 225 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 226 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 227 228 /* load, long offset */ 229 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 230 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 231 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 232 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 233 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 234 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 235 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 236 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 237 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 238 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 239 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 240 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 241 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 242 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 243 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 244 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 245 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 246 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 247 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 248 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 249 250 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 251 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 252 253 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 254 255 /* load constant */ 256 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 257 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 258 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 259 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 260 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 261 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 262 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 263 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 264 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 265 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 266 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 267 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 268 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 269 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 270 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 271 272 /* load unsigned/long constants (TO DO: check) */ 273 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 275 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 276 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 277 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 278 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 279 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 280 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 281 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 282 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 283 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 284 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 285 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 286 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 287 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 288 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 289 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 290 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 291 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 292 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 293 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 294 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 295 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 296 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 297 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 298 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 299 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 300 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 301 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 302 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 303 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 304 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 305 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 306 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 307 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 308 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 309 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 310 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 311 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 312 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 313 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 314 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 315 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 316 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 317 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 318 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 319 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 320 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 321 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 322 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 323 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 324 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 325 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 326 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 327 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 328 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 329 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 330 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 331 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 332 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 333 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 334 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 335 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 336 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 337 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 338 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 339 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 340 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 341 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 342 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 343 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 344 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 345 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 346 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 347 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 348 349 /* Vector instructions */ 350 351 /* Vector load */ 352 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 353 354 /* Vector store */ 355 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 356 357 /* Vector logical */ 358 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 359 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 360 361 /* Vector add */ 362 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 363 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 364 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 365 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 366 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 367 368 /* Vector subtract */ 369 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 370 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 371 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 372 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 373 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 374 375 /* Vector rotate */ 376 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 377 378 /* Vector shift */ 379 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 380 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 381 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 382 383 /* Vector count */ 384 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 385 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 386 387 /* Vector compare */ 388 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 389 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 390 391 /* Vector permute */ 392 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 393 394 /* Vector select */ 395 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 396 397 /* Vector splat */ 398 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 399 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 400 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 401 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 402 403 /* Vector AES */ 404 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 405 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 406 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 407 408 /* Vector SHA */ 409 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 410 411 /* VSX vector load */ 412 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 413 414 /* VSX vector store */ 415 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 416 417 /* VSX scalar load */ 418 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 419 420 /* VSX scalar store */ 421 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 422 423 /* VSX scalar as integer load */ 424 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 425 426 /* VSX scalar store as integer */ 427 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 428 429 /* VSX move from VSR */ 430 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 431 432 /* VSX move to VSR */ 433 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 434 435 /* VSX logical */ 436 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 437 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 438 439 /* VSX select */ 440 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 441 442 /* VSX merge */ 443 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 444 445 /* VSX splat */ 446 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 447 448 /* VSX permute */ 449 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 450 451 /* VSX shift */ 452 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 453 454 /* VSX scalar FP-FP conversion */ 455 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 456 457 /* VSX vector FP-FP conversion */ 458 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 459 460 /* VSX scalar FP-integer conversion */ 461 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 462 463 /* VSX scalar integer-FP conversion */ 464 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 465 466 /* VSX vector FP-integer conversion */ 467 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 468 469 /* VSX vector integer-FP conversion */ 470 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 471 472 /* 64-bit special registers */ 473 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 474 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 475 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 476 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 477 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 478 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 479 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 480 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 481 482 /* 32-bit special registers (gloss over sign-extension or not?) */ 483 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 484 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 485 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 486 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 487 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 488 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 489 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 490 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 491 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 492 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 493 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 494 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 495 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 496 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 497 {AMOVFL, C_REG, C_NONE, C_LCON, C_CREG, 69, 4, 0}, 498 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 499 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 500 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 501 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 502 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 503 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 504 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 505 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 506 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 507 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 508 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 509 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 510 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 511 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 512 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 513 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 514 {ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0}, 515 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 516 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 517 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 518 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 519 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 520 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 521 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 522 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 523 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 524 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 525 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 526 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 527 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 528 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 529 {obj.AUSEFIELD, C_ADDR, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 530 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 531 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 532 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 533 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 534 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 535 536 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 537 } 538 539 var oprange [ALAST & obj.AMask][]Optab 540 541 var xcmp [C_NCLASS][C_NCLASS]bool 542 543 func span9(ctxt *obj.Link, cursym *obj.LSym) { 544 p := cursym.Text 545 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 546 return 547 } 548 ctxt.Cursym = cursym 549 ctxt.Autosize = int32(p.To.Offset) 550 551 if oprange[AANDN&obj.AMask] == nil { 552 buildop(ctxt) 553 } 554 555 c := int64(0) 556 p.Pc = c 557 558 var m int 559 var o *Optab 560 for p = p.Link; p != nil; p = p.Link { 561 ctxt.Curp = p 562 p.Pc = c 563 o = oplook(ctxt, p) 564 m = int(o.size) 565 if m == 0 { 566 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD { 567 ctxt.Diag("zero-width instruction\n%v", p) 568 } 569 continue 570 } 571 572 c += int64(m) 573 } 574 575 cursym.Size = c 576 577 /* 578 * if any procedure is large enough to 579 * generate a large SBRA branch, then 580 * generate extra passes putting branches 581 * around jmps to fix. this is rare. 582 */ 583 bflag := 1 584 585 var otxt int64 586 var q *obj.Prog 587 for bflag != 0 { 588 if ctxt.Debugvlog != 0 { 589 ctxt.Logf("%5.2f span1\n", obj.Cputime()) 590 } 591 bflag = 0 592 c = 0 593 for p = cursym.Text.Link; p != nil; p = p.Link { 594 p.Pc = c 595 o = oplook(ctxt, p) 596 597 // very large conditional branches 598 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 599 otxt = p.Pcond.Pc - c 600 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 601 q = ctxt.NewProg() 602 q.Link = p.Link 603 p.Link = q 604 q.As = ABR 605 q.To.Type = obj.TYPE_BRANCH 606 q.Pcond = p.Pcond 607 p.Pcond = q 608 q = ctxt.NewProg() 609 q.Link = p.Link 610 p.Link = q 611 q.As = ABR 612 q.To.Type = obj.TYPE_BRANCH 613 q.Pcond = q.Link.Link 614 615 //addnop(p->link); 616 //addnop(p); 617 bflag = 1 618 } 619 } 620 621 m = int(o.size) 622 if m == 0 { 623 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD { 624 ctxt.Diag("zero-width instruction\n%v", p) 625 } 626 continue 627 } 628 629 c += int64(m) 630 } 631 632 cursym.Size = c 633 } 634 635 c += -c & (funcAlign - 1) 636 cursym.Size = c 637 638 /* 639 * lay out the code, emitting code and data relocations. 640 */ 641 642 cursym.Grow(cursym.Size) 643 644 bp := cursym.P 645 var i int32 646 var out [6]uint32 647 for p := cursym.Text.Link; p != nil; p = p.Link { 648 ctxt.Pc = p.Pc 649 ctxt.Curp = p 650 o = oplook(ctxt, p) 651 if int(o.size) > 4*len(out) { 652 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 653 } 654 asmout(ctxt, p, o, out[:]) 655 for i = 0; i < int32(o.size/4); i++ { 656 ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 657 bp = bp[4:] 658 } 659 } 660 } 661 662 func isint32(v int64) bool { 663 return int64(int32(v)) == v 664 } 665 666 func isuint32(v uint64) bool { 667 return uint64(uint32(v)) == v 668 } 669 670 func aclass(ctxt *obj.Link, a *obj.Addr) int { 671 switch a.Type { 672 case obj.TYPE_NONE: 673 return C_NONE 674 675 case obj.TYPE_REG: 676 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 677 return C_REG 678 } 679 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 680 return C_FREG 681 } 682 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 683 return C_VREG 684 } 685 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 686 return C_VSREG 687 } 688 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 689 return C_CREG 690 } 691 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 692 switch a.Reg { 693 case REG_LR: 694 return C_LR 695 696 case REG_XER: 697 return C_XER 698 699 case REG_CTR: 700 return C_CTR 701 } 702 703 return C_SPR 704 } 705 706 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 707 return C_SPR 708 } 709 if a.Reg == REG_FPSCR { 710 return C_FPSCR 711 } 712 if a.Reg == REG_MSR { 713 return C_MSR 714 } 715 return C_GOK 716 717 case obj.TYPE_MEM: 718 switch a.Name { 719 case obj.NAME_EXTERN, 720 obj.NAME_STATIC: 721 if a.Sym == nil { 722 break 723 } 724 ctxt.Instoffset = a.Offset 725 if a.Sym != nil { // use relocation 726 if a.Sym.Type == obj.STLSBSS { 727 if ctxt.Flag_shared { 728 return C_TLS_IE 729 } else { 730 return C_TLS_LE 731 } 732 } 733 return C_ADDR 734 } 735 return C_LEXT 736 737 case obj.NAME_GOTREF: 738 return C_GOTADDR 739 740 case obj.NAME_AUTO: 741 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 742 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 743 return C_SAUTO 744 } 745 return C_LAUTO 746 747 case obj.NAME_PARAM: 748 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 749 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 750 return C_SAUTO 751 } 752 return C_LAUTO 753 754 case obj.NAME_NONE: 755 ctxt.Instoffset = a.Offset 756 if ctxt.Instoffset == 0 { 757 return C_ZOREG 758 } 759 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 760 return C_SOREG 761 } 762 return C_LOREG 763 } 764 765 return C_GOK 766 767 case obj.TYPE_TEXTSIZE: 768 return C_TEXTSIZE 769 770 case obj.TYPE_CONST, 771 obj.TYPE_ADDR: 772 switch a.Name { 773 case obj.NAME_NONE: 774 ctxt.Instoffset = a.Offset 775 if a.Reg != 0 { 776 if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG { 777 return C_SACON 778 } 779 if isint32(ctxt.Instoffset) { 780 return C_LACON 781 } 782 return C_DACON 783 } 784 785 goto consize 786 787 case obj.NAME_EXTERN, 788 obj.NAME_STATIC: 789 s := a.Sym 790 if s == nil { 791 break 792 } 793 if s.Type == obj.SCONST { 794 ctxt.Instoffset = a.Offset 795 goto consize 796 } 797 798 ctxt.Instoffset = a.Offset 799 800 /* not sure why this barfs */ 801 return C_LCON 802 803 case obj.NAME_AUTO: 804 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 805 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 806 return C_SACON 807 } 808 return C_LACON 809 810 case obj.NAME_PARAM: 811 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 812 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 813 return C_SACON 814 } 815 return C_LACON 816 } 817 818 return C_GOK 819 820 consize: 821 if ctxt.Instoffset >= 0 { 822 if ctxt.Instoffset == 0 { 823 return C_ZCON 824 } 825 if ctxt.Instoffset <= 0x7fff { 826 return C_SCON 827 } 828 if ctxt.Instoffset <= 0xffff { 829 return C_ANDCON 830 } 831 if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 832 return C_UCON 833 } 834 if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) { 835 return C_LCON 836 } 837 return C_DCON 838 } 839 840 if ctxt.Instoffset >= -0x8000 { 841 return C_ADDCON 842 } 843 if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) { 844 return C_UCON 845 } 846 if isint32(ctxt.Instoffset) { 847 return C_LCON 848 } 849 return C_DCON 850 851 case obj.TYPE_BRANCH: 852 if a.Sym != nil && ctxt.Flag_dynlink { 853 return C_LBRAPIC 854 } 855 return C_SBRA 856 } 857 858 return C_GOK 859 } 860 861 func prasm(p *obj.Prog) { 862 fmt.Printf("%v\n", p) 863 } 864 865 func oplook(ctxt *obj.Link, p *obj.Prog) *Optab { 866 a1 := int(p.Optab) 867 if a1 != 0 { 868 return &optab[a1-1] 869 } 870 a1 = int(p.From.Class) 871 if a1 == 0 { 872 a1 = aclass(ctxt, &p.From) + 1 873 p.From.Class = int8(a1) 874 } 875 876 a1-- 877 a3 := C_NONE + 1 878 if p.From3 != nil { 879 a3 = int(p.From3.Class) 880 if a3 == 0 { 881 a3 = aclass(ctxt, p.From3) + 1 882 p.From3.Class = int8(a3) 883 } 884 } 885 886 a3-- 887 a4 := int(p.To.Class) 888 if a4 == 0 { 889 a4 = aclass(ctxt, &p.To) + 1 890 p.To.Class = int8(a4) 891 } 892 893 a4-- 894 a2 := C_NONE 895 if p.Reg != 0 { 896 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 897 a2 = C_REG 898 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 899 a2 = C_VREG 900 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 901 a2 = C_VSREG 902 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 903 a2 = C_FREG 904 } 905 } 906 907 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 908 ops := oprange[p.As&obj.AMask] 909 c1 := &xcmp[a1] 910 c3 := &xcmp[a3] 911 c4 := &xcmp[a4] 912 for i := range ops { 913 op := &ops[i] 914 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 915 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 916 return op 917 } 918 } 919 920 ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 921 prasm(p) 922 if ops == nil { 923 ops = optab 924 } 925 return &ops[0] 926 } 927 928 func cmp(a int, b int) bool { 929 if a == b { 930 return true 931 } 932 switch a { 933 case C_LCON: 934 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 935 return true 936 } 937 938 case C_ADDCON: 939 if b == C_ZCON || b == C_SCON { 940 return true 941 } 942 943 case C_ANDCON: 944 if b == C_ZCON || b == C_SCON { 945 return true 946 } 947 948 case C_SPR: 949 if b == C_LR || b == C_XER || b == C_CTR { 950 return true 951 } 952 953 case C_UCON: 954 if b == C_ZCON { 955 return true 956 } 957 958 case C_SCON: 959 if b == C_ZCON { 960 return true 961 } 962 963 case C_LACON: 964 if b == C_SACON { 965 return true 966 } 967 968 case C_LBRA: 969 if b == C_SBRA { 970 return true 971 } 972 973 case C_LEXT: 974 if b == C_SEXT { 975 return true 976 } 977 978 case C_LAUTO: 979 if b == C_SAUTO { 980 return true 981 } 982 983 case C_REG: 984 if b == C_ZCON { 985 return r0iszero != 0 /*TypeKind(100016)*/ 986 } 987 988 case C_LOREG: 989 if b == C_ZOREG || b == C_SOREG { 990 return true 991 } 992 993 case C_SOREG: 994 if b == C_ZOREG { 995 return true 996 } 997 998 case C_ANY: 999 return true 1000 } 1001 1002 return false 1003 } 1004 1005 type ocmp []Optab 1006 1007 func (x ocmp) Len() int { 1008 return len(x) 1009 } 1010 1011 func (x ocmp) Swap(i, j int) { 1012 x[i], x[j] = x[j], x[i] 1013 } 1014 1015 func (x ocmp) Less(i, j int) bool { 1016 p1 := &x[i] 1017 p2 := &x[j] 1018 n := int(p1.as) - int(p2.as) 1019 if n != 0 { 1020 return n < 0 1021 } 1022 n = int(p1.a1) - int(p2.a1) 1023 if n != 0 { 1024 return n < 0 1025 } 1026 n = int(p1.a2) - int(p2.a2) 1027 if n != 0 { 1028 return n < 0 1029 } 1030 n = int(p1.a3) - int(p2.a3) 1031 if n != 0 { 1032 return n < 0 1033 } 1034 n = int(p1.a4) - int(p2.a4) 1035 if n != 0 { 1036 return n < 0 1037 } 1038 return false 1039 } 1040 func opset(a, b0 obj.As) { 1041 oprange[a&obj.AMask] = oprange[b0] 1042 } 1043 1044 func buildop(ctxt *obj.Link) { 1045 var n int 1046 1047 for i := 0; i < C_NCLASS; i++ { 1048 for n = 0; n < C_NCLASS; n++ { 1049 if cmp(n, i) { 1050 xcmp[i][n] = true 1051 } 1052 } 1053 } 1054 for n = 0; optab[n].as != obj.AXXX; n++ { 1055 } 1056 sort.Sort(ocmp(optab[:n])) 1057 for i := 0; i < n; i++ { 1058 r := optab[i].as 1059 r0 := r & obj.AMask 1060 start := i 1061 for optab[i].as == r { 1062 i++ 1063 } 1064 oprange[r0] = optab[start:i] 1065 i-- 1066 1067 switch r { 1068 default: 1069 ctxt.Diag("unknown op in build: %v", r) 1070 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1071 1072 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1073 opset(ADCBI, r0) 1074 1075 opset(ADCBST, r0) 1076 opset(ADCBT, r0) 1077 opset(ADCBTST, r0) 1078 opset(ADCBZ, r0) 1079 opset(AICBI, r0) 1080 1081 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1082 opset(ASTWCCC, r0) 1083 opset(ASTBCCC, r0) 1084 1085 opset(ASTDCCC, r0) 1086 1087 case AREM: /* macro */ 1088 opset(AREMCC, r0) 1089 1090 opset(AREMV, r0) 1091 opset(AREMVCC, r0) 1092 1093 case AREMU: 1094 opset(AREMU, r0) 1095 opset(AREMUCC, r0) 1096 opset(AREMUV, r0) 1097 opset(AREMUVCC, r0) 1098 1099 case AREMD: 1100 opset(AREMDCC, r0) 1101 opset(AREMDV, r0) 1102 opset(AREMDVCC, r0) 1103 1104 case AREMDU: 1105 opset(AREMDU, r0) 1106 opset(AREMDUCC, r0) 1107 opset(AREMDUV, r0) 1108 opset(AREMDUVCC, r0) 1109 1110 case ADIVW: /* op Rb[,Ra],Rd */ 1111 opset(AMULHW, r0) 1112 1113 opset(AMULHWCC, r0) 1114 opset(AMULHWU, r0) 1115 opset(AMULHWUCC, r0) 1116 opset(AMULLWCC, r0) 1117 opset(AMULLWVCC, r0) 1118 opset(AMULLWV, r0) 1119 opset(ADIVWCC, r0) 1120 opset(ADIVWV, r0) 1121 opset(ADIVWVCC, r0) 1122 opset(ADIVWU, r0) 1123 opset(ADIVWUCC, r0) 1124 opset(ADIVWUV, r0) 1125 opset(ADIVWUVCC, r0) 1126 opset(AADDCC, r0) 1127 opset(AADDCV, r0) 1128 opset(AADDCVCC, r0) 1129 opset(AADDV, r0) 1130 opset(AADDVCC, r0) 1131 opset(AADDE, r0) 1132 opset(AADDECC, r0) 1133 opset(AADDEV, r0) 1134 opset(AADDEVCC, r0) 1135 opset(ACRAND, r0) 1136 opset(ACRANDN, r0) 1137 opset(ACREQV, r0) 1138 opset(ACRNAND, r0) 1139 opset(ACRNOR, r0) 1140 opset(ACROR, r0) 1141 opset(ACRORN, r0) 1142 opset(ACRXOR, r0) 1143 opset(AMULHD, r0) 1144 opset(AMULHDCC, r0) 1145 opset(AMULHDU, r0) 1146 opset(AMULHDUCC, r0) 1147 opset(AMULLD, r0) 1148 opset(AMULLDCC, r0) 1149 opset(AMULLDVCC, r0) 1150 opset(AMULLDV, r0) 1151 opset(ADIVD, r0) 1152 opset(ADIVDCC, r0) 1153 opset(ADIVDE, r0) 1154 opset(ADIVDEU, r0) 1155 opset(ADIVDECC, r0) 1156 opset(ADIVDEUCC, r0) 1157 opset(ADIVDVCC, r0) 1158 opset(ADIVDV, r0) 1159 opset(ADIVDU, r0) 1160 opset(ADIVDUCC, r0) 1161 opset(ADIVDUVCC, r0) 1162 opset(ADIVDUCC, r0) 1163 1164 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1165 opset(AMOVH, r0) 1166 1167 opset(AMOVHZ, r0) 1168 1169 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1170 opset(AMOVHU, r0) 1171 1172 opset(AMOVHZU, r0) 1173 opset(AMOVWU, r0) 1174 opset(AMOVWZU, r0) 1175 opset(AMOVDU, r0) 1176 opset(AMOVMW, r0) 1177 1178 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1179 opset(ALVEBX, r0) 1180 opset(ALVEHX, r0) 1181 opset(ALVEWX, r0) 1182 opset(ALVX, r0) 1183 opset(ALVXL, r0) 1184 opset(ALVSL, r0) 1185 opset(ALVSR, r0) 1186 1187 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1188 opset(ASTVEBX, r0) 1189 opset(ASTVEHX, r0) 1190 opset(ASTVEWX, r0) 1191 opset(ASTVX, r0) 1192 opset(ASTVXL, r0) 1193 1194 case AVAND: /* vand, vandc, vnand */ 1195 opset(AVANDL, r0) 1196 opset(AVANDC, r0) 1197 opset(AVNAND, r0) 1198 1199 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1200 opset(AVORL, r0) 1201 opset(AVORC, r0) 1202 opset(AVXOR, r0) 1203 opset(AVNOR, r0) 1204 opset(AVEQV, r0) 1205 1206 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1207 opset(AVADDUBM, r0) 1208 opset(AVADDUHM, r0) 1209 opset(AVADDUWM, r0) 1210 opset(AVADDUDM, r0) 1211 opset(AVADDUQM, r0) 1212 1213 case AVADDCU: /* vaddcuq, vaddcuw */ 1214 opset(AVADDCUQ, r0) 1215 opset(AVADDCUW, r0) 1216 1217 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1218 opset(AVADDUBS, r0) 1219 opset(AVADDUHS, r0) 1220 opset(AVADDUWS, r0) 1221 1222 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1223 opset(AVADDSBS, r0) 1224 opset(AVADDSHS, r0) 1225 opset(AVADDSWS, r0) 1226 1227 case AVADDE: /* vaddeuqm, vaddecuq */ 1228 opset(AVADDEUQM, r0) 1229 opset(AVADDECUQ, r0) 1230 1231 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1232 opset(AVSUBUBM, r0) 1233 opset(AVSUBUHM, r0) 1234 opset(AVSUBUWM, r0) 1235 opset(AVSUBUDM, r0) 1236 opset(AVSUBUQM, r0) 1237 1238 case AVSUBCU: /* vsubcuq, vsubcuw */ 1239 opset(AVSUBCUQ, r0) 1240 opset(AVSUBCUW, r0) 1241 1242 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1243 opset(AVSUBUBS, r0) 1244 opset(AVSUBUHS, r0) 1245 opset(AVSUBUWS, r0) 1246 1247 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1248 opset(AVSUBSBS, r0) 1249 opset(AVSUBSHS, r0) 1250 opset(AVSUBSWS, r0) 1251 1252 case AVSUBE: /* vsubeuqm, vsubecuq */ 1253 opset(AVSUBEUQM, r0) 1254 opset(AVSUBECUQ, r0) 1255 1256 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1257 opset(AVRLB, r0) 1258 opset(AVRLH, r0) 1259 opset(AVRLW, r0) 1260 opset(AVRLD, r0) 1261 1262 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1263 opset(AVSLB, r0) 1264 opset(AVSLH, r0) 1265 opset(AVSLW, r0) 1266 opset(AVSL, r0) 1267 opset(AVSLO, r0) 1268 opset(AVSRB, r0) 1269 opset(AVSRH, r0) 1270 opset(AVSRW, r0) 1271 opset(AVSR, r0) 1272 opset(AVSRO, r0) 1273 opset(AVSLD, r0) 1274 opset(AVSRD, r0) 1275 1276 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1277 opset(AVSRAB, r0) 1278 opset(AVSRAH, r0) 1279 opset(AVSRAW, r0) 1280 opset(AVSRAD, r0) 1281 1282 case AVSOI: /* vsldoi */ 1283 opset(AVSLDOI, r0) 1284 1285 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1286 opset(AVCLZB, r0) 1287 opset(AVCLZH, r0) 1288 opset(AVCLZW, r0) 1289 opset(AVCLZD, r0) 1290 1291 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1292 opset(AVPOPCNTB, r0) 1293 opset(AVPOPCNTH, r0) 1294 opset(AVPOPCNTW, r0) 1295 opset(AVPOPCNTD, r0) 1296 1297 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1298 opset(AVCMPEQUB, r0) 1299 opset(AVCMPEQUBCC, r0) 1300 opset(AVCMPEQUH, r0) 1301 opset(AVCMPEQUHCC, r0) 1302 opset(AVCMPEQUW, r0) 1303 opset(AVCMPEQUWCC, r0) 1304 opset(AVCMPEQUD, r0) 1305 opset(AVCMPEQUDCC, r0) 1306 1307 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1308 opset(AVCMPGTUB, r0) 1309 opset(AVCMPGTUBCC, r0) 1310 opset(AVCMPGTUH, r0) 1311 opset(AVCMPGTUHCC, r0) 1312 opset(AVCMPGTUW, r0) 1313 opset(AVCMPGTUWCC, r0) 1314 opset(AVCMPGTUD, r0) 1315 opset(AVCMPGTUDCC, r0) 1316 opset(AVCMPGTSB, r0) 1317 opset(AVCMPGTSBCC, r0) 1318 opset(AVCMPGTSH, r0) 1319 opset(AVCMPGTSHCC, r0) 1320 opset(AVCMPGTSW, r0) 1321 opset(AVCMPGTSWCC, r0) 1322 opset(AVCMPGTSD, r0) 1323 opset(AVCMPGTSDCC, r0) 1324 1325 case AVPERM: /* vperm */ 1326 opset(AVPERM, r0) 1327 1328 case AVSEL: /* vsel */ 1329 opset(AVSEL, r0) 1330 1331 case AVSPLT: /* vspltb, vsplth, vspltw */ 1332 opset(AVSPLTB, r0) 1333 opset(AVSPLTH, r0) 1334 opset(AVSPLTW, r0) 1335 1336 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1337 opset(AVSPLTISB, r0) 1338 opset(AVSPLTISH, r0) 1339 opset(AVSPLTISW, r0) 1340 1341 case AVCIPH: /* vcipher, vcipherlast */ 1342 opset(AVCIPHER, r0) 1343 opset(AVCIPHERLAST, r0) 1344 1345 case AVNCIPH: /* vncipher, vncipherlast */ 1346 opset(AVNCIPHER, r0) 1347 opset(AVNCIPHERLAST, r0) 1348 1349 case AVSBOX: /* vsbox */ 1350 opset(AVSBOX, r0) 1351 1352 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1353 opset(AVSHASIGMAW, r0) 1354 opset(AVSHASIGMAD, r0) 1355 1356 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1357 opset(ALXVD2X, r0) 1358 opset(ALXVDSX, r0) 1359 opset(ALXVW4X, r0) 1360 1361 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1362 opset(ASTXVD2X, r0) 1363 opset(ASTXVW4X, r0) 1364 1365 case ALXS: /* lxsdx */ 1366 opset(ALXSDX, r0) 1367 1368 case ASTXS: /* stxsdx */ 1369 opset(ASTXSDX, r0) 1370 1371 case ALXSI: /* lxsiwax, lxsiwzx */ 1372 opset(ALXSIWAX, r0) 1373 opset(ALXSIWZX, r0) 1374 1375 case ASTXSI: /* stxsiwx */ 1376 opset(ASTXSIWX, r0) 1377 1378 case AMFVSR: /* mfvsrd, mfvsrwz */ 1379 opset(AMFVSRD, r0) 1380 opset(AMFVSRWZ, r0) 1381 1382 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz */ 1383 opset(AMTVSRD, r0) 1384 opset(AMTVSRWA, r0) 1385 opset(AMTVSRWZ, r0) 1386 1387 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1388 opset(AXXLANDQ, r0) 1389 opset(AXXLANDC, r0) 1390 opset(AXXLEQV, r0) 1391 opset(AXXLNAND, r0) 1392 1393 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1394 opset(AXXLORC, r0) 1395 opset(AXXLNOR, r0) 1396 opset(AXXLORQ, r0) 1397 opset(AXXLXOR, r0) 1398 1399 case AXXSEL: /* xxsel */ 1400 opset(AXXSEL, r0) 1401 1402 case AXXMRG: /* xxmrghw, xxmrglw */ 1403 opset(AXXMRGHW, r0) 1404 opset(AXXMRGLW, r0) 1405 1406 case AXXSPLT: /* xxspltw */ 1407 opset(AXXSPLTW, r0) 1408 1409 case AXXPERM: /* xxpermdi */ 1410 opset(AXXPERMDI, r0) 1411 1412 case AXXSI: /* xxsldwi */ 1413 opset(AXXSLDWI, r0) 1414 1415 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1416 opset(AXSCVDPSP, r0) 1417 opset(AXSCVSPDP, r0) 1418 opset(AXSCVDPSPN, r0) 1419 opset(AXSCVSPDPN, r0) 1420 1421 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1422 opset(AXVCVDPSP, r0) 1423 opset(AXVCVSPDP, r0) 1424 1425 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1426 opset(AXSCVDPSXDS, r0) 1427 opset(AXSCVDPSXWS, r0) 1428 opset(AXSCVDPUXDS, r0) 1429 opset(AXSCVDPUXWS, r0) 1430 1431 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1432 opset(AXSCVSXDDP, r0) 1433 opset(AXSCVUXDDP, r0) 1434 opset(AXSCVSXDSP, r0) 1435 opset(AXSCVUXDSP, r0) 1436 1437 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1438 opset(AXVCVDPSXDS, r0) 1439 opset(AXVCVDPSXWS, r0) 1440 opset(AXVCVDPUXDS, r0) 1441 opset(AXVCVDPUXWS, r0) 1442 opset(AXVCVSPSXDS, r0) 1443 opset(AXVCVSPSXWS, r0) 1444 opset(AXVCVSPUXDS, r0) 1445 opset(AXVCVSPUXWS, r0) 1446 1447 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1448 opset(AXVCVSXDDP, r0) 1449 opset(AXVCVSXWDP, r0) 1450 opset(AXVCVUXDDP, r0) 1451 opset(AXVCVUXWDP, r0) 1452 opset(AXVCVSXDSP, r0) 1453 opset(AXVCVSXWSP, r0) 1454 opset(AXVCVUXDSP, r0) 1455 opset(AXVCVUXWSP, r0) 1456 1457 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1458 opset(AANDN, r0) 1459 1460 opset(AANDNCC, r0) 1461 opset(AEQV, r0) 1462 opset(AEQVCC, r0) 1463 opset(ANAND, r0) 1464 opset(ANANDCC, r0) 1465 opset(ANOR, r0) 1466 opset(ANORCC, r0) 1467 opset(AORCC, r0) 1468 opset(AORN, r0) 1469 opset(AORNCC, r0) 1470 opset(AXORCC, r0) 1471 1472 case AADDME: /* op Ra, Rd */ 1473 opset(AADDMECC, r0) 1474 1475 opset(AADDMEV, r0) 1476 opset(AADDMEVCC, r0) 1477 opset(AADDZE, r0) 1478 opset(AADDZECC, r0) 1479 opset(AADDZEV, r0) 1480 opset(AADDZEVCC, r0) 1481 opset(ASUBME, r0) 1482 opset(ASUBMECC, r0) 1483 opset(ASUBMEV, r0) 1484 opset(ASUBMEVCC, r0) 1485 opset(ASUBZE, r0) 1486 opset(ASUBZECC, r0) 1487 opset(ASUBZEV, r0) 1488 opset(ASUBZEVCC, r0) 1489 1490 case AADDC: 1491 opset(AADDCCC, r0) 1492 1493 case ABEQ: 1494 opset(ABGE, r0) 1495 opset(ABGT, r0) 1496 opset(ABLE, r0) 1497 opset(ABLT, r0) 1498 opset(ABNE, r0) 1499 opset(ABVC, r0) 1500 opset(ABVS, r0) 1501 1502 case ABR: 1503 opset(ABL, r0) 1504 1505 case ABC: 1506 opset(ABCL, r0) 1507 1508 case AEXTSB: /* op Rs, Ra */ 1509 opset(AEXTSBCC, r0) 1510 1511 opset(AEXTSH, r0) 1512 opset(AEXTSHCC, r0) 1513 opset(ACNTLZW, r0) 1514 opset(ACNTLZWCC, r0) 1515 opset(ACNTLZD, r0) 1516 opset(AEXTSW, r0) 1517 opset(AEXTSWCC, r0) 1518 opset(ACNTLZDCC, r0) 1519 1520 case AFABS: /* fop [s,]d */ 1521 opset(AFABSCC, r0) 1522 1523 opset(AFNABS, r0) 1524 opset(AFNABSCC, r0) 1525 opset(AFNEG, r0) 1526 opset(AFNEGCC, r0) 1527 opset(AFRSP, r0) 1528 opset(AFRSPCC, r0) 1529 opset(AFCTIW, r0) 1530 opset(AFCTIWCC, r0) 1531 opset(AFCTIWZ, r0) 1532 opset(AFCTIWZCC, r0) 1533 opset(AFCTID, r0) 1534 opset(AFCTIDCC, r0) 1535 opset(AFCTIDZ, r0) 1536 opset(AFCTIDZCC, r0) 1537 opset(AFCFID, r0) 1538 opset(AFCFIDCC, r0) 1539 opset(AFCFIDU, r0) 1540 opset(AFCFIDUCC, r0) 1541 opset(AFRES, r0) 1542 opset(AFRESCC, r0) 1543 opset(AFRIM, r0) 1544 opset(AFRIMCC, r0) 1545 opset(AFRIP, r0) 1546 opset(AFRIPCC, r0) 1547 opset(AFRIZ, r0) 1548 opset(AFRIZCC, r0) 1549 opset(AFRSQRTE, r0) 1550 opset(AFRSQRTECC, r0) 1551 opset(AFSQRT, r0) 1552 opset(AFSQRTCC, r0) 1553 opset(AFSQRTS, r0) 1554 opset(AFSQRTSCC, r0) 1555 1556 case AFADD: 1557 opset(AFADDS, r0) 1558 opset(AFADDCC, r0) 1559 opset(AFADDSCC, r0) 1560 opset(AFDIV, r0) 1561 opset(AFDIVS, r0) 1562 opset(AFDIVCC, r0) 1563 opset(AFDIVSCC, r0) 1564 opset(AFSUB, r0) 1565 opset(AFSUBS, r0) 1566 opset(AFSUBCC, r0) 1567 opset(AFSUBSCC, r0) 1568 1569 case AFMADD: 1570 opset(AFMADDCC, r0) 1571 opset(AFMADDS, r0) 1572 opset(AFMADDSCC, r0) 1573 opset(AFMSUB, r0) 1574 opset(AFMSUBCC, r0) 1575 opset(AFMSUBS, r0) 1576 opset(AFMSUBSCC, r0) 1577 opset(AFNMADD, r0) 1578 opset(AFNMADDCC, r0) 1579 opset(AFNMADDS, r0) 1580 opset(AFNMADDSCC, r0) 1581 opset(AFNMSUB, r0) 1582 opset(AFNMSUBCC, r0) 1583 opset(AFNMSUBS, r0) 1584 opset(AFNMSUBSCC, r0) 1585 opset(AFSEL, r0) 1586 opset(AFSELCC, r0) 1587 1588 case AFMUL: 1589 opset(AFMULS, r0) 1590 opset(AFMULCC, r0) 1591 opset(AFMULSCC, r0) 1592 1593 case AFCMPO: 1594 opset(AFCMPU, r0) 1595 1596 case AISEL: 1597 opset(AISEL, r0) 1598 1599 case AMTFSB0: 1600 opset(AMTFSB0CC, r0) 1601 opset(AMTFSB1, r0) 1602 opset(AMTFSB1CC, r0) 1603 1604 case ANEG: /* op [Ra,] Rd */ 1605 opset(ANEGCC, r0) 1606 1607 opset(ANEGV, r0) 1608 opset(ANEGVCC, r0) 1609 1610 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1611 opset(AXOR, r0) 1612 1613 case ASLW: 1614 opset(ASLWCC, r0) 1615 opset(ASRW, r0) 1616 opset(ASRWCC, r0) 1617 1618 case ASLD: 1619 opset(ASLDCC, r0) 1620 opset(ASRD, r0) 1621 opset(ASRDCC, r0) 1622 1623 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1624 opset(ASRAWCC, r0) 1625 1626 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1627 opset(ASRADCC, r0) 1628 1629 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1630 opset(ASUB, r0) 1631 1632 opset(ASUBCC, r0) 1633 opset(ASUBV, r0) 1634 opset(ASUBVCC, r0) 1635 opset(ASUBCCC, r0) 1636 opset(ASUBCV, r0) 1637 opset(ASUBCVCC, r0) 1638 opset(ASUBE, r0) 1639 opset(ASUBECC, r0) 1640 opset(ASUBEV, r0) 1641 opset(ASUBEVCC, r0) 1642 1643 case ASYNC: 1644 opset(AISYNC, r0) 1645 opset(ALWSYNC, r0) 1646 opset(APTESYNC, r0) 1647 opset(ATLBSYNC, r0) 1648 1649 case ARLWMI: 1650 opset(ARLWMICC, r0) 1651 opset(ARLWNM, r0) 1652 opset(ARLWNMCC, r0) 1653 1654 case ARLDMI: 1655 opset(ARLDMICC, r0) 1656 opset(ARLDIMI, r0) 1657 opset(ARLDIMICC, r0) 1658 1659 case ARLDC: 1660 opset(ARLDCCC, r0) 1661 1662 case ARLDCL: 1663 opset(ARLDCR, r0) 1664 opset(ARLDCLCC, r0) 1665 opset(ARLDCRCC, r0) 1666 1667 case ARLDICL: 1668 opset(ARLDICLCC, r0) 1669 opset(ARLDICR, r0) 1670 opset(ARLDICRCC, r0) 1671 1672 case AFMOVD: 1673 opset(AFMOVDCC, r0) 1674 opset(AFMOVDU, r0) 1675 opset(AFMOVS, r0) 1676 opset(AFMOVSU, r0) 1677 1678 case AECIWX: 1679 opset(ALBAR, r0) 1680 opset(ALWAR, r0) 1681 opset(ALDAR, r0) 1682 1683 case ASYSCALL: /* just the op; flow of control */ 1684 opset(ARFI, r0) 1685 1686 opset(ARFCI, r0) 1687 opset(ARFID, r0) 1688 opset(AHRFID, r0) 1689 1690 case AMOVHBR: 1691 opset(AMOVWBR, r0) 1692 opset(AMOVDBR, r0) 1693 1694 case ASLBMFEE: 1695 opset(ASLBMFEV, r0) 1696 1697 case ATW: 1698 opset(ATD, r0) 1699 1700 case ATLBIE: 1701 opset(ASLBIE, r0) 1702 opset(ATLBIEL, r0) 1703 1704 case AEIEIO: 1705 opset(ASLBIA, r0) 1706 1707 case ACMP: 1708 opset(ACMPW, r0) 1709 1710 case ACMPU: 1711 opset(ACMPWU, r0) 1712 1713 case AADD, 1714 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1715 AFMOVSX, 1716 AFMOVSZ, 1717 ALSW, 1718 AMOVW, 1719 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1720 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1721 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1722 AMOVB, /* macro: move byte with sign extension */ 1723 AMOVBU, /* macro: move byte with sign extension & update */ 1724 AMOVFL, 1725 AMULLW, 1726 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1727 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1728 ASTSW, 1729 ASLBMTE, 1730 AWORD, 1731 ADWORD, 1732 obj.ANOP, 1733 obj.ATEXT, 1734 obj.AUNDEF, 1735 obj.AUSEFIELD, 1736 obj.AFUNCDATA, 1737 obj.APCDATA, 1738 obj.ADUFFZERO, 1739 obj.ADUFFCOPY: 1740 break 1741 } 1742 } 1743 } 1744 1745 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1746 return o<<26 | xo<<1 | oe<<11 1747 } 1748 1749 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1750 return o<<26 | xo<<2 | oe<<11 1751 } 1752 1753 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1754 return o<<26 | xo<<3 | oe<<11 1755 } 1756 1757 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1758 return o<<26 | xo<<4 | oe<<11 1759 } 1760 1761 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1762 return o<<26 | xo | oe<<11 | rc&1 1763 } 1764 1765 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1766 return o<<26 | xo | oe<<11 | (rc&1)<<10 1767 } 1768 1769 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1770 return o<<26 | xo<<1 | oe<<10 | rc&1 1771 } 1772 1773 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1774 return OPVCC(o, xo, 0, rc) 1775 } 1776 1777 func OP(o uint32, xo uint32) uint32 { 1778 return OPVCC(o, xo, 0, 0) 1779 } 1780 1781 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1782 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1783 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1784 } 1785 1786 /* VX-form 2-register operands, r/r/none */ 1787 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1788 return op | (d&31)<<21 | (a&31)<<11 1789 } 1790 1791 /* VA-form 4-register operands */ 1792 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1793 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1794 } 1795 1796 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1797 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1798 } 1799 1800 /* VX-form 2-register + UIM operands */ 1801 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1802 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1803 } 1804 1805 /* VX-form 2-register + ST + SIX operands */ 1806 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1807 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1808 } 1809 1810 /* VA-form 3-register + SHB operands */ 1811 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1812 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1813 } 1814 1815 /* VX-form 1-register + SIM operands */ 1816 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1817 return op | (d&31)<<21 | (simm&31)<<16 1818 } 1819 1820 /* XX1-form 3-register operands, 1 VSR operand */ 1821 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1822 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1823 /* between 0-63, so we can properly set the rightmost bits. */ 1824 r := d - REG_VS0 1825 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1826 } 1827 1828 /* XX2-form 3-register operands, 2 VSR operands */ 1829 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1830 xt := d - REG_VS0 1831 xb := b - REG_VS0 1832 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1833 } 1834 1835 /* XX3-form 3 VSR operands */ 1836 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1837 xt := d - REG_VS0 1838 xa := a - REG_VS0 1839 xb := b - REG_VS0 1840 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1841 } 1842 1843 /* XX3-form 3 VSR operands + immediate */ 1844 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1845 xt := d - REG_VS0 1846 xa := a - REG_VS0 1847 xb := b - REG_VS0 1848 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1849 } 1850 1851 /* XX4-form, 4 VSR operands */ 1852 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1853 xt := d - REG_VS0 1854 xa := a - REG_VS0 1855 xb := b - REG_VS0 1856 xc := c - REG_VS0 1857 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1858 } 1859 1860 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1861 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1862 } 1863 1864 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1865 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1866 } 1867 1868 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1869 return op | li&0x03FFFFFC | aa<<1 1870 } 1871 1872 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1873 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1874 } 1875 1876 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1877 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1878 } 1879 1880 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1881 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1882 } 1883 1884 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1885 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1886 } 1887 1888 const ( 1889 /* each rhs is OPVCC(_, _, _, _) */ 1890 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1891 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1892 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1893 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1894 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1895 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1896 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1897 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1898 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1899 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1900 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1901 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1902 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1903 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1904 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1905 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 1906 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 1907 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 1908 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 1909 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 1910 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 1911 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 1912 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 1913 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 1914 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 1915 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 1916 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 1917 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 1918 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 1919 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 1920 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 1921 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 1922 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 1923 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 1924 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 1925 ) 1926 1927 func oclass(a *obj.Addr) int { 1928 return int(a.Class) - 1 1929 } 1930 1931 const ( 1932 D_FORM = iota 1933 DS_FORM 1934 ) 1935 1936 // opform returns the form (D_FORM or DS_FORM) of an instruction. Used to decide on 1937 // which relocation to use with a load or store and only supports the needed 1938 // instructions. 1939 func opform(ctxt *obj.Link, insn uint32) int { 1940 switch insn { 1941 default: 1942 ctxt.Diag("bad insn in loadform: %x", insn) 1943 case OPVCC(58, 0, 0, 0), // ld 1944 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 1945 OPVCC(62, 0, 0, 0): // std 1946 return DS_FORM 1947 case OP_ADDI, // add 1948 OPVCC(32, 0, 0, 0), // lwz 1949 OPVCC(42, 0, 0, 0), // lha 1950 OPVCC(40, 0, 0, 0), // lhz 1951 OPVCC(34, 0, 0, 0), // lbz 1952 OPVCC(50, 0, 0, 0), // lfd 1953 OPVCC(48, 0, 0, 0), // lfs 1954 OPVCC(36, 0, 0, 0), // stw 1955 OPVCC(44, 0, 0, 0), // sth 1956 OPVCC(38, 0, 0, 0), // stb 1957 OPVCC(54, 0, 0, 0), // stfd 1958 OPVCC(52, 0, 0, 0): // stfs 1959 return D_FORM 1960 } 1961 return 0 1962 } 1963 1964 // Encode instructions and create relocation for accessing s+d according to the 1965 // instruction op with source or destination (as appropriate) register reg. 1966 func symbolAccess(ctxt *obj.Link, s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 1967 var base uint32 1968 form := opform(ctxt, op) 1969 if ctxt.Flag_shared { 1970 base = REG_R2 1971 } else { 1972 base = REG_R0 1973 } 1974 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 1975 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 1976 rel := obj.Addrel(ctxt.Cursym) 1977 rel.Off = int32(ctxt.Pc) 1978 rel.Siz = 8 1979 rel.Sym = s 1980 rel.Add = d 1981 if ctxt.Flag_shared { 1982 switch form { 1983 case D_FORM: 1984 rel.Type = obj.R_ADDRPOWER_TOCREL 1985 case DS_FORM: 1986 rel.Type = obj.R_ADDRPOWER_TOCREL_DS 1987 } 1988 1989 } else { 1990 switch form { 1991 case D_FORM: 1992 rel.Type = obj.R_ADDRPOWER 1993 case DS_FORM: 1994 rel.Type = obj.R_ADDRPOWER_DS 1995 } 1996 } 1997 return 1998 } 1999 2000 /* 2001 * 32-bit masks 2002 */ 2003 func getmask(m []byte, v uint32) bool { 2004 m[1] = 0 2005 m[0] = m[1] 2006 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2007 if getmask(m, ^v) { 2008 i := int(m[0]) 2009 m[0] = m[1] + 1 2010 m[1] = byte(i - 1) 2011 return true 2012 } 2013 2014 return false 2015 } 2016 2017 for i := 0; i < 32; i++ { 2018 if v&(1<<uint(31-i)) != 0 { 2019 m[0] = byte(i) 2020 for { 2021 m[1] = byte(i) 2022 i++ 2023 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2024 break 2025 } 2026 } 2027 2028 for ; i < 32; i++ { 2029 if v&(1<<uint(31-i)) != 0 { 2030 return false 2031 } 2032 } 2033 return true 2034 } 2035 } 2036 2037 return false 2038 } 2039 2040 func maskgen(ctxt *obj.Link, p *obj.Prog, m []byte, v uint32) { 2041 if !getmask(m, v) { 2042 ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2043 } 2044 } 2045 2046 /* 2047 * 64-bit masks (rldic etc) 2048 */ 2049 func getmask64(m []byte, v uint64) bool { 2050 m[1] = 0 2051 m[0] = m[1] 2052 for i := 0; i < 64; i++ { 2053 if v&(uint64(1)<<uint(63-i)) != 0 { 2054 m[0] = byte(i) 2055 for { 2056 m[1] = byte(i) 2057 i++ 2058 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2059 break 2060 } 2061 } 2062 2063 for ; i < 64; i++ { 2064 if v&(uint64(1)<<uint(63-i)) != 0 { 2065 return false 2066 } 2067 } 2068 return true 2069 } 2070 } 2071 2072 return false 2073 } 2074 2075 func maskgen64(ctxt *obj.Link, p *obj.Prog, m []byte, v uint64) { 2076 if !getmask64(m, v) { 2077 ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2078 } 2079 } 2080 2081 func loadu32(r int, d int64) uint32 { 2082 v := int32(d >> 16) 2083 if isuint32(uint64(d)) { 2084 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2085 } 2086 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2087 } 2088 2089 func high16adjusted(d int32) uint16 { 2090 if d&0x8000 != 0 { 2091 return uint16((d >> 16) + 1) 2092 } 2093 return uint16(d >> 16) 2094 } 2095 2096 func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) { 2097 o1 := uint32(0) 2098 o2 := uint32(0) 2099 o3 := uint32(0) 2100 o4 := uint32(0) 2101 o5 := uint32(0) 2102 2103 //print("%v => case %d\n", p, o->type); 2104 switch o.type_ { 2105 default: 2106 ctxt.Diag("unknown type %d", o.type_) 2107 prasm(p) 2108 2109 case 0: /* pseudo ops */ 2110 break 2111 2112 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2113 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2114 v := regoff(ctxt, &p.From) 2115 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2116 //nerrors--; 2117 ctxt.Diag("literal operation on R0\n%v", p) 2118 } 2119 2120 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2121 break 2122 } 2123 2124 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2125 2126 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2127 r := int(p.Reg) 2128 2129 if r == 0 { 2130 r = int(p.To.Reg) 2131 } 2132 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2133 2134 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2135 d := vregoff(ctxt, &p.From) 2136 2137 v := int32(d) 2138 r := int(p.From.Reg) 2139 if r == 0 { 2140 r = int(o.param) 2141 } 2142 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2143 ctxt.Diag("literal operation on R0\n%v", p) 2144 } 2145 a := OP_ADDI 2146 if o.a1 == C_UCON { 2147 if d&0xffff != 0 { 2148 log.Fatalf("invalid handling of %v", p) 2149 } 2150 v >>= 16 2151 if r == REGZERO && isuint32(uint64(d)) { 2152 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2153 break 2154 } 2155 2156 a = OP_ADDIS 2157 } else { 2158 if int64(int16(d)) != d { 2159 log.Fatalf("invalid handling of %v", p) 2160 } 2161 } 2162 2163 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2164 2165 case 4: /* add/mul $scon,[r1],r2 */ 2166 v := regoff(ctxt, &p.From) 2167 2168 r := int(p.Reg) 2169 if r == 0 { 2170 r = int(p.To.Reg) 2171 } 2172 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2173 ctxt.Diag("literal operation on R0\n%v", p) 2174 } 2175 if int32(int16(v)) != v { 2176 log.Fatalf("mishandled instruction %v", p) 2177 } 2178 o1 = AOP_IRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2179 2180 case 5: /* syscall */ 2181 o1 = oprrr(ctxt, p.As) 2182 2183 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2184 r := int(p.Reg) 2185 2186 if r == 0 { 2187 r = int(p.To.Reg) 2188 } 2189 o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2190 2191 case 7: /* mov r, soreg ==> stw o(r) */ 2192 r := int(p.To.Reg) 2193 2194 if r == 0 { 2195 r = int(o.param) 2196 } 2197 v := regoff(ctxt, &p.To) 2198 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2199 if v != 0 { 2200 ctxt.Diag("illegal indexed instruction\n%v", p) 2201 } 2202 if ctxt.Flag_shared && r == REG_R13 { 2203 rel := obj.Addrel(ctxt.Cursym) 2204 rel.Off = int32(ctxt.Pc) 2205 rel.Siz = 4 2206 // This (and the matching part in the load case 2207 // below) are the only places in the ppc64 toolchain 2208 // that knows the name of the tls variable. Possibly 2209 // we could add some assembly syntax so that the name 2210 // of the variable does not have to be assumed. 2211 rel.Sym = obj.Linklookup(ctxt, "runtime.tls_g", 0) 2212 rel.Type = obj.R_POWER_TLS 2213 } 2214 o1 = AOP_RRR(opstorex(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2215 } else { 2216 if int32(int16(v)) != v { 2217 log.Fatalf("mishandled instruction %v", p) 2218 } 2219 o1 = AOP_IRR(opstore(ctxt, p.As), uint32(p.From.Reg), uint32(r), uint32(v)) 2220 } 2221 2222 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2223 r := int(p.From.Reg) 2224 2225 if r == 0 { 2226 r = int(o.param) 2227 } 2228 v := regoff(ctxt, &p.From) 2229 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2230 if v != 0 { 2231 ctxt.Diag("illegal indexed instruction\n%v", p) 2232 } 2233 if ctxt.Flag_shared && r == REG_R13 { 2234 rel := obj.Addrel(ctxt.Cursym) 2235 rel.Off = int32(ctxt.Pc) 2236 rel.Siz = 4 2237 rel.Sym = obj.Linklookup(ctxt, "runtime.tls_g", 0) 2238 rel.Type = obj.R_POWER_TLS 2239 } 2240 o1 = AOP_RRR(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2241 } else { 2242 if int32(int16(v)) != v { 2243 log.Fatalf("mishandled instruction %v", p) 2244 } 2245 o1 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2246 } 2247 2248 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2249 r := int(p.From.Reg) 2250 2251 if r == 0 { 2252 r = int(o.param) 2253 } 2254 v := regoff(ctxt, &p.From) 2255 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2256 if v != 0 { 2257 ctxt.Diag("illegal indexed instruction\n%v", p) 2258 } 2259 o1 = AOP_RRR(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2260 } else { 2261 o1 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2262 } 2263 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2264 2265 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2266 r := int(p.Reg) 2267 2268 if r == 0 { 2269 r = int(p.To.Reg) 2270 } 2271 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2272 2273 case 11: /* br/bl lbra */ 2274 v := int32(0) 2275 2276 if p.Pcond != nil { 2277 v = int32(p.Pcond.Pc - p.Pc) 2278 if v&03 != 0 { 2279 ctxt.Diag("odd branch target address\n%v", p) 2280 v &^= 03 2281 } 2282 2283 if v < -(1<<25) || v >= 1<<24 { 2284 ctxt.Diag("branch too far\n%v", p) 2285 } 2286 } 2287 2288 o1 = OP_BR(opirr(ctxt, p.As), uint32(v), 0) 2289 if p.To.Sym != nil { 2290 rel := obj.Addrel(ctxt.Cursym) 2291 rel.Off = int32(ctxt.Pc) 2292 rel.Siz = 4 2293 rel.Sym = p.To.Sym 2294 v += int32(p.To.Offset) 2295 if v&03 != 0 { 2296 ctxt.Diag("odd branch target address\n%v", p) 2297 v &^= 03 2298 } 2299 2300 rel.Add = int64(v) 2301 rel.Type = obj.R_CALLPOWER 2302 } 2303 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2304 2305 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2306 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2307 v := regoff(ctxt, &p.From) 2308 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2309 ctxt.Diag("literal operation on R0\n%v", p) 2310 } 2311 2312 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2313 break 2314 } 2315 2316 if p.As == AMOVW { 2317 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2318 } else { 2319 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2320 } 2321 2322 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2323 if p.As == AMOVBZ { 2324 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2325 } else if p.As == AMOVH { 2326 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2327 } else if p.As == AMOVHZ { 2328 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2329 } else if p.As == AMOVWZ { 2330 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2331 } else { 2332 ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2333 } 2334 2335 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2336 r := int(p.Reg) 2337 2338 if r == 0 { 2339 r = int(p.To.Reg) 2340 } 2341 d := vregoff(ctxt, p.From3) 2342 var a int 2343 switch p.As { 2344 2345 // These opcodes expect a mask operand that has to be converted into the 2346 // appropriate operand. The way these were defined, not all valid masks are possible. 2347 // Left here for compatibility in case they were used or generated. 2348 case ARLDCL, ARLDCLCC: 2349 var mask [2]uint8 2350 maskgen64(ctxt, p, mask[:], uint64(d)) 2351 2352 a = int(mask[0]) /* MB */ 2353 if mask[1] != 63 { 2354 ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2355 } 2356 2357 case ARLDCR, ARLDCRCC: 2358 var mask [2]uint8 2359 maskgen64(ctxt, p, mask[:], uint64(d)) 2360 2361 a = int(mask[1]) /* ME */ 2362 if mask[0] != 0 { 2363 ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2364 } 2365 2366 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2367 case ARLDICR, ARLDICRCC, ARLDICL, ARLDICLCC: 2368 a = int(d) 2369 2370 default: 2371 ctxt.Diag("unexpected op in rldc case\n%v", p) 2372 a = 0 2373 } 2374 2375 o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2376 o1 |= (uint32(a) & 31) << 6 2377 if a&0x20 != 0 { 2378 o1 |= 1 << 5 /* mb[5] is top bit */ 2379 } 2380 2381 case 17, /* bc bo,bi,lbra (same for now) */ 2382 16: /* bc bo,bi,sbra */ 2383 a := 0 2384 2385 r := int(p.Reg) 2386 2387 if p.From.Type == obj.TYPE_CONST { 2388 a = int(regoff(ctxt, &p.From)) 2389 } else if p.From.Type == obj.TYPE_REG { 2390 if r != 0 { 2391 ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2392 } 2393 // BI values for the CR 2394 switch p.From.Reg { 2395 case REG_CR0: 2396 r = BI_CR0 2397 case REG_CR1: 2398 r = BI_CR1 2399 case REG_CR2: 2400 r = BI_CR2 2401 case REG_CR3: 2402 r = BI_CR3 2403 case REG_CR4: 2404 r = BI_CR4 2405 case REG_CR5: 2406 r = BI_CR5 2407 case REG_CR6: 2408 r = BI_CR6 2409 case REG_CR7: 2410 r = BI_CR7 2411 default: 2412 ctxt.Diag("unrecognized register: expecting CR\n") 2413 } 2414 } 2415 v := int32(0) 2416 if p.Pcond != nil { 2417 v = int32(p.Pcond.Pc - p.Pc) 2418 } 2419 if v&03 != 0 { 2420 ctxt.Diag("odd branch target address\n%v", p) 2421 v &^= 03 2422 } 2423 2424 if v < -(1<<16) || v >= 1<<15 { 2425 ctxt.Diag("branch too far\n%v", p) 2426 } 2427 o1 = OP_BC(opirr(ctxt, p.As), uint32(a), uint32(r), uint32(v), 0) 2428 2429 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2430 var v int32 2431 if p.As == ABC || p.As == ABCL { 2432 v = regoff(ctxt, &p.To) & 31 2433 } else { 2434 v = 20 /* unconditional */ 2435 } 2436 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2437 o2 = OPVCC(19, 16, 0, 0) 2438 if p.As == ABL || p.As == ABCL { 2439 o2 |= 1 2440 } 2441 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2442 2443 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2444 var v int32 2445 if p.As == ABC || p.As == ABCL { 2446 v = regoff(ctxt, &p.From) & 31 2447 } else { 2448 v = 20 /* unconditional */ 2449 } 2450 r := int(p.Reg) 2451 if r == 0 { 2452 r = 0 2453 } 2454 switch oclass(&p.To) { 2455 case C_CTR: 2456 o1 = OPVCC(19, 528, 0, 0) 2457 2458 case C_LR: 2459 o1 = OPVCC(19, 16, 0, 0) 2460 2461 default: 2462 ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2463 v = 0 2464 } 2465 2466 if p.As == ABL || p.As == ABCL { 2467 o1 |= 1 2468 } 2469 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2470 2471 case 19: /* mov $lcon,r ==> cau+or */ 2472 d := vregoff(ctxt, &p.From) 2473 2474 if p.From.Sym == nil { 2475 o1 = loadu32(int(p.To.Reg), d) 2476 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2477 } else { 2478 o1, o2 = symbolAccess(ctxt, p.From.Sym, d, p.To.Reg, OP_ADDI) 2479 } 2480 2481 //if(dlm) reloc(&p->from, p->pc, 0); 2482 2483 case 20: /* add $ucon,,r */ 2484 v := regoff(ctxt, &p.From) 2485 2486 r := int(p.Reg) 2487 if r == 0 { 2488 r = int(p.To.Reg) 2489 } 2490 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2491 ctxt.Diag("literal operation on R0\n%v", p) 2492 } 2493 o1 = AOP_IRR(opirr(ctxt, -p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2494 2495 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2496 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2497 ctxt.Diag("can't synthesize large constant\n%v", p) 2498 } 2499 d := vregoff(ctxt, &p.From) 2500 o1 = loadu32(REGTMP, d) 2501 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2502 r := int(p.Reg) 2503 if r == 0 { 2504 r = int(p.To.Reg) 2505 } 2506 o3 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2507 if p.From.Sym != nil { 2508 ctxt.Diag("%v is not supported", p) 2509 } 2510 2511 //if(dlm) reloc(&p->from, p->pc, 0); 2512 2513 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2514 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2515 ctxt.Diag("can't synthesize large constant\n%v", p) 2516 } 2517 d := vregoff(ctxt, &p.From) 2518 o1 = loadu32(REGTMP, d) 2519 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2520 r := int(p.Reg) 2521 if r == 0 { 2522 r = int(p.To.Reg) 2523 } 2524 o3 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2525 if p.From.Sym != nil { 2526 ctxt.Diag("%v is not supported", p) 2527 } 2528 2529 //if(dlm) reloc(&p->from, p->pc, 0); 2530 2531 /*24*/ 2532 case 25: 2533 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2534 v := regoff(ctxt, &p.From) 2535 2536 if v < 0 { 2537 v = 0 2538 } else if v > 63 { 2539 v = 63 2540 } 2541 r := int(p.Reg) 2542 if r == 0 { 2543 r = int(p.To.Reg) 2544 } 2545 var a int 2546 switch p.As { 2547 case ASLD, ASLDCC: 2548 a = int(63 - v) 2549 o1 = OP_RLDICR 2550 2551 case ASRD, ASRDCC: 2552 a = int(v) 2553 v = 64 - v 2554 o1 = OP_RLDICL 2555 2556 default: 2557 ctxt.Diag("unexpected op in sldi case\n%v", p) 2558 a = 0 2559 o1 = 0 2560 } 2561 2562 o1 = AOP_RRR(o1, uint32(r), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2563 o1 |= (uint32(a) & 31) << 6 2564 if v&0x20 != 0 { 2565 o1 |= 1 << 1 2566 } 2567 if a&0x20 != 0 { 2568 o1 |= 1 << 5 /* mb[5] is top bit */ 2569 } 2570 if p.As == ASLDCC || p.As == ASRDCC { 2571 o1 |= 1 /* Rc */ 2572 } 2573 2574 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2575 if p.To.Reg == REGTMP { 2576 ctxt.Diag("can't synthesize large constant\n%v", p) 2577 } 2578 v := regoff(ctxt, &p.From) 2579 r := int(p.From.Reg) 2580 if r == 0 { 2581 r = int(o.param) 2582 } 2583 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2584 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2585 2586 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2587 v := regoff(ctxt, p.From3) 2588 2589 r := int(p.From.Reg) 2590 o1 = AOP_IRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2591 2592 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2593 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2594 ctxt.Diag("can't synthesize large constant\n%v", p) 2595 } 2596 v := regoff(ctxt, p.From3) 2597 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2598 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2599 o3 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2600 if p.From.Sym != nil { 2601 ctxt.Diag("%v is not supported", p) 2602 } 2603 2604 //if(dlm) reloc(&p->from3, p->pc, 0); 2605 2606 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2607 v := regoff(ctxt, &p.From) 2608 2609 d := vregoff(ctxt, p.From3) 2610 var mask [2]uint8 2611 maskgen64(ctxt, p, mask[:], uint64(d)) 2612 var a int 2613 switch p.As { 2614 case ARLDC, ARLDCCC: 2615 a = int(mask[0]) /* MB */ 2616 if int32(mask[1]) != (63 - v) { 2617 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2618 } 2619 2620 case ARLDCL, ARLDCLCC: 2621 a = int(mask[0]) /* MB */ 2622 if mask[1] != 63 { 2623 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2624 } 2625 2626 case ARLDCR, ARLDCRCC: 2627 a = int(mask[1]) /* ME */ 2628 if mask[0] != 0 { 2629 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2630 } 2631 2632 default: 2633 ctxt.Diag("unexpected op in rldic case\n%v", p) 2634 a = 0 2635 } 2636 2637 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2638 o1 |= (uint32(a) & 31) << 6 2639 if v&0x20 != 0 { 2640 o1 |= 1 << 1 2641 } 2642 if a&0x20 != 0 { 2643 o1 |= 1 << 5 /* mb[5] is top bit */ 2644 } 2645 2646 case 30: /* rldimi $sh,s,$mask,a */ 2647 v := regoff(ctxt, &p.From) 2648 2649 d := vregoff(ctxt, p.From3) 2650 2651 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2652 // the ppc64 asm. 2653 switch p.As { 2654 case ARLDMI, ARLDMICC: 2655 var mask [2]uint8 2656 maskgen64(ctxt, p, mask[:], uint64(d)) 2657 if int32(mask[1]) != (63 - v) { 2658 ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2659 } 2660 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2661 o1 |= (uint32(mask[0]) & 31) << 6 2662 if v&0x20 != 0 { 2663 o1 |= 1 << 1 2664 } 2665 if mask[0]&0x20 != 0 { 2666 o1 |= 1 << 5 /* mb[5] is top bit */ 2667 } 2668 2669 // Opcodes with shift count operands. 2670 case ARLDIMI, ARLDIMICC: 2671 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2672 o1 |= (uint32(d) & 31) << 6 2673 if v&0x20 != 0 { 2674 o1 |= 1 << 1 2675 } 2676 } 2677 2678 case 31: /* dword */ 2679 d := vregoff(ctxt, &p.From) 2680 2681 if ctxt.Arch.ByteOrder == binary.BigEndian { 2682 o1 = uint32(d >> 32) 2683 o2 = uint32(d) 2684 } else { 2685 o1 = uint32(d) 2686 o2 = uint32(d >> 32) 2687 } 2688 2689 if p.From.Sym != nil { 2690 rel := obj.Addrel(ctxt.Cursym) 2691 rel.Off = int32(ctxt.Pc) 2692 rel.Siz = 8 2693 rel.Sym = p.From.Sym 2694 rel.Add = p.From.Offset 2695 rel.Type = obj.R_ADDR 2696 o2 = 0 2697 o1 = o2 2698 } 2699 2700 case 32: /* fmul frc,fra,frd */ 2701 r := int(p.Reg) 2702 2703 if r == 0 { 2704 r = int(p.To.Reg) 2705 } 2706 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2707 2708 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2709 r := int(p.From.Reg) 2710 2711 if oclass(&p.From) == C_NONE { 2712 r = int(p.To.Reg) 2713 } 2714 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), 0, uint32(r)) 2715 2716 case 34: /* FMADDx fra,frb,frc,frd (d=a*b+c); FSELx a<0? (d=b): (d=c) */ 2717 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.From3.Reg)&31)<<6 2718 2719 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2720 v := regoff(ctxt, &p.To) 2721 2722 r := int(p.To.Reg) 2723 if r == 0 { 2724 r = int(o.param) 2725 } 2726 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2727 o2 = AOP_IRR(opstore(ctxt, p.As), uint32(p.From.Reg), REGTMP, uint32(v)) 2728 2729 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2730 v := regoff(ctxt, &p.From) 2731 2732 r := int(p.From.Reg) 2733 if r == 0 { 2734 r = int(o.param) 2735 } 2736 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2737 o2 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2738 2739 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2740 v := regoff(ctxt, &p.From) 2741 2742 r := int(p.From.Reg) 2743 if r == 0 { 2744 r = int(o.param) 2745 } 2746 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2747 o2 = AOP_IRR(opload(ctxt, p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2748 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2749 2750 case 40: /* word */ 2751 o1 = uint32(regoff(ctxt, &p.From)) 2752 2753 case 41: /* stswi */ 2754 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(regoff(ctxt, p.From3))&0x7F)<<11 2755 2756 case 42: /* lswi */ 2757 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(regoff(ctxt, p.From3))&0x7F)<<11 2758 2759 case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */ 2760 o1 = AOP_RRR(oprrr(ctxt, p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2761 2762 case 44: /* indexed store */ 2763 o1 = AOP_RRR(opstorex(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2764 2765 case 45: /* indexed load */ 2766 o1 = AOP_RRR(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2767 2768 case 46: /* plain op */ 2769 o1 = oprrr(ctxt, p.As) 2770 2771 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2772 r := int(p.From.Reg) 2773 2774 if r == 0 { 2775 r = int(p.To.Reg) 2776 } 2777 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), 0) 2778 2779 case 48: /* op Rs, Ra */ 2780 r := int(p.From.Reg) 2781 2782 if r == 0 { 2783 r = int(p.To.Reg) 2784 } 2785 o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), 0) 2786 2787 case 49: /* op Rb; op $n, Rb */ 2788 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2789 v := regoff(ctxt, &p.From) & 1 2790 o1 = AOP_RRR(oprrr(ctxt, p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2791 } else { 2792 o1 = AOP_RRR(oprrr(ctxt, p.As), 0, 0, uint32(p.From.Reg)) 2793 } 2794 2795 case 50: /* rem[u] r1[,r2],r3 */ 2796 r := int(p.Reg) 2797 2798 if r == 0 { 2799 r = int(p.To.Reg) 2800 } 2801 v := oprrr(ctxt, p.As) 2802 t := v & (1<<10 | 1) /* OE|Rc */ 2803 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2804 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2805 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2806 if p.As == AREMU { 2807 o4 = o3 2808 2809 /* Clear top 32 bits */ 2810 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2811 } 2812 2813 case 51: /* remd[u] r1[,r2],r3 */ 2814 r := int(p.Reg) 2815 2816 if r == 0 { 2817 r = int(p.To.Reg) 2818 } 2819 v := oprrr(ctxt, p.As) 2820 t := v & (1<<10 | 1) /* OE|Rc */ 2821 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2822 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2823 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2824 2825 case 52: /* mtfsbNx cr(n) */ 2826 v := regoff(ctxt, &p.From) & 31 2827 2828 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(v), 0, 0) 2829 2830 case 53: /* mffsX ,fr1 */ 2831 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2832 2833 case 54: /* mov msr,r1; mov r1, msr*/ 2834 if oclass(&p.From) == C_REG { 2835 if p.As == AMOVD { 2836 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2837 } else { 2838 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 2839 } 2840 } else { 2841 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 2842 } 2843 2844 case 55: /* op Rb, Rd */ 2845 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 2846 2847 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 2848 v := regoff(ctxt, &p.From) 2849 2850 r := int(p.Reg) 2851 if r == 0 { 2852 r = int(p.To.Reg) 2853 } 2854 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 2855 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 2856 o1 |= 1 << 1 /* mb[5] */ 2857 } 2858 2859 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 2860 v := regoff(ctxt, &p.From) 2861 2862 r := int(p.Reg) 2863 if r == 0 { 2864 r = int(p.To.Reg) 2865 } 2866 2867 /* 2868 * Let user (gs) shoot himself in the foot. 2869 * qc has already complained. 2870 * 2871 if(v < 0 || v > 31) 2872 ctxt->diag("illegal shift %ld\n%v", v, p); 2873 */ 2874 if v < 0 { 2875 v = 0 2876 } else if v > 32 { 2877 v = 32 2878 } 2879 var mask [2]uint8 2880 if p.As == ASRW || p.As == ASRWCC { /* shift right */ 2881 mask[0] = uint8(v) 2882 mask[1] = 31 2883 v = 32 - v 2884 } else { 2885 mask[0] = 0 2886 mask[1] = uint8(31 - v) 2887 } 2888 2889 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 2890 if p.As == ASLWCC || p.As == ASRWCC { 2891 o1 |= 1 /* Rc */ 2892 } 2893 2894 case 58: /* logical $andcon,[s],a */ 2895 v := regoff(ctxt, &p.From) 2896 2897 r := int(p.Reg) 2898 if r == 0 { 2899 r = int(p.To.Reg) 2900 } 2901 o1 = LOP_IRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2902 2903 case 59: /* or/and $ucon,,r */ 2904 v := regoff(ctxt, &p.From) 2905 2906 r := int(p.Reg) 2907 if r == 0 { 2908 r = int(p.To.Reg) 2909 } 2910 o1 = LOP_IRR(opirr(ctxt, -p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 2911 2912 case 60: /* tw to,a,b */ 2913 r := int(regoff(ctxt, &p.From) & 31) 2914 2915 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 2916 2917 case 61: /* tw to,a,$simm */ 2918 r := int(regoff(ctxt, &p.From) & 31) 2919 2920 v := regoff(ctxt, &p.To) 2921 o1 = AOP_IRR(opirr(ctxt, p.As), uint32(r), uint32(p.Reg), uint32(v)) 2922 2923 case 62: /* rlwmi $sh,s,$mask,a */ 2924 v := regoff(ctxt, &p.From) 2925 2926 var mask [2]uint8 2927 maskgen(ctxt, p, mask[:], uint32(regoff(ctxt, p.From3))) 2928 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 2929 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 2930 2931 case 63: /* rlwmi b,s,$mask,a */ 2932 var mask [2]uint8 2933 maskgen(ctxt, p, mask[:], uint32(regoff(ctxt, p.From3))) 2934 2935 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 2936 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 2937 2938 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 2939 var v int32 2940 if p.From3Type() != obj.TYPE_NONE { 2941 v = regoff(ctxt, p.From3) & 255 2942 } else { 2943 v = 255 2944 } 2945 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 2946 2947 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 2948 if p.To.Reg == 0 { 2949 ctxt.Diag("must specify FPSCR(n)\n%v", p) 2950 } 2951 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(regoff(ctxt, &p.From))&31)<<12 2952 2953 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 2954 var r int 2955 var v int32 2956 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 2957 r = int(p.From.Reg) 2958 v = int32(p.To.Reg) 2959 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 2960 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 2961 } else { 2962 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 2963 } 2964 } else { 2965 r = int(p.To.Reg) 2966 v = int32(p.From.Reg) 2967 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 2968 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 2969 } else { 2970 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 2971 } 2972 } 2973 2974 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 2975 2976 case 67: /* mcrf crfD,crfS */ 2977 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 2978 ctxt.Diag("illegal CR field number\n%v", p) 2979 } 2980 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 2981 2982 case 68: /* mfcr rD; mfocrf CRM,rD */ 2983 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 2984 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 2985 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 2986 } else { 2987 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 2988 } 2989 2990 case 69: /* mtcrf CRM,rS */ 2991 var v int32 2992 if p.From3Type() != obj.TYPE_NONE { 2993 if p.To.Reg != 0 { 2994 ctxt.Diag("can't use both mask and CR(n)\n%v", p) 2995 } 2996 v = regoff(ctxt, p.From3) & 0xff 2997 } else { 2998 if p.To.Reg == 0 { 2999 v = 0xff /* CR */ 3000 } else { 3001 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3002 } 3003 } 3004 3005 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3006 3007 case 70: /* [f]cmp r,r,cr*/ 3008 var r int 3009 if p.Reg == 0 { 3010 r = 0 3011 } else { 3012 r = (int(p.Reg) & 7) << 2 3013 } 3014 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3015 3016 case 71: /* cmp[l] r,i,cr*/ 3017 var r int 3018 if p.Reg == 0 { 3019 r = 0 3020 } else { 3021 r = (int(p.Reg) & 7) << 2 3022 } 3023 o1 = AOP_RRR(opirr(ctxt, p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(regoff(ctxt, &p.To))&0xffff 3024 3025 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3026 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3027 3028 case 73: /* mcrfs crfD,crfS */ 3029 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3030 ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3031 } 3032 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3033 3034 case 77: /* syscall $scon, syscall Rx */ 3035 if p.From.Type == obj.TYPE_CONST { 3036 if p.From.Offset > BIG || p.From.Offset < -BIG { 3037 ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3038 } 3039 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3040 } else if p.From.Type == obj.TYPE_REG { 3041 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3042 } else { 3043 ctxt.Diag("illegal syscall: %v", p) 3044 o1 = 0x7fe00008 // trap always 3045 } 3046 3047 o2 = oprrr(ctxt, p.As) 3048 o3 = AOP_RRR(oprrr(ctxt, AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3049 3050 case 78: /* undef */ 3051 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3052 always to be an illegal instruction." */ 3053 3054 /* relocation operations */ 3055 case 74: 3056 v := vregoff(ctxt, &p.To) 3057 o1, o2 = symbolAccess(ctxt, p.To.Sym, v, p.From.Reg, opstore(ctxt, p.As)) 3058 3059 //if(dlm) reloc(&p->to, p->pc, 1); 3060 3061 case 75: 3062 v := vregoff(ctxt, &p.From) 3063 o1, o2 = symbolAccess(ctxt, p.From.Sym, v, p.To.Reg, opload(ctxt, p.As)) 3064 3065 //if(dlm) reloc(&p->from, p->pc, 1); 3066 3067 case 76: 3068 v := vregoff(ctxt, &p.From) 3069 o1, o2 = symbolAccess(ctxt, p.From.Sym, v, p.To.Reg, opload(ctxt, p.As)) 3070 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3071 3072 //if(dlm) reloc(&p->from, p->pc, 1); 3073 3074 case 79: 3075 if p.From.Offset != 0 { 3076 ctxt.Diag("invalid offset against tls var %v", p) 3077 } 3078 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3079 rel := obj.Addrel(ctxt.Cursym) 3080 rel.Off = int32(ctxt.Pc) 3081 rel.Siz = 4 3082 rel.Sym = p.From.Sym 3083 rel.Type = obj.R_POWER_TLS_LE 3084 3085 case 80: 3086 if p.From.Offset != 0 { 3087 ctxt.Diag("invalid offset against tls var %v", p) 3088 } 3089 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3090 o2 = AOP_IRR(opload(ctxt, AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3091 rel := obj.Addrel(ctxt.Cursym) 3092 rel.Off = int32(ctxt.Pc) 3093 rel.Siz = 8 3094 rel.Sym = p.From.Sym 3095 rel.Type = obj.R_POWER_TLS_IE 3096 3097 case 81: 3098 v := vregoff(ctxt, &p.To) 3099 if v != 0 { 3100 ctxt.Diag("invalid offset against GOT slot %v", p) 3101 } 3102 3103 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3104 o2 = AOP_IRR(opload(ctxt, AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3105 rel := obj.Addrel(ctxt.Cursym) 3106 rel.Off = int32(ctxt.Pc) 3107 rel.Siz = 8 3108 rel.Sym = p.From.Sym 3109 rel.Type = obj.R_ADDRPOWER_GOT 3110 case 82: /* vector instructions, VX-form and VC-form */ 3111 if p.From.Type == obj.TYPE_REG { 3112 /* reg reg none OR reg reg reg */ 3113 /* 3-register operand order: VRA, VRB, VRT */ 3114 /* 2-register operand order: VRA, VRT */ 3115 o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3116 } else if p.From3Type() == obj.TYPE_CONST { 3117 /* imm imm reg reg */ 3118 /* operand order: SIX, VRA, ST, VRT */ 3119 six := int(regoff(ctxt, &p.From)) 3120 st := int(regoff(ctxt, p.From3)) 3121 o1 = AOP_IIRR(opiirr(ctxt, p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3122 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3123 /* imm reg reg */ 3124 /* operand order: UIM, VRB, VRT */ 3125 uim := int(regoff(ctxt, &p.From)) 3126 o1 = AOP_VIRR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3127 } else { 3128 /* imm reg */ 3129 /* operand order: SIM, VRT */ 3130 sim := int(regoff(ctxt, &p.From)) 3131 o1 = AOP_IR(opirr(ctxt, p.As), uint32(p.To.Reg), uint32(sim)) 3132 } 3133 3134 case 83: /* vector instructions, VA-form */ 3135 if p.From.Type == obj.TYPE_REG { 3136 /* reg reg reg reg */ 3137 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3138 o1 = AOP_RRRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3139 } else if p.From.Type == obj.TYPE_CONST { 3140 /* imm reg reg reg */ 3141 /* operand order: SHB, VRA, VRB, VRT */ 3142 shb := int(regoff(ctxt, &p.From)) 3143 o1 = AOP_IRRR(opirrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(shb)) 3144 } 3145 3146 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3147 bc := vregoff(ctxt, &p.From) 3148 3149 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3150 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(bc)) 3151 3152 case 85: /* vector instructions, VX-form */ 3153 /* reg none reg */ 3154 /* 2-register operand order: VRB, VRT */ 3155 o1 = AOP_RR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3156 3157 case 86: /* VSX indexed store, XX1-form */ 3158 /* reg reg reg */ 3159 /* 3-register operand order: XT, (RB)(RA*1) */ 3160 o1 = AOP_XX1(opstorex(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3161 3162 case 87: /* VSX indexed load, XX1-form */ 3163 /* reg reg reg */ 3164 /* 3-register operand order: (RB)(RA*1), XT */ 3165 o1 = AOP_XX1(oploadx(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3166 3167 case 88: /* VSX instructions, XX1-form */ 3168 /* reg reg none OR reg reg reg */ 3169 /* 3-register operand order: RA, RB, XT */ 3170 /* 2-register operand order: XS, RA or RA, XT */ 3171 xt := int32(p.To.Reg) 3172 xs := int32(p.From.Reg) 3173 if REG_VS0 <= xt && xt <= REG_VS63 { 3174 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3175 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3176 o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3177 } 3178 3179 case 89: /* VSX instructions, XX2-form */ 3180 /* reg none reg OR reg imm reg */ 3181 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3182 uim := int(regoff(ctxt, p.From3)) 3183 o1 = AOP_XX2(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3184 3185 case 90: /* VSX instructions, XX3-form */ 3186 if p.From3Type() == obj.TYPE_NONE { 3187 /* reg reg reg */ 3188 /* 3-register operand order: XA, XB, XT */ 3189 o1 = AOP_XX3(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3190 } else if p.From3Type() == obj.TYPE_CONST { 3191 /* reg reg reg imm */ 3192 /* operand order: XA, XB, DM, XT */ 3193 dm := int(regoff(ctxt, p.From3)) 3194 o1 = AOP_XX3I(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3195 } 3196 3197 case 91: /* VSX instructions, XX4-form */ 3198 /* reg reg reg reg */ 3199 /* 3-register operand order: XA, XB, XC, XT */ 3200 o1 = AOP_XX4(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3201 3202 } 3203 3204 out[0] = o1 3205 out[1] = o2 3206 out[2] = o3 3207 out[3] = o4 3208 out[4] = o5 3209 return 3210 } 3211 3212 func vregoff(ctxt *obj.Link, a *obj.Addr) int64 { 3213 ctxt.Instoffset = 0 3214 if a != nil { 3215 aclass(ctxt, a) 3216 } 3217 return ctxt.Instoffset 3218 } 3219 3220 func regoff(ctxt *obj.Link, a *obj.Addr) int32 { 3221 return int32(vregoff(ctxt, a)) 3222 } 3223 3224 func oprrr(ctxt *obj.Link, a obj.As) uint32 { 3225 switch a { 3226 case AADD: 3227 return OPVCC(31, 266, 0, 0) 3228 case AADDCC: 3229 return OPVCC(31, 266, 0, 1) 3230 case AADDV: 3231 return OPVCC(31, 266, 1, 0) 3232 case AADDVCC: 3233 return OPVCC(31, 266, 1, 1) 3234 case AADDC: 3235 return OPVCC(31, 10, 0, 0) 3236 case AADDCCC: 3237 return OPVCC(31, 10, 0, 1) 3238 case AADDCV: 3239 return OPVCC(31, 10, 1, 0) 3240 case AADDCVCC: 3241 return OPVCC(31, 10, 1, 1) 3242 case AADDE: 3243 return OPVCC(31, 138, 0, 0) 3244 case AADDECC: 3245 return OPVCC(31, 138, 0, 1) 3246 case AADDEV: 3247 return OPVCC(31, 138, 1, 0) 3248 case AADDEVCC: 3249 return OPVCC(31, 138, 1, 1) 3250 case AADDME: 3251 return OPVCC(31, 234, 0, 0) 3252 case AADDMECC: 3253 return OPVCC(31, 234, 0, 1) 3254 case AADDMEV: 3255 return OPVCC(31, 234, 1, 0) 3256 case AADDMEVCC: 3257 return OPVCC(31, 234, 1, 1) 3258 case AADDZE: 3259 return OPVCC(31, 202, 0, 0) 3260 case AADDZECC: 3261 return OPVCC(31, 202, 0, 1) 3262 case AADDZEV: 3263 return OPVCC(31, 202, 1, 0) 3264 case AADDZEVCC: 3265 return OPVCC(31, 202, 1, 1) 3266 3267 case AAND: 3268 return OPVCC(31, 28, 0, 0) 3269 case AANDCC: 3270 return OPVCC(31, 28, 0, 1) 3271 case AANDN: 3272 return OPVCC(31, 60, 0, 0) 3273 case AANDNCC: 3274 return OPVCC(31, 60, 0, 1) 3275 3276 case ACMP: 3277 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3278 case ACMPU: 3279 return OPVCC(31, 32, 0, 0) | 1<<21 3280 case ACMPW: 3281 return OPVCC(31, 0, 0, 0) /* L=0 */ 3282 case ACMPWU: 3283 return OPVCC(31, 32, 0, 0) 3284 3285 case ACNTLZW: 3286 return OPVCC(31, 26, 0, 0) 3287 case ACNTLZWCC: 3288 return OPVCC(31, 26, 0, 1) 3289 case ACNTLZD: 3290 return OPVCC(31, 58, 0, 0) 3291 case ACNTLZDCC: 3292 return OPVCC(31, 58, 0, 1) 3293 3294 case ACRAND: 3295 return OPVCC(19, 257, 0, 0) 3296 case ACRANDN: 3297 return OPVCC(19, 129, 0, 0) 3298 case ACREQV: 3299 return OPVCC(19, 289, 0, 0) 3300 case ACRNAND: 3301 return OPVCC(19, 225, 0, 0) 3302 case ACRNOR: 3303 return OPVCC(19, 33, 0, 0) 3304 case ACROR: 3305 return OPVCC(19, 449, 0, 0) 3306 case ACRORN: 3307 return OPVCC(19, 417, 0, 0) 3308 case ACRXOR: 3309 return OPVCC(19, 193, 0, 0) 3310 3311 case ADCBF: 3312 return OPVCC(31, 86, 0, 0) 3313 case ADCBI: 3314 return OPVCC(31, 470, 0, 0) 3315 case ADCBST: 3316 return OPVCC(31, 54, 0, 0) 3317 case ADCBT: 3318 return OPVCC(31, 278, 0, 0) 3319 case ADCBTST: 3320 return OPVCC(31, 246, 0, 0) 3321 case ADCBZ: 3322 return OPVCC(31, 1014, 0, 0) 3323 3324 case AREM, ADIVW: 3325 return OPVCC(31, 491, 0, 0) 3326 3327 case AREMCC, ADIVWCC: 3328 return OPVCC(31, 491, 0, 1) 3329 3330 case AREMV, ADIVWV: 3331 return OPVCC(31, 491, 1, 0) 3332 3333 case AREMVCC, ADIVWVCC: 3334 return OPVCC(31, 491, 1, 1) 3335 3336 case AREMU, ADIVWU: 3337 return OPVCC(31, 459, 0, 0) 3338 3339 case AREMUCC, ADIVWUCC: 3340 return OPVCC(31, 459, 0, 1) 3341 3342 case AREMUV, ADIVWUV: 3343 return OPVCC(31, 459, 1, 0) 3344 3345 case AREMUVCC, ADIVWUVCC: 3346 return OPVCC(31, 459, 1, 1) 3347 3348 case AREMD, ADIVD: 3349 return OPVCC(31, 489, 0, 0) 3350 3351 case AREMDCC, ADIVDCC: 3352 return OPVCC(31, 489, 0, 1) 3353 3354 case ADIVDE: 3355 return OPVCC(31, 425, 0, 0) 3356 3357 case ADIVDECC: 3358 return OPVCC(31, 425, 0, 1) 3359 3360 case ADIVDEU: 3361 return OPVCC(31, 393, 0, 0) 3362 3363 case ADIVDEUCC: 3364 return OPVCC(31, 393, 0, 1) 3365 3366 case AREMDV, ADIVDV: 3367 return OPVCC(31, 489, 1, 0) 3368 3369 case AREMDVCC, ADIVDVCC: 3370 return OPVCC(31, 489, 1, 1) 3371 3372 case AREMDU, ADIVDU: 3373 return OPVCC(31, 457, 0, 0) 3374 3375 case AREMDUCC, ADIVDUCC: 3376 return OPVCC(31, 457, 0, 1) 3377 3378 case AREMDUV, ADIVDUV: 3379 return OPVCC(31, 457, 1, 0) 3380 3381 case AREMDUVCC, ADIVDUVCC: 3382 return OPVCC(31, 457, 1, 1) 3383 3384 case AEIEIO: 3385 return OPVCC(31, 854, 0, 0) 3386 3387 case AEQV: 3388 return OPVCC(31, 284, 0, 0) 3389 case AEQVCC: 3390 return OPVCC(31, 284, 0, 1) 3391 3392 case AEXTSB: 3393 return OPVCC(31, 954, 0, 0) 3394 case AEXTSBCC: 3395 return OPVCC(31, 954, 0, 1) 3396 case AEXTSH: 3397 return OPVCC(31, 922, 0, 0) 3398 case AEXTSHCC: 3399 return OPVCC(31, 922, 0, 1) 3400 case AEXTSW: 3401 return OPVCC(31, 986, 0, 0) 3402 case AEXTSWCC: 3403 return OPVCC(31, 986, 0, 1) 3404 3405 case AFABS: 3406 return OPVCC(63, 264, 0, 0) 3407 case AFABSCC: 3408 return OPVCC(63, 264, 0, 1) 3409 case AFADD: 3410 return OPVCC(63, 21, 0, 0) 3411 case AFADDCC: 3412 return OPVCC(63, 21, 0, 1) 3413 case AFADDS: 3414 return OPVCC(59, 21, 0, 0) 3415 case AFADDSCC: 3416 return OPVCC(59, 21, 0, 1) 3417 case AFCMPO: 3418 return OPVCC(63, 32, 0, 0) 3419 case AFCMPU: 3420 return OPVCC(63, 0, 0, 0) 3421 case AFCFID: 3422 return OPVCC(63, 846, 0, 0) 3423 case AFCFIDCC: 3424 return OPVCC(63, 846, 0, 1) 3425 case AFCFIDU: 3426 return OPVCC(63, 974, 0, 0) 3427 case AFCFIDUCC: 3428 return OPVCC(63, 974, 0, 1) 3429 case AFCTIW: 3430 return OPVCC(63, 14, 0, 0) 3431 case AFCTIWCC: 3432 return OPVCC(63, 14, 0, 1) 3433 case AFCTIWZ: 3434 return OPVCC(63, 15, 0, 0) 3435 case AFCTIWZCC: 3436 return OPVCC(63, 15, 0, 1) 3437 case AFCTID: 3438 return OPVCC(63, 814, 0, 0) 3439 case AFCTIDCC: 3440 return OPVCC(63, 814, 0, 1) 3441 case AFCTIDZ: 3442 return OPVCC(63, 815, 0, 0) 3443 case AFCTIDZCC: 3444 return OPVCC(63, 815, 0, 1) 3445 case AFDIV: 3446 return OPVCC(63, 18, 0, 0) 3447 case AFDIVCC: 3448 return OPVCC(63, 18, 0, 1) 3449 case AFDIVS: 3450 return OPVCC(59, 18, 0, 0) 3451 case AFDIVSCC: 3452 return OPVCC(59, 18, 0, 1) 3453 case AFMADD: 3454 return OPVCC(63, 29, 0, 0) 3455 case AFMADDCC: 3456 return OPVCC(63, 29, 0, 1) 3457 case AFMADDS: 3458 return OPVCC(59, 29, 0, 0) 3459 case AFMADDSCC: 3460 return OPVCC(59, 29, 0, 1) 3461 3462 case AFMOVS, AFMOVD: 3463 return OPVCC(63, 72, 0, 0) /* load */ 3464 case AFMOVDCC: 3465 return OPVCC(63, 72, 0, 1) 3466 case AFMSUB: 3467 return OPVCC(63, 28, 0, 0) 3468 case AFMSUBCC: 3469 return OPVCC(63, 28, 0, 1) 3470 case AFMSUBS: 3471 return OPVCC(59, 28, 0, 0) 3472 case AFMSUBSCC: 3473 return OPVCC(59, 28, 0, 1) 3474 case AFMUL: 3475 return OPVCC(63, 25, 0, 0) 3476 case AFMULCC: 3477 return OPVCC(63, 25, 0, 1) 3478 case AFMULS: 3479 return OPVCC(59, 25, 0, 0) 3480 case AFMULSCC: 3481 return OPVCC(59, 25, 0, 1) 3482 case AFNABS: 3483 return OPVCC(63, 136, 0, 0) 3484 case AFNABSCC: 3485 return OPVCC(63, 136, 0, 1) 3486 case AFNEG: 3487 return OPVCC(63, 40, 0, 0) 3488 case AFNEGCC: 3489 return OPVCC(63, 40, 0, 1) 3490 case AFNMADD: 3491 return OPVCC(63, 31, 0, 0) 3492 case AFNMADDCC: 3493 return OPVCC(63, 31, 0, 1) 3494 case AFNMADDS: 3495 return OPVCC(59, 31, 0, 0) 3496 case AFNMADDSCC: 3497 return OPVCC(59, 31, 0, 1) 3498 case AFNMSUB: 3499 return OPVCC(63, 30, 0, 0) 3500 case AFNMSUBCC: 3501 return OPVCC(63, 30, 0, 1) 3502 case AFNMSUBS: 3503 return OPVCC(59, 30, 0, 0) 3504 case AFNMSUBSCC: 3505 return OPVCC(59, 30, 0, 1) 3506 case AFRES: 3507 return OPVCC(59, 24, 0, 0) 3508 case AFRESCC: 3509 return OPVCC(59, 24, 0, 1) 3510 case AFRIM: 3511 return OPVCC(63, 488, 0, 0) 3512 case AFRIMCC: 3513 return OPVCC(63, 488, 0, 1) 3514 case AFRIP: 3515 return OPVCC(63, 456, 0, 0) 3516 case AFRIPCC: 3517 return OPVCC(63, 456, 0, 1) 3518 case AFRIZ: 3519 return OPVCC(63, 424, 0, 0) 3520 case AFRIZCC: 3521 return OPVCC(63, 424, 0, 1) 3522 case AFRSP: 3523 return OPVCC(63, 12, 0, 0) 3524 case AFRSPCC: 3525 return OPVCC(63, 12, 0, 1) 3526 case AFRSQRTE: 3527 return OPVCC(63, 26, 0, 0) 3528 case AFRSQRTECC: 3529 return OPVCC(63, 26, 0, 1) 3530 case AFSEL: 3531 return OPVCC(63, 23, 0, 0) 3532 case AFSELCC: 3533 return OPVCC(63, 23, 0, 1) 3534 case AFSQRT: 3535 return OPVCC(63, 22, 0, 0) 3536 case AFSQRTCC: 3537 return OPVCC(63, 22, 0, 1) 3538 case AFSQRTS: 3539 return OPVCC(59, 22, 0, 0) 3540 case AFSQRTSCC: 3541 return OPVCC(59, 22, 0, 1) 3542 case AFSUB: 3543 return OPVCC(63, 20, 0, 0) 3544 case AFSUBCC: 3545 return OPVCC(63, 20, 0, 1) 3546 case AFSUBS: 3547 return OPVCC(59, 20, 0, 0) 3548 case AFSUBSCC: 3549 return OPVCC(59, 20, 0, 1) 3550 3551 case AICBI: 3552 return OPVCC(31, 982, 0, 0) 3553 case AISYNC: 3554 return OPVCC(19, 150, 0, 0) 3555 3556 case AMTFSB0: 3557 return OPVCC(63, 70, 0, 0) 3558 case AMTFSB0CC: 3559 return OPVCC(63, 70, 0, 1) 3560 case AMTFSB1: 3561 return OPVCC(63, 38, 0, 0) 3562 case AMTFSB1CC: 3563 return OPVCC(63, 38, 0, 1) 3564 3565 case AMULHW: 3566 return OPVCC(31, 75, 0, 0) 3567 case AMULHWCC: 3568 return OPVCC(31, 75, 0, 1) 3569 case AMULHWU: 3570 return OPVCC(31, 11, 0, 0) 3571 case AMULHWUCC: 3572 return OPVCC(31, 11, 0, 1) 3573 case AMULLW: 3574 return OPVCC(31, 235, 0, 0) 3575 case AMULLWCC: 3576 return OPVCC(31, 235, 0, 1) 3577 case AMULLWV: 3578 return OPVCC(31, 235, 1, 0) 3579 case AMULLWVCC: 3580 return OPVCC(31, 235, 1, 1) 3581 3582 case AMULHD: 3583 return OPVCC(31, 73, 0, 0) 3584 case AMULHDCC: 3585 return OPVCC(31, 73, 0, 1) 3586 case AMULHDU: 3587 return OPVCC(31, 9, 0, 0) 3588 case AMULHDUCC: 3589 return OPVCC(31, 9, 0, 1) 3590 case AMULLD: 3591 return OPVCC(31, 233, 0, 0) 3592 case AMULLDCC: 3593 return OPVCC(31, 233, 0, 1) 3594 case AMULLDV: 3595 return OPVCC(31, 233, 1, 0) 3596 case AMULLDVCC: 3597 return OPVCC(31, 233, 1, 1) 3598 3599 case ANAND: 3600 return OPVCC(31, 476, 0, 0) 3601 case ANANDCC: 3602 return OPVCC(31, 476, 0, 1) 3603 case ANEG: 3604 return OPVCC(31, 104, 0, 0) 3605 case ANEGCC: 3606 return OPVCC(31, 104, 0, 1) 3607 case ANEGV: 3608 return OPVCC(31, 104, 1, 0) 3609 case ANEGVCC: 3610 return OPVCC(31, 104, 1, 1) 3611 case ANOR: 3612 return OPVCC(31, 124, 0, 0) 3613 case ANORCC: 3614 return OPVCC(31, 124, 0, 1) 3615 case AOR: 3616 return OPVCC(31, 444, 0, 0) 3617 case AORCC: 3618 return OPVCC(31, 444, 0, 1) 3619 case AORN: 3620 return OPVCC(31, 412, 0, 0) 3621 case AORNCC: 3622 return OPVCC(31, 412, 0, 1) 3623 3624 case ARFI: 3625 return OPVCC(19, 50, 0, 0) 3626 case ARFCI: 3627 return OPVCC(19, 51, 0, 0) 3628 case ARFID: 3629 return OPVCC(19, 18, 0, 0) 3630 case AHRFID: 3631 return OPVCC(19, 274, 0, 0) 3632 3633 case ARLWMI: 3634 return OPVCC(20, 0, 0, 0) 3635 case ARLWMICC: 3636 return OPVCC(20, 0, 0, 1) 3637 case ARLWNM: 3638 return OPVCC(23, 0, 0, 0) 3639 case ARLWNMCC: 3640 return OPVCC(23, 0, 0, 1) 3641 3642 case ARLDCL: 3643 return OPVCC(30, 8, 0, 0) 3644 case ARLDCR: 3645 return OPVCC(30, 9, 0, 0) 3646 3647 case ARLDICL: 3648 return OPVCC(30, 0, 0, 0) 3649 case ARLDICLCC: 3650 return OPVCC(30, 0, 0, 1) 3651 case ARLDICR: 3652 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3653 case ARLDICRCC: 3654 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3655 3656 case ASYSCALL: 3657 return OPVCC(17, 1, 0, 0) 3658 3659 case ASLW: 3660 return OPVCC(31, 24, 0, 0) 3661 case ASLWCC: 3662 return OPVCC(31, 24, 0, 1) 3663 case ASLD: 3664 return OPVCC(31, 27, 0, 0) 3665 case ASLDCC: 3666 return OPVCC(31, 27, 0, 1) 3667 3668 case ASRAW: 3669 return OPVCC(31, 792, 0, 0) 3670 case ASRAWCC: 3671 return OPVCC(31, 792, 0, 1) 3672 case ASRAD: 3673 return OPVCC(31, 794, 0, 0) 3674 case ASRADCC: 3675 return OPVCC(31, 794, 0, 1) 3676 3677 case ASRW: 3678 return OPVCC(31, 536, 0, 0) 3679 case ASRWCC: 3680 return OPVCC(31, 536, 0, 1) 3681 case ASRD: 3682 return OPVCC(31, 539, 0, 0) 3683 case ASRDCC: 3684 return OPVCC(31, 539, 0, 1) 3685 3686 case ASUB: 3687 return OPVCC(31, 40, 0, 0) 3688 case ASUBCC: 3689 return OPVCC(31, 40, 0, 1) 3690 case ASUBV: 3691 return OPVCC(31, 40, 1, 0) 3692 case ASUBVCC: 3693 return OPVCC(31, 40, 1, 1) 3694 case ASUBC: 3695 return OPVCC(31, 8, 0, 0) 3696 case ASUBCCC: 3697 return OPVCC(31, 8, 0, 1) 3698 case ASUBCV: 3699 return OPVCC(31, 8, 1, 0) 3700 case ASUBCVCC: 3701 return OPVCC(31, 8, 1, 1) 3702 case ASUBE: 3703 return OPVCC(31, 136, 0, 0) 3704 case ASUBECC: 3705 return OPVCC(31, 136, 0, 1) 3706 case ASUBEV: 3707 return OPVCC(31, 136, 1, 0) 3708 case ASUBEVCC: 3709 return OPVCC(31, 136, 1, 1) 3710 case ASUBME: 3711 return OPVCC(31, 232, 0, 0) 3712 case ASUBMECC: 3713 return OPVCC(31, 232, 0, 1) 3714 case ASUBMEV: 3715 return OPVCC(31, 232, 1, 0) 3716 case ASUBMEVCC: 3717 return OPVCC(31, 232, 1, 1) 3718 case ASUBZE: 3719 return OPVCC(31, 200, 0, 0) 3720 case ASUBZECC: 3721 return OPVCC(31, 200, 0, 1) 3722 case ASUBZEV: 3723 return OPVCC(31, 200, 1, 0) 3724 case ASUBZEVCC: 3725 return OPVCC(31, 200, 1, 1) 3726 3727 case ASYNC: 3728 return OPVCC(31, 598, 0, 0) 3729 case ALWSYNC: 3730 return OPVCC(31, 598, 0, 0) | 1<<21 3731 3732 case APTESYNC: 3733 return OPVCC(31, 598, 0, 0) | 2<<21 3734 3735 case ATLBIE: 3736 return OPVCC(31, 306, 0, 0) 3737 case ATLBIEL: 3738 return OPVCC(31, 274, 0, 0) 3739 case ATLBSYNC: 3740 return OPVCC(31, 566, 0, 0) 3741 case ASLBIA: 3742 return OPVCC(31, 498, 0, 0) 3743 case ASLBIE: 3744 return OPVCC(31, 434, 0, 0) 3745 case ASLBMFEE: 3746 return OPVCC(31, 915, 0, 0) 3747 case ASLBMFEV: 3748 return OPVCC(31, 851, 0, 0) 3749 case ASLBMTE: 3750 return OPVCC(31, 402, 0, 0) 3751 3752 case ATW: 3753 return OPVCC(31, 4, 0, 0) 3754 case ATD: 3755 return OPVCC(31, 68, 0, 0) 3756 3757 /* Vector (VMX/Altivec) instructions */ 3758 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 3759 /* are enabled starting at POWER6 (ISA 2.05). */ 3760 case AVANDL: 3761 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 3762 case AVANDC: 3763 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 3764 case AVNAND: 3765 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 3766 3767 case AVORL: 3768 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 3769 case AVORC: 3770 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 3771 case AVNOR: 3772 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 3773 case AVXOR: 3774 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 3775 case AVEQV: 3776 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 3777 3778 case AVADDUBM: 3779 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 3780 case AVADDUHM: 3781 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 3782 case AVADDUWM: 3783 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 3784 case AVADDUDM: 3785 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 3786 case AVADDUQM: 3787 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 3788 3789 case AVADDCUQ: 3790 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 3791 case AVADDCUW: 3792 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 3793 3794 case AVADDUBS: 3795 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 3796 case AVADDUHS: 3797 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 3798 case AVADDUWS: 3799 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 3800 3801 case AVADDSBS: 3802 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 3803 case AVADDSHS: 3804 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 3805 case AVADDSWS: 3806 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 3807 3808 case AVADDEUQM: 3809 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 3810 case AVADDECUQ: 3811 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 3812 3813 case AVSUBUBM: 3814 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 3815 case AVSUBUHM: 3816 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 3817 case AVSUBUWM: 3818 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 3819 case AVSUBUDM: 3820 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 3821 case AVSUBUQM: 3822 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 3823 3824 case AVSUBCUQ: 3825 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 3826 case AVSUBCUW: 3827 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 3828 3829 case AVSUBUBS: 3830 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 3831 case AVSUBUHS: 3832 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 3833 case AVSUBUWS: 3834 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 3835 3836 case AVSUBSBS: 3837 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 3838 case AVSUBSHS: 3839 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 3840 case AVSUBSWS: 3841 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 3842 3843 case AVSUBEUQM: 3844 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 3845 case AVSUBECUQ: 3846 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 3847 3848 case AVRLB: 3849 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 3850 case AVRLH: 3851 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 3852 case AVRLW: 3853 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 3854 case AVRLD: 3855 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 3856 3857 case AVSLB: 3858 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 3859 case AVSLH: 3860 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 3861 case AVSLW: 3862 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 3863 case AVSL: 3864 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 3865 case AVSLO: 3866 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 3867 case AVSRB: 3868 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 3869 case AVSRH: 3870 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 3871 case AVSRW: 3872 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 3873 case AVSR: 3874 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 3875 case AVSRO: 3876 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 3877 case AVSLD: 3878 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 3879 case AVSRD: 3880 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 3881 3882 case AVSRAB: 3883 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 3884 case AVSRAH: 3885 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 3886 case AVSRAW: 3887 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 3888 case AVSRAD: 3889 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 3890 3891 case AVCLZB: 3892 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 3893 case AVCLZH: 3894 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 3895 case AVCLZW: 3896 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 3897 case AVCLZD: 3898 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 3899 3900 case AVPOPCNTB: 3901 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 3902 case AVPOPCNTH: 3903 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 3904 case AVPOPCNTW: 3905 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 3906 case AVPOPCNTD: 3907 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 3908 3909 case AVCMPEQUB: 3910 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 3911 case AVCMPEQUBCC: 3912 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 3913 case AVCMPEQUH: 3914 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 3915 case AVCMPEQUHCC: 3916 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 3917 case AVCMPEQUW: 3918 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 3919 case AVCMPEQUWCC: 3920 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 3921 case AVCMPEQUD: 3922 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 3923 case AVCMPEQUDCC: 3924 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 3925 3926 case AVCMPGTUB: 3927 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 3928 case AVCMPGTUBCC: 3929 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 3930 case AVCMPGTUH: 3931 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 3932 case AVCMPGTUHCC: 3933 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 3934 case AVCMPGTUW: 3935 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 3936 case AVCMPGTUWCC: 3937 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 3938 case AVCMPGTUD: 3939 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 3940 case AVCMPGTUDCC: 3941 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 3942 case AVCMPGTSB: 3943 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 3944 case AVCMPGTSBCC: 3945 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 3946 case AVCMPGTSH: 3947 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 3948 case AVCMPGTSHCC: 3949 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 3950 case AVCMPGTSW: 3951 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 3952 case AVCMPGTSWCC: 3953 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 3954 case AVCMPGTSD: 3955 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 3956 case AVCMPGTSDCC: 3957 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 3958 3959 case AVPERM: 3960 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 3961 3962 case AVSEL: 3963 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 3964 3965 case AVCIPHER: 3966 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 3967 case AVCIPHERLAST: 3968 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 3969 case AVNCIPHER: 3970 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 3971 case AVNCIPHERLAST: 3972 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 3973 case AVSBOX: 3974 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 3975 /* End of vector instructions */ 3976 3977 /* Vector scalar (VSX) instructions */ 3978 /* ISA 2.06 enables these for POWER7. */ 3979 case AMFVSRD: 3980 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 3981 case AMFVSRWZ: 3982 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 3983 3984 case AMTVSRD: 3985 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 3986 case AMTVSRWA: 3987 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 3988 case AMTVSRWZ: 3989 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 3990 3991 case AXXLANDQ: 3992 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 3993 case AXXLANDC: 3994 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 3995 case AXXLEQV: 3996 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 3997 case AXXLNAND: 3998 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 3999 4000 case AXXLORC: 4001 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4002 case AXXLNOR: 4003 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4004 case AXXLORQ: 4005 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4006 case AXXLXOR: 4007 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4008 4009 case AXXSEL: 4010 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4011 4012 case AXXMRGHW: 4013 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4014 case AXXMRGLW: 4015 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4016 4017 case AXXSPLTW: 4018 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4019 4020 case AXXPERMDI: 4021 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4022 4023 case AXXSLDWI: 4024 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4025 4026 case AXSCVDPSP: 4027 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4028 case AXSCVSPDP: 4029 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4030 case AXSCVDPSPN: 4031 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4032 case AXSCVSPDPN: 4033 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4034 4035 case AXVCVDPSP: 4036 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4037 case AXVCVSPDP: 4038 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4039 4040 case AXSCVDPSXDS: 4041 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4042 case AXSCVDPSXWS: 4043 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4044 case AXSCVDPUXDS: 4045 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4046 case AXSCVDPUXWS: 4047 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4048 4049 case AXSCVSXDDP: 4050 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4051 case AXSCVUXDDP: 4052 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4053 case AXSCVSXDSP: 4054 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4055 case AXSCVUXDSP: 4056 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4057 4058 case AXVCVDPSXDS: 4059 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4060 case AXVCVDPSXWS: 4061 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4062 case AXVCVDPUXDS: 4063 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4064 case AXVCVDPUXWS: 4065 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4066 case AXVCVSPSXDS: 4067 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4068 case AXVCVSPSXWS: 4069 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4070 case AXVCVSPUXDS: 4071 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4072 case AXVCVSPUXWS: 4073 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4074 4075 case AXVCVSXDDP: 4076 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4077 case AXVCVSXWDP: 4078 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4079 case AXVCVUXDDP: 4080 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4081 case AXVCVUXWDP: 4082 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4083 case AXVCVSXDSP: 4084 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4085 case AXVCVSXWSP: 4086 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4087 case AXVCVUXDSP: 4088 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4089 case AXVCVUXWSP: 4090 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4091 /* End of VSX instructions */ 4092 4093 case AXOR: 4094 return OPVCC(31, 316, 0, 0) 4095 case AXORCC: 4096 return OPVCC(31, 316, 0, 1) 4097 } 4098 4099 ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4100 return 0 4101 } 4102 4103 func opirrr(ctxt *obj.Link, a obj.As) uint32 { 4104 switch a { 4105 /* Vector (VMX/Altivec) instructions */ 4106 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4107 /* are enabled starting at POWER6 (ISA 2.05). */ 4108 case AVSLDOI: 4109 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4110 } 4111 4112 ctxt.Diag("bad i/r/r/r opcode %v", a) 4113 return 0 4114 } 4115 4116 func opiirr(ctxt *obj.Link, a obj.As) uint32 { 4117 switch a { 4118 /* Vector (VMX/Altivec) instructions */ 4119 /* ISA 2.07 enables these for POWER8 and beyond. */ 4120 case AVSHASIGMAW: 4121 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4122 case AVSHASIGMAD: 4123 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4124 } 4125 4126 ctxt.Diag("bad i/i/r/r opcode %v", a) 4127 return 0 4128 } 4129 4130 func opirr(ctxt *obj.Link, a obj.As) uint32 { 4131 switch a { 4132 case AADD: 4133 return OPVCC(14, 0, 0, 0) 4134 case AADDC: 4135 return OPVCC(12, 0, 0, 0) 4136 case AADDCCC: 4137 return OPVCC(13, 0, 0, 0) 4138 case -AADD: 4139 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4140 4141 case AANDCC: 4142 return OPVCC(28, 0, 0, 0) 4143 case -AANDCC: 4144 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4145 4146 case ABR: 4147 return OPVCC(18, 0, 0, 0) 4148 case ABL: 4149 return OPVCC(18, 0, 0, 0) | 1 4150 case obj.ADUFFZERO: 4151 return OPVCC(18, 0, 0, 0) | 1 4152 case obj.ADUFFCOPY: 4153 return OPVCC(18, 0, 0, 0) | 1 4154 case ABC: 4155 return OPVCC(16, 0, 0, 0) 4156 case ABCL: 4157 return OPVCC(16, 0, 0, 0) | 1 4158 4159 case ABEQ: 4160 return AOP_RRR(16<<26, 12, 2, 0) 4161 case ABGE: 4162 return AOP_RRR(16<<26, 4, 0, 0) 4163 case ABGT: 4164 return AOP_RRR(16<<26, 12, 1, 0) 4165 case ABLE: 4166 return AOP_RRR(16<<26, 4, 1, 0) 4167 case ABLT: 4168 return AOP_RRR(16<<26, 12, 0, 0) 4169 case ABNE: 4170 return AOP_RRR(16<<26, 4, 2, 0) 4171 case ABVC: 4172 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4173 case ABVS: 4174 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4175 4176 case ACMP: 4177 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4178 case ACMPU: 4179 return OPVCC(10, 0, 0, 0) | 1<<21 4180 case ACMPW: 4181 return OPVCC(11, 0, 0, 0) /* L=0 */ 4182 case ACMPWU: 4183 return OPVCC(10, 0, 0, 0) 4184 case ALSW: 4185 return OPVCC(31, 597, 0, 0) 4186 4187 case AMULLW: 4188 return OPVCC(7, 0, 0, 0) 4189 4190 case AOR: 4191 return OPVCC(24, 0, 0, 0) 4192 case -AOR: 4193 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4194 4195 case ARLWMI: 4196 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4197 case ARLWMICC: 4198 return OPVCC(20, 0, 0, 1) 4199 case ARLDMI: 4200 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4201 case ARLDMICC: 4202 return OPVCC(30, 0, 0, 1) | 3<<2 4203 case ARLDIMI: 4204 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4205 case ARLDIMICC: 4206 return OPVCC(30, 0, 0, 1) | 3<<2 4207 case ARLWNM: 4208 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4209 case ARLWNMCC: 4210 return OPVCC(21, 0, 0, 1) 4211 4212 case ARLDCL: 4213 return OPVCC(30, 0, 0, 0) /* rldicl */ 4214 case ARLDCLCC: 4215 return OPVCC(30, 0, 0, 1) 4216 case ARLDCR: 4217 return OPVCC(30, 1, 0, 0) /* rldicr */ 4218 case ARLDCRCC: 4219 return OPVCC(30, 1, 0, 1) 4220 case ARLDC: 4221 return OPVCC(30, 0, 0, 0) | 2<<2 4222 case ARLDCCC: 4223 return OPVCC(30, 0, 0, 1) | 2<<2 4224 4225 case ASRAW: 4226 return OPVCC(31, 824, 0, 0) 4227 case ASRAWCC: 4228 return OPVCC(31, 824, 0, 1) 4229 case ASRAD: 4230 return OPVCC(31, (413 << 1), 0, 0) 4231 case ASRADCC: 4232 return OPVCC(31, (413 << 1), 0, 1) 4233 4234 case ASTSW: 4235 return OPVCC(31, 725, 0, 0) 4236 4237 case ASUBC: 4238 return OPVCC(8, 0, 0, 0) 4239 4240 case ATW: 4241 return OPVCC(3, 0, 0, 0) 4242 case ATD: 4243 return OPVCC(2, 0, 0, 0) 4244 4245 /* Vector (VMX/Altivec) instructions */ 4246 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4247 /* are enabled starting at POWER6 (ISA 2.05). */ 4248 case AVSPLTB: 4249 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4250 case AVSPLTH: 4251 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4252 case AVSPLTW: 4253 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4254 4255 case AVSPLTISB: 4256 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4257 case AVSPLTISH: 4258 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4259 case AVSPLTISW: 4260 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4261 /* End of vector instructions */ 4262 4263 case AXOR: 4264 return OPVCC(26, 0, 0, 0) /* XORIL */ 4265 case -AXOR: 4266 return OPVCC(27, 0, 0, 0) /* XORIU */ 4267 } 4268 4269 ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4270 return 0 4271 } 4272 4273 /* 4274 * load o(a),d 4275 */ 4276 func opload(ctxt *obj.Link, a obj.As) uint32 { 4277 switch a { 4278 case AMOVD: 4279 return OPVCC(58, 0, 0, 0) /* ld */ 4280 case AMOVDU: 4281 return OPVCC(58, 0, 0, 1) /* ldu */ 4282 case AMOVWZ: 4283 return OPVCC(32, 0, 0, 0) /* lwz */ 4284 case AMOVWZU: 4285 return OPVCC(33, 0, 0, 0) /* lwzu */ 4286 case AMOVW: 4287 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4288 4289 /* no AMOVWU */ 4290 case AMOVB, AMOVBZ: 4291 return OPVCC(34, 0, 0, 0) 4292 /* load */ 4293 4294 case AMOVBU, AMOVBZU: 4295 return OPVCC(35, 0, 0, 0) 4296 case AFMOVD: 4297 return OPVCC(50, 0, 0, 0) 4298 case AFMOVDU: 4299 return OPVCC(51, 0, 0, 0) 4300 case AFMOVS: 4301 return OPVCC(48, 0, 0, 0) 4302 case AFMOVSU: 4303 return OPVCC(49, 0, 0, 0) 4304 case AMOVH: 4305 return OPVCC(42, 0, 0, 0) 4306 case AMOVHU: 4307 return OPVCC(43, 0, 0, 0) 4308 case AMOVHZ: 4309 return OPVCC(40, 0, 0, 0) 4310 case AMOVHZU: 4311 return OPVCC(41, 0, 0, 0) 4312 case AMOVMW: 4313 return OPVCC(46, 0, 0, 0) /* lmw */ 4314 } 4315 4316 ctxt.Diag("bad load opcode %v", a) 4317 return 0 4318 } 4319 4320 /* 4321 * indexed load a(b),d 4322 */ 4323 func oploadx(ctxt *obj.Link, a obj.As) uint32 { 4324 switch a { 4325 case AMOVWZ: 4326 return OPVCC(31, 23, 0, 0) /* lwzx */ 4327 case AMOVWZU: 4328 return OPVCC(31, 55, 0, 0) /* lwzux */ 4329 case AMOVW: 4330 return OPVCC(31, 341, 0, 0) /* lwax */ 4331 case AMOVWU: 4332 return OPVCC(31, 373, 0, 0) /* lwaux */ 4333 4334 case AMOVB, AMOVBZ: 4335 return OPVCC(31, 87, 0, 0) /* lbzx */ 4336 4337 case AMOVBU, AMOVBZU: 4338 return OPVCC(31, 119, 0, 0) /* lbzux */ 4339 case AFMOVD: 4340 return OPVCC(31, 599, 0, 0) /* lfdx */ 4341 case AFMOVDU: 4342 return OPVCC(31, 631, 0, 0) /* lfdux */ 4343 case AFMOVS: 4344 return OPVCC(31, 535, 0, 0) /* lfsx */ 4345 case AFMOVSU: 4346 return OPVCC(31, 567, 0, 0) /* lfsux */ 4347 case AFMOVSX: 4348 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4349 case AFMOVSZ: 4350 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4351 case AMOVH: 4352 return OPVCC(31, 343, 0, 0) /* lhax */ 4353 case AMOVHU: 4354 return OPVCC(31, 375, 0, 0) /* lhaux */ 4355 case AMOVHBR: 4356 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4357 case AMOVWBR: 4358 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4359 case AMOVDBR: 4360 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4361 case AMOVHZ: 4362 return OPVCC(31, 279, 0, 0) /* lhzx */ 4363 case AMOVHZU: 4364 return OPVCC(31, 311, 0, 0) /* lhzux */ 4365 case AECIWX: 4366 return OPVCC(31, 310, 0, 0) /* eciwx */ 4367 case ALBAR: 4368 return OPVCC(31, 52, 0, 0) /* lbarx */ 4369 case ALWAR: 4370 return OPVCC(31, 20, 0, 0) /* lwarx */ 4371 case ALDAR: 4372 return OPVCC(31, 84, 0, 0) 4373 case ALSW: 4374 return OPVCC(31, 533, 0, 0) /* lswx */ 4375 case AMOVD: 4376 return OPVCC(31, 21, 0, 0) /* ldx */ 4377 case AMOVDU: 4378 return OPVCC(31, 53, 0, 0) /* ldux */ 4379 4380 /* Vector (VMX/Altivec) instructions */ 4381 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4382 /* are enabled starting at POWER6 (ISA 2.05). */ 4383 case ALVEBX: 4384 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4385 case ALVEHX: 4386 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4387 case ALVEWX: 4388 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4389 case ALVX: 4390 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4391 case ALVXL: 4392 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4393 case ALVSL: 4394 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4395 case ALVSR: 4396 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4397 /* End of vector instructions */ 4398 4399 /* Vector scalar (VSX) instructions */ 4400 /* ISA 2.06 enables these for POWER7. */ 4401 case ALXVD2X: 4402 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4403 case ALXVDSX: 4404 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4405 case ALXVW4X: 4406 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4407 4408 case ALXSDX: 4409 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4410 4411 case ALXSIWAX: 4412 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4413 case ALXSIWZX: 4414 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4415 /* End of vector scalar instructions */ 4416 4417 } 4418 4419 ctxt.Diag("bad loadx opcode %v", a) 4420 return 0 4421 } 4422 4423 /* 4424 * store s,o(d) 4425 */ 4426 func opstore(ctxt *obj.Link, a obj.As) uint32 { 4427 switch a { 4428 case AMOVB, AMOVBZ: 4429 return OPVCC(38, 0, 0, 0) /* stb */ 4430 4431 case AMOVBU, AMOVBZU: 4432 return OPVCC(39, 0, 0, 0) /* stbu */ 4433 case AFMOVD: 4434 return OPVCC(54, 0, 0, 0) /* stfd */ 4435 case AFMOVDU: 4436 return OPVCC(55, 0, 0, 0) /* stfdu */ 4437 case AFMOVS: 4438 return OPVCC(52, 0, 0, 0) /* stfs */ 4439 case AFMOVSU: 4440 return OPVCC(53, 0, 0, 0) /* stfsu */ 4441 4442 case AMOVHZ, AMOVH: 4443 return OPVCC(44, 0, 0, 0) /* sth */ 4444 4445 case AMOVHZU, AMOVHU: 4446 return OPVCC(45, 0, 0, 0) /* sthu */ 4447 case AMOVMW: 4448 return OPVCC(47, 0, 0, 0) /* stmw */ 4449 case ASTSW: 4450 return OPVCC(31, 725, 0, 0) /* stswi */ 4451 4452 case AMOVWZ, AMOVW: 4453 return OPVCC(36, 0, 0, 0) /* stw */ 4454 4455 case AMOVWZU, AMOVWU: 4456 return OPVCC(37, 0, 0, 0) /* stwu */ 4457 case AMOVD: 4458 return OPVCC(62, 0, 0, 0) /* std */ 4459 case AMOVDU: 4460 return OPVCC(62, 0, 0, 1) /* stdu */ 4461 } 4462 4463 ctxt.Diag("unknown store opcode %v", a) 4464 return 0 4465 } 4466 4467 /* 4468 * indexed store s,a(b) 4469 */ 4470 func opstorex(ctxt *obj.Link, a obj.As) uint32 { 4471 switch a { 4472 case AMOVB, AMOVBZ: 4473 return OPVCC(31, 215, 0, 0) /* stbx */ 4474 4475 case AMOVBU, AMOVBZU: 4476 return OPVCC(31, 247, 0, 0) /* stbux */ 4477 case AFMOVD: 4478 return OPVCC(31, 727, 0, 0) /* stfdx */ 4479 case AFMOVDU: 4480 return OPVCC(31, 759, 0, 0) /* stfdux */ 4481 case AFMOVS: 4482 return OPVCC(31, 663, 0, 0) /* stfsx */ 4483 case AFMOVSU: 4484 return OPVCC(31, 695, 0, 0) /* stfsux */ 4485 case AFMOVSX: 4486 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4487 4488 case AMOVHZ, AMOVH: 4489 return OPVCC(31, 407, 0, 0) /* sthx */ 4490 case AMOVHBR: 4491 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4492 4493 case AMOVHZU, AMOVHU: 4494 return OPVCC(31, 439, 0, 0) /* sthux */ 4495 4496 case AMOVWZ, AMOVW: 4497 return OPVCC(31, 151, 0, 0) /* stwx */ 4498 4499 case AMOVWZU, AMOVWU: 4500 return OPVCC(31, 183, 0, 0) /* stwux */ 4501 case ASTSW: 4502 return OPVCC(31, 661, 0, 0) /* stswx */ 4503 case AMOVWBR: 4504 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4505 case ASTBCCC: 4506 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4507 case ASTWCCC: 4508 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4509 case ASTDCCC: 4510 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4511 case AECOWX: 4512 return OPVCC(31, 438, 0, 0) /* ecowx */ 4513 case AMOVD: 4514 return OPVCC(31, 149, 0, 0) /* stdx */ 4515 case AMOVDU: 4516 return OPVCC(31, 181, 0, 0) /* stdux */ 4517 4518 /* Vector (VMX/Altivec) instructions */ 4519 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4520 /* are enabled starting at POWER6 (ISA 2.05). */ 4521 case ASTVEBX: 4522 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4523 case ASTVEHX: 4524 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4525 case ASTVEWX: 4526 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4527 case ASTVX: 4528 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4529 case ASTVXL: 4530 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4531 /* End of vector instructions */ 4532 4533 /* Vector scalar (VSX) instructions */ 4534 /* ISA 2.06 enables these for POWER7. */ 4535 case ASTXVD2X: 4536 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4537 case ASTXVW4X: 4538 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4539 4540 case ASTXSDX: 4541 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4542 4543 case ASTXSIWX: 4544 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4545 /* End of vector scalar instructions */ 4546 4547 } 4548 4549 ctxt.Diag("unknown storex opcode %v", a) 4550 return 0 4551 } 4552
