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      1 /* tc-i960.c - All the i80960-specific stuff
      2    Copyright (C) 1989-2014 Free Software Foundation, Inc.
      3 
      4    This file is part of GAS.
      5 
      6    GAS is free software; you can redistribute it and/or modify
      7    it under the terms of the GNU General Public License as published by
      8    the Free Software Foundation; either version 3, or (at your option)
      9    any later version.
     10 
     11    GAS is distributed in the hope that it will be useful,
     12    but WITHOUT ANY WARRANTY; without even the implied warranty of
     13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14    GNU General Public License for more details.
     15 
     16    You should have received a copy of the GNU General Public License
     17    along with GAS; see the file COPYING.  If not, write to the Free
     18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
     19    02110-1301, USA.  */
     20 
     21 /* See comment on md_parse_option for 80960-specific invocation options.  */
     22 
     23 /* There are 4 different lengths of (potentially) symbol-based displacements
     24    in the 80960 instruction set, each of which could require address fix-ups
     25    and (in the case of external symbols) emission of relocation directives:
     26 
     27    32-bit (MEMB)
     28         This is a standard length for the base assembler and requires no
     29         special action.
     30 
     31    13-bit (COBR)
     32         This is a non-standard length, but the base assembler has a
     33         hook for bit field address fixups: the fixS structure can
     34         point to a descriptor of the field, in which case our
     35         md_number_to_field() routine gets called to process it.
     36 
     37         I made the hook a little cleaner by having fix_new() (in the base
     38         assembler) return a pointer to the fixS in question.  And I made it a
     39         little simpler by storing the field size (in this case 13) instead of
     40         of a pointer to another structure:  80960 displacements are ALWAYS
     41         stored in the low-order bits of a 4-byte word.
     42 
     43         Since the target of a COBR cannot be external, no relocation
     44         directives for this size displacement have to be generated.
     45         But the base assembler had to be modified to issue error
     46         messages if the symbol did turn out to be external.
     47 
     48    24-bit (CTRL)
     49         Fixups are handled as for the 13-bit case (except that 24 is stored
     50         in the fixS).
     51 
     52         The relocation directive generated is the same as that for the 32-bit
     53         displacement, except that it's PC-relative (the 32-bit displacement
     54         never is).   The i80960 version of the linker needs a mod to
     55         distinguish and handle the 24-bit case.
     56 
     57    12-bit (MEMA)
     58         MEMA formats are always promoted to MEMB (32-bit) if the displacement
     59         is based on a symbol, because it could be relocated at link time.
     60         The only time we use the 12-bit format is if an absolute value of
     61         less than 4096 is specified, in which case we need neither a fixup nor
     62         a relocation directive.  */
     63 
     64 #include "as.h"
     65 
     66 #include "safe-ctype.h"
     67 
     68 #include "opcode/i960.h"
     69 
     70 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
     71 
     72 #define TC_S_IS_SYSPROC(s)	((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32))
     73 #define TC_S_IS_BALNAME(s)	(S_GET_OTHER (s) == N_BALNAME)
     74 #define TC_S_IS_CALLNAME(s)	(S_GET_OTHER (s) == N_CALLNAME)
     75 #define TC_S_IS_BADPROC(s)	((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s))
     76 
     77 #define TC_S_SET_SYSPROC(s, p)	(S_SET_OTHER ((s), (p) + 1))
     78 #define TC_S_GET_SYSPROC(s)	(S_GET_OTHER (s) - 1)
     79 
     80 #define TC_S_FORCE_TO_BALNAME(s)	(S_SET_OTHER ((s), N_BALNAME))
     81 #define TC_S_FORCE_TO_CALLNAME(s)	(S_SET_OTHER ((s), N_CALLNAME))
     82 #define TC_S_FORCE_TO_SYSPROC(s)	{;}
     83 
     84 #else /* ! OBJ_A/BOUT */
     85 #ifdef OBJ_COFF
     86 
     87 #define TC_S_IS_SYSPROC(s)	(S_GET_STORAGE_CLASS (s) == C_SCALL)
     88 #define TC_S_IS_BALNAME(s)	(SF_GET_BALNAME (s))
     89 #define TC_S_IS_CALLNAME(s)	(SF_GET_CALLNAME (s))
     90 #define TC_S_IS_BADPROC(s)	(TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s))
     91 
     92 #define TC_S_SET_SYSPROC(s, p)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
     93 #define TC_S_GET_SYSPROC(s)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
     94 
     95 #define TC_S_FORCE_TO_BALNAME(s)	(SF_SET_BALNAME (s))
     96 #define TC_S_FORCE_TO_CALLNAME(s)	(SF_SET_CALLNAME (s))
     97 #define TC_S_FORCE_TO_SYSPROC(s)	(S_SET_STORAGE_CLASS ((s), C_SCALL))
     98 
     99 #else /* ! OBJ_COFF */
    100 #ifdef OBJ_ELF
    101 #define TC_S_IS_SYSPROC(s)	0
    102 
    103 #define TC_S_IS_BALNAME(s)	0
    104 #define TC_S_IS_CALLNAME(s)	0
    105 #define TC_S_IS_BADPROC(s)	0
    106 
    107 #define TC_S_SET_SYSPROC(s, p)
    108 #define TC_S_GET_SYSPROC(s)     0
    109 
    110 #define TC_S_FORCE_TO_BALNAME(s)
    111 #define TC_S_FORCE_TO_CALLNAME(s)
    112 #define TC_S_FORCE_TO_SYSPROC(s)
    113 #else
    114  #error COFF, a.out, b.out, and ELF are the only supported formats.
    115 #endif /* ! OBJ_ELF */
    116 #endif /* ! OBJ_COFF */
    117 #endif /* ! OBJ_A/BOUT */
    118 
    119 extern char *input_line_pointer;
    120 
    121 /* Local i80960 routines.  */
    122 struct memS;
    123 struct regop;
    124 
    125 /* See md_parse_option() for meanings of these options.  */
    126 static char norelax;			/* True if -norelax switch seen.  */
    127 static char instrument_branches;	/* True if -b switch seen.  */
    128 
    129 /* Characters that always start a comment.
    130    If the pre-processor is disabled, these aren't very useful.  */
    131 const char comment_chars[] = "#";
    132 
    133 /* Characters that only start a comment at the beginning of
    134    a line.  If the line seems to have the form '# 123 filename'
    135    .line and .file directives will appear in the pre-processed output.
    136 
    137    Note that input_file.c hand checks for '#' at the beginning of the
    138    first line of the input file.  This is because the compiler outputs
    139    #NO_APP at the beginning of its output.  */
    140 
    141 /* Also note that comments started like this one will always work.  */
    142 
    143 const char line_comment_chars[]   = "#";
    144 const char line_separator_chars[] = ";";
    145 
    146 /* Chars that can be used to separate mant from exp in floating point nums.  */
    147 const char EXP_CHARS[] = "eE";
    148 
    149 /* Chars that mean this number is a floating point constant,
    150    as in 0f12.456 or 0d1.2345e12.  */
    151 const char FLT_CHARS[] = "fFdDtT";
    152 
    153 /* Table used by base assembler to relax addresses based on varying length
    154    instructions.  The fields are:
    155      1) most positive reach of this state,
    156      2) most negative reach of this state,
    157      3) how many bytes this mode will add to the size of the current frag
    158      4) which index into the table to try if we can't fit into this one.
    159 
    160    For i80960, the only application is the (de-)optimization of cobr
    161    instructions into separate compare and branch instructions when a 13-bit
    162    displacement won't hack it.  */
    163 const relax_typeS md_relax_table[] =
    164 {
    165   {0, 0, 0, 0},				/* State 0 => no more relaxation possible.  */
    166   {4088, -4096, 0, 2},			/* State 1: conditional branch (cobr).  */
    167   {0x800000 - 8, -0x800000, 4, 0},	/* State 2: compare (reg) & branch (ctrl).  */
    168 };
    169 
    170 /* These are the machine dependent pseudo-ops.
    171 
    172    This table describes all the machine specific pseudo-ops the assembler
    173    has to support.  The fields are:
    174         pseudo-op name without dot
    175         function to call to execute this pseudo-op
    176         integer arg to pass to the function.  */
    177 #define S_LEAFPROC	1
    178 #define S_SYSPROC	2
    179 
    180 /* Macros to extract info from an 'expressionS' structure 'e'.  */
    181 #define adds(e)	e.X_add_symbol
    182 #define offs(e)	e.X_add_number
    183 
    184 /* Branch-prediction bits for CTRL/COBR format opcodes.  */
    185 #define BP_MASK		0x00000002	/* Mask for branch-prediction bit.  */
    186 #define BP_TAKEN	0x00000000	/* Value to OR in to predict branch.  */
    187 #define BP_NOT_TAKEN	0x00000002	/* Value to OR in to predict no branch.  */
    188 
    189 /* Some instruction opcodes that we need explicitly.  */
    190 #define BE	0x12000000
    191 #define BG	0x11000000
    192 #define BGE	0x13000000
    193 #define BL	0x14000000
    194 #define BLE	0x16000000
    195 #define BNE	0x15000000
    196 #define BNO	0x10000000
    197 #define BO	0x17000000
    198 #define CHKBIT	0x5a002700
    199 #define CMPI	0x5a002080
    200 #define CMPO	0x5a002000
    201 
    202 #define B	0x08000000
    203 #define BAL	0x0b000000
    204 #define CALL	0x09000000
    205 #define CALLS	0x66003800
    206 #define RET	0x0a000000
    207 
    208 /* These masks are used to build up a set of MEMB mode bits.  */
    209 #define	A_BIT		0x0400
    210 #define	I_BIT		0x0800
    211 #define MEMB_BIT	0x1000
    212 #define	D_BIT		0x2000
    213 
    214 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
    215    used).  */
    216 #define MEMA_ABASE	0x2000
    217 
    218 /* Info from which a MEMA or MEMB format instruction can be generated.  */
    219 typedef struct memS
    220   {
    221     /* (First) 32 bits of instruction.  */
    222     long opcode;
    223     /* 0-(none), 12- or, 32-bit displacement needed.  */
    224     int disp;
    225     /* The expression in the source instruction from which the
    226        displacement should be determined.  */
    227     char *e;
    228   }
    229 memS;
    230 
    231 /* The two pieces of info we need to generate a register operand.  */
    232 struct regop
    233   {
    234     int mode;			/* 0 =>local/global/spec reg; 1=> literal or fp reg.  */
    235     int special;		/* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0).  */
    236     int n;			/* Register number or literal value.  */
    237   };
    238 
    239 /* Number and assembler mnemonic for all registers that can appear in
    240    operands.  */
    241 static const struct
    242   {
    243     char *reg_name;
    244     int reg_num;
    245   }
    246 regnames[] =
    247 {
    248   { "pfp", 0 },
    249   { "sp", 1 },
    250   { "rip", 2 },
    251   { "r3", 3 },
    252   { "r4", 4 },
    253   { "r5", 5 },
    254   { "r6", 6 },
    255   { "r7", 7 },
    256   { "r8", 8 },
    257   { "r9", 9 },
    258   { "r10", 10 },
    259   { "r11", 11 },
    260   { "r12", 12 },
    261   { "r13", 13 },
    262   { "r14", 14 },
    263   { "r15", 15 },
    264   { "g0", 16 },
    265   { "g1", 17 },
    266   { "g2", 18 },
    267   { "g3", 19 },
    268   { "g4", 20 },
    269   { "g5", 21 },
    270   { "g6", 22 },
    271   { "g7", 23 },
    272   { "g8", 24 },
    273   { "g9", 25 },
    274   { "g10", 26 },
    275   { "g11", 27 },
    276   { "g12", 28 },
    277   { "g13", 29 },
    278   { "g14", 30 },
    279   { "fp", 31 },
    280 
    281   /* Numbers for special-function registers are for assembler internal
    282      use only: they are scaled back to range [0-31] for binary output.  */
    283 #define SF0	32
    284 
    285   { "sf0", 32 },
    286   { "sf1", 33 },
    287   { "sf2", 34 },
    288   { "sf3", 35 },
    289   { "sf4", 36 },
    290   { "sf5", 37 },
    291   { "sf6", 38 },
    292   { "sf7", 39 },
    293   { "sf8", 40 },
    294   { "sf9", 41 },
    295   { "sf10", 42 },
    296   { "sf11", 43 },
    297   { "sf12", 44 },
    298   { "sf13", 45 },
    299   { "sf14", 46 },
    300   { "sf15", 47 },
    301   { "sf16", 48 },
    302   { "sf17", 49 },
    303   { "sf18", 50 },
    304   { "sf19", 51 },
    305   { "sf20", 52 },
    306   { "sf21", 53 },
    307   { "sf22", 54 },
    308   { "sf23", 55 },
    309   { "sf24", 56 },
    310   { "sf25", 57 },
    311   { "sf26", 58 },
    312   { "sf27", 59 },
    313   { "sf28", 60 },
    314   { "sf29", 61 },
    315   { "sf30", 62 },
    316   { "sf31", 63 },
    317 
    318   /* Numbers for floating point registers are for assembler internal
    319      use only: they are scaled back to [0-3] for binary output.  */
    320 #define FP0	64
    321 
    322   { "fp0", 64 },
    323   { "fp1", 65 },
    324   { "fp2", 66 },
    325   { "fp3", 67 },
    326 
    327   { NULL, 0 },				/* END OF LIST */
    328 };
    329 
    330 #define	IS_RG_REG(n)	((0 <= (n)) && ((n) < SF0))
    331 #define	IS_SF_REG(n)	((SF0 <= (n)) && ((n) < FP0))
    332 #define	IS_FP_REG(n)	((n) >= FP0)
    333 
    334 /* Number and assembler mnemonic for all registers that can appear as
    335    'abase' (indirect addressing) registers.  */
    336 static const struct
    337 {
    338   char *areg_name;
    339   int areg_num;
    340 }
    341 aregs[] =
    342 {
    343   { "(pfp)", 0 },
    344   { "(sp)", 1 },
    345   { "(rip)", 2 },
    346   { "(r3)", 3 },
    347   { "(r4)", 4 },
    348   { "(r5)", 5 },
    349   { "(r6)", 6 },
    350   { "(r7)", 7 },
    351   { "(r8)", 8 },
    352   { "(r9)", 9 },
    353   { "(r10)", 10 },
    354   { "(r11)", 11 },
    355   { "(r12)", 12 },
    356   { "(r13)", 13 },
    357   { "(r14)", 14 },
    358   { "(r15)", 15 },
    359   { "(g0)", 16 },
    360   { "(g1)", 17 },
    361   { "(g2)", 18 },
    362   { "(g3)", 19 },
    363   { "(g4)", 20 },
    364   { "(g5)", 21 },
    365   { "(g6)", 22 },
    366   { "(g7)", 23 },
    367   { "(g8)", 24 },
    368   { "(g9)", 25 },
    369   { "(g10)", 26 },
    370   { "(g11)", 27 },
    371   { "(g12)", 28 },
    372   { "(g13)", 29 },
    373   { "(g14)", 30 },
    374   { "(fp)", 31 },
    375 
    376 #define IPREL	32
    377   /* For assembler internal use only: this number never appears in binary
    378      output.  */
    379   { "(ip)", IPREL },
    380 
    381   { NULL, 0 },				/* END OF LIST */
    382 };
    383 
    384 /* Hash tables.  */
    385 static struct hash_control *op_hash;	/* Opcode mnemonics.  */
    386 static struct hash_control *reg_hash;	/* Register name hash table.  */
    387 static struct hash_control *areg_hash;	/* Abase register hash table.  */
    388 
    389 /* Architecture for which we are assembling.  */
    390 #define ARCH_ANY	0	/* Default: no architecture checking done.  */
    391 #define ARCH_KA		1
    392 #define ARCH_KB		2
    393 #define ARCH_MC		3
    394 #define ARCH_CA		4
    395 #define ARCH_JX		5
    396 #define ARCH_HX		6
    397 int architecture = ARCH_ANY;	/* Architecture requested on invocation line.  */
    398 int iclasses_seen;		/* OR of instruction classes (I_* constants)
    399 				      for which we've actually assembled
    400 				        instructions.  */
    401 
    402 /* BRANCH-PREDICTION INSTRUMENTATION
    403 
    404         The following supports generation of branch-prediction instrumentation
    405         (turned on by -b switch).  The instrumentation collects counts
    406         of branches taken/not-taken for later input to a utility that will
    407         set the branch prediction bits of the instructions in accordance with
    408         the behavior observed.  (Note that the KX series does not have
    409         brach-prediction.)
    410 
    411         The instrumentation consists of:
    412 
    413         (1) before and after each conditional branch, a call to an external
    414             routine that increments and steps over an inline counter.  The
    415             counter itself, initialized to 0, immediately follows the call
    416             instruction.  For each branch, the counter following the branch
    417             is the number of times the branch was not taken, and the difference
    418             between the counters is the number of times it was taken.  An
    419             example of an instrumented conditional branch:
    420 
    421                                 call    BR_CNT_FUNC
    422                                 .word   0
    423                 LBRANCH23:      be      label
    424                                 call    BR_CNT_FUNC
    425                                 .word   0
    426 
    427         (2) a table of pointers to the instrumented branches, so that an
    428             external postprocessing routine can locate all of the counters.
    429             the table begins with a 2-word header: a pointer to the next in
    430             a linked list of such tables (initialized to 0);  and a count
    431             of the number of entries in the table (exclusive of the header.
    432 
    433             Note that input source code is expected to already contain calls
    434             an external routine that will link the branch local table into a
    435             list of such tables.  */
    436 
    437 /* Number of branches instrumented so far.  Also used to generate
    438    unique local labels for each instrumented branch.  */
    439 static int br_cnt;
    440 
    441 #define BR_LABEL_BASE	"LBRANCH"
    442 /* Basename of local labels on instrumented branches, to avoid
    443    conflict with compiler- generated local labels.  */
    444 
    445 #define BR_CNT_FUNC	"__inc_branch"
    446 /* Name of the external routine that will increment (and step over) an
    447    inline counter.  */
    448 
    449 #define BR_TAB_NAME	"__BRANCH_TABLE__"
    450 /* Name of the table of pointers to branches.  A local (i.e.,
    451    non-external) symbol.  */
    452 
    453 static void ctrl_fmt (char *, long, int);
    454 
    455 
    456 void
    458 md_begin (void)
    459 {
    460   int i;			/* Loop counter.  */
    461   const struct i960_opcode *oP;	/* Pointer into opcode table.  */
    462   const char *retval;		/* Value returned by hash functions.  */
    463 
    464   op_hash = hash_new ();
    465   reg_hash = hash_new ();
    466   areg_hash = hash_new ();
    467 
    468   /* For some reason, the base assembler uses an empty string for "no
    469      error message", instead of a NULL pointer.  */
    470   retval = 0;
    471 
    472   for (oP = i960_opcodes; oP->name && !retval; oP++)
    473     retval = hash_insert (op_hash, oP->name, (void *) oP);
    474 
    475   for (i = 0; regnames[i].reg_name && !retval; i++)
    476     retval = hash_insert (reg_hash, regnames[i].reg_name,
    477 			  (char *) &regnames[i].reg_num);
    478 
    479   for (i = 0; aregs[i].areg_name && !retval; i++)
    480     retval = hash_insert (areg_hash, aregs[i].areg_name,
    481 			  (char *) &aregs[i].areg_num);
    482 
    483   if (retval)
    484     as_fatal (_("Hashing returned \"%s\"."), retval);
    485 }
    486 
    487 /* parse_expr:		parse an expression
    488 
    489    Use base assembler's expression parser to parse an expression.
    490    It, unfortunately, runs off a global which we have to save/restore
    491    in order to make it work for us.
    492 
    493    An empty expression string is treated as an absolute 0.
    494 
    495    Sets O_illegal regardless of expression evaluation if entire input
    496    string is not consumed in the evaluation -- tolerate no dangling junk!  */
    497 
    498 static void
    499 parse_expr (char *textP,		/* Text of expression to be parsed.  */
    500 	    expressionS *expP)		/* Where to put the results of parsing.  */
    501 {
    502   char *save_in;		/* Save global here.  */
    503   symbolS *symP;
    504 
    505   know (textP);
    506 
    507   if (*textP == '\0')
    508     {
    509       /* Treat empty string as absolute 0.  */
    510       expP->X_add_symbol = expP->X_op_symbol = NULL;
    511       expP->X_add_number = 0;
    512       expP->X_op = O_constant;
    513     }
    514   else
    515     {
    516       save_in = input_line_pointer;	/* Save global.  */
    517       input_line_pointer = textP;	/* Make parser work for us.  */
    518 
    519       (void) expression (expP);
    520       if ((size_t) (input_line_pointer - textP) != strlen (textP))
    521 	/* Did not consume all of the input.  */
    522 	expP->X_op = O_illegal;
    523 
    524       symP = expP->X_add_symbol;
    525       if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
    526 	/* Register name in an expression.  */
    527 	/* FIXME: this isn't much of a check any more.  */
    528 	expP->X_op = O_illegal;
    529 
    530       input_line_pointer = save_in;	/* Restore global.  */
    531     }
    532 }
    533 
    534 /* emit:	output instruction binary
    535 
    536    Output instruction binary, in target byte order, 4 bytes at a time.
    537    Return pointer to where it was placed.  */
    538 
    539 static char *
    540 emit (long instr)		/* Word to be output, host byte order.  */
    541 {
    542   char *toP;			/* Where to output it.  */
    543 
    544   toP = frag_more (4);		/* Allocate storage.  */
    545   md_number_to_chars (toP, instr, 4);	/* Convert to target byte order.  */
    546   return toP;
    547 }
    548 
    549 /* get_cdisp:	handle displacement for a COBR or CTRL instruction.
    550 
    551    Parse displacement for a COBR or CTRL instruction.
    552 
    553    If successful, output the instruction opcode and set up for it,
    554    depending on the arg 'var_frag', either:
    555   	    o an address fixup to be done when all symbol values are known, or
    556   	    o a varying length code fragment, with address fixup info.  This
    557   		will be done for cobr instructions that may have to be relaxed
    558   		in to compare/branch instructions (8 bytes) if the final
    559   		address displacement is greater than 13 bits.  */
    560 
    561 static void
    562 get_cdisp (char *dispP, /* Displacement as specified in source instruction.  */
    563 	   char *ifmtP, /* "COBR" or "CTRL" (for use in error message).  */
    564 	   long instr,  /* Instruction needing the displacement.  */
    565 	   int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL).  */
    566 	   int var_frag,/* 1 if varying length code fragment should be emitted;
    567 			   0 if an address fix should be emitted.  */
    568 	   int callj)	/* 1 if callj relocation should be done; else 0.  */
    569 {
    570   expressionS e;		/* Parsed expression.  */
    571   fixS *fixP;			/* Structure describing needed address fix.  */
    572   char *outP;			/* Where instruction binary is output to.  */
    573 
    574   fixP = NULL;
    575 
    576   parse_expr (dispP, &e);
    577   switch (e.X_op)
    578     {
    579     case O_illegal:
    580       as_bad (_("expression syntax error"));
    581 
    582     case O_symbol:
    583       if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
    584 	  || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
    585 	{
    586 	  if (var_frag)
    587 	    {
    588 	      outP = frag_more (8);	/* Allocate worst-case storage.  */
    589 	      md_number_to_chars (outP, instr, 4);
    590 	      frag_variant (rs_machine_dependent, 4, 4, 1,
    591 			    adds (e), offs (e), outP);
    592 	    }
    593 	  else
    594 	    {
    595 	      /* Set up a new fix structure, so address can be updated
    596 	         when all symbol values are known.  */
    597 	      outP = emit (instr);
    598 	      fixP = fix_new (frag_now,
    599 			      outP - frag_now->fr_literal,
    600 			      4,
    601 			      adds (e),
    602 			      offs (e),
    603 			      1,
    604 			      NO_RELOC);
    605 
    606 	      fixP->fx_tcbit = callj;
    607 
    608 	      /* We want to modify a bit field when the address is
    609 	         known.  But we don't need all the garbage in the
    610 	         bit_fix structure.  So we're going to lie and store
    611 	         the number of bits affected instead of a pointer.  */
    612 	      fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
    613 	    }
    614 	}
    615       else
    616 	as_bad (_("attempt to branch into different segment"));
    617       break;
    618 
    619     default:
    620       as_bad (_("target of %s instruction must be a label"), ifmtP);
    621       break;
    622     }
    623 }
    624 
    625 static int
    626 md_chars_to_number (char * val,		/* Value in target byte order.  */
    627 		    int n)		/* Number of bytes in the input.  */
    628 {
    629   int retval;
    630 
    631   for (retval = 0; n--;)
    632     {
    633       retval <<= 8;
    634       retval |= (unsigned char) val[n];
    635     }
    636   return retval;
    637 }
    638 
    639 /* mema_to_memb:	convert a MEMA-format opcode to a MEMB-format opcode.
    640 
    641    There are 2 possible MEMA formats:
    642   	- displacement only
    643   	- displacement + abase
    644 
    645    They are distinguished by the setting of the MEMA_ABASE bit.  */
    646 
    647 static void
    648 mema_to_memb (char * opcodeP)	/* Where to find the opcode, in target byte order.  */
    649 {
    650   long opcode;			/* Opcode in host byte order.  */
    651   long mode;			/* Mode bits for MEMB instruction.  */
    652 
    653   opcode = md_chars_to_number (opcodeP, 4);
    654   know (!(opcode & MEMB_BIT));
    655 
    656   mode = MEMB_BIT | D_BIT;
    657   if (opcode & MEMA_ABASE)
    658     mode |= A_BIT;
    659 
    660   opcode &= 0xffffc000;		/* Clear MEMA offset and mode bits.  */
    661   opcode |= mode;		/* Set MEMB mode bits.  */
    662 
    663   md_number_to_chars (opcodeP, opcode, 4);
    664 }
    665 
    666 /* targ_has_sfr:
    667 
    668    Return TRUE iff the target architecture supports the specified
    669    special-function register (sfr).  */
    670 
    671 static int
    672 targ_has_sfr (int n)		/* Number (0-31) of sfr.  */
    673 {
    674   switch (architecture)
    675     {
    676     case ARCH_KA:
    677     case ARCH_KB:
    678     case ARCH_MC:
    679     case ARCH_JX:
    680       return 0;
    681     case ARCH_HX:
    682       return ((0 <= n) && (n <= 4));
    683     case ARCH_CA:
    684     default:
    685       return ((0 <= n) && (n <= 2));
    686     }
    687 }
    688 
    689 /* Look up a (suspected) register name in the register table and return the
    690    associated register number (or -1 if not found).  */
    691 
    692 static int
    693 get_regnum (char *regname)	/* Suspected register name.  */
    694 {
    695   int *rP;
    696 
    697   rP = (int *) hash_find (reg_hash, regname);
    698   return (rP == NULL) ? -1 : *rP;
    699 }
    700 
    701 /* syntax: Issue a syntax error.  */
    702 
    703 static void
    704 syntax (void)
    705 {
    706   as_bad (_("syntax error"));
    707 }
    708 
    709 /* parse_regop: parse a register operand.
    710 
    711    In case of illegal operand, issue a message and return some valid
    712    information so instruction processing can continue.  */
    713 
    714 static void
    715 parse_regop (struct regop *regopP,	/* Where to put description of register operand.  */
    716 	     char *optext,		/* Text of operand.  */
    717 	     char opdesc)      		/* Descriptor byte:  what's legal for this operand.  */
    718 {
    719   int n;			/* Register number.  */
    720   expressionS e;		/* Parsed expression.  */
    721 
    722   /* See if operand is a register.  */
    723   n = get_regnum (optext);
    724   if (n >= 0)
    725     {
    726       if (IS_RG_REG (n))
    727 	{
    728 	  /* Global or local register.  */
    729 	  if (!REG_ALIGN (opdesc, n))
    730 	    as_bad (_("unaligned register"));
    731 
    732 	  regopP->n = n;
    733 	  regopP->mode = 0;
    734 	  regopP->special = 0;
    735 	  return;
    736 	}
    737       else if (IS_FP_REG (n) && FP_OK (opdesc))
    738 	{
    739 	  /* Floating point register, and it's allowed.  */
    740 	  regopP->n = n - FP0;
    741 	  regopP->mode = 1;
    742 	  regopP->special = 0;
    743 	  return;
    744 	}
    745       else if (IS_SF_REG (n) && SFR_OK (opdesc))
    746 	{
    747 	  /* Special-function register, and it's allowed.  */
    748 	  regopP->n = n - SF0;
    749 	  regopP->mode = 0;
    750 	  regopP->special = 1;
    751 	  if (!targ_has_sfr (regopP->n))
    752 	    as_bad (_("no such sfr in this architecture"));
    753 
    754 	  return;
    755 	}
    756     }
    757   else if (LIT_OK (opdesc))
    758     {
    759       /* How about a literal?  */
    760       regopP->mode = 1;
    761       regopP->special = 0;
    762       if (FP_OK (opdesc))
    763 	{
    764 	  /* Floating point literal acceptable.  */
    765 	  /* Skip over 0f, 0d, or 0e prefix.  */
    766 	  if ((optext[0] == '0')
    767 	      && (optext[1] >= 'd')
    768 	      && (optext[1] <= 'f'))
    769 	    optext += 2;
    770 
    771 	  if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
    772 	    {
    773 	      regopP->n = 0x10;
    774 	      return;
    775 	    }
    776 
    777 	  if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
    778 	    {
    779 	      regopP->n = 0x16;
    780 	      return;
    781 	    }
    782 	}
    783       else
    784 	{
    785 	  /* Fixed point literal acceptable.  */
    786 	  parse_expr (optext, &e);
    787 	  if (e.X_op != O_constant
    788 	      || (offs (e) < 0) || (offs (e) > 31))
    789 	    {
    790 	      as_bad (_("illegal literal"));
    791 	      offs (e) = 0;
    792 	    }
    793 	  regopP->n = offs (e);
    794 	  return;
    795 	}
    796     }
    797 
    798   /* Nothing worked.  */
    799   syntax ();
    800   regopP->mode = 0;		/* Register r0 is always a good one.  */
    801   regopP->n = 0;
    802   regopP->special = 0;
    803 }
    804 
    805 /* get_ispec:	parse a memory operand for an index specification
    806 
    807    Here, an "index specification" is taken to be anything surrounded
    808    by square brackets and NOT followed by anything else.
    809 
    810    If it's found, detach it from the input string, remove the surrounding
    811    square brackets, and return a pointer to it.  Otherwise, return NULL.  */
    812 
    813 static char *
    814 get_ispec (char *textP)  /* Pointer to memory operand from source instruction, no white space.  */
    815 
    816 {
    817   /* Points to start of index specification.  */
    818   char *start;
    819   /* Points to end of index specification.  */
    820   char *end;
    821 
    822   /* Find opening square bracket, if any.  */
    823   start = strchr (textP, '[');
    824 
    825   if (start != NULL)
    826     {
    827       /* Eliminate '[', detach from rest of operand.  */
    828       *start++ = '\0';
    829 
    830       end = strchr (start, ']');
    831 
    832       if (end == NULL)
    833 	as_bad (_("unmatched '['"));
    834       else
    835 	{
    836 	  /* Eliminate ']' and make sure it was the last thing
    837 	     in the string.  */
    838 	  *end = '\0';
    839 	  if (*(end + 1) != '\0')
    840 	    as_bad (_("garbage after index spec ignored"));
    841 	}
    842     }
    843   return start;
    844 }
    845 
    846 /* parse_memop:	parse a memory operand
    847 
    848   	This routine is based on the observation that the 4 mode bits of the
    849   	MEMB format, taken individually, have fairly consistent meaning:
    850 
    851   		 M3 (bit 13): 1 if displacement is present (D_BIT)
    852   		 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
    853   		 M1 (bit 11): 1 if index is present (I_BIT)
    854   		 M0 (bit 10): 1 if abase is present (A_BIT)
    855 
    856   	So we parse the memory operand and set bits in the mode as we find
    857   	things.  Then at the end, if we go to MEMB format, we need only set
    858   	the MEMB bit (M2) and our mode is built for us.
    859 
    860   	Unfortunately, I said "fairly consistent".  The exceptions:
    861 
    862   		 DBIA
    863   		 0100	Would seem illegal, but means "abase-only".
    864 
    865   		 0101	Would seem to mean "abase-only" -- it means IP-relative.
    866   			Must be converted to 0100.
    867 
    868   		 0110	Would seem to mean "index-only", but is reserved.
    869   			We turn on the D bit and provide a 0 displacement.
    870 
    871   	The other thing to observe is that we parse from the right, peeling
    872   	things * off as we go:  first any index spec, then any abase, then
    873   	the displacement.  */
    874 
    875 static void
    876 parse_memop (memS *memP,	/* Where to put the results.  */
    877 	     char *argP,	/* Text of the operand to be parsed.  */
    878 	     int optype)	/* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16.  */
    879 {
    880   char *indexP;			/* Pointer to index specification with "[]" removed.  */
    881   char *p;			/* Temp char pointer.  */
    882   char iprel_flag;		/* True if this is an IP-relative operand.  */
    883   int regnum;			/* Register number.  */
    884   /* Scale factor: 1,2,4,8, or 16.  Later converted to internal format
    885      (0,1,2,3,4 respectively).  */
    886   int scale;
    887   int mode;			/* MEMB mode bits.  */
    888   int *intP;			/* Pointer to register number.  */
    889 
    890   /* The following table contains the default scale factors for each
    891      type of memory instruction.  It is accessed using (optype-MEM1)
    892      as an index -- thus it assumes the 'optype' constants are
    893      assigned consecutive values, in the order they appear in this
    894      table.  */
    895   static const int def_scale[] =
    896   {
    897     1,				/* MEM1 */
    898     2,				/* MEM2 */
    899     4,				/* MEM4 */
    900     8,				/* MEM8 */
    901     -1,				/* MEM12 -- no valid default */
    902     16				/* MEM16 */
    903   };
    904 
    905   iprel_flag = mode = 0;
    906 
    907   /* Any index present? */
    908   indexP = get_ispec (argP);
    909   if (indexP)
    910     {
    911       p = strchr (indexP, '*');
    912       if (p == NULL)
    913 	{
    914 	  /* No explicit scale -- use default for this instruction
    915 	     type and assembler mode.  */
    916 	  if (flag_mri)
    917 	    scale = 1;
    918 	  else
    919 	    /* GNU960 compatibility */
    920 	    scale = def_scale[optype - MEM1];
    921 	}
    922       else
    923 	{
    924 	  *p++ = '\0';		/* Eliminate '*' */
    925 
    926 	  /* Now indexP->a '\0'-terminated register name,
    927 	     and p->a scale factor.  */
    928 
    929 	  if (!strcmp (p, "16"))
    930 	    scale = 16;
    931 	  else if (strchr ("1248", *p) && (p[1] == '\0'))
    932 	    scale = *p - '0';
    933 	  else
    934 	    scale = -1;
    935 	}
    936 
    937       regnum = get_regnum (indexP);	/* Get index reg. # */
    938       if (!IS_RG_REG (regnum))
    939 	{
    940 	  as_bad (_("invalid index register"));
    941 	  return;
    942 	}
    943 
    944       /* Convert scale to its binary encoding.  */
    945       switch (scale)
    946 	{
    947 	case 1:
    948 	  scale = 0 << 7;
    949 	  break;
    950 	case 2:
    951 	  scale = 1 << 7;
    952 	  break;
    953 	case 4:
    954 	  scale = 2 << 7;
    955 	  break;
    956 	case 8:
    957 	  scale = 3 << 7;
    958 	  break;
    959 	case 16:
    960 	  scale = 4 << 7;
    961 	  break;
    962 	default:
    963 	  as_bad (_("invalid scale factor"));
    964 	  return;
    965 	};
    966 
    967       memP->opcode |= scale | regnum;	/* Set index bits in opcode.  */
    968       mode |= I_BIT;			/* Found a valid index spec.  */
    969     }
    970 
    971   /* Any abase (Register Indirect) specification present?  */
    972   if ((p = strrchr (argP, '(')) != NULL)
    973     {
    974       /* "(" is there -- does it start a legal abase spec?  If not, it
    975          could be part of a displacement expression.  */
    976       intP = (int *) hash_find (areg_hash, p);
    977       if (intP != NULL)
    978 	{
    979 	  /* Got an abase here.  */
    980 	  regnum = *intP;
    981 	  *p = '\0';		/* Discard register spec.  */
    982 	  if (regnum == IPREL)
    983 	    /* We have to specialcase ip-rel mode.  */
    984 	    iprel_flag = 1;
    985 	  else
    986 	    {
    987 	      memP->opcode |= regnum << 14;
    988 	      mode |= A_BIT;
    989 	    }
    990 	}
    991     }
    992 
    993   /* Any expression present?  */
    994   memP->e = argP;
    995   if (*argP != '\0')
    996     mode |= D_BIT;
    997 
    998   /* Special-case ip-relative addressing.  */
    999   if (iprel_flag)
   1000     {
   1001       if (mode & I_BIT)
   1002 	syntax ();
   1003       else
   1004 	{
   1005 	  memP->opcode |= 5 << 10;	/* IP-relative mode.  */
   1006 	  memP->disp = 32;
   1007 	}
   1008       return;
   1009     }
   1010 
   1011   /* Handle all other modes.  */
   1012   switch (mode)
   1013     {
   1014     case D_BIT | A_BIT:
   1015       /* Go with MEMA instruction format for now (grow to MEMB later
   1016          if 12 bits is not enough for the displacement).  MEMA format
   1017          has a single mode bit: set it to indicate that abase is
   1018          present.  */
   1019       memP->opcode |= MEMA_ABASE;
   1020       memP->disp = 12;
   1021       break;
   1022 
   1023     case D_BIT:
   1024       /* Go with MEMA instruction format for now (grow to MEMB later
   1025          if 12 bits is not enough for the displacement).  */
   1026       memP->disp = 12;
   1027       break;
   1028 
   1029     case A_BIT:
   1030       /* For some reason, the bit string for this mode is not
   1031          consistent: it should be 0 (exclusive of the MEMB bit), so we
   1032          set it "by hand" here.  */
   1033       memP->opcode |= MEMB_BIT;
   1034       break;
   1035 
   1036     case A_BIT | I_BIT:
   1037       /* set MEMB bit in mode, and OR in mode bits.  */
   1038       memP->opcode |= mode | MEMB_BIT;
   1039       break;
   1040 
   1041     case I_BIT:
   1042       /* Treat missing displacement as displacement of 0.  */
   1043       mode |= D_BIT;
   1044       /* Fall into next case.  */
   1045     case D_BIT | A_BIT | I_BIT:
   1046     case D_BIT | I_BIT:
   1047       /* Set MEMB bit in mode, and OR in mode bits.  */
   1048       memP->opcode |= mode | MEMB_BIT;
   1049       memP->disp = 32;
   1050       break;
   1051 
   1052     default:
   1053       syntax ();
   1054       break;
   1055     }
   1056 }
   1057 
   1058 /* Generate a MEMA- or MEMB-format instruction.  */
   1059 
   1060 static void
   1061 mem_fmt (char *args[],		/* args[0]->opcode mnemonic, args[1-3]->operands.  */
   1062 	 struct i960_opcode *oP,/* Pointer to description of instruction.  */
   1063 	 int callx)		/* Is this a callx opcode.  */
   1064 {
   1065   int i;			/* Loop counter.  */
   1066   struct regop regop;		/* Description of register operand.  */
   1067   char opdesc;			/* Operand descriptor byte.  */
   1068   memS instr;			/* Description of binary to be output.  */
   1069   char *outP;			/* Where the binary was output to.  */
   1070   expressionS exp;		/* Parsed expression.  */
   1071   /* ->description of deferred address fixup.  */
   1072   fixS *fixP;
   1073 
   1074 #ifdef OBJ_COFF
   1075   /* COFF support isn't in place yet for callx relaxing.  */
   1076   callx = 0;
   1077 #endif
   1078 
   1079   memset (&instr, '\0', sizeof (memS));
   1080   instr.opcode = oP->opcode;
   1081 
   1082   /* Process operands.  */
   1083   for (i = 1; i <= oP->num_ops; i++)
   1084     {
   1085       opdesc = oP->operand[i - 1];
   1086 
   1087       if (MEMOP (opdesc))
   1088 	parse_memop (&instr, args[i], oP->format);
   1089       else
   1090 	{
   1091 	  parse_regop (&regop, args[i], opdesc);
   1092 	  instr.opcode |= regop.n << 19;
   1093 	}
   1094     }
   1095 
   1096   /* Parse the displacement; this must be done before emitting the
   1097      opcode, in case it is an expression using `.'.  */
   1098   parse_expr (instr.e, &exp);
   1099 
   1100   /* Output opcode.  */
   1101   outP = emit (instr.opcode);
   1102 
   1103   if (instr.disp == 0)
   1104     return;
   1105 
   1106   /* Process the displacement.  */
   1107   switch (exp.X_op)
   1108     {
   1109     case O_illegal:
   1110       as_bad (_("expression syntax error"));
   1111       break;
   1112 
   1113     case O_constant:
   1114       if (instr.disp == 32)
   1115 	(void) emit (offs (exp));	/* Output displacement.  */
   1116       else
   1117 	{
   1118 	  /* 12-bit displacement.  */
   1119 	  if (offs (exp) & ~0xfff)
   1120 	    {
   1121 	      /* Won't fit in 12 bits: convert already-output
   1122 	         instruction to MEMB format, output
   1123 	         displacement.  */
   1124 	      mema_to_memb (outP);
   1125 	      (void) emit (offs (exp));
   1126 	    }
   1127 	  else
   1128 	    {
   1129 	      /* WILL fit in 12 bits:  OR into opcode and
   1130 	         overwrite the binary we already put out.  */
   1131 	      instr.opcode |= offs (exp);
   1132 	      md_number_to_chars (outP, instr.opcode, 4);
   1133 	    }
   1134 	}
   1135       break;
   1136 
   1137     default:
   1138       if (instr.disp == 12)
   1139 	/* Displacement is dependent on a symbol, whose value
   1140 	   may change at link time.  We HAVE to reserve 32 bits.
   1141 	   Convert already-output opcode to MEMB format.  */
   1142 	mema_to_memb (outP);
   1143 
   1144       /* Output 0 displacement and set up address fixup for when
   1145          this symbol's value becomes known.  */
   1146       outP = emit ((long) 0);
   1147       fixP = fix_new_exp (frag_now,
   1148 			  outP - frag_now->fr_literal,
   1149 			  4, &exp, 0, NO_RELOC);
   1150       /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
   1151          being in the instruction stream, specifically as part of a callx
   1152          instruction.  */
   1153       fixP->fx_bsr = callx;
   1154       break;
   1155     }
   1156 }
   1157 
   1158 /* targ_has_iclass:
   1159 
   1160    Return TRUE iff the target architecture supports the indicated
   1161    class of instructions.  */
   1162 
   1163 static int
   1164 targ_has_iclass (int ic) /* Instruction class;  one of:
   1165 			    I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2.  */
   1166 {
   1167   iclasses_seen |= ic;
   1168 
   1169   switch (architecture)
   1170     {
   1171     case ARCH_KA:
   1172       return ic & (I_BASE | I_KX);
   1173     case ARCH_KB:
   1174       return ic & (I_BASE | I_KX | I_FP | I_DEC);
   1175     case ARCH_MC:
   1176       return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
   1177     case ARCH_CA:
   1178       return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
   1179     case ARCH_JX:
   1180       return ic & (I_BASE | I_CX2 | I_JX);
   1181     case ARCH_HX:
   1182       return ic & (I_BASE | I_CX2 | I_JX | I_HX);
   1183     default:
   1184       if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
   1185 	  && (iclasses_seen & (I_CX | I_CX2)))
   1186 	{
   1187 	  as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
   1188 	  iclasses_seen &= ~ic;
   1189 	}
   1190       return 1;
   1191     }
   1192 }
   1193 
   1194 /* shift_ok:
   1195    Determine if a "shlo" instruction can be used to implement a "ldconst".
   1196    This means that some number X < 32 can be shifted left to produce the
   1197    constant of interest.
   1198 
   1199    Return the shift count, or 0 if we can't do it.
   1200    Caller calculates X by shifting original constant right 'shift' places.  */
   1201 
   1202 static int
   1203 shift_ok (int n)		/* The constant of interest.  */
   1204 {
   1205   int shift;			/* The shift count.  */
   1206 
   1207   if (n <= 0)
   1208     /* Can't do it for negative numbers.  */
   1209     return 0;
   1210 
   1211   /* Shift 'n' right until a 1 is about to be lost.  */
   1212   for (shift = 0; (n & 1) == 0; shift++)
   1213     n >>= 1;
   1214 
   1215   if (n >= 32)
   1216     return 0;
   1217 
   1218   return shift;
   1219 }
   1220 
   1221 /* parse_ldcont:
   1222    Parse and replace a 'ldconst' pseudo-instruction with an appropriate
   1223    i80960 instruction.
   1224 
   1225    Assumes the input consists of:
   1226   		arg[0]	opcode mnemonic ('ldconst')
   1227   		arg[1]  first operand (constant)
   1228   		arg[2]	name of register to be loaded
   1229 
   1230    Replaces opcode and/or operands as appropriate.
   1231 
   1232    Returns the new number of arguments, or -1 on failure.  */
   1233 
   1234 static int
   1235 parse_ldconst (char *arg[])	/* See above.  */
   1236 {
   1237   int n;			/* Constant to be loaded.  */
   1238   int shift;			/* Shift count for "shlo" instruction.  */
   1239   static char buf[5];		/* Literal for first operand.  */
   1240   static char buf2[5];		/* Literal for second operand.  */
   1241   expressionS e;		/* Parsed expression.  */
   1242 
   1243   arg[3] = NULL;		/* So we can tell at the end if it got used or not.  */
   1244 
   1245   parse_expr (arg[1], &e);
   1246   switch (e.X_op)
   1247     {
   1248     default:
   1249       /* We're dependent on one or more symbols -- use "lda".  */
   1250       arg[0] = "lda";
   1251       break;
   1252 
   1253     case O_constant:
   1254       /* Try the following mappings:
   1255               ldconst   0,<reg>  -> mov  0,<reg>
   1256               ldconst  31,<reg>  -> mov  31,<reg>
   1257               ldconst  32,<reg>  -> addo 1,31,<reg>
   1258               ldconst  62,<reg>  -> addo 31,31,<reg>
   1259               ldconst  64,<reg>  -> shlo 8,3,<reg>
   1260               ldconst  -1,<reg>  -> subo 1,0,<reg>
   1261               ldconst -31,<reg>  -> subo 31,0,<reg>
   1262 
   1263          Anything else becomes:
   1264                 lda xxx,<reg>.  */
   1265       n = offs (e);
   1266       if ((0 <= n) && (n <= 31))
   1267 	arg[0] = "mov";
   1268       else if ((-31 <= n) && (n <= -1))
   1269 	{
   1270 	  arg[0] = "subo";
   1271 	  arg[3] = arg[2];
   1272 	  sprintf (buf, "%d", -n);
   1273 	  arg[1] = buf;
   1274 	  arg[2] = "0";
   1275 	}
   1276       else if ((32 <= n) && (n <= 62))
   1277 	{
   1278 	  arg[0] = "addo";
   1279 	  arg[3] = arg[2];
   1280 	  arg[1] = "31";
   1281 	  sprintf (buf, "%d", n - 31);
   1282 	  arg[2] = buf;
   1283 	}
   1284       else if ((shift = shift_ok (n)) != 0)
   1285 	{
   1286 	  arg[0] = "shlo";
   1287 	  arg[3] = arg[2];
   1288 	  sprintf (buf, "%d", shift);
   1289 	  arg[1] = buf;
   1290 	  sprintf (buf2, "%d", n >> shift);
   1291 	  arg[2] = buf2;
   1292 	}
   1293       else
   1294 	arg[0] = "lda";
   1295       break;
   1296 
   1297     case O_illegal:
   1298       as_bad (_("invalid constant"));
   1299       return -1;
   1300       break;
   1301     }
   1302   return (arg[3] == 0) ? 2 : 3;
   1303 }
   1304 
   1305 /* reg_fmt:	generate a REG-format instruction.  */
   1306 
   1307 static void
   1308 reg_fmt (char *args[],		/* args[0]->opcode mnemonic, args[1-3]->operands.  */
   1309 	 struct i960_opcode *oP)/* Pointer to description of instruction.  */
   1310 {
   1311   long instr;			/* Binary to be output.  */
   1312   struct regop regop;		/* Description of register operand.  */
   1313   int n_ops;			/* Number of operands.  */
   1314 
   1315   instr = oP->opcode;
   1316   n_ops = oP->num_ops;
   1317 
   1318   if (n_ops >= 1)
   1319     {
   1320       parse_regop (&regop, args[1], oP->operand[0]);
   1321 
   1322       if ((n_ops == 1) && !(instr & M3))
   1323 	{
   1324 	  /* 1-operand instruction in which the dst field should
   1325 	     be used (instead of src1).  */
   1326 	  regop.n <<= 19;
   1327 	  if (regop.special)
   1328 	    regop.mode = regop.special;
   1329 	  regop.mode <<= 13;
   1330 	  regop.special = 0;
   1331 	}
   1332       else
   1333 	{
   1334 	  /* regop.n goes in bit 0, needs no shifting.  */
   1335 	  regop.mode <<= 11;
   1336 	  regop.special <<= 5;
   1337 	}
   1338       instr |= regop.n | regop.mode | regop.special;
   1339     }
   1340 
   1341   if (n_ops >= 2)
   1342     {
   1343       parse_regop (&regop, args[2], oP->operand[1]);
   1344 
   1345       if ((n_ops == 2) && !(instr & M3))
   1346 	{
   1347 	  /* 2-operand instruction in which the dst field should
   1348 	     be used instead of src2).  */
   1349 	  regop.n <<= 19;
   1350 	  if (regop.special)
   1351 	    regop.mode = regop.special;
   1352 	  regop.mode <<= 13;
   1353 	  regop.special = 0;
   1354 	}
   1355       else
   1356 	{
   1357 	  regop.n <<= 14;
   1358 	  regop.mode <<= 12;
   1359 	  regop.special <<= 6;
   1360 	}
   1361       instr |= regop.n | regop.mode | regop.special;
   1362     }
   1363   if (n_ops == 3)
   1364     {
   1365       parse_regop (&regop, args[3], oP->operand[2]);
   1366       if (regop.special)
   1367 	regop.mode = regop.special;
   1368       instr |= (regop.n <<= 19) | (regop.mode <<= 13);
   1369     }
   1370   emit (instr);
   1371 }
   1372 
   1373 /* get_args:	break individual arguments out of comma-separated list
   1374 
   1375    Input assumptions:
   1376   	- all comments and labels have been removed
   1377   	- all strings of whitespace have been collapsed to a single blank.
   1378   	- all character constants ('x') have been replaced with decimal
   1379 
   1380    Output:
   1381   	args[0] is untouched. args[1] points to first operand, etc. All args:
   1382   	- are NULL-terminated
   1383   	- contain no whitespace
   1384 
   1385    Return value:
   1386    Number of operands (0,1,2, or 3) or -1 on error.  */
   1387 
   1388 static int
   1389 get_args (char *p, 	/* Pointer to comma-separated operands; Mucked by us.  */
   1390 	  char *args[]) /* Output arg: pointers to operands placed in args[1-3].
   1391 			   Must accommodate 4 entries (args[0-3]).  */
   1392 
   1393 {
   1394   int n;		/* Number of operands.  */
   1395   char *to;
   1396 
   1397   /* Skip lead white space.  */
   1398   while (*p == ' ')
   1399     p++;
   1400 
   1401   if (*p == '\0')
   1402     return 0;
   1403 
   1404   n = 1;
   1405   args[1] = p;
   1406 
   1407   /* Squeze blanks out by moving non-blanks toward start of string.
   1408      Isolate operands, whenever comma is found.  */
   1409   to = p;
   1410   while (*p != '\0')
   1411     {
   1412       if (*p == ' '
   1413 	  && (! ISALNUM (p[1])
   1414 	      || ! ISALNUM (p[-1])))
   1415 	p++;
   1416       else if (*p == ',')
   1417 	{
   1418 	  /* Start of operand.  */
   1419 	  if (n == 3)
   1420 	    {
   1421 	      as_bad (_("too many operands"));
   1422 	      return -1;
   1423 	    }
   1424 	  *to++ = '\0';		/* Terminate argument.  */
   1425 	  args[++n] = to;	/* Start next argument.  */
   1426 	  p++;
   1427 	}
   1428       else
   1429 	*to++ = *p++;
   1430     }
   1431   *to = '\0';
   1432   return n;
   1433 }
   1434 
   1435 /* i_scan:	perform lexical scan of ascii assembler instruction.
   1436 
   1437    Input assumptions:
   1438   	- input string is an i80960 instruction (not a pseudo-op)
   1439   	- all comments and labels have been removed
   1440   	- all strings of whitespace have been collapsed to a single blank.
   1441 
   1442    Output:
   1443   	args[0] points to opcode, other entries point to operands. All strings:
   1444   	- are NULL-terminated
   1445   	- contain no whitespace
   1446   	- have character constants ('x') replaced with a decimal number
   1447 
   1448    Return value:
   1449      Number of operands (0,1,2, or 3) or -1 on error.  */
   1450 
   1451 static int
   1452 i_scan (char *iP,     /* Pointer to ascii instruction;  Mucked by us.  */
   1453 	char *args[]) /* Output arg: pointers to opcode and operands placed here.
   1454 			 Must accommodate 4 entries.  */
   1455 {
   1456   /* Isolate opcode.  */
   1457   if (*(iP) == ' ')
   1458     iP++;
   1459 
   1460   args[0] = iP;
   1461   for (; *iP != ' '; iP++)
   1462     {
   1463       if (*iP == '\0')
   1464 	{
   1465 	  /* There are no operands.  */
   1466 	  if (args[0] == iP)
   1467 	    {
   1468 	      /* We never moved: there was no opcode either!  */
   1469 	      as_bad (_("missing opcode"));
   1470 	      return -1;
   1471 	    }
   1472 	  return 0;
   1473 	}
   1474     }
   1475   *iP++ = '\0';
   1476   return (get_args (iP, args));
   1477 }
   1478 
   1479 static void
   1480 brcnt_emit (void)
   1481 {
   1482   /* Emit call to "increment" routine.  */
   1483   ctrl_fmt (BR_CNT_FUNC, CALL, 1);
   1484   /* Emit inline counter to be incremented.  */
   1485   emit (0);
   1486 }
   1487 
   1488 static char *
   1489 brlab_next (void)
   1490 {
   1491   static char buf[20];
   1492 
   1493   sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
   1494   return buf;
   1495 }
   1496 
   1497 static void
   1498 ctrl_fmt (char *targP,		/* Pointer to text of lone operand (if any).  */
   1499 	  long opcode,		/* Template of instruction.  */
   1500 	  int num_ops)		/* Number of operands.  */
   1501 {
   1502   int instrument;		/* TRUE iff we should add instrumentation to track
   1503 				   how often the branch is taken.  */
   1504 
   1505   if (num_ops == 0)
   1506     emit (opcode);		/* Output opcode.  */
   1507   else
   1508     {
   1509       instrument = instrument_branches && (opcode != CALL)
   1510 	&& (opcode != B) && (opcode != RET) && (opcode != BAL);
   1511 
   1512       if (instrument)
   1513 	{
   1514 	  brcnt_emit ();
   1515 	  colon (brlab_next ());
   1516 	}
   1517 
   1518       /* The operand MUST be an ip-relative displacement. Parse it
   1519          and set up address fix for the instruction we just output.  */
   1520       get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
   1521 
   1522       if (instrument)
   1523 	brcnt_emit ();
   1524     }
   1525 }
   1526 
   1527 static void
   1528 cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
   1529 	  char *arg[],
   1530 	  /* Opcode, with branch-prediction bits already set if necessary.  */
   1531 	  long opcode,
   1532 	  /* Pointer to description of instruction.  */
   1533 	  struct i960_opcode *oP)
   1534 {
   1535   long instr;			/* 32-bit instruction.  */
   1536   struct regop regop;		/* Description of register operand.  */
   1537   int n;			/* Number of operands.  */
   1538   int var_frag;			/* 1 if varying length code fragment should
   1539 				     be emitted;  0 if an address fix
   1540 				        should be emitted.  */
   1541 
   1542   instr = opcode;
   1543   n = oP->num_ops;
   1544 
   1545   if (n >= 1)
   1546     {
   1547       /* First operand (if any) of a COBR is always a register
   1548 	 operand.  Parse it.  */
   1549       parse_regop (&regop, arg[1], oP->operand[0]);
   1550       instr |= (regop.n << 19) | (regop.mode << 13);
   1551     }
   1552 
   1553   if (n >= 2)
   1554     {
   1555       /* Second operand (if any) of a COBR is always a register
   1556 	 operand.  Parse it.  */
   1557       parse_regop (&regop, arg[2], oP->operand[1]);
   1558       instr |= (regop.n << 14) | regop.special;
   1559     }
   1560 
   1561   if (n < 3)
   1562     emit (instr);
   1563   else
   1564     {
   1565       if (instrument_branches)
   1566 	{
   1567 	  brcnt_emit ();
   1568 	  colon (brlab_next ());
   1569 	}
   1570 
   1571       /* A third operand to a COBR is always a displacement.  Parse
   1572          it; if it's relaxable (a cobr "j" directive, or any cobr
   1573          other than bbs/bbc when the "-norelax" option is not in use)
   1574          set up a variable code fragment; otherwise set up an address
   1575          fix.  */
   1576       var_frag = !norelax || (oP->format == COJ);	/* TRUE or FALSE */
   1577       get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
   1578 
   1579       if (instrument_branches)
   1580 	brcnt_emit ();
   1581     }
   1582 }
   1583 
   1584 /* Assumptions about the passed-in text:
   1585   	- all comments, labels removed
   1586   	- text is an instruction
   1587   	- all white space compressed to single blanks
   1588   	- all character constants have been replaced with decimal.  */
   1589 
   1590 void
   1591 md_assemble (char *textP)
   1592 {
   1593   /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
   1594      mnemonic arg[1-3]->operands, with char constants replaced by
   1595      decimal numbers.  */
   1596   char *args[4];
   1597   /* Number of instruction operands.  */
   1598   int n_ops;
   1599   /* Pointer to instruction description.  */
   1600   struct i960_opcode *oP;
   1601   /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
   1602      or ".t").  */
   1603   int branch_predict;
   1604   /* Setting of branch-prediction bit(s) to be OR'd into instruction
   1605      opcode of CTRL/COBR format instructions.  */
   1606   long bp_bits;
   1607   /* Offset of last character in opcode mnemonic.  */
   1608   int n;
   1609   const char *bp_error_msg = _("branch prediction invalid on this opcode");
   1610 
   1611   /* Parse instruction into opcode and operands.  */
   1612   memset (args, '\0', sizeof (args));
   1613 
   1614   n_ops = i_scan (textP, args);
   1615 
   1616   if (n_ops == -1)
   1617     return;			/* Error message already issued.  */
   1618 
   1619   /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction.  */
   1620   if (!strcmp (args[0], "ldconst"))
   1621     {
   1622       n_ops = parse_ldconst (args);
   1623       if (n_ops == -1)
   1624 	return;
   1625     }
   1626 
   1627   /* Check for branch-prediction suffix on opcode mnemonic, strip it off.  */
   1628   n = strlen (args[0]) - 1;
   1629   branch_predict = 0;
   1630   bp_bits = 0;
   1631 
   1632   if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
   1633     {
   1634       /* We could check here to see if the target architecture
   1635 	 supports branch prediction, but why bother?  The bit will
   1636 	 just be ignored by processors that don't use it.  */
   1637       branch_predict = 1;
   1638       bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
   1639       args[0][n - 1] = '\0';	/* Strip suffix from opcode mnemonic */
   1640     }
   1641 
   1642   /* Look up opcode mnemonic in table and check number of operands.
   1643      Check that opcode is legal for the target architecture.  If all
   1644      looks good, assemble instruction.  */
   1645   oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
   1646   if (!oP || !targ_has_iclass (oP->iclass))
   1647     as_bad (_("invalid opcode, \"%s\"."), args[0]);
   1648   else if (n_ops != oP->num_ops)
   1649     as_bad (_("improper number of operands.  expecting %d, got %d"),
   1650 	    oP->num_ops, n_ops);
   1651   else
   1652     {
   1653       switch (oP->format)
   1654 	{
   1655 	case FBRA:
   1656 	case CTRL:
   1657 	  ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
   1658 	  if (oP->format == FBRA)
   1659 	    /* Now generate a 'bno' to same arg */
   1660 	    ctrl_fmt (args[1], BNO | bp_bits, 1);
   1661 	  break;
   1662 	case COBR:
   1663 	case COJ:
   1664 	  cobr_fmt (args, oP->opcode | bp_bits, oP);
   1665 	  break;
   1666 	case REG:
   1667 	  if (branch_predict)
   1668 	    as_warn ("%s", bp_error_msg);
   1669 	  reg_fmt (args, oP);
   1670 	  break;
   1671 	case MEM1:
   1672 	  if (args[0][0] == 'c' && args[0][1] == 'a')
   1673 	    {
   1674 	      if (branch_predict)
   1675 		as_warn ("%s", bp_error_msg);
   1676 	      mem_fmt (args, oP, 1);
   1677 	      break;
   1678 	    }
   1679 	case MEM2:
   1680 	case MEM4:
   1681 	case MEM8:
   1682 	case MEM12:
   1683 	case MEM16:
   1684 	  if (branch_predict)
   1685 	    as_warn ("%s", bp_error_msg);
   1686 	  mem_fmt (args, oP, 0);
   1687 	  break;
   1688 	case CALLJ:
   1689 	  if (branch_predict)
   1690 	    as_warn ("%s", bp_error_msg);
   1691 	  /* Output opcode & set up "fixup" (relocation); flag
   1692 	     relocation as 'callj' type.  */
   1693 	  know (oP->num_ops == 1);
   1694 	  get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
   1695 	  break;
   1696 	default:
   1697 	  BAD_CASE (oP->format);
   1698 	  break;
   1699 	}
   1700     }
   1701 }
   1702 
   1703 void
   1704 md_number_to_chars (char *buf,
   1705 		    valueT value,
   1706 		    int n)
   1707 {
   1708   number_to_chars_littleendian (buf, value, n);
   1709 }
   1710 
   1711 char *
   1712 md_atof (int type, char *litP, int *sizeP)
   1713 {
   1714   return ieee_md_atof (type, litP, sizeP, FALSE);
   1715 }
   1716 
   1717 static void
   1718 md_number_to_imm (char *buf, long val, int n)
   1719 {
   1720   md_number_to_chars (buf, val, n);
   1721 }
   1722 
   1723 static void
   1724 md_number_to_field (char *instrP,		/* Pointer to instruction to be fixed.  */
   1725 		    long val,			/* Address fixup value.  */
   1726 		    bit_fixS *bfixP)		/* Description of bit field to be fixed up.  */
   1727 {
   1728   int numbits;			/* Length of bit field to be fixed.  */
   1729   long instr;			/* 32-bit instruction to be fixed-up.  */
   1730   long sign;			/* 0 or -1, according to sign bit of 'val'.  */
   1731 
   1732   /* Convert instruction back to host byte order.  */
   1733   instr = md_chars_to_number (instrP, 4);
   1734 
   1735   /* Surprise! -- we stored the number of bits to be modified rather
   1736      than a pointer to a structure.  */
   1737   numbits = (int) (size_t) bfixP;
   1738   if (numbits == 1)
   1739     /* This is a no-op, stuck here by reloc_callj().  */
   1740     return;
   1741 
   1742   know ((numbits == 13) || (numbits == 24));
   1743 
   1744   /* Propagate sign bit of 'val' for the given number of bits.  Result
   1745      should be all 0 or all 1.  */
   1746   sign = val >> ((int) numbits - 1);
   1747   if (((val < 0) && (sign != -1))
   1748       || ((val > 0) && (sign != 0)))
   1749     as_bad (_("Fixup of %ld too large for field width of %d"),
   1750 	    val, numbits);
   1751   else
   1752     {
   1753       /* Put bit field into instruction and write back in target
   1754          * byte order.  */
   1755       val &= ~(-1 << (int) numbits);	/* Clear unused sign bits.  */
   1756       instr |= val;
   1757       md_number_to_chars (instrP, instr, 4);
   1758     }
   1759 }
   1760 
   1761 
   1763 /* md_parse_option
   1764   	Invocation line includes a switch not recognized by the base assembler.
   1765   	See if it's a processor-specific option.  For the 960, these are:
   1766 
   1767   	-norelax:
   1768   		Conditional branch instructions that require displacements
   1769   		greater than 13 bits (or that have external targets) should
   1770   		generate errors.  The default is to replace each such
   1771   		instruction with the corresponding compare (or chkbit) and
   1772   		branch instructions.  Note that the Intel "j" cobr directives
   1773   		are ALWAYS "de-optimized" in this way when necessary,
   1774   		regardless of the setting of this option.
   1775 
   1776   	-b:
   1777   		Add code to collect information about branches taken, for
   1778   		later optimization of branch prediction bits by a separate
   1779   		tool.  COBR and CNTL format instructions have branch
   1780   		prediction bits (in the CX architecture);  if "BR" represents
   1781   		an instruction in one of these classes, the following rep-
   1782   		resents the code generated by the assembler:
   1783 
   1784   			call	<increment routine>
   1785   			.word	0	# pre-counter
   1786   		Label:  BR
   1787   			call	<increment routine>
   1788   			.word	0	# post-counter
   1789 
   1790   		A table of all such "Labels" is also generated.
   1791 
   1792   	-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
   1793   		Select the 80960 architecture.  Instructions or features not
   1794   		supported by the selected architecture cause fatal errors.
   1795   		The default is to generate code for any instruction or feature
   1796   		that is supported by SOME version of the 960 (even if this
   1797   		means mixing architectures!).  */
   1798 
   1799 const char *md_shortopts = "A:b";
   1800 struct option md_longopts[] =
   1801 {
   1802 #define OPTION_LINKRELAX (OPTION_MD_BASE)
   1803   {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
   1804   {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
   1805 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
   1806   {"norelax", no_argument, NULL, OPTION_NORELAX},
   1807   {"no-relax", no_argument, NULL, OPTION_NORELAX},
   1808   {NULL, no_argument, NULL, 0}
   1809 };
   1810 size_t md_longopts_size = sizeof (md_longopts);
   1811 
   1812 struct tabentry
   1813 {
   1814   char *flag;
   1815   int arch;
   1816 };
   1817 static const struct tabentry arch_tab[] =
   1818 {
   1819   {"KA", ARCH_KA},
   1820   {"KB", ARCH_KB},
   1821   {"SA", ARCH_KA},		/* Synonym for KA.  */
   1822   {"SB", ARCH_KB},		/* Synonym for KB.  */
   1823   {"KC", ARCH_MC},		/* Synonym for MC.  */
   1824   {"MC", ARCH_MC},
   1825   {"CA", ARCH_CA},
   1826   {"JX", ARCH_JX},
   1827   {"HX", ARCH_HX},
   1828   {NULL, 0}
   1829 };
   1830 
   1831 int
   1832 md_parse_option (int c, char *arg)
   1833 {
   1834   switch (c)
   1835     {
   1836     case OPTION_LINKRELAX:
   1837       linkrelax = 1;
   1838       flag_keep_locals = 1;
   1839       break;
   1840 
   1841     case OPTION_NORELAX:
   1842       norelax = 1;
   1843       break;
   1844 
   1845     case 'b':
   1846       instrument_branches = 1;
   1847       break;
   1848 
   1849     case 'A':
   1850       {
   1851 	const struct tabentry *tp;
   1852 	char *p = arg;
   1853 
   1854 	for (tp = arch_tab; tp->flag != NULL; tp++)
   1855 	  if (!strcmp (p, tp->flag))
   1856 	    break;
   1857 
   1858 	if (tp->flag == NULL)
   1859 	  {
   1860 	    as_bad (_("invalid architecture %s"), p);
   1861 	    return 0;
   1862 	  }
   1863 	else
   1864 	  architecture = tp->arch;
   1865       }
   1866       break;
   1867 
   1868     default:
   1869       return 0;
   1870     }
   1871 
   1872   return 1;
   1873 }
   1874 
   1875 void
   1876 md_show_usage (FILE *stream)
   1877 {
   1878   int i;
   1879 
   1880   fprintf (stream, _("I960 options:\n"));
   1881   for (i = 0; arch_tab[i].flag; i++)
   1882     fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
   1883   fprintf (stream, _("\n\
   1884 			specify variant of 960 architecture\n\
   1885 -b			add code to collect statistics about branches taken\n\
   1886 -link-relax		preserve individual alignment directives so linker\n\
   1887 			can do relaxing (b.out format only)\n\
   1888 -no-relax		don't alter compare-and-branch instructions for\n\
   1889 			long displacements\n"));
   1890 }
   1891 
   1892 /* relax_cobr:
   1894    Replace cobr instruction in a code fragment with equivalent branch and
   1895    compare instructions, so it can reach beyond a 13-bit displacement.
   1896    Set up an address fix/relocation for the new branch instruction.  */
   1897 
   1898 /* This "conditional jump" table maps cobr instructions into
   1899    equivalent compare and branch opcodes.  */
   1900 
   1901 static const
   1902 struct
   1903 {
   1904   long compare;
   1905   long branch;
   1906 }
   1907 
   1908 coj[] =
   1909 {				/* COBR OPCODE: */
   1910   { CHKBIT, BNO },		/*      0x30 - bbc */
   1911   { CMPO, BG },			/*      0x31 - cmpobg */
   1912   { CMPO, BE },			/*      0x32 - cmpobe */
   1913   { CMPO, BGE },		/*      0x33 - cmpobge */
   1914   { CMPO, BL },			/*      0x34 - cmpobl */
   1915   { CMPO, BNE },		/*      0x35 - cmpobne */
   1916   { CMPO, BLE },		/*      0x36 - cmpoble */
   1917   { CHKBIT, BO },		/*      0x37 - bbs */
   1918   { CMPI, BNO },		/*      0x38 - cmpibno */
   1919   { CMPI, BG },			/*      0x39 - cmpibg */
   1920   { CMPI, BE },			/*      0x3a - cmpibe */
   1921   { CMPI, BGE },		/*      0x3b - cmpibge */
   1922   { CMPI, BL },			/*      0x3c - cmpibl */
   1923   { CMPI, BNE },		/*      0x3d - cmpibne */
   1924   { CMPI, BLE },		/*      0x3e - cmpible */
   1925   { CMPI, BO },			/*      0x3f - cmpibo */
   1926 };
   1927 
   1928 static void
   1929 relax_cobr (fragS *fragP)	/* fragP->fr_opcode is assumed to point to
   1930 				   the cobr instruction, which comes at the
   1931 				   end of the code fragment.  */
   1932 {
   1933   int opcode, src1, src2, m1, s2;
   1934   /* Bit fields from cobr instruction.  */
   1935   long bp_bits;			/* Branch prediction bits from cobr instruction.  */
   1936   long instr;			/* A single i960 instruction.  */
   1937   /* ->instruction to be replaced.  */
   1938   char *iP;
   1939   fixS *fixP;			/* Relocation that can be done at assembly time.  */
   1940 
   1941   /* Pick up & parse cobr instruction.  */
   1942   iP = fragP->fr_opcode;
   1943   instr = md_chars_to_number (iP, 4);
   1944   opcode = ((instr >> 24) & 0xff) - 0x30;	/* "-0x30" for table index.  */
   1945   src1 = (instr >> 19) & 0x1f;
   1946   m1 = (instr >> 13) & 1;
   1947   s2 = instr & 1;
   1948   src2 = (instr >> 14) & 0x1f;
   1949   bp_bits = instr & BP_MASK;
   1950 
   1951   /* Generate and output compare instruction.  */
   1952   instr = coj[opcode].compare
   1953     | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
   1954   md_number_to_chars (iP, instr, 4);
   1955 
   1956   /* Output branch instruction.  */
   1957   md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
   1958 
   1959   /* Set up address fixup/relocation.  */
   1960   fixP = fix_new (fragP,
   1961 		  iP + 4 - fragP->fr_literal,
   1962 		  4,
   1963 		  fragP->fr_symbol,
   1964 		  fragP->fr_offset,
   1965 		  1,
   1966 		  NO_RELOC);
   1967 
   1968   fixP->fx_bit_fixP = (bit_fixS *) 24;	/* Store size of bit field.  */
   1969 
   1970   fragP->fr_fix += 4;
   1971   frag_wane (fragP);
   1972 }
   1973 
   1974 /* md_convert_frag:
   1975 
   1976    Called by base assembler after address relaxation is finished:  modify
   1977    variable fragments according to how much relaxation was done.
   1978 
   1979    If the fragment substate is still 1, a 13-bit displacement was enough
   1980    to reach the symbol in question.  Set up an address fixup, but otherwise
   1981    leave the cobr instruction alone.
   1982 
   1983    If the fragment substate is 2, a 13-bit displacement was not enough.
   1984    Replace the cobr with a two instructions (a compare and a branch).  */
   1985 
   1986 void
   1987 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
   1988 		 segT sec ATTRIBUTE_UNUSED,
   1989 		 fragS *fragP)
   1990 {
   1991   /* Structure describing needed address fix.  */
   1992   fixS *fixP;
   1993 
   1994   switch (fragP->fr_subtype)
   1995     {
   1996     case 1:
   1997       /* Leave single cobr instruction.  */
   1998       fixP = fix_new (fragP,
   1999 		      fragP->fr_opcode - fragP->fr_literal,
   2000 		      4,
   2001 		      fragP->fr_symbol,
   2002 		      fragP->fr_offset,
   2003 		      1,
   2004 		      NO_RELOC);
   2005 
   2006       fixP->fx_bit_fixP = (bit_fixS *) 13;	/* Size of bit field.  */
   2007       break;
   2008     case 2:
   2009       /* Replace cobr with compare/branch instructions.  */
   2010       relax_cobr (fragP);
   2011       break;
   2012     default:
   2013       BAD_CASE (fragP->fr_subtype);
   2014       break;
   2015     }
   2016 }
   2017 
   2018 /* md_estimate_size_before_relax:  How much does it look like *fragP will grow?
   2019 
   2020    Called by base assembler just before address relaxation.
   2021    Return the amount by which the fragment will grow.
   2022 
   2023    Any symbol that is now undefined will not become defined; cobr's
   2024    based on undefined symbols will have to be replaced with a compare
   2025    instruction and a branch instruction, and the code fragment will grow
   2026    by 4 bytes.  */
   2027 
   2028 int
   2029 md_estimate_size_before_relax (fragS *fragP, segT segment_type)
   2030 {
   2031   /* If symbol is undefined in this segment, go to "relaxed" state
   2032      (compare and branch instructions instead of cobr) right now.  */
   2033   if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
   2034     {
   2035       relax_cobr (fragP);
   2036       return 4;
   2037     }
   2038 
   2039   return md_relax_table[fragP->fr_subtype].rlx_length;
   2040 }
   2041 
   2042 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
   2043 
   2044 /* md_ri_to_chars:
   2045    This routine exists in order to overcome machine byte-order problems
   2046    when dealing with bit-field entries in the relocation_info struct.
   2047 
   2048    But relocation info will be used on the host machine only (only
   2049    executable code is actually downloaded to the i80960).  Therefore,
   2050    we leave it in host byte order.  */
   2051 
   2052 static void
   2053 md_ri_to_chars (char *where, struct relocation_info *ri)
   2054 {
   2055   host_number_to_chars (where, ri->r_address, 4);
   2056   host_number_to_chars (where + 4, ri->r_index, 3);
   2057 #if WORDS_BIGENDIAN
   2058   where[7] = (ri->r_pcrel << 7
   2059 	      | ri->r_length << 5
   2060 	      | ri->r_extern << 4
   2061 	      | ri->r_bsr << 3
   2062 	      | ri->r_disp << 2
   2063 	      | ri->r_callj << 1
   2064 	      | ri->nuthin << 0);
   2065 #else
   2066   where[7] = (ri->r_pcrel << 0
   2067 	      | ri->r_length << 1
   2068 	      | ri->r_extern << 3
   2069 	      | ri->r_bsr << 4
   2070 	      | ri->r_disp << 5
   2071 	      | ri->r_callj << 6
   2072 	      | ri->nuthin << 7);
   2073 #endif
   2074 }
   2075 
   2076 #endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
   2077 
   2078 
   2079 /* brtab_emit:	generate the fetch-prediction branch table.
   2081 
   2082    See the comments above the declaration of 'br_cnt' for details on
   2083    branch-prediction instrumentation.
   2084 
   2085    The code emitted here would be functionally equivalent to the following
   2086    example assembler source.
   2087 
   2088   			.data
   2089   			.align	2
   2090   	   BR_TAB_NAME:
   2091   			.word	0		# link to next table
   2092   			.word	3		# length of table
   2093   			.word	LBRANCH0	# 1st entry in table proper
   2094   			.word	LBRANCH1
   2095   			.word	LBRANCH2  */
   2096 
   2097 void
   2098 brtab_emit (void)
   2099 {
   2100   int i;
   2101   char buf[20];
   2102   /* Where the binary was output to.  */
   2103   char *p;
   2104 
   2105   if (!instrument_branches)
   2106     return;
   2107 
   2108   subseg_set (data_section, 0);	/*      .data */
   2109   frag_align (2, 0, 0);		/*      .align 2 */
   2110   record_alignment (now_seg, 2);
   2111   colon (BR_TAB_NAME);		/* BR_TAB_NAME: */
   2112   emit (0);			/*      .word 0 #link to next table */
   2113   emit (br_cnt);		/*      .word n #length of table */
   2114 
   2115   for (i = 0; i < br_cnt; i++)
   2116     {
   2117       sprintf (buf, "%s%d", BR_LABEL_BASE, i);
   2118       p = emit (0);
   2119       fix_new (frag_now,
   2120 	       p - frag_now->fr_literal,
   2121 	       4, symbol_find (buf), 0, 0, NO_RELOC);
   2122     }
   2123 }
   2124 
   2125 /* s_leafproc:	process .leafproc pseudo-op
   2126 
   2127   	.leafproc takes two arguments, the second one is optional:
   2128   		arg[1]: name of 'call' entry point to leaf procedure
   2129   		arg[2]: name of 'bal' entry point to leaf procedure
   2130 
   2131   	If the two arguments are identical, or if the second one is missing,
   2132   	the first argument is taken to be the 'bal' entry point.
   2133 
   2134   	If there are 2 distinct arguments, we must make sure that the 'bal'
   2135   	entry point immediately follows the 'call' entry point in the linked
   2136   	list of symbols.  */
   2137 
   2138 static void
   2139 s_leafproc (int n_ops,		/* Number of operands.  */
   2140 	    char *args[])	/* args[1]->1st operand, args[2]->2nd operand.  */
   2141 {
   2142   symbolS *callP;		/* Pointer to leafproc 'call' entry point symbol.  */
   2143   symbolS *balP;		/* Pointer to leafproc 'bal' entry point symbol.  */
   2144 
   2145   if ((n_ops != 1) && (n_ops != 2))
   2146     {
   2147       as_bad (_("should have 1 or 2 operands"));
   2148       return;
   2149     }
   2150 
   2151   /* Find or create symbol for 'call' entry point.  */
   2152   callP = symbol_find_or_make (args[1]);
   2153 
   2154   if (TC_S_IS_CALLNAME (callP))
   2155     as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
   2156 
   2157   /* If that was the only argument, use it as the 'bal' entry point.
   2158      Otherwise, mark it as the 'call' entry point and find or create
   2159      another symbol for the 'bal' entry point.  */
   2160   if ((n_ops == 1) || !strcmp (args[1], args[2]))
   2161     {
   2162       TC_S_FORCE_TO_BALNAME (callP);
   2163     }
   2164   else
   2165     {
   2166       TC_S_FORCE_TO_CALLNAME (callP);
   2167 
   2168       balP = symbol_find_or_make (args[2]);
   2169       if (TC_S_IS_CALLNAME (balP))
   2170 	as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
   2171 
   2172       TC_S_FORCE_TO_BALNAME (balP);
   2173 
   2174 #ifndef OBJ_ELF
   2175       tc_set_bal_of_call (callP, balP);
   2176 #endif
   2177     }
   2178 }
   2179 
   2180 /* s_sysproc: process .sysproc pseudo-op
   2181 
   2182    .sysproc takes two arguments:
   2183      arg[1]: name of entry point to system procedure
   2184      arg[2]: 'entry_num' (index) of system procedure in the range
   2185      [0,31] inclusive.
   2186 
   2187    For [ab].out, we store the 'entrynum' in the 'n_other' field of
   2188    the symbol.  Since that entry is normally 0, we bias 'entrynum'
   2189    by adding 1 to it.  It must be unbiased before it is used.  */
   2190 
   2191 static void
   2192 s_sysproc (int n_ops,		/* Number of operands.  */
   2193 	   char *args[])	/* args[1]->1st operand, args[2]->2nd operand.  */
   2194 {
   2195   expressionS exp;
   2196   symbolS *symP;
   2197 
   2198   if (n_ops != 2)
   2199     {
   2200       as_bad (_("should have two operands"));
   2201       return;
   2202     }
   2203 
   2204   /* Parse "entry_num" argument and check it for validity.  */
   2205   parse_expr (args[2], &exp);
   2206   if (exp.X_op != O_constant
   2207       || (offs (exp) < 0)
   2208       || (offs (exp) > 31))
   2209     {
   2210       as_bad (_("'entry_num' must be absolute number in [0,31]"));
   2211       return;
   2212     }
   2213 
   2214   /* Find/make symbol and stick entry number (biased by +1) into it.  */
   2215   symP = symbol_find_or_make (args[1]);
   2216 
   2217   if (TC_S_IS_SYSPROC (symP))
   2218     as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
   2219 
   2220   TC_S_SET_SYSPROC (symP, offs (exp));	/* Encode entry number.  */
   2221   TC_S_FORCE_TO_SYSPROC (symP);
   2222 }
   2223 
   2224 /* parse_po:	parse machine-dependent pseudo-op
   2225 
   2226    This is a top-level routine for machine-dependent pseudo-ops.  It slurps
   2227    up the rest of the input line, breaks out the individual arguments,
   2228    and dispatches them to the correct handler.  */
   2229 
   2230 static void
   2231 parse_po (int po_num)	/* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC.  */
   2232 {
   2233   /* Pointers operands, with no embedded whitespace.
   2234      arg[0] unused, arg[1-3]->operands.  */
   2235   char *args[4];
   2236   int n_ops;			/* Number of operands.  */
   2237   char *p;			/* Pointer to beginning of unparsed argument string.  */
   2238   char eol;			/* Character that indicated end of line.  */
   2239 
   2240   extern char is_end_of_line[];
   2241 
   2242   /* Advance input pointer to end of line.  */
   2243   p = input_line_pointer;
   2244   while (!is_end_of_line[(unsigned char) *input_line_pointer])
   2245     input_line_pointer++;
   2246 
   2247   eol = *input_line_pointer;	/* Save end-of-line char.  */
   2248   *input_line_pointer = '\0';	/* Terminate argument list.  */
   2249 
   2250   /* Parse out operands.  */
   2251   n_ops = get_args (p, args);
   2252   if (n_ops == -1)
   2253     return;
   2254 
   2255   /* Dispatch to correct handler.  */
   2256   switch (po_num)
   2257     {
   2258     case S_SYSPROC:
   2259       s_sysproc (n_ops, args);
   2260       break;
   2261     case S_LEAFPROC:
   2262       s_leafproc (n_ops, args);
   2263       break;
   2264     default:
   2265       BAD_CASE (po_num);
   2266       break;
   2267     }
   2268 
   2269   /* Restore eol, so line numbers get updated correctly.  Base
   2270      assembler assumes we leave input pointer pointing at char
   2271      following the eol.  */
   2272   *input_line_pointer++ = eol;
   2273 }
   2274 
   2275 /* reloc_callj:	Relocate a 'callj' instruction
   2276 
   2277   	This is a "non-(GNU)-standard" machine-dependent hook.  The base
   2278   	assembler calls it when it decides it can relocate an address at
   2279   	assembly time instead of emitting a relocation directive.
   2280 
   2281   	Check to see if the relocation involves a 'callj' instruction to a:
   2282   	    sysproc:	Replace the default 'call' instruction with a 'calls'
   2283   	    leafproc:	Replace the default 'call' instruction with a 'bal'.
   2284   	    other proc:	Do nothing.
   2285 
   2286   	See b.out.h for details on the 'n_other' field in a symbol structure.
   2287 
   2288    IMPORTANT!:
   2289   	Assumes the caller has already figured out, in the case of a leafproc,
   2290   	to use the 'bal' entry point, and has substituted that symbol into the
   2291   	passed fixup structure.  */
   2292 
   2293 int
   2294 reloc_callj (fixS *fixP)  /* Relocation that can be done at assembly time.  */
   2295 {
   2296   /* Points to the binary for the instruction being relocated.  */
   2297   char *where;
   2298 
   2299   if (!fixP->fx_tcbit)
   2300     /* This wasn't a callj instruction in the first place.  */
   2301     return 0;
   2302 
   2303   where = fixP->fx_frag->fr_literal + fixP->fx_where;
   2304 
   2305   if (TC_S_IS_SYSPROC (fixP->fx_addsy))
   2306     {
   2307       /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
   2308          procedure number is (other-1).  */
   2309       md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
   2310 
   2311       /* Nothing else needs to be done for this instruction.  Make
   2312          sure 'md_number_to_field()' will perform a no-op.  */
   2313       fixP->fx_bit_fixP = (bit_fixS *) 1;
   2314     }
   2315   else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
   2316     {
   2317       /* Should not happen: see block comment above.  */
   2318       as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
   2319     }
   2320   else if (TC_S_IS_BALNAME (fixP->fx_addsy))
   2321     {
   2322       /* Replace 'call' with 'bal'; both instructions have the same
   2323          format, so calling code should complete relocation as if
   2324          nothing happened here.  */
   2325       md_number_to_chars (where, BAL, 4);
   2326     }
   2327   else if (TC_S_IS_BADPROC (fixP->fx_addsy))
   2328     as_bad (_("Looks like a proc, but can't tell what kind.\n"));
   2329 
   2330   /* Otherwise Symbol is neither a sysproc nor a leafproc.  */
   2331   return 0;
   2332 }
   2333 
   2334 /* Handle the MRI .endian pseudo-op.  */
   2335 
   2336 static void
   2337 s_endian (int ignore ATTRIBUTE_UNUSED)
   2338 {
   2339   char *name;
   2340   char c;
   2341 
   2342   name = input_line_pointer;
   2343   c = get_symbol_end ();
   2344   if (strcasecmp (name, "little") == 0)
   2345     ;
   2346   else if (strcasecmp (name, "big") == 0)
   2347     as_bad (_("big endian mode is not supported"));
   2348   else
   2349     as_warn (_("ignoring unrecognized .endian type `%s'"), name);
   2350 
   2351   *input_line_pointer = c;
   2352 
   2353   demand_empty_rest_of_line ();
   2354 }
   2355 
   2356 /* We have no need to default values of symbols.  */
   2357 
   2358 symbolS *
   2359 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
   2360 {
   2361   return 0;
   2362 }
   2363 
   2364 /* Exactly what point is a PC-relative offset relative TO?
   2365    On the i960, they're relative to the address of the instruction,
   2366    which we have set up as the address of the fixup too.  */
   2367 long
   2368 md_pcrel_from (fixS *fixP)
   2369 {
   2370   return fixP->fx_where + fixP->fx_frag->fr_address;
   2371 }
   2372 
   2373 void
   2374 md_apply_fix (fixS *fixP,
   2375 	       valueT *valP,
   2376 	       segT seg ATTRIBUTE_UNUSED)
   2377 {
   2378   long val = *valP;
   2379   char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
   2380 
   2381   if (!fixP->fx_bit_fixP)
   2382     {
   2383       md_number_to_imm (place, val, fixP->fx_size);
   2384     }
   2385   else if ((int) (size_t) fixP->fx_bit_fixP == 13
   2386 	   && fixP->fx_addsy != NULL
   2387 	   && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
   2388     {
   2389       /* This is a COBR instruction.  They have only a
   2390 	 13-bit displacement and are only to be used
   2391 	 for local branches: flag as error, don't generate
   2392 	 relocation.  */
   2393       as_bad_where (fixP->fx_file, fixP->fx_line,
   2394 		    _("can't use COBR format with external label"));
   2395       fixP->fx_addsy = NULL;
   2396     }
   2397   else
   2398     md_number_to_field (place, val, fixP->fx_bit_fixP);
   2399 
   2400   if (fixP->fx_addsy == NULL)
   2401     fixP->fx_done = 1;
   2402 }
   2403 
   2404 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
   2405 void
   2406 tc_bout_fix_to_chars (char *where,
   2407 		      fixS *fixP,
   2408 		      relax_addressT segment_address_in_file)
   2409 {
   2410   static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
   2411   struct relocation_info ri;
   2412   symbolS *symbolP;
   2413 
   2414   memset ((char *) &ri, '\0', sizeof (ri));
   2415   symbolP = fixP->fx_addsy;
   2416   know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
   2417   ri.r_bsr = fixP->fx_bsr;	/*SAC LD RELAX HACK */
   2418   /* These two 'cuz of NS32K */
   2419   ri.r_callj = fixP->fx_tcbit;
   2420   if (fixP->fx_bit_fixP)
   2421     ri.r_length = 2;
   2422   else
   2423     ri.r_length = nbytes_r_length[fixP->fx_size];
   2424   ri.r_pcrel = fixP->fx_pcrel;
   2425   ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
   2426 
   2427   if (fixP->fx_r_type != NO_RELOC)
   2428     {
   2429       switch (fixP->fx_r_type)
   2430 	{
   2431 	case rs_align:
   2432 	  ri.r_index = -2;
   2433 	  ri.r_pcrel = 1;
   2434 	  ri.r_length = fixP->fx_size - 1;
   2435 	  break;
   2436 	case rs_org:
   2437 	  ri.r_index = -2;
   2438 	  ri.r_pcrel = 0;
   2439 	  break;
   2440 	case rs_fill:
   2441 	  ri.r_index = -1;
   2442 	  break;
   2443 	default:
   2444 	  abort ();
   2445 	}
   2446       ri.r_extern = 0;
   2447     }
   2448   else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
   2449     {
   2450       ri.r_extern = 1;
   2451       ri.r_index = symbolP->sy_number;
   2452     }
   2453   else
   2454     {
   2455       ri.r_extern = 0;
   2456       ri.r_index = S_GET_TYPE (symbolP);
   2457     }
   2458 
   2459   /* Output the relocation information in machine-dependent form.  */
   2460   md_ri_to_chars (where, &ri);
   2461 }
   2462 
   2463 #endif /* OBJ_AOUT or OBJ_BOUT */
   2464 
   2465 /* Align an address by rounding it up to the specified boundary.  */
   2466 
   2467 valueT
   2468 md_section_align (segT seg,
   2469 		  valueT addr)		/* Address to be rounded up.  */
   2470 {
   2471   int align;
   2472 
   2473   align = bfd_get_section_alignment (stdoutput, seg);
   2474   return (addr + (1 << align) - 1) & (-1 << align);
   2475 }
   2476 
   2477 extern int coff_flags;
   2478 
   2479 /* For aout or bout, the bal immediately follows the call.
   2480 
   2481    For coff, we cheat and store a pointer to the bal symbol in the
   2482    second aux entry of the call.  */
   2483 
   2484 #undef OBJ_ABOUT
   2485 #ifdef OBJ_AOUT
   2486 #define OBJ_ABOUT
   2487 #endif
   2488 #ifdef OBJ_BOUT
   2489 #define OBJ_ABOUT
   2490 #endif
   2491 
   2492 void
   2493 tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED,
   2494 		    symbolS *balP ATTRIBUTE_UNUSED)
   2495 {
   2496   know (TC_S_IS_CALLNAME (callP));
   2497   know (TC_S_IS_BALNAME (balP));
   2498 
   2499 #ifdef OBJ_COFF
   2500 
   2501   callP->sy_tc = balP;
   2502   S_SET_NUMBER_AUXILIARY (callP, 2);
   2503 
   2504 #else /* ! OBJ_COFF */
   2505 #ifdef OBJ_ABOUT
   2506 
   2507   /* If the 'bal' entry doesn't immediately follow the 'call'
   2508      symbol, unlink it from the symbol list and re-insert it.  */
   2509   if (symbol_next (callP) != balP)
   2510     {
   2511       symbol_remove (balP, &symbol_rootP, &symbol_lastP);
   2512       symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
   2513     }				/* if not in order */
   2514 
   2515 #else /* ! OBJ_ABOUT */
   2516   as_fatal ("Only supported for a.out, b.out, or COFF");
   2517 #endif /* ! OBJ_ABOUT */
   2518 #endif /* ! OBJ_COFF */
   2519 }
   2520 
   2521 symbolS *
   2522 tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED)
   2523 {
   2524   symbolS *retval;
   2525 
   2526   know (TC_S_IS_CALLNAME (callP));
   2527 
   2528 #ifdef OBJ_COFF
   2529   retval = callP->sy_tc;
   2530 #else
   2531 #ifdef OBJ_ABOUT
   2532   retval = symbol_next (callP);
   2533 #else
   2534   as_fatal ("Only supported for a.out, b.out, or COFF");
   2535 #endif /* ! OBJ_ABOUT */
   2536 #endif /* ! OBJ_COFF */
   2537 
   2538   know (TC_S_IS_BALNAME (retval));
   2539   return retval;
   2540 }
   2541 
   2542 #ifdef OBJ_COFF
   2543 void
   2544 tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED)
   2545 {
   2546   if (TC_S_IS_CALLNAME (symbolP))
   2547     {
   2548       symbolS *balP = tc_get_bal_of_call (symbolP);
   2549 
   2550       symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
   2551       if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
   2552 	S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
   2553       else
   2554 	S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
   2555       S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
   2556       /* Fix up the bal symbol.  */
   2557       S_SET_STORAGE_CLASS (balP, C_LABEL);
   2558     }
   2559 }
   2560 #endif /* OBJ_COFF */
   2561 
   2562 void
   2563 i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED)
   2564 {
   2565   if (!linkrelax)
   2566     return;
   2567 
   2568 #ifndef OBJ_BOUT
   2569   as_bad (_("option --link-relax is only supported in b.out format"));
   2570   linkrelax = 0;
   2571   return;
   2572 #else
   2573 
   2574   /* The text section "ends" with another alignment reloc, to which we
   2575      aren't adding padding.  */
   2576   if (fragp->fr_next == text_last_frag
   2577       || fragp->fr_next == data_last_frag)
   2578     return;
   2579 
   2580   /* alignment directive */
   2581   fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
   2582 	   (int) fragp->fr_type);
   2583 #endif /* OBJ_BOUT */
   2584 }
   2585 
   2586 int
   2587 i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED)
   2588 {
   2589   if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
   2590     {
   2591       /* Relocation should be done via the associated 'bal'
   2592          entry point symbol.  */
   2593       if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
   2594 	{
   2595 	  as_bad_where (fixP->fx_file, fixP->fx_line,
   2596 			_("No 'bal' entry point for leafproc %s"),
   2597 			S_GET_NAME (fixP->fx_addsy));
   2598 	  return 0;
   2599 	}
   2600       fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
   2601     }
   2602 
   2603   return 1;
   2604 }
   2605 
   2606 /* From cgen.c:  */
   2607 
   2608 static short
   2609 tc_bfd_fix2rtype (fixS *fixP)
   2610 {
   2611   if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
   2612     return BFD_RELOC_32;
   2613 
   2614   if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
   2615     return BFD_RELOC_24_PCREL;
   2616 
   2617   abort ();
   2618   return 0;
   2619 }
   2620 
   2621 /* Translate internal representation of relocation info to BFD target
   2622    format.
   2623 
   2624    FIXME: To what extent can we get all relevant targets to use this?  */
   2625 
   2626 arelent *
   2627 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
   2628 {
   2629   arelent * reloc;
   2630 
   2631   reloc = xmalloc (sizeof (arelent));
   2632 
   2633   /* HACK: Is this right?  */
   2634   fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
   2635 
   2636   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
   2637   if (reloc->howto == NULL)
   2638     {
   2639       as_bad_where (fixP->fx_file, fixP->fx_line,
   2640 		    _("internal error: can't export reloc type %d (`%s')"),
   2641 		    fixP->fx_r_type,
   2642 		    bfd_get_reloc_code_name (fixP->fx_r_type));
   2643       return NULL;
   2644     }
   2645 
   2646   gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
   2647 
   2648   reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   2649   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   2650   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
   2651   reloc->addend = fixP->fx_addnumber;
   2652 
   2653   return reloc;
   2654 }
   2655 
   2656 /* end from cgen.c */
   2657 
   2658 const pseudo_typeS md_pseudo_table[] =
   2659 {
   2660   {"bss", s_lcomm, 1},
   2661   {"endian", s_endian, 0},
   2662   {"extended", float_cons, 't'},
   2663   {"leafproc", parse_po, S_LEAFPROC},
   2664   {"sysproc", parse_po, S_SYSPROC},
   2665 
   2666   {"word", cons, 4},
   2667   {"quad", cons, 16},
   2668 
   2669   {0, 0, 0}
   2670 };
   2671