1 /* Print Motorola 68k instructions. 2 Copyright (C) 1986-2014 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include "sysdep.h" 22 #include "dis-asm.h" 23 #include "floatformat.h" 24 #include "libiberty.h" 25 #include "opintl.h" 26 27 #include "opcode/m68k.h" 28 29 /* Local function prototypes. */ 30 31 const char * const fpcr_names[] = 32 { 33 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", 34 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" 35 }; 36 37 static char *const reg_names[] = 38 { 39 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", 40 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", 41 "%ps", "%pc" 42 }; 43 44 /* Name of register halves for MAC/EMAC. 45 Seperate from reg_names since 'spu', 'fpl' look weird. */ 46 static char *const reg_half_names[] = 47 { 48 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", 49 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7", 50 "%ps", "%pc" 51 }; 52 53 /* Sign-extend an (unsigned char). */ 54 #if __STDC__ == 1 55 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch)) 56 #else 57 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128) 58 #endif 59 60 /* Get a 1 byte signed integer. */ 61 #define NEXTBYTE(p, val) \ 62 do \ 63 { \ 64 p += 2; \ 65 if (!FETCH_DATA (info, p)) \ 66 return -3; \ 67 val = COERCE_SIGNED_CHAR (p[-1]); \ 68 } \ 69 while (0) 70 71 /* Get a 2 byte signed integer. */ 72 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) 73 74 #define NEXTWORD(p, val, ret_val) \ 75 do \ 76 { \ 77 p += 2; \ 78 if (!FETCH_DATA (info, p)) \ 79 return ret_val; \ 80 val = COERCE16 ((p[-2] << 8) + p[-1]); \ 81 } \ 82 while (0) 83 84 /* Get a 4 byte signed integer. */ 85 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000) 86 87 #define NEXTLONG(p, val, ret_val) \ 88 do \ 89 { \ 90 p += 4; \ 91 if (!FETCH_DATA (info, p)) \ 92 return ret_val; \ 93 val = COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \ 94 } \ 95 while (0) 96 97 /* Get a 4 byte unsigned integer. */ 98 #define NEXTULONG(p, val) \ 99 do \ 100 { \ 101 p += 4; \ 102 if (!FETCH_DATA (info, p)) \ 103 return -3; \ 104 val = (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]); \ 105 } \ 106 while (0) 107 108 /* Get a single precision float. */ 109 #define NEXTSINGLE(val, p) \ 110 do \ 111 { \ 112 p += 4; \ 113 if (!FETCH_DATA (info, p)) \ 114 return -3; \ 115 floatformat_to_double (& floatformat_ieee_single_big, \ 116 (char *) p - 4, & val); \ 117 } \ 118 while (0) 119 120 /* Get a double precision float. */ 121 #define NEXTDOUBLE(val, p) \ 122 do \ 123 { \ 124 p += 8; \ 125 if (!FETCH_DATA (info, p)) \ 126 return -3; \ 127 floatformat_to_double (& floatformat_ieee_double_big, \ 128 (char *) p - 8, & val); \ 129 } \ 130 while (0) 131 132 /* Get an extended precision float. */ 133 #define NEXTEXTEND(val, p) \ 134 do \ 135 { \ 136 p += 12; \ 137 if (!FETCH_DATA (info, p)) \ 138 return -3; \ 139 floatformat_to_double (& floatformat_m68881_ext, \ 140 (char *) p - 12, & val); \ 141 } \ 142 while (0) 143 144 /* Need a function to convert from packed to double 145 precision. Actually, it's easier to print a 146 packed number than a double anyway, so maybe 147 there should be a special case to handle this... */ 148 #define NEXTPACKED(p, val) \ 149 do \ 150 { \ 151 p += 12; \ 152 if (!FETCH_DATA (info, p)) \ 153 return -3; \ 154 val = 0.0; \ 155 } \ 156 while (0) 157 158 159 /* Maximum length of an instruction. */ 161 #define MAXLEN 22 162 163 struct private 164 { 165 /* Points to first byte not fetched. */ 166 bfd_byte *max_fetched; 167 bfd_byte the_buffer[MAXLEN]; 168 bfd_vma insn_start; 169 }; 170 171 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 172 to ADDR (exclusive) are valid. Returns 1 for success, 0 on error. */ 173 #define FETCH_DATA(info, addr) \ 174 ((addr) <= ((struct private *) (info->private_data))->max_fetched \ 175 ? 1 : fetch_data ((info), (addr))) 176 177 static int 178 fetch_data (struct disassemble_info *info, bfd_byte *addr) 179 { 180 int status; 181 struct private *priv = (struct private *)info->private_data; 182 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); 183 184 status = (*info->read_memory_func) (start, 185 priv->max_fetched, 186 addr - priv->max_fetched, 187 info); 188 if (status != 0) 189 { 190 (*info->memory_error_func) (status, start, info); 191 return 0; 192 } 193 else 194 priv->max_fetched = addr; 195 return 1; 196 } 197 198 /* This function is used to print to the bit-bucket. */ 200 static int 201 dummy_printer (FILE *file ATTRIBUTE_UNUSED, 202 const char *format ATTRIBUTE_UNUSED, 203 ...) 204 { 205 return 0; 206 } 207 208 static void 209 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED, 210 struct disassemble_info *info ATTRIBUTE_UNUSED) 211 { 212 } 213 214 /* Fetch BITS bits from a position in the instruction specified by CODE. 215 CODE is a "place to put an argument", or 'x' for a destination 216 that is a general address (mode and register). 217 BUFFER contains the instruction. 218 Returns -1 on failure. */ 219 220 static int 221 fetch_arg (unsigned char *buffer, 222 int code, 223 int bits, 224 disassemble_info *info) 225 { 226 int val = 0; 227 228 switch (code) 229 { 230 case '/': /* MAC/EMAC mask bit. */ 231 val = buffer[3] >> 5; 232 break; 233 234 case 'G': /* EMAC ACC load. */ 235 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1); 236 break; 237 238 case 'H': /* EMAC ACC !load. */ 239 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1); 240 break; 241 242 case ']': /* EMAC ACCEXT bit. */ 243 val = buffer[0] >> 2; 244 break; 245 246 case 'I': /* MAC/EMAC scale factor. */ 247 val = buffer[2] >> 1; 248 break; 249 250 case 'F': /* EMAC ACCx. */ 251 val = buffer[0] >> 1; 252 break; 253 254 case 'f': 255 val = buffer[1]; 256 break; 257 258 case 's': 259 val = buffer[1]; 260 break; 261 262 case 'd': /* Destination, for register or quick. */ 263 val = (buffer[0] << 8) + buffer[1]; 264 val >>= 9; 265 break; 266 267 case 'x': /* Destination, for general arg. */ 268 val = (buffer[0] << 8) + buffer[1]; 269 val >>= 6; 270 break; 271 272 case 'k': 273 if (! FETCH_DATA (info, buffer + 3)) 274 return -1; 275 val = (buffer[3] >> 4); 276 break; 277 278 case 'C': 279 if (! FETCH_DATA (info, buffer + 3)) 280 return -1; 281 val = buffer[3]; 282 break; 283 284 case '1': 285 if (! FETCH_DATA (info, buffer + 3)) 286 return -1; 287 val = (buffer[2] << 8) + buffer[3]; 288 val >>= 12; 289 break; 290 291 case '2': 292 if (! FETCH_DATA (info, buffer + 3)) 293 return -1; 294 val = (buffer[2] << 8) + buffer[3]; 295 val >>= 6; 296 break; 297 298 case '3': 299 case 'j': 300 if (! FETCH_DATA (info, buffer + 3)) 301 return -1; 302 val = (buffer[2] << 8) + buffer[3]; 303 break; 304 305 case '4': 306 if (! FETCH_DATA (info, buffer + 5)) 307 return -1; 308 val = (buffer[4] << 8) + buffer[5]; 309 val >>= 12; 310 break; 311 312 case '5': 313 if (! FETCH_DATA (info, buffer + 5)) 314 return -1; 315 val = (buffer[4] << 8) + buffer[5]; 316 val >>= 6; 317 break; 318 319 case '6': 320 if (! FETCH_DATA (info, buffer + 5)) 321 return -1; 322 val = (buffer[4] << 8) + buffer[5]; 323 break; 324 325 case '7': 326 if (! FETCH_DATA (info, buffer + 3)) 327 return -1; 328 val = (buffer[2] << 8) + buffer[3]; 329 val >>= 7; 330 break; 331 332 case '8': 333 if (! FETCH_DATA (info, buffer + 3)) 334 return -1; 335 val = (buffer[2] << 8) + buffer[3]; 336 val >>= 10; 337 break; 338 339 case '9': 340 if (! FETCH_DATA (info, buffer + 3)) 341 return -1; 342 val = (buffer[2] << 8) + buffer[3]; 343 val >>= 5; 344 break; 345 346 case 'e': 347 val = (buffer[1] >> 6); 348 break; 349 350 case 'E': 351 if (! FETCH_DATA (info, buffer + 3)) 352 return -1; 353 val = (buffer[2] >> 1); 354 break; 355 356 case 'm': 357 val = (buffer[1] & 0x40 ? 0x8 : 0) 358 | ((buffer[0] >> 1) & 0x7) 359 | (buffer[3] & 0x80 ? 0x10 : 0); 360 break; 361 362 case 'n': 363 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); 364 break; 365 366 case 'o': 367 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); 368 break; 369 370 case 'M': 371 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); 372 break; 373 374 case 'N': 375 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); 376 break; 377 378 case 'h': 379 val = buffer[2] >> 2; 380 break; 381 382 default: 383 abort (); 384 } 385 386 /* bits is never too big. */ 387 return val & ((1 << bits) - 1); 388 } 389 390 /* Check if an EA is valid for a particular code. This is required 391 for the EMAC instructions since the type of source address determines 392 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it 393 is a non-load EMAC instruction and the bits mean register Ry. 394 A similar case exists for the movem instructions where the register 395 mask is interpreted differently for different EAs. */ 396 397 static bfd_boolean 398 m68k_valid_ea (char code, int val) 399 { 400 int mode, mask; 401 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \ 402 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \ 403 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11) 404 405 switch (code) 406 { 407 case '*': 408 mask = M (1,1,1,1,1,1,1,1,1,1,1,1); 409 break; 410 case '~': 411 mask = M (0,0,1,1,1,1,1,1,1,0,0,0); 412 break; 413 case '%': 414 mask = M (1,1,1,1,1,1,1,1,1,0,0,0); 415 break; 416 case ';': 417 mask = M (1,0,1,1,1,1,1,1,1,1,1,1); 418 break; 419 case '@': 420 mask = M (1,0,1,1,1,1,1,1,1,1,1,0); 421 break; 422 case '!': 423 mask = M (0,0,1,0,0,1,1,1,1,1,1,0); 424 break; 425 case '&': 426 mask = M (0,0,1,0,0,1,1,1,1,0,0,0); 427 break; 428 case '$': 429 mask = M (1,0,1,1,1,1,1,1,1,0,0,0); 430 break; 431 case '?': 432 mask = M (1,0,1,0,0,1,1,1,1,0,0,0); 433 break; 434 case '/': 435 mask = M (1,0,1,0,0,1,1,1,1,1,1,0); 436 break; 437 case '|': 438 mask = M (0,0,1,0,0,1,1,1,1,1,1,0); 439 break; 440 case '>': 441 mask = M (0,0,1,0,1,1,1,1,1,0,0,0); 442 break; 443 case '<': 444 mask = M (0,0,1,1,0,1,1,1,1,1,1,0); 445 break; 446 case 'm': 447 mask = M (1,1,1,1,1,0,0,0,0,0,0,0); 448 break; 449 case 'n': 450 mask = M (0,0,0,0,0,1,0,0,0,1,0,0); 451 break; 452 case 'o': 453 mask = M (0,0,0,0,0,0,1,1,1,0,1,1); 454 break; 455 case 'p': 456 mask = M (1,1,1,1,1,1,0,0,0,0,0,0); 457 break; 458 case 'q': 459 mask = M (1,0,1,1,1,1,0,0,0,0,0,0); 460 break; 461 case 'v': 462 mask = M (1,0,1,1,1,1,0,1,1,0,0,0); 463 break; 464 case 'b': 465 mask = M (1,0,1,1,1,1,0,0,0,1,0,0); 466 break; 467 case 'w': 468 mask = M (0,0,1,1,1,1,0,0,0,1,0,0); 469 break; 470 case 'y': 471 mask = M (0,0,1,0,0,1,0,0,0,0,0,0); 472 break; 473 case 'z': 474 mask = M (0,0,1,0,0,1,0,0,0,1,0,0); 475 break; 476 case '4': 477 mask = M (0,0,1,1,1,1,0,0,0,0,0,0); 478 break; 479 default: 480 abort (); 481 } 482 #undef M 483 484 mode = (val >> 3) & 7; 485 if (mode == 7) 486 mode += val & 7; 487 return (mask & (1 << mode)) != 0; 488 } 489 490 /* Print a base register REGNO and displacement DISP, on INFO->STREAM. 491 REGNO = -1 for pc, -2 for none (suppressed). */ 492 493 static void 494 print_base (int regno, bfd_vma disp, disassemble_info *info) 495 { 496 if (regno == -1) 497 { 498 (*info->fprintf_func) (info->stream, "%%pc@("); 499 (*info->print_address_func) (disp, info); 500 } 501 else 502 { 503 char buf[50]; 504 505 if (regno == -2) 506 (*info->fprintf_func) (info->stream, "@("); 507 else if (regno == -3) 508 (*info->fprintf_func) (info->stream, "%%zpc@("); 509 else 510 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); 511 512 sprintf_vma (buf, disp); 513 (*info->fprintf_func) (info->stream, "%s", buf); 514 } 515 } 516 517 /* Print an indexed argument. The base register is BASEREG (-1 for pc). 518 P points to extension word, in buffer. 519 ADDR is the nominal core address of that extension word. 520 Returns NULL upon error. */ 521 522 static unsigned char * 523 print_indexed (int basereg, 524 unsigned char *p, 525 bfd_vma addr, 526 disassemble_info *info) 527 { 528 int word; 529 static char *const scales[] = { "", ":2", ":4", ":8" }; 530 bfd_vma base_disp; 531 bfd_vma outer_disp; 532 char buf[40]; 533 char vmabuf[50]; 534 535 NEXTWORD (p, word, NULL); 536 537 /* Generate the text for the index register. 538 Where this will be output is not yet determined. */ 539 sprintf (buf, "%s:%c%s", 540 reg_names[(word >> 12) & 0xf], 541 (word & 0x800) ? 'l' : 'w', 542 scales[(word >> 9) & 3]); 543 544 /* Handle the 68000 style of indexing. */ 545 546 if ((word & 0x100) == 0) 547 { 548 base_disp = word & 0xff; 549 if ((base_disp & 0x80) != 0) 550 base_disp -= 0x100; 551 if (basereg == -1) 552 base_disp += addr; 553 print_base (basereg, base_disp, info); 554 (*info->fprintf_func) (info->stream, ",%s)", buf); 555 return p; 556 } 557 558 /* Handle the generalized kind. */ 559 /* First, compute the displacement to add to the base register. */ 560 if (word & 0200) 561 { 562 if (basereg == -1) 563 basereg = -3; 564 else 565 basereg = -2; 566 } 567 if (word & 0100) 568 buf[0] = '\0'; 569 base_disp = 0; 570 switch ((word >> 4) & 3) 571 { 572 case 2: 573 NEXTWORD (p, base_disp, NULL); 574 break; 575 case 3: 576 NEXTLONG (p, base_disp, NULL); 577 } 578 if (basereg == -1) 579 base_disp += addr; 580 581 /* Handle single-level case (not indirect). */ 582 if ((word & 7) == 0) 583 { 584 print_base (basereg, base_disp, info); 585 if (buf[0] != '\0') 586 (*info->fprintf_func) (info->stream, ",%s", buf); 587 (*info->fprintf_func) (info->stream, ")"); 588 return p; 589 } 590 591 /* Two level. Compute displacement to add after indirection. */ 592 outer_disp = 0; 593 switch (word & 3) 594 { 595 case 2: 596 NEXTWORD (p, outer_disp, NULL); 597 break; 598 case 3: 599 NEXTLONG (p, outer_disp, NULL); 600 } 601 602 print_base (basereg, base_disp, info); 603 if ((word & 4) == 0 && buf[0] != '\0') 604 { 605 (*info->fprintf_func) (info->stream, ",%s", buf); 606 buf[0] = '\0'; 607 } 608 sprintf_vma (vmabuf, outer_disp); 609 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); 610 if (buf[0] != '\0') 611 (*info->fprintf_func) (info->stream, ",%s", buf); 612 (*info->fprintf_func) (info->stream, ")"); 613 614 return p; 615 } 616 617 #define FETCH_ARG(size, val) \ 618 do \ 619 { \ 620 val = fetch_arg (buffer, place, size, info); \ 621 if (val < 0) \ 622 return -3; \ 623 } \ 624 while (0) 625 626 /* Returns number of bytes "eaten" by the operand, or 627 return -1 if an invalid operand was found, or -2 if 628 an opcode tabe error was found or -3 to simply abort. 629 ADDR is the pc for this arg to be relative to. */ 630 631 static int 632 print_insn_arg (const char *d, 633 unsigned char *buffer, 634 unsigned char *p0, 635 bfd_vma addr, 636 disassemble_info *info) 637 { 638 int val = 0; 639 int place = d[1]; 640 unsigned char *p = p0; 641 int regno; 642 const char *regname; 643 unsigned char *p1; 644 double flval; 645 int flt_p; 646 bfd_signed_vma disp; 647 unsigned int uval; 648 649 switch (*d) 650 { 651 case 'c': /* Cache identifier. */ 652 { 653 static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; 654 FETCH_ARG (2, val); 655 (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]); 656 break; 657 } 658 659 case 'a': /* Address register indirect only. Cf. case '+'. */ 660 { 661 FETCH_ARG (3, val); 662 (*info->fprintf_func) (info->stream, "%s@", reg_names[val + 8]); 663 break; 664 } 665 666 case '_': /* 32-bit absolute address for move16. */ 667 { 668 NEXTULONG (p, uval); 669 (*info->print_address_func) (uval, info); 670 break; 671 } 672 673 case 'C': 674 (*info->fprintf_func) (info->stream, "%%ccr"); 675 break; 676 677 case 'S': 678 (*info->fprintf_func) (info->stream, "%%sr"); 679 break; 680 681 case 'U': 682 (*info->fprintf_func) (info->stream, "%%usp"); 683 break; 684 685 case 'E': 686 (*info->fprintf_func) (info->stream, "%%acc"); 687 break; 688 689 case 'G': 690 (*info->fprintf_func) (info->stream, "%%macsr"); 691 break; 692 693 case 'H': 694 (*info->fprintf_func) (info->stream, "%%mask"); 695 break; 696 697 case 'J': 698 { 699 /* FIXME: There's a problem here, different m68k processors call the 700 same address different names. The tables below try to get it right 701 using info->mach, but only for v4e. */ 702 struct regname { char * name; int value; }; 703 static const struct regname names[] = 704 { 705 {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, 706 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, 707 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, 708 {"%rgpiobar", 0x009}, {"%acr4",0x00c}, 709 {"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f}, 710 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, 711 {"%msp", 0x803}, {"%isp", 0x804}, 712 {"%pc", 0x80f}, 713 /* Reg c04 is sometimes called flashbar or rambar. 714 Reg c05 is also sometimes called rambar. */ 715 {"%rambar0", 0xc04}, {"%rambar1", 0xc05}, 716 717 /* reg c0e is sometimes called mbar2 or secmbar. 718 reg c0f is sometimes called mbar. */ 719 {"%mbar0", 0xc0e}, {"%mbar1", 0xc0f}, 720 721 /* Should we be calling this psr like we do in case 'Y'? */ 722 {"%mmusr",0x805}, 723 724 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}, 725 726 /* Fido added these. */ 727 {"%cac", 0xffe}, {"%mbo", 0xfff} 728 }; 729 /* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */ 730 static const struct regname names_v4e[] = 731 { 732 {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005}, 733 {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008}, 734 }; 735 unsigned int arch_mask; 736 737 arch_mask = bfd_m68k_mach_to_features (info->mach); 738 FETCH_ARG (12, val); 739 if (arch_mask & (mcfisa_b | mcfisa_c)) 740 { 741 for (regno = ARRAY_SIZE (names_v4e); --regno >= 0;) 742 if (names_v4e[regno].value == val) 743 { 744 (*info->fprintf_func) (info->stream, "%s", names_v4e[regno].name); 745 break; 746 } 747 if (regno >= 0) 748 break; 749 } 750 for (regno = ARRAY_SIZE (names) - 1; regno >= 0; regno--) 751 if (names[regno].value == val) 752 { 753 (*info->fprintf_func) (info->stream, "%s", names[regno].name); 754 break; 755 } 756 if (regno < 0) 757 (*info->fprintf_func) (info->stream, "0x%x", val); 758 } 759 break; 760 761 case 'Q': 762 FETCH_ARG (3, val); 763 /* 0 means 8, except for the bkpt instruction... */ 764 if (val == 0 && d[1] != 's') 765 val = 8; 766 (*info->fprintf_func) (info->stream, "#%d", val); 767 break; 768 769 case 'x': 770 FETCH_ARG (3, val); 771 /* 0 means -1. */ 772 if (val == 0) 773 val = -1; 774 (*info->fprintf_func) (info->stream, "#%d", val); 775 break; 776 777 case 'j': 778 FETCH_ARG (3, val); 779 (*info->fprintf_func) (info->stream, "#%d", val+1); 780 break; 781 782 case 'K': 783 FETCH_ARG (9, val); 784 (*info->fprintf_func) (info->stream, "#%d", val); 785 break; 786 787 case 'M': 788 if (place == 'h') 789 { 790 static char *const scalefactor_name[] = { "<<", ">>" }; 791 792 FETCH_ARG (1, val); 793 (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]); 794 } 795 else 796 { 797 FETCH_ARG (8, val); 798 if (val & 0x80) 799 val = val - 0x100; 800 (*info->fprintf_func) (info->stream, "#%d", val); 801 } 802 break; 803 804 case 'T': 805 FETCH_ARG (4, val); 806 (*info->fprintf_func) (info->stream, "#%d", val); 807 break; 808 809 case 'D': 810 FETCH_ARG (3, val); 811 (*info->fprintf_func) (info->stream, "%s", reg_names[val]); 812 break; 813 814 case 'A': 815 FETCH_ARG (3, val); 816 (*info->fprintf_func) (info->stream, "%s", reg_names[val + 010]); 817 break; 818 819 case 'R': 820 FETCH_ARG (4, val); 821 (*info->fprintf_func) (info->stream, "%s", reg_names[val]); 822 break; 823 824 case 'r': 825 FETCH_ARG (4, regno); 826 if (regno > 7) 827 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]); 828 else 829 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]); 830 break; 831 832 case 'F': 833 FETCH_ARG (3, val); 834 (*info->fprintf_func) (info->stream, "%%fp%d", val); 835 break; 836 837 case 'O': 838 FETCH_ARG (6, val); 839 if (val & 0x20) 840 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]); 841 else 842 (*info->fprintf_func) (info->stream, "%d", val); 843 break; 844 845 case '+': 846 FETCH_ARG (3, val); 847 (*info->fprintf_func) (info->stream, "%s@+", reg_names[val + 8]); 848 break; 849 850 case '-': 851 FETCH_ARG (3, val); 852 (*info->fprintf_func) (info->stream, "%s@-", reg_names[val + 8]); 853 break; 854 855 case 'k': 856 if (place == 'k') 857 { 858 FETCH_ARG (3, val); 859 (*info->fprintf_func) (info->stream, "{%s}", reg_names[val]); 860 } 861 else if (place == 'C') 862 { 863 FETCH_ARG (7, val); 864 if (val > 63) /* This is a signed constant. */ 865 val -= 128; 866 (*info->fprintf_func) (info->stream, "{#%d}", val); 867 } 868 else 869 return -1; 870 break; 871 872 case '#': 873 case '^': 874 p1 = buffer + (*d == '#' ? 2 : 4); 875 if (place == 's') 876 FETCH_ARG (4, val); 877 else if (place == 'C') 878 FETCH_ARG (7, val); 879 else if (place == '8') 880 FETCH_ARG (3, val); 881 else if (place == '3') 882 FETCH_ARG (8, val); 883 else if (place == 'b') 884 NEXTBYTE (p1, val); 885 else if (place == 'w' || place == 'W') 886 NEXTWORD (p1, val, -3); 887 else if (place == 'l') 888 NEXTLONG (p1, val, -3); 889 else 890 return -2; 891 892 (*info->fprintf_func) (info->stream, "#%d", val); 893 break; 894 895 case 'B': 896 if (place == 'b') 897 NEXTBYTE (p, disp); 898 else if (place == 'B') 899 disp = COERCE_SIGNED_CHAR (buffer[1]); 900 else if (place == 'w' || place == 'W') 901 NEXTWORD (p, disp, -3); 902 else if (place == 'l' || place == 'L' || place == 'C') 903 NEXTLONG (p, disp, -3); 904 else if (place == 'g') 905 { 906 NEXTBYTE (buffer, disp); 907 if (disp == 0) 908 NEXTWORD (p, disp, -3); 909 else if (disp == -1) 910 NEXTLONG (p, disp, -3); 911 } 912 else if (place == 'c') 913 { 914 if (buffer[1] & 0x40) /* If bit six is one, long offset. */ 915 NEXTLONG (p, disp, -3); 916 else 917 NEXTWORD (p, disp, -3); 918 } 919 else 920 return -2; 921 922 (*info->print_address_func) (addr + disp, info); 923 break; 924 925 case 'd': 926 { 927 int val1; 928 929 NEXTWORD (p, val, -3); 930 FETCH_ARG (3, val1); 931 (*info->fprintf_func) (info->stream, "%s@(%d)", reg_names[val1 + 8], val); 932 break; 933 } 934 935 case 's': 936 FETCH_ARG (3, val); 937 (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]); 938 break; 939 940 case 'e': 941 FETCH_ARG (2, val); 942 (*info->fprintf_func) (info->stream, "%%acc%d", val); 943 break; 944 945 case 'g': 946 FETCH_ARG (1, val); 947 (*info->fprintf_func) (info->stream, "%%accext%s", val == 0 ? "01" : "23"); 948 break; 949 950 case 'i': 951 FETCH_ARG (2, val); 952 if (val == 1) 953 (*info->fprintf_func) (info->stream, "<<"); 954 else if (val == 3) 955 (*info->fprintf_func) (info->stream, ">>"); 956 else 957 return -1; 958 break; 959 960 case 'I': 961 /* Get coprocessor ID... */ 962 val = fetch_arg (buffer, 'd', 3, info); 963 if (val < 0) 964 return -3; 965 if (val != 1) /* Unusual coprocessor ID? */ 966 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); 967 break; 968 969 case '4': 970 case '*': 971 case '~': 972 case '%': 973 case ';': 974 case '@': 975 case '!': 976 case '$': 977 case '?': 978 case '/': 979 case '&': 980 case '|': 981 case '<': 982 case '>': 983 case 'm': 984 case 'n': 985 case 'o': 986 case 'p': 987 case 'q': 988 case 'v': 989 case 'b': 990 case 'w': 991 case 'y': 992 case 'z': 993 if (place == 'd') 994 { 995 val = fetch_arg (buffer, 'x', 6, info); 996 if (val < 0) 997 return -3; 998 val = ((val & 7) << 3) + ((val >> 3) & 7); 999 } 1000 else 1001 { 1002 val = fetch_arg (buffer, 's', 6, info); 1003 if (val < 0) 1004 return -3; 1005 } 1006 1007 /* If the <ea> is invalid for *d, then reject this match. */ 1008 if (!m68k_valid_ea (*d, val)) 1009 return -1; 1010 1011 /* Get register number assuming address register. */ 1012 regno = (val & 7) + 8; 1013 regname = reg_names[regno]; 1014 switch (val >> 3) 1015 { 1016 case 0: 1017 (*info->fprintf_func) (info->stream, "%s", reg_names[val]); 1018 break; 1019 1020 case 1: 1021 (*info->fprintf_func) (info->stream, "%s", regname); 1022 break; 1023 1024 case 2: 1025 (*info->fprintf_func) (info->stream, "%s@", regname); 1026 break; 1027 1028 case 3: 1029 (*info->fprintf_func) (info->stream, "%s@+", regname); 1030 break; 1031 1032 case 4: 1033 (*info->fprintf_func) (info->stream, "%s@-", regname); 1034 break; 1035 1036 case 5: 1037 NEXTWORD (p, val, -3); 1038 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val); 1039 break; 1040 1041 case 6: 1042 p = print_indexed (regno, p, addr, info); 1043 if (p == NULL) 1044 return -3; 1045 break; 1046 1047 case 7: 1048 switch (val & 7) 1049 { 1050 case 0: 1051 NEXTWORD (p, val, -3); 1052 (*info->print_address_func) (val, info); 1053 break; 1054 1055 case 1: 1056 NEXTULONG (p, uval); 1057 (*info->print_address_func) (uval, info); 1058 break; 1059 1060 case 2: 1061 NEXTWORD (p, val, -3); 1062 (*info->fprintf_func) (info->stream, "%%pc@("); 1063 (*info->print_address_func) (addr + val, info); 1064 (*info->fprintf_func) (info->stream, ")"); 1065 break; 1066 1067 case 3: 1068 p = print_indexed (-1, p, addr, info); 1069 if (p == NULL) 1070 return -3; 1071 break; 1072 1073 case 4: 1074 flt_p = 1; /* Assume it's a float... */ 1075 switch (place) 1076 { 1077 case 'b': 1078 NEXTBYTE (p, val); 1079 flt_p = 0; 1080 break; 1081 1082 case 'w': 1083 NEXTWORD (p, val, -3); 1084 flt_p = 0; 1085 break; 1086 1087 case 'l': 1088 NEXTLONG (p, val, -3); 1089 flt_p = 0; 1090 break; 1091 1092 case 'f': 1093 NEXTSINGLE (flval, p); 1094 break; 1095 1096 case 'F': 1097 NEXTDOUBLE (flval, p); 1098 break; 1099 1100 case 'x': 1101 NEXTEXTEND (flval, p); 1102 break; 1103 1104 case 'p': 1105 NEXTPACKED (p, flval); 1106 break; 1107 1108 default: 1109 return -1; 1110 } 1111 if (flt_p) /* Print a float? */ 1112 (*info->fprintf_func) (info->stream, "#0e%g", flval); 1113 else 1114 (*info->fprintf_func) (info->stream, "#%d", val); 1115 break; 1116 1117 default: 1118 return -1; 1119 } 1120 } 1121 1122 /* If place is '/', then this is the case of the mask bit for 1123 mac/emac loads. Now that the arg has been printed, grab the 1124 mask bit and if set, add a '&' to the arg. */ 1125 if (place == '/') 1126 { 1127 FETCH_ARG (1, val); 1128 if (val) 1129 info->fprintf_func (info->stream, "&"); 1130 } 1131 break; 1132 1133 case 'L': 1134 case 'l': 1135 if (place == 'w') 1136 { 1137 char doneany; 1138 p1 = buffer + 2; 1139 NEXTWORD (p1, val, -3); 1140 /* Move the pointer ahead if this point is farther ahead 1141 than the last. */ 1142 p = p1 > p ? p1 : p; 1143 if (val == 0) 1144 { 1145 (*info->fprintf_func) (info->stream, "#0"); 1146 break; 1147 } 1148 if (*d == 'l') 1149 { 1150 int newval = 0; 1151 1152 for (regno = 0; regno < 16; ++regno) 1153 if (val & (0x8000 >> regno)) 1154 newval |= 1 << regno; 1155 val = newval; 1156 } 1157 val &= 0xffff; 1158 doneany = 0; 1159 for (regno = 0; regno < 16; ++regno) 1160 if (val & (1 << regno)) 1161 { 1162 int first_regno; 1163 1164 if (doneany) 1165 (*info->fprintf_func) (info->stream, "/"); 1166 doneany = 1; 1167 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]); 1168 first_regno = regno; 1169 while (val & (1 << (regno + 1))) 1170 ++regno; 1171 if (regno > first_regno) 1172 (*info->fprintf_func) (info->stream, "-%s", 1173 reg_names[regno]); 1174 } 1175 } 1176 else if (place == '3') 1177 { 1178 /* `fmovem' insn. */ 1179 char doneany; 1180 1181 FETCH_ARG (8, val); 1182 if (val == 0) 1183 { 1184 (*info->fprintf_func) (info->stream, "#0"); 1185 break; 1186 } 1187 if (*d == 'l') 1188 { 1189 int newval = 0; 1190 1191 for (regno = 0; regno < 8; ++regno) 1192 if (val & (0x80 >> regno)) 1193 newval |= 1 << regno; 1194 val = newval; 1195 } 1196 val &= 0xff; 1197 doneany = 0; 1198 for (regno = 0; regno < 8; ++regno) 1199 if (val & (1 << regno)) 1200 { 1201 int first_regno; 1202 if (doneany) 1203 (*info->fprintf_func) (info->stream, "/"); 1204 doneany = 1; 1205 (*info->fprintf_func) (info->stream, "%%fp%d", regno); 1206 first_regno = regno; 1207 while (val & (1 << (regno + 1))) 1208 ++regno; 1209 if (regno > first_regno) 1210 (*info->fprintf_func) (info->stream, "-%%fp%d", regno); 1211 } 1212 } 1213 else if (place == '8') 1214 { 1215 FETCH_ARG (3, val); 1216 /* fmoveml for FP status registers. */ 1217 (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]); 1218 } 1219 else 1220 return -2; 1221 break; 1222 1223 case 'X': 1224 place = '8'; 1225 case 'Y': 1226 case 'Z': 1227 case 'W': 1228 case '0': 1229 case '1': 1230 case '2': 1231 case '3': 1232 { 1233 char *name = 0; 1234 1235 FETCH_ARG (5, val); 1236 switch (val) 1237 { 1238 case 2: name = "%tt0"; break; 1239 case 3: name = "%tt1"; break; 1240 case 0x10: name = "%tc"; break; 1241 case 0x11: name = "%drp"; break; 1242 case 0x12: name = "%srp"; break; 1243 case 0x13: name = "%crp"; break; 1244 case 0x14: name = "%cal"; break; 1245 case 0x15: name = "%val"; break; 1246 case 0x16: name = "%scc"; break; 1247 case 0x17: name = "%ac"; break; 1248 case 0x18: name = "%psr"; break; 1249 case 0x19: name = "%pcsr"; break; 1250 case 0x1c: 1251 case 0x1d: 1252 { 1253 int break_reg = ((buffer[3] >> 2) & 7); 1254 1255 (*info->fprintf_func) 1256 (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", 1257 break_reg); 1258 } 1259 break; 1260 default: 1261 (*info->fprintf_func) (info->stream, "<mmu register %d>", val); 1262 } 1263 if (name) 1264 (*info->fprintf_func) (info->stream, "%s", name); 1265 } 1266 break; 1267 1268 case 'f': 1269 { 1270 int fc; 1271 1272 FETCH_ARG (5, fc); 1273 if (fc == 1) 1274 (*info->fprintf_func) (info->stream, "%%dfc"); 1275 else if (fc == 0) 1276 (*info->fprintf_func) (info->stream, "%%sfc"); 1277 else 1278 /* xgettext:c-format */ 1279 (*info->fprintf_func) (info->stream, _("<function code %d>"), fc); 1280 } 1281 break; 1282 1283 case 'V': 1284 (*info->fprintf_func) (info->stream, "%%val"); 1285 break; 1286 1287 case 't': 1288 { 1289 int level; 1290 1291 FETCH_ARG (3, level); 1292 (*info->fprintf_func) (info->stream, "%d", level); 1293 } 1294 break; 1295 1296 case 'u': 1297 { 1298 short is_upper = 0; 1299 int reg; 1300 1301 FETCH_ARG (5, reg); 1302 if (reg & 0x10) 1303 { 1304 is_upper = 1; 1305 reg &= 0xf; 1306 } 1307 (*info->fprintf_func) (info->stream, "%s%s", 1308 reg_half_names[reg], 1309 is_upper ? "u" : "l"); 1310 } 1311 break; 1312 1313 default: 1314 return -2; 1315 } 1316 1317 return p - p0; 1318 } 1319 1320 /* Try to match the current instruction to best and if so, return the 1321 number of bytes consumed from the instruction stream, else zero. */ 1322 1323 static int 1324 match_insn_m68k (bfd_vma memaddr, 1325 disassemble_info * info, 1326 const struct m68k_opcode * best) 1327 { 1328 unsigned char *save_p; 1329 unsigned char *p; 1330 const char *d; 1331 const char *args = best->args; 1332 1333 struct private *priv = (struct private *) info->private_data; 1334 bfd_byte *buffer = priv->the_buffer; 1335 fprintf_ftype save_printer = info->fprintf_func; 1336 void (* save_print_address) (bfd_vma, struct disassemble_info *) 1337 = info->print_address_func; 1338 1339 if (*args == '.') 1340 args++; 1341 1342 /* Point at first word of argument data, 1343 and at descriptor for first argument. */ 1344 p = buffer + 2; 1345 1346 /* Figure out how long the fixed-size portion of the instruction is. 1347 The only place this is stored in the opcode table is 1348 in the arguments--look for arguments which specify fields in the 2nd 1349 or 3rd words of the instruction. */ 1350 for (d = args; *d; d += 2) 1351 { 1352 /* I don't think it is necessary to be checking d[0] here; 1353 I suspect all this could be moved to the case statement below. */ 1354 if (d[0] == '#') 1355 { 1356 if (d[1] == 'l' && p - buffer < 6) 1357 p = buffer + 6; 1358 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') 1359 p = buffer + 4; 1360 } 1361 1362 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) 1363 p = buffer + 4; 1364 1365 switch (d[1]) 1366 { 1367 case '1': 1368 case '2': 1369 case '3': 1370 case '7': 1371 case '8': 1372 case '9': 1373 case 'i': 1374 if (p - buffer < 4) 1375 p = buffer + 4; 1376 break; 1377 case '4': 1378 case '5': 1379 case '6': 1380 if (p - buffer < 6) 1381 p = buffer + 6; 1382 break; 1383 default: 1384 break; 1385 } 1386 } 1387 1388 /* pflusha is an exceptions. It takes no arguments but is two words 1389 long. Recognize it by looking at the lower 16 bits of the mask. */ 1390 if (p - buffer < 4 && (best->match & 0xFFFF) != 0) 1391 p = buffer + 4; 1392 1393 /* lpstop is another exception. It takes a one word argument but is 1394 three words long. */ 1395 if (p - buffer < 6 1396 && (best->match & 0xffff) == 0xffff 1397 && args[0] == '#' 1398 && args[1] == 'w') 1399 { 1400 /* Copy the one word argument into the usual location for a one 1401 word argument, to simplify printing it. We can get away with 1402 this because we know exactly what the second word is, and we 1403 aren't going to print anything based on it. */ 1404 p = buffer + 6; 1405 FETCH_DATA (info, p); 1406 buffer[2] = buffer[4]; 1407 buffer[3] = buffer[5]; 1408 } 1409 1410 FETCH_DATA (info, p); 1411 1412 save_p = p; 1413 info->print_address_func = dummy_print_address; 1414 info->fprintf_func = (fprintf_ftype) dummy_printer; 1415 1416 /* We scan the operands twice. The first time we don't print anything, 1417 but look for errors. */ 1418 for (d = args; *d; d += 2) 1419 { 1420 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); 1421 1422 if (eaten >= 0) 1423 p += eaten; 1424 else if (eaten == -1 || eaten == -3) 1425 { 1426 info->fprintf_func = save_printer; 1427 info->print_address_func = save_print_address; 1428 return 0; 1429 } 1430 else 1431 { 1432 /* We must restore the print functions before trying to print the 1433 error message. */ 1434 info->fprintf_func = save_printer; 1435 info->print_address_func = save_print_address; 1436 info->fprintf_func (info->stream, 1437 /* xgettext:c-format */ 1438 _("<internal error in opcode table: %s %s>\n"), 1439 best->name, best->args); 1440 return 2; 1441 } 1442 } 1443 1444 p = save_p; 1445 info->fprintf_func = save_printer; 1446 info->print_address_func = save_print_address; 1447 1448 d = args; 1449 1450 info->fprintf_func (info->stream, "%s", best->name); 1451 1452 if (*d) 1453 info->fprintf_func (info->stream, " "); 1454 1455 while (*d) 1456 { 1457 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); 1458 d += 2; 1459 1460 if (*d && *(d - 2) != 'I' && *d != 'k') 1461 info->fprintf_func (info->stream, ","); 1462 } 1463 1464 return p - buffer; 1465 } 1466 1467 /* Try to interpret the instruction at address MEMADDR as one that 1468 can execute on a processor with the features given by ARCH_MASK. 1469 If successful, print the instruction to INFO->STREAM and return 1470 its length in bytes. Return 0 otherwise. */ 1471 1472 static int 1473 m68k_scan_mask (bfd_vma memaddr, disassemble_info *info, 1474 unsigned int arch_mask) 1475 { 1476 int i; 1477 const char *d; 1478 static const struct m68k_opcode **opcodes[16]; 1479 static int numopcodes[16]; 1480 int val; 1481 int major_opcode; 1482 1483 struct private *priv = (struct private *) info->private_data; 1484 bfd_byte *buffer = priv->the_buffer; 1485 1486 if (!opcodes[0]) 1487 { 1488 /* Speed up the matching by sorting the opcode 1489 table on the upper four bits of the opcode. */ 1490 const struct m68k_opcode **opc_pointer[16]; 1491 1492 /* First count how many opcodes are in each of the sixteen buckets. */ 1493 for (i = 0; i < m68k_numopcodes; i++) 1494 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; 1495 1496 /* Then create a sorted table of pointers 1497 that point into the unsorted table. */ 1498 opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *) 1499 * m68k_numopcodes); 1500 opcodes[0] = opc_pointer[0]; 1501 1502 for (i = 1; i < 16; i++) 1503 { 1504 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; 1505 opcodes[i] = opc_pointer[i]; 1506 } 1507 1508 for (i = 0; i < m68k_numopcodes; i++) 1509 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; 1510 } 1511 1512 FETCH_DATA (info, buffer + 2); 1513 major_opcode = (buffer[0] >> 4) & 15; 1514 1515 for (i = 0; i < numopcodes[major_opcode]; i++) 1516 { 1517 const struct m68k_opcode *opc = opcodes[major_opcode][i]; 1518 unsigned long opcode = opc->opcode; 1519 unsigned long match = opc->match; 1520 const char *args = opc->args; 1521 1522 if (*args == '.') 1523 args++; 1524 1525 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) 1526 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) 1527 /* Only fetch the next two bytes if we need to. */ 1528 && (((0xffff & match) == 0) 1529 || 1530 (FETCH_DATA (info, buffer + 4) 1531 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) 1532 && ((0xff & buffer[3] & match) == (0xff & opcode))) 1533 ) 1534 && (opc->arch & arch_mask) != 0) 1535 { 1536 /* Don't use for printout the variants of divul and divsl 1537 that have the same register number in two places. 1538 The more general variants will match instead. */ 1539 for (d = args; *d; d += 2) 1540 if (d[1] == 'D') 1541 break; 1542 1543 /* Don't use for printout the variants of most floating 1544 point coprocessor instructions which use the same 1545 register number in two places, as above. */ 1546 if (*d == '\0') 1547 for (d = args; *d; d += 2) 1548 if (d[1] == 't') 1549 break; 1550 1551 /* Don't match fmovel with more than one register; 1552 wait for fmoveml. */ 1553 if (*d == '\0') 1554 { 1555 for (d = args; *d; d += 2) 1556 { 1557 if (d[0] == 's' && d[1] == '8') 1558 { 1559 val = fetch_arg (buffer, d[1], 3, info); 1560 if (val < 0) 1561 return 0; 1562 if ((val & (val - 1)) != 0) 1563 break; 1564 } 1565 } 1566 } 1567 1568 /* Don't match FPU insns with non-default coprocessor ID. */ 1569 if (*d == '\0') 1570 { 1571 for (d = args; *d; d += 2) 1572 { 1573 if (d[0] == 'I') 1574 { 1575 val = fetch_arg (buffer, 'd', 3, info); 1576 if (val != 1) 1577 break; 1578 } 1579 } 1580 } 1581 1582 if (*d == '\0') 1583 if ((val = match_insn_m68k (memaddr, info, opc))) 1584 return val; 1585 } 1586 } 1587 return 0; 1588 } 1589 1590 /* Print the m68k instruction at address MEMADDR in debugged memory, 1591 on INFO->STREAM. Returns length of the instruction, in bytes. */ 1592 1593 int 1594 print_insn_m68k (bfd_vma memaddr, disassemble_info *info) 1595 { 1596 unsigned int arch_mask; 1597 struct private priv; 1598 int val; 1599 1600 bfd_byte *buffer = priv.the_buffer; 1601 1602 info->private_data = & priv; 1603 /* Tell objdump to use two bytes per chunk 1604 and six bytes per line for displaying raw data. */ 1605 info->bytes_per_chunk = 2; 1606 info->bytes_per_line = 6; 1607 info->display_endian = BFD_ENDIAN_BIG; 1608 priv.max_fetched = priv.the_buffer; 1609 priv.insn_start = memaddr; 1610 1611 arch_mask = bfd_m68k_mach_to_features (info->mach); 1612 if (!arch_mask) 1613 { 1614 /* First try printing an m680x0 instruction. Try printing a Coldfire 1615 one if that fails. */ 1616 val = m68k_scan_mask (memaddr, info, m68k_mask); 1617 if (val == 0) 1618 val = m68k_scan_mask (memaddr, info, mcf_mask); 1619 } 1620 else 1621 { 1622 val = m68k_scan_mask (memaddr, info, arch_mask); 1623 } 1624 1625 if (val == 0) 1626 /* Handle undefined instructions. */ 1627 info->fprintf_func (info->stream, ".short 0x%04x", (buffer[0] << 8) + buffer[1]); 1628 1629 return val ? val : 2; 1630 } 1631
