Lines Matching refs:MmioWrite32
38 MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
41 MmioWrite32(HDLCD_REG_INT_MASK, 0);
44 MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);
47 MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
48 MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);
49 MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);
50 MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
51 MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
52 MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
93 MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
96 MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);
97 MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);
98 MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1);
101 MmioWrite32(HDLCD_REG_V_SYNC, VSync);
102 MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch);
103 MmioWrite32(HDLCD_REG_V_DATA, VRes - 1);
104 MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch);
107 MmioWrite32(HDLCD_REG_H_SYNC, HSync);
108 MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch);
109 MmioWrite32(HDLCD_REG_H_DATA, HRes - 1);
110 MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch);
113 MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);
124 MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
