Lines Matching full:evex
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
3203 /* Build the EVEX prefix. */
3222 EVEX prefix. */
3232 the EVEX prefix. */
3257 /* 4 byte EVEX prefix. */
3278 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3282 /* The fifth bit of the second EVEX byte is 1's compliment of the
3302 /* EVEX instructions shouldn't need the REX prefix. */
3323 /* The third byte of the EVEX prefix. */
3326 /* The fourth byte of the EVEX prefix. */
3337 switch (i.tm.opcode_modifier.evex)
3406 || i.tm.opcode_modifier.evex)
3650 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4612 /* VREX is only valid with EVEX prefix. */
4613 if (i.need_vrex && !t->opcode_modifier.evex)
6144 if (i.tm.opcode_modifier.evex)
6146 /* For EVEX instructions, when there are 5 operands, the
6980 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6982 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7050 /* For EVEX instructions i.vrex should become 0 after
7273 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
10068 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10071 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10072 for EVEX.W bit ignored instructions\n"));
10075 encode EVEX instructions with specific EVEX.RC value\n\
