1 /* tc-i386.c -- Assemble code for the Intel 80386 2 Copyright (C) 1989-2014 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 /* Intel 80386 machine specific gas. 22 Written by Eliot Dresselhaus (eliot (at) mgm.mit.edu). 23 x86_64 support by Jan Hubicka (jh (at) suse.cz) 24 VIA PadLock support by Michal Ludvig (mludvig (at) suse.cz) 25 Bugs & suggestions are completely welcome. This is free software. 26 Please help us make it better. */ 27 28 #include "as.h" 29 #include "safe-ctype.h" 30 #include "subsegs.h" 31 #include "dwarf2dbg.h" 32 #include "dw2gencfi.h" 33 #include "elf/x86-64.h" 34 #include "opcodes/i386-init.h" 35 36 #ifndef REGISTER_WARNINGS 37 #define REGISTER_WARNINGS 1 38 #endif 39 40 #ifndef INFER_ADDR_PREFIX 41 #define INFER_ADDR_PREFIX 1 42 #endif 43 44 #ifndef DEFAULT_ARCH 45 #define DEFAULT_ARCH "i386" 46 #endif 47 48 #ifndef INLINE 49 #if __GNUC__ >= 2 50 #define INLINE __inline__ 51 #else 52 #define INLINE 53 #endif 54 #endif 55 56 /* Prefixes will be emitted in the order defined below. 57 WAIT_PREFIX must be the first prefix since FWAIT is really is an 58 instruction, and so must come before any prefixes. 59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ 61 #define WAIT_PREFIX 0 62 #define SEG_PREFIX 1 63 #define ADDR_PREFIX 2 64 #define DATA_PREFIX 3 65 #define REP_PREFIX 4 66 #define HLE_PREFIX REP_PREFIX 67 #define BND_PREFIX REP_PREFIX 68 #define LOCK_PREFIX 5 69 #define REX_PREFIX 6 /* must come last. */ 70 #define MAX_PREFIXES 7 /* max prefixes per opcode */ 71 72 /* we define the syntax here (modulo base,index,scale syntax) */ 73 #define REGISTER_PREFIX '%' 74 #define IMMEDIATE_PREFIX '$' 75 #define ABSOLUTE_PREFIX '*' 76 77 /* these are the instruction mnemonic suffixes in AT&T syntax or 78 memory operand size in Intel syntax. */ 79 #define WORD_MNEM_SUFFIX 'w' 80 #define BYTE_MNEM_SUFFIX 'b' 81 #define SHORT_MNEM_SUFFIX 's' 82 #define LONG_MNEM_SUFFIX 'l' 83 #define QWORD_MNEM_SUFFIX 'q' 84 #define XMMWORD_MNEM_SUFFIX 'x' 85 #define YMMWORD_MNEM_SUFFIX 'y' 86 #define ZMMWORD_MNEM_SUFFIX 'z' 87 /* Intel Syntax. Use a non-ascii letter since since it never appears 88 in instructions. */ 89 #define LONG_DOUBLE_MNEM_SUFFIX '\1' 90 91 #define END_OF_INSN '\0' 92 93 /* 94 'templates' is for grouping together 'template' structures for opcodes 95 of the same name. This is only used for storing the insns in the grand 96 ole hash table of insns. 97 The templates themselves start at START and range up to (but not including) 98 END. 99 */ 100 typedef struct 101 { 102 const insn_template *start; 103 const insn_template *end; 104 } 105 templates; 106 107 /* 386 operand encoding bytes: see 386 book for details of this. */ 108 typedef struct 109 { 110 unsigned int regmem; /* codes register or memory operand */ 111 unsigned int reg; /* codes register operand (or extended opcode) */ 112 unsigned int mode; /* how to interpret regmem & reg */ 113 } 114 modrm_byte; 115 116 /* x86-64 extension prefix. */ 117 typedef int rex_byte; 118 119 /* 386 opcode byte to code indirect addressing. */ 120 typedef struct 121 { 122 unsigned base; 123 unsigned index; 124 unsigned scale; 125 } 126 sib_byte; 127 128 /* x86 arch names, types and features */ 129 typedef struct 130 { 131 const char *name; /* arch name */ 132 unsigned int len; /* arch string length */ 133 enum processor_type type; /* arch type */ 134 i386_cpu_flags flags; /* cpu feature flags */ 135 unsigned int skip; /* show_arch should skip this. */ 136 unsigned int negated; /* turn off indicated flags. */ 137 } 138 arch_entry; 139 140 static void update_code_flag (int, int); 141 static void set_code_flag (int); 142 static void set_16bit_gcc_code_flag (int); 143 static void set_intel_syntax (int); 144 static void set_intel_mnemonic (int); 145 static void set_allow_index_reg (int); 146 static void set_check (int); 147 static void set_cpu_arch (int); 148 #ifdef TE_PE 149 static void pe_directive_secrel (int); 150 #endif 151 static void signed_cons (int); 152 static char *output_invalid (int c); 153 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, 154 const char *); 155 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, 156 const char *); 157 static int i386_att_operand (char *); 158 static int i386_intel_operand (char *, int); 159 static int i386_intel_simplify (expressionS *); 160 static int i386_intel_parse_name (const char *, expressionS *); 161 static const reg_entry *parse_register (char *, char **); 162 static char *parse_insn (char *, char *); 163 static char *parse_operands (char *, const char *); 164 static void swap_operands (void); 165 static void swap_2_operands (int, int); 166 static void optimize_imm (void); 167 static void optimize_disp (void); 168 static const insn_template *match_template (void); 169 static int check_string (void); 170 static int process_suffix (void); 171 static int check_byte_reg (void); 172 static int check_long_reg (void); 173 static int check_qword_reg (void); 174 static int check_word_reg (void); 175 static int finalize_imm (void); 176 static int process_operands (void); 177 static const seg_entry *build_modrm_byte (void); 178 static void output_insn (void); 179 static void output_imm (fragS *, offsetT); 180 static void output_disp (fragS *, offsetT); 181 #ifndef I386COFF 182 static void s_bss (int); 183 #endif 184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 185 static void handle_large_common (int small ATTRIBUTE_UNUSED); 186 #endif 187 188 static const char *default_arch = DEFAULT_ARCH; 189 190 /* This struct describes rounding control and SAE in the instruction. */ 191 struct RC_Operation 192 { 193 enum rc_type 194 { 195 rne = 0, 196 rd, 197 ru, 198 rz, 199 saeonly 200 } type; 201 int operand; 202 }; 203 204 static struct RC_Operation rc_op; 205 206 /* The struct describes masking, applied to OPERAND in the instruction. 207 MASK is a pointer to the corresponding mask register. ZEROING tells 208 whether merging or zeroing mask is used. */ 209 struct Mask_Operation 210 { 211 const reg_entry *mask; 212 unsigned int zeroing; 213 /* The operand where this operation is associated. */ 214 int operand; 215 }; 216 217 static struct Mask_Operation mask_op; 218 219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is 220 broadcast factor. */ 221 struct Broadcast_Operation 222 { 223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ 224 int type; 225 226 /* Index of broadcasted operand. */ 227 int operand; 228 }; 229 230 static struct Broadcast_Operation broadcast_op; 231 232 /* VEX prefix. */ 233 typedef struct 234 { 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ 236 unsigned char bytes[4]; 237 unsigned int length; 238 /* Destination or source register specifier. */ 239 const reg_entry *register_specifier; 240 } vex_prefix; 241 242 /* 'md_assemble ()' gathers together information and puts it into a 243 i386_insn. */ 244 245 union i386_op 246 { 247 expressionS *disps; 248 expressionS *imms; 249 const reg_entry *regs; 250 }; 251 252 enum i386_error 253 { 254 operand_size_mismatch, 255 operand_type_mismatch, 256 register_type_mismatch, 257 number_of_operands_mismatch, 258 invalid_instruction_suffix, 259 bad_imm4, 260 old_gcc_only, 261 unsupported_with_intel_mnemonic, 262 unsupported_syntax, 263 unsupported, 264 invalid_vsib_address, 265 invalid_vector_register_set, 266 unsupported_vector_index_register, 267 unsupported_broadcast, 268 broadcast_not_on_src_operand, 269 broadcast_needed, 270 unsupported_masking, 271 mask_not_on_destination, 272 no_default_mask, 273 unsupported_rc_sae, 274 rc_sae_operand_not_last_imm, 275 invalid_register_operand, 276 try_vector_disp8 277 }; 278 279 struct _i386_insn 280 { 281 /* TM holds the template for the insn were currently assembling. */ 282 insn_template tm; 283 284 /* SUFFIX holds the instruction size suffix for byte, word, dword 285 or qword, if given. */ 286 char suffix; 287 288 /* OPERANDS gives the number of given operands. */ 289 unsigned int operands; 290 291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 292 of given register, displacement, memory operands and immediate 293 operands. */ 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 295 296 /* TYPES [i] is the type (see above #defines) which tells us how to 297 use OP[i] for the corresponding operand. */ 298 i386_operand_type types[MAX_OPERANDS]; 299 300 /* Displacement expression, immediate expression, or register for each 301 operand. */ 302 union i386_op op[MAX_OPERANDS]; 303 304 /* Flags for operands. */ 305 unsigned int flags[MAX_OPERANDS]; 306 #define Operand_PCrel 1 307 308 /* Relocation type for operand */ 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS]; 310 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 312 the base index byte below. */ 313 const reg_entry *base_reg; 314 const reg_entry *index_reg; 315 unsigned int log2_scale_factor; 316 317 /* SEG gives the seg_entries of this insn. They are zero unless 318 explicit segment overrides are given. */ 319 const seg_entry *seg[2]; 320 321 /* PREFIX holds all the given prefix opcodes (usually null). 322 PREFIXES is the number of prefix opcodes. */ 323 unsigned int prefixes; 324 unsigned char prefix[MAX_PREFIXES]; 325 326 /* RM and SIB are the modrm byte and the sib byte where the 327 addressing modes of this insn are encoded. */ 328 modrm_byte rm; 329 rex_byte rex; 330 rex_byte vrex; 331 sib_byte sib; 332 vex_prefix vex; 333 334 /* Masking attributes. */ 335 struct Mask_Operation *mask; 336 337 /* Rounding control and SAE attributes. */ 338 struct RC_Operation *rounding; 339 340 /* Broadcasting attributes. */ 341 struct Broadcast_Operation *broadcast; 342 343 /* Compressed disp8*N attribute. */ 344 unsigned int memshift; 345 346 /* Swap operand in encoding. */ 347 unsigned int swap_operand; 348 349 /* Prefer 8bit or 32bit displacement in encoding. */ 350 enum 351 { 352 disp_encoding_default = 0, 353 disp_encoding_8bit, 354 disp_encoding_32bit 355 } disp_encoding; 356 357 /* REP prefix. */ 358 const char *rep_prefix; 359 360 /* HLE prefix. */ 361 const char *hle_prefix; 362 363 /* Have BND prefix. */ 364 const char *bnd_prefix; 365 366 /* Need VREX to support upper 16 registers. */ 367 int need_vrex; 368 369 /* Error message. */ 370 enum i386_error error; 371 }; 372 373 typedef struct _i386_insn i386_insn; 374 375 /* Link RC type with corresponding string, that'll be looked for in 376 asm. */ 377 struct RC_name 378 { 379 enum rc_type type; 380 const char *name; 381 unsigned int len; 382 }; 383 384 static const struct RC_name RC_NamesTable[] = 385 { 386 { rne, STRING_COMMA_LEN ("rn-sae") }, 387 { rd, STRING_COMMA_LEN ("rd-sae") }, 388 { ru, STRING_COMMA_LEN ("ru-sae") }, 389 { rz, STRING_COMMA_LEN ("rz-sae") }, 390 { saeonly, STRING_COMMA_LEN ("sae") }, 391 }; 392 393 /* List of chars besides those in app.c:symbol_chars that can start an 394 operand. Used to prevent the scrubber eating vital white-space. */ 395 const char extra_symbol_chars[] = "*%-([{" 396 #ifdef LEX_AT 397 "@" 398 #endif 399 #ifdef LEX_QM 400 "?" 401 #endif 402 ; 403 404 #if (defined (TE_I386AIX) \ 405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ 406 && !defined (TE_GNU) \ 407 && !defined (TE_LINUX) \ 408 && !defined (TE_NACL) \ 409 && !defined (TE_NETWARE) \ 410 && !defined (TE_FreeBSD) \ 411 && !defined (TE_DragonFly) \ 412 && !defined (TE_NetBSD))) 413 /* This array holds the chars that always start a comment. If the 414 pre-processor is disabled, these aren't very useful. The option 415 --divide will remove '/' from this list. */ 416 const char *i386_comment_chars = "#/"; 417 #define SVR4_COMMENT_CHARS 1 418 #define PREFIX_SEPARATOR '\\' 419 420 #else 421 const char *i386_comment_chars = "#"; 422 #define PREFIX_SEPARATOR '/' 423 #endif 424 425 /* This array holds the chars that only start a comment at the beginning of 426 a line. If the line seems to have the form '# 123 filename' 427 .line and .file directives will appear in the pre-processed output. 428 Note that input_file.c hand checks for '#' at the beginning of the 429 first line of the input file. This is because the compiler outputs 430 #NO_APP at the beginning of its output. 431 Also note that comments started like this one will always work if 432 '/' isn't otherwise defined. */ 433 const char line_comment_chars[] = "#/"; 434 435 const char line_separator_chars[] = ";"; 436 437 /* Chars that can be used to separate mant from exp in floating point 438 nums. */ 439 const char EXP_CHARS[] = "eE"; 440 441 /* Chars that mean this number is a floating point constant 442 As in 0f12.456 443 or 0d1.2345e12. */ 444 const char FLT_CHARS[] = "fFdDxX"; 445 446 /* Tables for lexical analysis. */ 447 static char mnemonic_chars[256]; 448 static char register_chars[256]; 449 static char operand_chars[256]; 450 static char identifier_chars[256]; 451 static char digit_chars[256]; 452 453 /* Lexical macros. */ 454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 455 #define is_operand_char(x) (operand_chars[(unsigned char) x]) 456 #define is_register_char(x) (register_chars[(unsigned char) x]) 457 #define is_space_char(x) ((x) == ' ') 458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 459 #define is_digit_char(x) (digit_chars[(unsigned char) x]) 460 461 /* All non-digit non-letter characters that may occur in an operand. */ 462 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 463 464 /* md_assemble() always leaves the strings it's passed unaltered. To 465 effect this we maintain a stack of saved characters that we've smashed 466 with '\0's (indicating end of strings for various sub-fields of the 467 assembler instruction). */ 468 static char save_stack[32]; 469 static char *save_stack_p; 470 #define END_STRING_AND_SAVE(s) \ 471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 472 #define RESTORE_END_STRING(s) \ 473 do { *(s) = *--save_stack_p; } while (0) 474 475 /* The instruction we're assembling. */ 476 static i386_insn i; 477 478 /* Possible templates for current insn. */ 479 static const templates *current_templates; 480 481 /* Per instruction expressionS buffers: max displacements & immediates. */ 482 static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; 483 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; 484 485 /* Current operand we are working on. */ 486 static int this_operand = -1; 487 488 /* We support four different modes. FLAG_CODE variable is used to distinguish 489 these. */ 490 491 enum flag_code { 492 CODE_32BIT, 493 CODE_16BIT, 494 CODE_64BIT }; 495 496 static enum flag_code flag_code; 497 static unsigned int object_64bit; 498 static unsigned int disallow_64bit_reloc; 499 static int use_rela_relocations = 0; 500 501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 504 505 /* The ELF ABI to use. */ 506 enum x86_elf_abi 507 { 508 I386_ABI, 509 X86_64_ABI, 510 X86_64_X32_ABI 511 }; 512 513 static enum x86_elf_abi x86_elf_abi = I386_ABI; 514 #endif 515 516 #if defined (TE_PE) || defined (TE_PEP) 517 /* Use big object file format. */ 518 static int use_big_obj = 0; 519 #endif 520 521 /* 1 for intel syntax, 522 0 if att syntax. */ 523 static int intel_syntax = 0; 524 525 /* 1 for intel mnemonic, 526 0 if att mnemonic. */ 527 static int intel_mnemonic = !SYSV386_COMPAT; 528 529 /* 1 if support old (<= 2.8.1) versions of gcc. */ 530 static int old_gcc = OLDGCC_COMPAT; 531 532 /* 1 if pseudo registers are permitted. */ 533 static int allow_pseudo_reg = 0; 534 535 /* 1 if register prefix % not required. */ 536 static int allow_naked_reg = 0; 537 538 /* 1 if the assembler should add BND prefix for all control-tranferring 539 instructions supporting it, even if this prefix wasn't specified 540 explicitly. */ 541 static int add_bnd_prefix = 0; 542 543 /* 1 if pseudo index register, eiz/riz, is allowed . */ 544 static int allow_index_reg = 0; 545 546 /* 1 if the assembler should ignore LOCK prefix, even if it was 547 specified explicitly. */ 548 static int omit_lock_prefix = 0; 549 550 static enum check_kind 551 { 552 check_none = 0, 553 check_warning, 554 check_error 555 } 556 sse_check, operand_check = check_warning; 557 558 /* Register prefix used for error message. */ 559 static const char *register_prefix = "%"; 560 561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, 562 leave, push, and pop instructions so that gcc has the same stack 563 frame as in 32 bit mode. */ 564 static char stackop_size = '\0'; 565 566 /* Non-zero to optimize code alignment. */ 567 int optimize_align_code = 1; 568 569 /* Non-zero to quieten some warnings. */ 570 static int quiet_warnings = 0; 571 572 /* CPU name. */ 573 static const char *cpu_arch_name = NULL; 574 static char *cpu_sub_arch_name = NULL; 575 576 /* CPU feature flags. */ 577 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; 578 579 /* If we have selected a cpu we are generating instructions for. */ 580 static int cpu_arch_tune_set = 0; 581 582 /* Cpu we are generating instructions for. */ 583 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; 584 585 /* CPU feature flags of cpu we are generating instructions for. */ 586 static i386_cpu_flags cpu_arch_tune_flags; 587 588 /* CPU instruction set architecture used. */ 589 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; 590 591 /* CPU feature flags of instruction set architecture used. */ 592 i386_cpu_flags cpu_arch_isa_flags; 593 594 /* If set, conditional jumps are not automatically promoted to handle 595 larger than a byte offset. */ 596 static unsigned int no_cond_jump_promotion = 0; 597 598 /* Encode SSE instructions with VEX prefix. */ 599 static unsigned int sse2avx; 600 601 /* Encode scalar AVX instructions with specific vector length. */ 602 static enum 603 { 604 vex128 = 0, 605 vex256 606 } avxscalar; 607 608 /* Encode scalar EVEX LIG instructions with specific vector length. */ 609 static enum 610 { 611 evexl128 = 0, 612 evexl256, 613 evexl512 614 } evexlig; 615 616 /* Encode EVEX WIG instructions with specific evex.w. */ 617 static enum 618 { 619 evexw0 = 0, 620 evexw1 621 } evexwig; 622 623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */ 624 static enum rc_type evexrcig = rne; 625 626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ 627 static symbolS *GOT_symbol; 628 629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */ 630 unsigned int x86_dwarf2_return_column; 631 632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 633 int x86_cie_data_alignment; 634 635 /* Interface to relax_segment. 636 There are 3 major relax states for 386 jump insns because the 637 different types of jumps add different sizes to frags when we're 638 figuring out what sort of jump to choose to reach a given label. */ 639 640 /* Types. */ 641 #define UNCOND_JUMP 0 642 #define COND_JUMP 1 643 #define COND_JUMP86 2 644 645 /* Sizes. */ 646 #define CODE16 1 647 #define SMALL 0 648 #define SMALL16 (SMALL | CODE16) 649 #define BIG 2 650 #define BIG16 (BIG | CODE16) 651 652 #ifndef INLINE 653 #ifdef __GNUC__ 654 #define INLINE __inline__ 655 #else 656 #define INLINE 657 #endif 658 #endif 659 660 #define ENCODE_RELAX_STATE(type, size) \ 661 ((relax_substateT) (((type) << 2) | (size))) 662 #define TYPE_FROM_RELAX_STATE(s) \ 663 ((s) >> 2) 664 #define DISP_SIZE_FROM_RELAX_STATE(s) \ 665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) 666 667 /* This table is used by relax_frag to promote short jumps to long 668 ones where necessary. SMALL (short) jumps may be promoted to BIG 669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 670 don't allow a short jump in a 32 bit code segment to be promoted to 671 a 16 bit offset jump because it's slower (requires data size 672 prefix), and doesn't work, unless the destination is in the bottom 673 64k of the code segment (The top 16 bits of eip are zeroed). */ 674 675 const relax_typeS md_relax_table[] = 676 { 677 /* The fields are: 678 1) most positive reach of this state, 679 2) most negative reach of this state, 680 3) how many bytes this mode will have in the variable part of the frag 681 4) which index into the table to try if we can't fit into this one. */ 682 683 /* UNCOND_JUMP states. */ 684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 686 /* dword jmp adds 4 bytes to frag: 687 0 extra opcode bytes, 4 displacement bytes. */ 688 {0, 0, 4, 0}, 689 /* word jmp adds 2 byte2 to frag: 690 0 extra opcode bytes, 2 displacement bytes. */ 691 {0, 0, 2, 0}, 692 693 /* COND_JUMP states. */ 694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 696 /* dword conditionals adds 5 bytes to frag: 697 1 extra opcode byte, 4 displacement bytes. */ 698 {0, 0, 5, 0}, 699 /* word conditionals add 3 bytes to frag: 700 1 extra opcode byte, 2 displacement bytes. */ 701 {0, 0, 3, 0}, 702 703 /* COND_JUMP86 states. */ 704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, 705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, 706 /* dword conditionals adds 5 bytes to frag: 707 1 extra opcode byte, 4 displacement bytes. */ 708 {0, 0, 5, 0}, 709 /* word conditionals add 4 bytes to frag: 710 1 displacement byte and a 3 byte long branch insn. */ 711 {0, 0, 4, 0} 712 }; 713 714 static const arch_entry cpu_arch[] = 715 { 716 /* Do not replace the first two entries - i386_target_format() 717 relies on them being there in this order. */ 718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, 719 CPU_GENERIC32_FLAGS, 0, 0 }, 720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, 721 CPU_GENERIC64_FLAGS, 0, 0 }, 722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, 723 CPU_NONE_FLAGS, 0, 0 }, 724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, 725 CPU_I186_FLAGS, 0, 0 }, 726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, 727 CPU_I286_FLAGS, 0, 0 }, 728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, 729 CPU_I386_FLAGS, 0, 0 }, 730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, 731 CPU_I486_FLAGS, 0, 0 }, 732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, 733 CPU_I586_FLAGS, 0, 0 }, 734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, 735 CPU_I686_FLAGS, 0, 0 }, 736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, 737 CPU_I586_FLAGS, 0, 0 }, 738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, 739 CPU_PENTIUMPRO_FLAGS, 0, 0 }, 740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, 741 CPU_P2_FLAGS, 0, 0 }, 742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, 743 CPU_P3_FLAGS, 0, 0 }, 744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, 745 CPU_P4_FLAGS, 0, 0 }, 746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, 747 CPU_CORE_FLAGS, 0, 0 }, 748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, 749 CPU_NOCONA_FLAGS, 0, 0 }, 750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, 751 CPU_CORE_FLAGS, 1, 0 }, 752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, 753 CPU_CORE_FLAGS, 0, 0 }, 754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, 755 CPU_CORE2_FLAGS, 1, 0 }, 756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, 757 CPU_CORE2_FLAGS, 0, 0 }, 758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, 759 CPU_COREI7_FLAGS, 0, 0 }, 760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, 761 CPU_L1OM_FLAGS, 0, 0 }, 762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, 763 CPU_K1OM_FLAGS, 0, 0 }, 764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, 765 CPU_K6_FLAGS, 0, 0 }, 766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, 767 CPU_K6_2_FLAGS, 0, 0 }, 768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, 769 CPU_ATHLON_FLAGS, 0, 0 }, 770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, 771 CPU_K8_FLAGS, 1, 0 }, 772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, 773 CPU_K8_FLAGS, 0, 0 }, 774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, 775 CPU_K8_FLAGS, 0, 0 }, 776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, 777 CPU_AMDFAM10_FLAGS, 0, 0 }, 778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, 779 CPU_BDVER1_FLAGS, 0, 0 }, 780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, 781 CPU_BDVER2_FLAGS, 0, 0 }, 782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, 783 CPU_BDVER3_FLAGS, 0, 0 }, 784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, 785 CPU_BDVER4_FLAGS, 0, 0 }, 786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, 787 CPU_BTVER1_FLAGS, 0, 0 }, 788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, 789 CPU_BTVER2_FLAGS, 0, 0 }, 790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, 791 CPU_8087_FLAGS, 0, 0 }, 792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, 793 CPU_287_FLAGS, 0, 0 }, 794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, 795 CPU_387_FLAGS, 0, 0 }, 796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, 797 CPU_ANY87_FLAGS, 0, 1 }, 798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, 799 CPU_MMX_FLAGS, 0, 0 }, 800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, 801 CPU_3DNOWA_FLAGS, 0, 1 }, 802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, 803 CPU_SSE_FLAGS, 0, 0 }, 804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, 805 CPU_SSE2_FLAGS, 0, 0 }, 806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, 807 CPU_SSE3_FLAGS, 0, 0 }, 808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, 809 CPU_SSSE3_FLAGS, 0, 0 }, 810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, 811 CPU_SSE4_1_FLAGS, 0, 0 }, 812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, 813 CPU_SSE4_2_FLAGS, 0, 0 }, 814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, 815 CPU_SSE4_2_FLAGS, 0, 0 }, 816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, 817 CPU_ANY_SSE_FLAGS, 0, 1 }, 818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, 819 CPU_AVX_FLAGS, 0, 0 }, 820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, 821 CPU_AVX2_FLAGS, 0, 0 }, 822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, 823 CPU_AVX512F_FLAGS, 0, 0 }, 824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, 825 CPU_AVX512CD_FLAGS, 0, 0 }, 826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, 827 CPU_AVX512ER_FLAGS, 0, 0 }, 828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, 829 CPU_AVX512PF_FLAGS, 0, 0 }, 830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, 831 CPU_AVX512DQ_FLAGS, 0, 0 }, 832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, 833 CPU_AVX512BW_FLAGS, 0, 0 }, 834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, 835 CPU_AVX512VL_FLAGS, 0, 0 }, 836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, 837 CPU_ANY_AVX_FLAGS, 0, 1 }, 838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, 839 CPU_VMX_FLAGS, 0, 0 }, 840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, 841 CPU_VMFUNC_FLAGS, 0, 0 }, 842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, 843 CPU_SMX_FLAGS, 0, 0 }, 844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, 845 CPU_XSAVE_FLAGS, 0, 0 }, 846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, 847 CPU_XSAVEOPT_FLAGS, 0, 0 }, 848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, 849 CPU_XSAVEC_FLAGS, 0, 0 }, 850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, 851 CPU_XSAVES_FLAGS, 0, 0 }, 852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, 853 CPU_AES_FLAGS, 0, 0 }, 854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, 855 CPU_PCLMUL_FLAGS, 0, 0 }, 856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, 857 CPU_PCLMUL_FLAGS, 1, 0 }, 858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, 859 CPU_FSGSBASE_FLAGS, 0, 0 }, 860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, 861 CPU_RDRND_FLAGS, 0, 0 }, 862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, 863 CPU_F16C_FLAGS, 0, 0 }, 864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, 865 CPU_BMI2_FLAGS, 0, 0 }, 866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, 867 CPU_FMA_FLAGS, 0, 0 }, 868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, 869 CPU_FMA4_FLAGS, 0, 0 }, 870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, 871 CPU_XOP_FLAGS, 0, 0 }, 872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, 873 CPU_LWP_FLAGS, 0, 0 }, 874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, 875 CPU_MOVBE_FLAGS, 0, 0 }, 876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, 877 CPU_CX16_FLAGS, 0, 0 }, 878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, 879 CPU_EPT_FLAGS, 0, 0 }, 880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, 881 CPU_LZCNT_FLAGS, 0, 0 }, 882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, 883 CPU_HLE_FLAGS, 0, 0 }, 884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, 885 CPU_RTM_FLAGS, 0, 0 }, 886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, 887 CPU_INVPCID_FLAGS, 0, 0 }, 888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, 889 CPU_CLFLUSH_FLAGS, 0, 0 }, 890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, 891 CPU_NOP_FLAGS, 0, 0 }, 892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, 893 CPU_SYSCALL_FLAGS, 0, 0 }, 894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, 895 CPU_RDTSCP_FLAGS, 0, 0 }, 896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, 897 CPU_3DNOW_FLAGS, 0, 0 }, 898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, 899 CPU_3DNOWA_FLAGS, 0, 0 }, 900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, 901 CPU_PADLOCK_FLAGS, 0, 0 }, 902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, 903 CPU_SVME_FLAGS, 1, 0 }, 904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, 905 CPU_SVME_FLAGS, 0, 0 }, 906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, 907 CPU_SSE4A_FLAGS, 0, 0 }, 908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, 909 CPU_ABM_FLAGS, 0, 0 }, 910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, 911 CPU_BMI_FLAGS, 0, 0 }, 912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, 913 CPU_TBM_FLAGS, 0, 0 }, 914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, 915 CPU_ADX_FLAGS, 0, 0 }, 916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, 917 CPU_RDSEED_FLAGS, 0, 0 }, 918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, 919 CPU_PRFCHW_FLAGS, 0, 0 }, 920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, 921 CPU_SMAP_FLAGS, 0, 0 }, 922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, 923 CPU_MPX_FLAGS, 0, 0 }, 924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, 925 CPU_SHA_FLAGS, 0, 0 }, 926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, 927 CPU_CLFLUSHOPT_FLAGS, 0, 0 }, 928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, 929 CPU_PREFETCHWT1_FLAGS, 0, 0 }, 930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, 931 CPU_SE1_FLAGS, 0, 0 }, 932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, 933 CPU_CLWB_FLAGS, 0, 0 }, 934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN, 935 CPU_PCOMMIT_FLAGS, 0, 0 }, 936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, 937 CPU_AVX512IFMA_FLAGS, 0, 0 }, 938 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, 939 CPU_AVX512VBMI_FLAGS, 0, 0 }, 940 }; 941 942 #ifdef I386COFF 943 /* Like s_lcomm_internal in gas/read.c but the alignment string 944 is allowed to be optional. */ 945 946 static symbolS * 947 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) 948 { 949 addressT align = 0; 950 951 SKIP_WHITESPACE (); 952 953 if (needs_align 954 && *input_line_pointer == ',') 955 { 956 align = parse_align (needs_align - 1); 957 958 if (align == (addressT) -1) 959 return NULL; 960 } 961 else 962 { 963 if (size >= 8) 964 align = 3; 965 else if (size >= 4) 966 align = 2; 967 else if (size >= 2) 968 align = 1; 969 else 970 align = 0; 971 } 972 973 bss_alloc (symbolP, size, align); 974 return symbolP; 975 } 976 977 static void 978 pe_lcomm (int needs_align) 979 { 980 s_comm_internal (needs_align * 2, pe_lcomm_internal); 981 } 982 #endif 983 984 const pseudo_typeS md_pseudo_table[] = 985 { 986 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 987 {"align", s_align_bytes, 0}, 988 #else 989 {"align", s_align_ptwo, 0}, 990 #endif 991 {"arch", set_cpu_arch, 0}, 992 #ifndef I386COFF 993 {"bss", s_bss, 0}, 994 #else 995 {"lcomm", pe_lcomm, 1}, 996 #endif 997 {"ffloat", float_cons, 'f'}, 998 {"dfloat", float_cons, 'd'}, 999 {"tfloat", float_cons, 'x'}, 1000 {"value", cons, 2}, 1001 {"slong", signed_cons, 4}, 1002 {"noopt", s_ignore, 0}, 1003 {"optim", s_ignore, 0}, 1004 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, 1005 {"code16", set_code_flag, CODE_16BIT}, 1006 {"code32", set_code_flag, CODE_32BIT}, 1007 {"code64", set_code_flag, CODE_64BIT}, 1008 {"intel_syntax", set_intel_syntax, 1}, 1009 {"att_syntax", set_intel_syntax, 0}, 1010 {"intel_mnemonic", set_intel_mnemonic, 1}, 1011 {"att_mnemonic", set_intel_mnemonic, 0}, 1012 {"allow_index_reg", set_allow_index_reg, 1}, 1013 {"disallow_index_reg", set_allow_index_reg, 0}, 1014 {"sse_check", set_check, 0}, 1015 {"operand_check", set_check, 1}, 1016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1017 {"largecomm", handle_large_common, 0}, 1018 #else 1019 {"file", (void (*) (int)) dwarf2_directive_file, 0}, 1020 {"loc", dwarf2_directive_loc, 0}, 1021 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, 1022 #endif 1023 #ifdef TE_PE 1024 {"secrel32", pe_directive_secrel, 0}, 1025 #endif 1026 {0, 0, 0} 1027 }; 1028 1029 /* For interface with expression (). */ 1030 extern char *input_line_pointer; 1031 1032 /* Hash table for instruction mnemonic lookup. */ 1033 static struct hash_control *op_hash; 1034 1035 /* Hash table for register lookup. */ 1036 static struct hash_control *reg_hash; 1037 1038 void 1040 i386_align_code (fragS *fragP, int count) 1041 { 1042 /* Various efficient no-op patterns for aligning code labels. 1043 Note: Don't try to assemble the instructions in the comments. 1044 0L and 0w are not legal. */ 1045 static const char f32_1[] = 1046 {0x90}; /* nop */ 1047 static const char f32_2[] = 1048 {0x66,0x90}; /* xchg %ax,%ax */ 1049 static const char f32_3[] = 1050 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 1051 static const char f32_4[] = 1052 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 1053 static const char f32_5[] = 1054 {0x90, /* nop */ 1055 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 1056 static const char f32_6[] = 1057 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 1058 static const char f32_7[] = 1059 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 1060 static const char f32_8[] = 1061 {0x90, /* nop */ 1062 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 1063 static const char f32_9[] = 1064 {0x89,0xf6, /* movl %esi,%esi */ 1065 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1066 static const char f32_10[] = 1067 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1069 static const char f32_11[] = 1070 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 1071 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1072 static const char f32_12[] = 1073 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 1074 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 1075 static const char f32_13[] = 1076 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1078 static const char f32_14[] = 1079 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 1081 static const char f16_3[] = 1082 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 1083 static const char f16_4[] = 1084 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 1085 static const char f16_5[] = 1086 {0x90, /* nop */ 1087 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 1088 static const char f16_6[] = 1089 {0x89,0xf6, /* mov %si,%si */ 1090 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 1091 static const char f16_7[] = 1092 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 1093 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 1094 static const char f16_8[] = 1095 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 1096 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 1097 static const char jump_31[] = 1098 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ 1099 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 1100 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 1101 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 1102 static const char *const f32_patt[] = { 1103 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 1104 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 1105 }; 1106 static const char *const f16_patt[] = { 1107 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 1108 }; 1109 /* nopl (%[re]ax) */ 1110 static const char alt_3[] = 1111 {0x0f,0x1f,0x00}; 1112 /* nopl 0(%[re]ax) */ 1113 static const char alt_4[] = 1114 {0x0f,0x1f,0x40,0x00}; 1115 /* nopl 0(%[re]ax,%[re]ax,1) */ 1116 static const char alt_5[] = 1117 {0x0f,0x1f,0x44,0x00,0x00}; 1118 /* nopw 0(%[re]ax,%[re]ax,1) */ 1119 static const char alt_6[] = 1120 {0x66,0x0f,0x1f,0x44,0x00,0x00}; 1121 /* nopl 0L(%[re]ax) */ 1122 static const char alt_7[] = 1123 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 1124 /* nopl 0L(%[re]ax,%[re]ax,1) */ 1125 static const char alt_8[] = 1126 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1127 /* nopw 0L(%[re]ax,%[re]ax,1) */ 1128 static const char alt_9[] = 1129 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1130 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1131 static const char alt_10[] = 1132 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1133 /* data16 1134 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1135 static const char alt_long_11[] = 1136 {0x66, 1137 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1138 /* data16 1139 data16 1140 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1141 static const char alt_long_12[] = 1142 {0x66, 1143 0x66, 1144 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1145 /* data16 1146 data16 1147 data16 1148 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1149 static const char alt_long_13[] = 1150 {0x66, 1151 0x66, 1152 0x66, 1153 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1154 /* data16 1155 data16 1156 data16 1157 data16 1158 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1159 static const char alt_long_14[] = 1160 {0x66, 1161 0x66, 1162 0x66, 1163 0x66, 1164 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1165 /* data16 1166 data16 1167 data16 1168 data16 1169 data16 1170 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1171 static const char alt_long_15[] = 1172 {0x66, 1173 0x66, 1174 0x66, 1175 0x66, 1176 0x66, 1177 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1178 /* nopl 0(%[re]ax,%[re]ax,1) 1179 nopw 0(%[re]ax,%[re]ax,1) */ 1180 static const char alt_short_11[] = 1181 {0x0f,0x1f,0x44,0x00,0x00, 1182 0x66,0x0f,0x1f,0x44,0x00,0x00}; 1183 /* nopw 0(%[re]ax,%[re]ax,1) 1184 nopw 0(%[re]ax,%[re]ax,1) */ 1185 static const char alt_short_12[] = 1186 {0x66,0x0f,0x1f,0x44,0x00,0x00, 1187 0x66,0x0f,0x1f,0x44,0x00,0x00}; 1188 /* nopw 0(%[re]ax,%[re]ax,1) 1189 nopl 0L(%[re]ax) */ 1190 static const char alt_short_13[] = 1191 {0x66,0x0f,0x1f,0x44,0x00,0x00, 1192 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 1193 /* nopl 0L(%[re]ax) 1194 nopl 0L(%[re]ax) */ 1195 static const char alt_short_14[] = 1196 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, 1197 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 1198 /* nopl 0L(%[re]ax) 1199 nopl 0L(%[re]ax,%[re]ax,1) */ 1200 static const char alt_short_15[] = 1201 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, 1202 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1203 static const char *const alt_short_patt[] = { 1204 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, 1205 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, 1206 alt_short_14, alt_short_15 1207 }; 1208 static const char *const alt_long_patt[] = { 1209 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, 1210 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, 1211 alt_long_14, alt_long_15 1212 }; 1213 1214 /* Only align for at least a positive non-zero boundary. */ 1215 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) 1216 return; 1217 1218 /* We need to decide which NOP sequence to use for 32bit and 1219 64bit. When -mtune= is used: 1220 1221 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and 1222 PROCESSOR_GENERIC32, f32_patt will be used. 1223 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, 1224 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and 1225 PROCESSOR_GENERIC64, alt_long_patt will be used. 1226 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and 1227 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt 1228 will be used. 1229 1230 When -mtune= isn't used, alt_long_patt will be used if 1231 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will 1232 be used. 1233 1234 When -march= or .arch is used, we can't use anything beyond 1235 cpu_arch_isa_flags. */ 1236 1237 if (flag_code == CODE_16BIT) 1238 { 1239 if (count > 8) 1240 { 1241 memcpy (fragP->fr_literal + fragP->fr_fix, 1242 jump_31, count); 1243 /* Adjust jump offset. */ 1244 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 1245 } 1246 else 1247 memcpy (fragP->fr_literal + fragP->fr_fix, 1248 f16_patt[count - 1], count); 1249 } 1250 else 1251 { 1252 const char *const *patt = NULL; 1253 1254 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) 1255 { 1256 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ 1257 switch (cpu_arch_tune) 1258 { 1259 case PROCESSOR_UNKNOWN: 1260 /* We use cpu_arch_isa_flags to check if we SHOULD 1261 optimize with nops. */ 1262 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1263 patt = alt_long_patt; 1264 else 1265 patt = f32_patt; 1266 break; 1267 case PROCESSOR_PENTIUM4: 1268 case PROCESSOR_NOCONA: 1269 case PROCESSOR_CORE: 1270 case PROCESSOR_CORE2: 1271 case PROCESSOR_COREI7: 1272 case PROCESSOR_L1OM: 1273 case PROCESSOR_K1OM: 1274 case PROCESSOR_GENERIC64: 1275 patt = alt_long_patt; 1276 break; 1277 case PROCESSOR_K6: 1278 case PROCESSOR_ATHLON: 1279 case PROCESSOR_K8: 1280 case PROCESSOR_AMDFAM10: 1281 case PROCESSOR_BD: 1282 case PROCESSOR_BT: 1283 patt = alt_short_patt; 1284 break; 1285 case PROCESSOR_I386: 1286 case PROCESSOR_I486: 1287 case PROCESSOR_PENTIUM: 1288 case PROCESSOR_PENTIUMPRO: 1289 case PROCESSOR_GENERIC32: 1290 patt = f32_patt; 1291 break; 1292 } 1293 } 1294 else 1295 { 1296 switch (fragP->tc_frag_data.tune) 1297 { 1298 case PROCESSOR_UNKNOWN: 1299 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be 1300 PROCESSOR_UNKNOWN. */ 1301 abort (); 1302 break; 1303 1304 case PROCESSOR_I386: 1305 case PROCESSOR_I486: 1306 case PROCESSOR_PENTIUM: 1307 case PROCESSOR_K6: 1308 case PROCESSOR_ATHLON: 1309 case PROCESSOR_K8: 1310 case PROCESSOR_AMDFAM10: 1311 case PROCESSOR_BD: 1312 case PROCESSOR_BT: 1313 case PROCESSOR_GENERIC32: 1314 /* We use cpu_arch_isa_flags to check if we CAN optimize 1315 with nops. */ 1316 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1317 patt = alt_short_patt; 1318 else 1319 patt = f32_patt; 1320 break; 1321 case PROCESSOR_PENTIUMPRO: 1322 case PROCESSOR_PENTIUM4: 1323 case PROCESSOR_NOCONA: 1324 case PROCESSOR_CORE: 1325 case PROCESSOR_CORE2: 1326 case PROCESSOR_COREI7: 1327 case PROCESSOR_L1OM: 1328 case PROCESSOR_K1OM: 1329 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1330 patt = alt_long_patt; 1331 else 1332 patt = f32_patt; 1333 break; 1334 case PROCESSOR_GENERIC64: 1335 patt = alt_long_patt; 1336 break; 1337 } 1338 } 1339 1340 if (patt == f32_patt) 1341 { 1342 /* If the padding is less than 15 bytes, we use the normal 1343 ones. Otherwise, we use a jump instruction and adjust 1344 its offset. */ 1345 int limit; 1346 1347 /* For 64bit, the limit is 3 bytes. */ 1348 if (flag_code == CODE_64BIT 1349 && fragP->tc_frag_data.isa_flags.bitfield.cpulm) 1350 limit = 3; 1351 else 1352 limit = 15; 1353 if (count < limit) 1354 memcpy (fragP->fr_literal + fragP->fr_fix, 1355 patt[count - 1], count); 1356 else 1357 { 1358 memcpy (fragP->fr_literal + fragP->fr_fix, 1359 jump_31, count); 1360 /* Adjust jump offset. */ 1361 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 1362 } 1363 } 1364 else 1365 { 1366 /* Maximum length of an instruction is 15 byte. If the 1367 padding is greater than 15 bytes and we don't use jump, 1368 we have to break it into smaller pieces. */ 1369 int padding = count; 1370 while (padding > 15) 1371 { 1372 padding -= 15; 1373 memcpy (fragP->fr_literal + fragP->fr_fix + padding, 1374 patt [14], 15); 1375 } 1376 1377 if (padding) 1378 memcpy (fragP->fr_literal + fragP->fr_fix, 1379 patt [padding - 1], padding); 1380 } 1381 } 1382 fragP->fr_var = count; 1383 } 1384 1385 static INLINE int 1386 operand_type_all_zero (const union i386_operand_type *x) 1387 { 1388 switch (ARRAY_SIZE(x->array)) 1389 { 1390 case 3: 1391 if (x->array[2]) 1392 return 0; 1393 case 2: 1394 if (x->array[1]) 1395 return 0; 1396 case 1: 1397 return !x->array[0]; 1398 default: 1399 abort (); 1400 } 1401 } 1402 1403 static INLINE void 1404 operand_type_set (union i386_operand_type *x, unsigned int v) 1405 { 1406 switch (ARRAY_SIZE(x->array)) 1407 { 1408 case 3: 1409 x->array[2] = v; 1410 case 2: 1411 x->array[1] = v; 1412 case 1: 1413 x->array[0] = v; 1414 break; 1415 default: 1416 abort (); 1417 } 1418 } 1419 1420 static INLINE int 1421 operand_type_equal (const union i386_operand_type *x, 1422 const union i386_operand_type *y) 1423 { 1424 switch (ARRAY_SIZE(x->array)) 1425 { 1426 case 3: 1427 if (x->array[2] != y->array[2]) 1428 return 0; 1429 case 2: 1430 if (x->array[1] != y->array[1]) 1431 return 0; 1432 case 1: 1433 return x->array[0] == y->array[0]; 1434 break; 1435 default: 1436 abort (); 1437 } 1438 } 1439 1440 static INLINE int 1441 cpu_flags_all_zero (const union i386_cpu_flags *x) 1442 { 1443 switch (ARRAY_SIZE(x->array)) 1444 { 1445 case 3: 1446 if (x->array[2]) 1447 return 0; 1448 case 2: 1449 if (x->array[1]) 1450 return 0; 1451 case 1: 1452 return !x->array[0]; 1453 default: 1454 abort (); 1455 } 1456 } 1457 1458 static INLINE void 1459 cpu_flags_set (union i386_cpu_flags *x, unsigned int v) 1460 { 1461 switch (ARRAY_SIZE(x->array)) 1462 { 1463 case 3: 1464 x->array[2] = v; 1465 case 2: 1466 x->array[1] = v; 1467 case 1: 1468 x->array[0] = v; 1469 break; 1470 default: 1471 abort (); 1472 } 1473 } 1474 1475 static INLINE int 1476 cpu_flags_equal (const union i386_cpu_flags *x, 1477 const union i386_cpu_flags *y) 1478 { 1479 switch (ARRAY_SIZE(x->array)) 1480 { 1481 case 3: 1482 if (x->array[2] != y->array[2]) 1483 return 0; 1484 case 2: 1485 if (x->array[1] != y->array[1]) 1486 return 0; 1487 case 1: 1488 return x->array[0] == y->array[0]; 1489 break; 1490 default: 1491 abort (); 1492 } 1493 } 1494 1495 static INLINE int 1496 cpu_flags_check_cpu64 (i386_cpu_flags f) 1497 { 1498 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) 1499 || (flag_code != CODE_64BIT && f.bitfield.cpu64)); 1500 } 1501 1502 static INLINE i386_cpu_flags 1503 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) 1504 { 1505 switch (ARRAY_SIZE (x.array)) 1506 { 1507 case 3: 1508 x.array [2] &= y.array [2]; 1509 case 2: 1510 x.array [1] &= y.array [1]; 1511 case 1: 1512 x.array [0] &= y.array [0]; 1513 break; 1514 default: 1515 abort (); 1516 } 1517 return x; 1518 } 1519 1520 static INLINE i386_cpu_flags 1521 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) 1522 { 1523 switch (ARRAY_SIZE (x.array)) 1524 { 1525 case 3: 1526 x.array [2] |= y.array [2]; 1527 case 2: 1528 x.array [1] |= y.array [1]; 1529 case 1: 1530 x.array [0] |= y.array [0]; 1531 break; 1532 default: 1533 abort (); 1534 } 1535 return x; 1536 } 1537 1538 static INLINE i386_cpu_flags 1539 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) 1540 { 1541 switch (ARRAY_SIZE (x.array)) 1542 { 1543 case 3: 1544 x.array [2] &= ~y.array [2]; 1545 case 2: 1546 x.array [1] &= ~y.array [1]; 1547 case 1: 1548 x.array [0] &= ~y.array [0]; 1549 break; 1550 default: 1551 abort (); 1552 } 1553 return x; 1554 } 1555 1556 #define CPU_FLAGS_ARCH_MATCH 0x1 1557 #define CPU_FLAGS_64BIT_MATCH 0x2 1558 #define CPU_FLAGS_AES_MATCH 0x4 1559 #define CPU_FLAGS_PCLMUL_MATCH 0x8 1560 #define CPU_FLAGS_AVX_MATCH 0x10 1561 1562 #define CPU_FLAGS_32BIT_MATCH \ 1563 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ 1564 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) 1565 #define CPU_FLAGS_PERFECT_MATCH \ 1566 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) 1567 1568 /* Return CPU flags match bits. */ 1569 1570 static int 1571 cpu_flags_match (const insn_template *t) 1572 { 1573 i386_cpu_flags x = t->cpu_flags; 1574 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; 1575 1576 x.bitfield.cpu64 = 0; 1577 x.bitfield.cpuno64 = 0; 1578 1579 if (cpu_flags_all_zero (&x)) 1580 { 1581 /* This instruction is available on all archs. */ 1582 match |= CPU_FLAGS_32BIT_MATCH; 1583 } 1584 else 1585 { 1586 /* This instruction is available only on some archs. */ 1587 i386_cpu_flags cpu = cpu_arch_flags; 1588 1589 cpu.bitfield.cpu64 = 0; 1590 cpu.bitfield.cpuno64 = 0; 1591 cpu = cpu_flags_and (x, cpu); 1592 if (!cpu_flags_all_zero (&cpu)) 1593 { 1594 if (x.bitfield.cpuavx) 1595 { 1596 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ 1597 if (cpu.bitfield.cpuavx) 1598 { 1599 /* Check SSE2AVX. */ 1600 if (!t->opcode_modifier.sse2avx|| sse2avx) 1601 { 1602 match |= (CPU_FLAGS_ARCH_MATCH 1603 | CPU_FLAGS_AVX_MATCH); 1604 /* Check AES. */ 1605 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) 1606 match |= CPU_FLAGS_AES_MATCH; 1607 /* Check PCLMUL. */ 1608 if (!x.bitfield.cpupclmul 1609 || cpu.bitfield.cpupclmul) 1610 match |= CPU_FLAGS_PCLMUL_MATCH; 1611 } 1612 } 1613 else 1614 match |= CPU_FLAGS_ARCH_MATCH; 1615 } 1616 else 1617 match |= CPU_FLAGS_32BIT_MATCH; 1618 } 1619 } 1620 return match; 1621 } 1622 1623 static INLINE i386_operand_type 1624 operand_type_and (i386_operand_type x, i386_operand_type y) 1625 { 1626 switch (ARRAY_SIZE (x.array)) 1627 { 1628 case 3: 1629 x.array [2] &= y.array [2]; 1630 case 2: 1631 x.array [1] &= y.array [1]; 1632 case 1: 1633 x.array [0] &= y.array [0]; 1634 break; 1635 default: 1636 abort (); 1637 } 1638 return x; 1639 } 1640 1641 static INLINE i386_operand_type 1642 operand_type_or (i386_operand_type x, i386_operand_type y) 1643 { 1644 switch (ARRAY_SIZE (x.array)) 1645 { 1646 case 3: 1647 x.array [2] |= y.array [2]; 1648 case 2: 1649 x.array [1] |= y.array [1]; 1650 case 1: 1651 x.array [0] |= y.array [0]; 1652 break; 1653 default: 1654 abort (); 1655 } 1656 return x; 1657 } 1658 1659 static INLINE i386_operand_type 1660 operand_type_xor (i386_operand_type x, i386_operand_type y) 1661 { 1662 switch (ARRAY_SIZE (x.array)) 1663 { 1664 case 3: 1665 x.array [2] ^= y.array [2]; 1666 case 2: 1667 x.array [1] ^= y.array [1]; 1668 case 1: 1669 x.array [0] ^= y.array [0]; 1670 break; 1671 default: 1672 abort (); 1673 } 1674 return x; 1675 } 1676 1677 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; 1678 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; 1679 static const i386_operand_type control = OPERAND_TYPE_CONTROL; 1680 static const i386_operand_type inoutportreg 1681 = OPERAND_TYPE_INOUTPORTREG; 1682 static const i386_operand_type reg16_inoutportreg 1683 = OPERAND_TYPE_REG16_INOUTPORTREG; 1684 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; 1685 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; 1686 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; 1687 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; 1688 static const i386_operand_type anydisp 1689 = OPERAND_TYPE_ANYDISP; 1690 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; 1691 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; 1692 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM; 1693 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; 1694 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; 1695 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; 1696 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; 1697 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; 1698 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; 1699 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; 1700 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; 1701 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; 1702 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; 1703 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; 1704 1705 enum operand_type 1706 { 1707 reg, 1708 imm, 1709 disp, 1710 anymem 1711 }; 1712 1713 static INLINE int 1714 operand_type_check (i386_operand_type t, enum operand_type c) 1715 { 1716 switch (c) 1717 { 1718 case reg: 1719 return (t.bitfield.reg8 1720 || t.bitfield.reg16 1721 || t.bitfield.reg32 1722 || t.bitfield.reg64); 1723 1724 case imm: 1725 return (t.bitfield.imm8 1726 || t.bitfield.imm8s 1727 || t.bitfield.imm16 1728 || t.bitfield.imm32 1729 || t.bitfield.imm32s 1730 || t.bitfield.imm64); 1731 1732 case disp: 1733 return (t.bitfield.disp8 1734 || t.bitfield.disp16 1735 || t.bitfield.disp32 1736 || t.bitfield.disp32s 1737 || t.bitfield.disp64); 1738 1739 case anymem: 1740 return (t.bitfield.disp8 1741 || t.bitfield.disp16 1742 || t.bitfield.disp32 1743 || t.bitfield.disp32s 1744 || t.bitfield.disp64 1745 || t.bitfield.baseindex); 1746 1747 default: 1748 abort (); 1749 } 1750 1751 return 0; 1752 } 1753 1754 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on 1755 operand J for instruction template T. */ 1756 1757 static INLINE int 1758 match_reg_size (const insn_template *t, unsigned int j) 1759 { 1760 return !((i.types[j].bitfield.byte 1761 && !t->operand_types[j].bitfield.byte) 1762 || (i.types[j].bitfield.word 1763 && !t->operand_types[j].bitfield.word) 1764 || (i.types[j].bitfield.dword 1765 && !t->operand_types[j].bitfield.dword) 1766 || (i.types[j].bitfield.qword 1767 && !t->operand_types[j].bitfield.qword)); 1768 } 1769 1770 /* Return 1 if there is no conflict in any size on operand J for 1771 instruction template T. */ 1772 1773 static INLINE int 1774 match_mem_size (const insn_template *t, unsigned int j) 1775 { 1776 return (match_reg_size (t, j) 1777 && !((i.types[j].bitfield.unspecified 1778 && !t->operand_types[j].bitfield.unspecified) 1779 || (i.types[j].bitfield.fword 1780 && !t->operand_types[j].bitfield.fword) 1781 || (i.types[j].bitfield.tbyte 1782 && !t->operand_types[j].bitfield.tbyte) 1783 || (i.types[j].bitfield.xmmword 1784 && !t->operand_types[j].bitfield.xmmword) 1785 || (i.types[j].bitfield.ymmword 1786 && !t->operand_types[j].bitfield.ymmword) 1787 || (i.types[j].bitfield.zmmword 1788 && !t->operand_types[j].bitfield.zmmword))); 1789 } 1790 1791 /* Return 1 if there is no size conflict on any operands for 1792 instruction template T. */ 1793 1794 static INLINE int 1795 operand_size_match (const insn_template *t) 1796 { 1797 unsigned int j; 1798 int match = 1; 1799 1800 /* Don't check jump instructions. */ 1801 if (t->opcode_modifier.jump 1802 || t->opcode_modifier.jumpbyte 1803 || t->opcode_modifier.jumpdword 1804 || t->opcode_modifier.jumpintersegment) 1805 return match; 1806 1807 /* Check memory and accumulator operand size. */ 1808 for (j = 0; j < i.operands; j++) 1809 { 1810 if (t->operand_types[j].bitfield.anysize) 1811 continue; 1812 1813 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) 1814 { 1815 match = 0; 1816 break; 1817 } 1818 1819 if (i.types[j].bitfield.mem && !match_mem_size (t, j)) 1820 { 1821 match = 0; 1822 break; 1823 } 1824 } 1825 1826 if (match) 1827 return match; 1828 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) 1829 { 1830 mismatch: 1831 i.error = operand_size_mismatch; 1832 return 0; 1833 } 1834 1835 /* Check reverse. */ 1836 gas_assert (i.operands == 2); 1837 1838 match = 1; 1839 for (j = 0; j < 2; j++) 1840 { 1841 if (t->operand_types[j].bitfield.acc 1842 && !match_reg_size (t, j ? 0 : 1)) 1843 goto mismatch; 1844 1845 if (i.types[j].bitfield.mem 1846 && !match_mem_size (t, j ? 0 : 1)) 1847 goto mismatch; 1848 } 1849 1850 return match; 1851 } 1852 1853 static INLINE int 1854 operand_type_match (i386_operand_type overlap, 1855 i386_operand_type given) 1856 { 1857 i386_operand_type temp = overlap; 1858 1859 temp.bitfield.jumpabsolute = 0; 1860 temp.bitfield.unspecified = 0; 1861 temp.bitfield.byte = 0; 1862 temp.bitfield.word = 0; 1863 temp.bitfield.dword = 0; 1864 temp.bitfield.fword = 0; 1865 temp.bitfield.qword = 0; 1866 temp.bitfield.tbyte = 0; 1867 temp.bitfield.xmmword = 0; 1868 temp.bitfield.ymmword = 0; 1869 temp.bitfield.zmmword = 0; 1870 if (operand_type_all_zero (&temp)) 1871 goto mismatch; 1872 1873 if (given.bitfield.baseindex == overlap.bitfield.baseindex 1874 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) 1875 return 1; 1876 1877 mismatch: 1878 i.error = operand_type_mismatch; 1879 return 0; 1880 } 1881 1882 /* If given types g0 and g1 are registers they must be of the same type 1883 unless the expected operand type register overlap is null. 1884 Note that Acc in a template matches every size of reg. */ 1885 1886 static INLINE int 1887 operand_type_register_match (i386_operand_type m0, 1888 i386_operand_type g0, 1889 i386_operand_type t0, 1890 i386_operand_type m1, 1891 i386_operand_type g1, 1892 i386_operand_type t1) 1893 { 1894 if (!operand_type_check (g0, reg)) 1895 return 1; 1896 1897 if (!operand_type_check (g1, reg)) 1898 return 1; 1899 1900 if (g0.bitfield.reg8 == g1.bitfield.reg8 1901 && g0.bitfield.reg16 == g1.bitfield.reg16 1902 && g0.bitfield.reg32 == g1.bitfield.reg32 1903 && g0.bitfield.reg64 == g1.bitfield.reg64) 1904 return 1; 1905 1906 if (m0.bitfield.acc) 1907 { 1908 t0.bitfield.reg8 = 1; 1909 t0.bitfield.reg16 = 1; 1910 t0.bitfield.reg32 = 1; 1911 t0.bitfield.reg64 = 1; 1912 } 1913 1914 if (m1.bitfield.acc) 1915 { 1916 t1.bitfield.reg8 = 1; 1917 t1.bitfield.reg16 = 1; 1918 t1.bitfield.reg32 = 1; 1919 t1.bitfield.reg64 = 1; 1920 } 1921 1922 if (!(t0.bitfield.reg8 & t1.bitfield.reg8) 1923 && !(t0.bitfield.reg16 & t1.bitfield.reg16) 1924 && !(t0.bitfield.reg32 & t1.bitfield.reg32) 1925 && !(t0.bitfield.reg64 & t1.bitfield.reg64)) 1926 return 1; 1927 1928 i.error = register_type_mismatch; 1929 1930 return 0; 1931 } 1932 1933 static INLINE unsigned int 1934 register_number (const reg_entry *r) 1935 { 1936 unsigned int nr = r->reg_num; 1937 1938 if (r->reg_flags & RegRex) 1939 nr += 8; 1940 1941 return nr; 1942 } 1943 1944 static INLINE unsigned int 1945 mode_from_disp_size (i386_operand_type t) 1946 { 1947 if (t.bitfield.disp8 || t.bitfield.vec_disp8) 1948 return 1; 1949 else if (t.bitfield.disp16 1950 || t.bitfield.disp32 1951 || t.bitfield.disp32s) 1952 return 2; 1953 else 1954 return 0; 1955 } 1956 1957 static INLINE int 1958 fits_in_signed_byte (addressT num) 1959 { 1960 return num + 0x80 <= 0xff; 1961 } 1962 1963 static INLINE int 1964 fits_in_unsigned_byte (addressT num) 1965 { 1966 return num <= 0xff; 1967 } 1968 1969 static INLINE int 1970 fits_in_unsigned_word (addressT num) 1971 { 1972 return num <= 0xffff; 1973 } 1974 1975 static INLINE int 1976 fits_in_signed_word (addressT num) 1977 { 1978 return num + 0x8000 <= 0xffff; 1979 } 1980 1981 static INLINE int 1982 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) 1983 { 1984 #ifndef BFD64 1985 return 1; 1986 #else 1987 return num + 0x80000000 <= 0xffffffff; 1988 #endif 1989 } /* fits_in_signed_long() */ 1990 1991 static INLINE int 1992 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) 1993 { 1994 #ifndef BFD64 1995 return 1; 1996 #else 1997 return num <= 0xffffffff; 1998 #endif 1999 } /* fits_in_unsigned_long() */ 2000 2001 static INLINE int 2002 fits_in_vec_disp8 (offsetT num) 2003 { 2004 int shift = i.memshift; 2005 unsigned int mask; 2006 2007 if (shift == -1) 2008 abort (); 2009 2010 mask = (1 << shift) - 1; 2011 2012 /* Return 0 if NUM isn't properly aligned. */ 2013 if ((num & mask)) 2014 return 0; 2015 2016 /* Check if NUM will fit in 8bit after shift. */ 2017 return fits_in_signed_byte (num >> shift); 2018 } 2019 2020 static INLINE int 2021 fits_in_imm4 (offsetT num) 2022 { 2023 return (num & 0xf) == num; 2024 } 2025 2026 static i386_operand_type 2027 smallest_imm_type (offsetT num) 2028 { 2029 i386_operand_type t; 2030 2031 operand_type_set (&t, 0); 2032 t.bitfield.imm64 = 1; 2033 2034 if (cpu_arch_tune != PROCESSOR_I486 && num == 1) 2035 { 2036 /* This code is disabled on the 486 because all the Imm1 forms 2037 in the opcode table are slower on the i486. They're the 2038 versions with the implicitly specified single-position 2039 displacement, which has another syntax if you really want to 2040 use that form. */ 2041 t.bitfield.imm1 = 1; 2042 t.bitfield.imm8 = 1; 2043 t.bitfield.imm8s = 1; 2044 t.bitfield.imm16 = 1; 2045 t.bitfield.imm32 = 1; 2046 t.bitfield.imm32s = 1; 2047 } 2048 else if (fits_in_signed_byte (num)) 2049 { 2050 t.bitfield.imm8 = 1; 2051 t.bitfield.imm8s = 1; 2052 t.bitfield.imm16 = 1; 2053 t.bitfield.imm32 = 1; 2054 t.bitfield.imm32s = 1; 2055 } 2056 else if (fits_in_unsigned_byte (num)) 2057 { 2058 t.bitfield.imm8 = 1; 2059 t.bitfield.imm16 = 1; 2060 t.bitfield.imm32 = 1; 2061 t.bitfield.imm32s = 1; 2062 } 2063 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 2064 { 2065 t.bitfield.imm16 = 1; 2066 t.bitfield.imm32 = 1; 2067 t.bitfield.imm32s = 1; 2068 } 2069 else if (fits_in_signed_long (num)) 2070 { 2071 t.bitfield.imm32 = 1; 2072 t.bitfield.imm32s = 1; 2073 } 2074 else if (fits_in_unsigned_long (num)) 2075 t.bitfield.imm32 = 1; 2076 2077 return t; 2078 } 2079 2080 static offsetT 2081 offset_in_range (offsetT val, int size) 2082 { 2083 addressT mask; 2084 2085 switch (size) 2086 { 2087 case 1: mask = ((addressT) 1 << 8) - 1; break; 2088 case 2: mask = ((addressT) 1 << 16) - 1; break; 2089 case 4: mask = ((addressT) 2 << 31) - 1; break; 2090 #ifdef BFD64 2091 case 8: mask = ((addressT) 2 << 63) - 1; break; 2092 #endif 2093 default: abort (); 2094 } 2095 2096 #ifdef BFD64 2097 /* If BFD64, sign extend val for 32bit address mode. */ 2098 if (flag_code != CODE_64BIT 2099 || i.prefix[ADDR_PREFIX]) 2100 if ((val & ~(((addressT) 2 << 31) - 1)) == 0) 2101 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 2102 #endif 2103 2104 if ((val & ~mask) != 0 && (val & ~mask) != ~mask) 2105 { 2106 char buf1[40], buf2[40]; 2107 2108 sprint_value (buf1, val); 2109 sprint_value (buf2, val & mask); 2110 as_warn (_("%s shortened to %s"), buf1, buf2); 2111 } 2112 return val & mask; 2113 } 2114 2115 enum PREFIX_GROUP 2116 { 2117 PREFIX_EXIST = 0, 2118 PREFIX_LOCK, 2119 PREFIX_REP, 2120 PREFIX_OTHER 2121 }; 2122 2123 /* Returns 2124 a. PREFIX_EXIST if attempting to add a prefix where one from the 2125 same class already exists. 2126 b. PREFIX_LOCK if lock prefix is added. 2127 c. PREFIX_REP if rep/repne prefix is added. 2128 d. PREFIX_OTHER if other prefix is added. 2129 */ 2130 2131 static enum PREFIX_GROUP 2132 add_prefix (unsigned int prefix) 2133 { 2134 enum PREFIX_GROUP ret = PREFIX_OTHER; 2135 unsigned int q; 2136 2137 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 2138 && flag_code == CODE_64BIT) 2139 { 2140 if ((i.prefix[REX_PREFIX] & prefix & REX_W) 2141 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) 2142 && (prefix & (REX_R | REX_X | REX_B)))) 2143 ret = PREFIX_EXIST; 2144 q = REX_PREFIX; 2145 } 2146 else 2147 { 2148 switch (prefix) 2149 { 2150 default: 2151 abort (); 2152 2153 case CS_PREFIX_OPCODE: 2154 case DS_PREFIX_OPCODE: 2155 case ES_PREFIX_OPCODE: 2156 case FS_PREFIX_OPCODE: 2157 case GS_PREFIX_OPCODE: 2158 case SS_PREFIX_OPCODE: 2159 q = SEG_PREFIX; 2160 break; 2161 2162 case REPNE_PREFIX_OPCODE: 2163 case REPE_PREFIX_OPCODE: 2164 q = REP_PREFIX; 2165 ret = PREFIX_REP; 2166 break; 2167 2168 case LOCK_PREFIX_OPCODE: 2169 q = LOCK_PREFIX; 2170 ret = PREFIX_LOCK; 2171 break; 2172 2173 case FWAIT_OPCODE: 2174 q = WAIT_PREFIX; 2175 break; 2176 2177 case ADDR_PREFIX_OPCODE: 2178 q = ADDR_PREFIX; 2179 break; 2180 2181 case DATA_PREFIX_OPCODE: 2182 q = DATA_PREFIX; 2183 break; 2184 } 2185 if (i.prefix[q] != 0) 2186 ret = PREFIX_EXIST; 2187 } 2188 2189 if (ret) 2190 { 2191 if (!i.prefix[q]) 2192 ++i.prefixes; 2193 i.prefix[q] |= prefix; 2194 } 2195 else 2196 as_bad (_("same type of prefix used twice")); 2197 2198 return ret; 2199 } 2200 2201 static void 2202 update_code_flag (int value, int check) 2203 { 2204 PRINTF_LIKE ((*as_error)); 2205 2206 flag_code = (enum flag_code) value; 2207 if (flag_code == CODE_64BIT) 2208 { 2209 cpu_arch_flags.bitfield.cpu64 = 1; 2210 cpu_arch_flags.bitfield.cpuno64 = 0; 2211 } 2212 else 2213 { 2214 cpu_arch_flags.bitfield.cpu64 = 0; 2215 cpu_arch_flags.bitfield.cpuno64 = 1; 2216 } 2217 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) 2218 { 2219 if (check) 2220 as_error = as_fatal; 2221 else 2222 as_error = as_bad; 2223 (*as_error) (_("64bit mode not supported on `%s'."), 2224 cpu_arch_name ? cpu_arch_name : default_arch); 2225 } 2226 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) 2227 { 2228 if (check) 2229 as_error = as_fatal; 2230 else 2231 as_error = as_bad; 2232 (*as_error) (_("32bit mode not supported on `%s'."), 2233 cpu_arch_name ? cpu_arch_name : default_arch); 2234 } 2235 stackop_size = '\0'; 2236 } 2237 2238 static void 2239 set_code_flag (int value) 2240 { 2241 update_code_flag (value, 0); 2242 } 2243 2244 static void 2245 set_16bit_gcc_code_flag (int new_code_flag) 2246 { 2247 flag_code = (enum flag_code) new_code_flag; 2248 if (flag_code != CODE_16BIT) 2249 abort (); 2250 cpu_arch_flags.bitfield.cpu64 = 0; 2251 cpu_arch_flags.bitfield.cpuno64 = 1; 2252 stackop_size = LONG_MNEM_SUFFIX; 2253 } 2254 2255 static void 2256 set_intel_syntax (int syntax_flag) 2257 { 2258 /* Find out if register prefixing is specified. */ 2259 int ask_naked_reg = 0; 2260 2261 SKIP_WHITESPACE (); 2262 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2263 { 2264 char *string = input_line_pointer; 2265 int e = get_symbol_end (); 2266 2267 if (strcmp (string, "prefix") == 0) 2268 ask_naked_reg = 1; 2269 else if (strcmp (string, "noprefix") == 0) 2270 ask_naked_reg = -1; 2271 else 2272 as_bad (_("bad argument to syntax directive.")); 2273 *input_line_pointer = e; 2274 } 2275 demand_empty_rest_of_line (); 2276 2277 intel_syntax = syntax_flag; 2278 2279 if (ask_naked_reg == 0) 2280 allow_naked_reg = (intel_syntax 2281 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 2282 else 2283 allow_naked_reg = (ask_naked_reg < 0); 2284 2285 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); 2286 2287 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; 2288 identifier_chars['$'] = intel_syntax ? '$' : 0; 2289 register_prefix = allow_naked_reg ? "" : "%"; 2290 } 2291 2292 static void 2293 set_intel_mnemonic (int mnemonic_flag) 2294 { 2295 intel_mnemonic = mnemonic_flag; 2296 } 2297 2298 static void 2299 set_allow_index_reg (int flag) 2300 { 2301 allow_index_reg = flag; 2302 } 2303 2304 static void 2305 set_check (int what) 2306 { 2307 enum check_kind *kind; 2308 const char *str; 2309 2310 if (what) 2311 { 2312 kind = &operand_check; 2313 str = "operand"; 2314 } 2315 else 2316 { 2317 kind = &sse_check; 2318 str = "sse"; 2319 } 2320 2321 SKIP_WHITESPACE (); 2322 2323 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2324 { 2325 char *string = input_line_pointer; 2326 int e = get_symbol_end (); 2327 2328 if (strcmp (string, "none") == 0) 2329 *kind = check_none; 2330 else if (strcmp (string, "warning") == 0) 2331 *kind = check_warning; 2332 else if (strcmp (string, "error") == 0) 2333 *kind = check_error; 2334 else 2335 as_bad (_("bad argument to %s_check directive."), str); 2336 *input_line_pointer = e; 2337 } 2338 else 2339 as_bad (_("missing argument for %s_check directive"), str); 2340 2341 demand_empty_rest_of_line (); 2342 } 2343 2344 static void 2345 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, 2346 i386_cpu_flags new_flag ATTRIBUTE_UNUSED) 2347 { 2348 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2349 static const char *arch; 2350 2351 /* Intel LIOM is only supported on ELF. */ 2352 if (!IS_ELF) 2353 return; 2354 2355 if (!arch) 2356 { 2357 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise 2358 use default_arch. */ 2359 arch = cpu_arch_name; 2360 if (!arch) 2361 arch = default_arch; 2362 } 2363 2364 /* If we are targeting Intel L1OM, we must enable it. */ 2365 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM 2366 || new_flag.bitfield.cpul1om) 2367 return; 2368 2369 /* If we are targeting Intel K1OM, we must enable it. */ 2370 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM 2371 || new_flag.bitfield.cpuk1om) 2372 return; 2373 2374 as_bad (_("`%s' is not supported on `%s'"), name, arch); 2375 #endif 2376 } 2377 2378 static void 2379 set_cpu_arch (int dummy ATTRIBUTE_UNUSED) 2380 { 2381 SKIP_WHITESPACE (); 2382 2383 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2384 { 2385 char *string = input_line_pointer; 2386 int e = get_symbol_end (); 2387 unsigned int j; 2388 i386_cpu_flags flags; 2389 2390 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 2391 { 2392 if (strcmp (string, cpu_arch[j].name) == 0) 2393 { 2394 check_cpu_arch_compatible (string, cpu_arch[j].flags); 2395 2396 if (*string != '.') 2397 { 2398 cpu_arch_name = cpu_arch[j].name; 2399 cpu_sub_arch_name = NULL; 2400 cpu_arch_flags = cpu_arch[j].flags; 2401 if (flag_code == CODE_64BIT) 2402 { 2403 cpu_arch_flags.bitfield.cpu64 = 1; 2404 cpu_arch_flags.bitfield.cpuno64 = 0; 2405 } 2406 else 2407 { 2408 cpu_arch_flags.bitfield.cpu64 = 0; 2409 cpu_arch_flags.bitfield.cpuno64 = 1; 2410 } 2411 cpu_arch_isa = cpu_arch[j].type; 2412 cpu_arch_isa_flags = cpu_arch[j].flags; 2413 if (!cpu_arch_tune_set) 2414 { 2415 cpu_arch_tune = cpu_arch_isa; 2416 cpu_arch_tune_flags = cpu_arch_isa_flags; 2417 } 2418 break; 2419 } 2420 2421 if (!cpu_arch[j].negated) 2422 flags = cpu_flags_or (cpu_arch_flags, 2423 cpu_arch[j].flags); 2424 else 2425 flags = cpu_flags_and_not (cpu_arch_flags, 2426 cpu_arch[j].flags); 2427 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 2428 { 2429 if (cpu_sub_arch_name) 2430 { 2431 char *name = cpu_sub_arch_name; 2432 cpu_sub_arch_name = concat (name, 2433 cpu_arch[j].name, 2434 (const char *) NULL); 2435 free (name); 2436 } 2437 else 2438 cpu_sub_arch_name = xstrdup (cpu_arch[j].name); 2439 cpu_arch_flags = flags; 2440 cpu_arch_isa_flags = flags; 2441 } 2442 *input_line_pointer = e; 2443 demand_empty_rest_of_line (); 2444 return; 2445 } 2446 } 2447 if (j >= ARRAY_SIZE (cpu_arch)) 2448 as_bad (_("no such architecture: `%s'"), string); 2449 2450 *input_line_pointer = e; 2451 } 2452 else 2453 as_bad (_("missing cpu architecture")); 2454 2455 no_cond_jump_promotion = 0; 2456 if (*input_line_pointer == ',' 2457 && !is_end_of_line[(unsigned char) input_line_pointer[1]]) 2458 { 2459 char *string = ++input_line_pointer; 2460 int e = get_symbol_end (); 2461 2462 if (strcmp (string, "nojumps") == 0) 2463 no_cond_jump_promotion = 1; 2464 else if (strcmp (string, "jumps") == 0) 2465 ; 2466 else 2467 as_bad (_("no such architecture modifier: `%s'"), string); 2468 2469 *input_line_pointer = e; 2470 } 2471 2472 demand_empty_rest_of_line (); 2473 } 2474 2475 enum bfd_architecture 2476 i386_arch (void) 2477 { 2478 if (cpu_arch_isa == PROCESSOR_L1OM) 2479 { 2480 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2481 || flag_code != CODE_64BIT) 2482 as_fatal (_("Intel L1OM is 64bit ELF only")); 2483 return bfd_arch_l1om; 2484 } 2485 else if (cpu_arch_isa == PROCESSOR_K1OM) 2486 { 2487 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2488 || flag_code != CODE_64BIT) 2489 as_fatal (_("Intel K1OM is 64bit ELF only")); 2490 return bfd_arch_k1om; 2491 } 2492 else 2493 return bfd_arch_i386; 2494 } 2495 2496 unsigned long 2497 i386_mach (void) 2498 { 2499 if (!strncmp (default_arch, "x86_64", 6)) 2500 { 2501 if (cpu_arch_isa == PROCESSOR_L1OM) 2502 { 2503 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2504 || default_arch[6] != '\0') 2505 as_fatal (_("Intel L1OM is 64bit ELF only")); 2506 return bfd_mach_l1om; 2507 } 2508 else if (cpu_arch_isa == PROCESSOR_K1OM) 2509 { 2510 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2511 || default_arch[6] != '\0') 2512 as_fatal (_("Intel K1OM is 64bit ELF only")); 2513 return bfd_mach_k1om; 2514 } 2515 else if (default_arch[6] == '\0') 2516 return bfd_mach_x86_64; 2517 else 2518 return bfd_mach_x64_32; 2519 } 2520 else if (!strcmp (default_arch, "i386")) 2521 return bfd_mach_i386_i386; 2522 else 2523 as_fatal (_("unknown architecture")); 2524 } 2525 2526 void 2528 md_begin (void) 2529 { 2530 const char *hash_err; 2531 2532 /* Initialize op_hash hash table. */ 2533 op_hash = hash_new (); 2534 2535 { 2536 const insn_template *optab; 2537 templates *core_optab; 2538 2539 /* Setup for loop. */ 2540 optab = i386_optab; 2541 core_optab = (templates *) xmalloc (sizeof (templates)); 2542 core_optab->start = optab; 2543 2544 while (1) 2545 { 2546 ++optab; 2547 if (optab->name == NULL 2548 || strcmp (optab->name, (optab - 1)->name) != 0) 2549 { 2550 /* different name --> ship out current template list; 2551 add to hash table; & begin anew. */ 2552 core_optab->end = optab; 2553 hash_err = hash_insert (op_hash, 2554 (optab - 1)->name, 2555 (void *) core_optab); 2556 if (hash_err) 2557 { 2558 as_fatal (_("can't hash %s: %s"), 2559 (optab - 1)->name, 2560 hash_err); 2561 } 2562 if (optab->name == NULL) 2563 break; 2564 core_optab = (templates *) xmalloc (sizeof (templates)); 2565 core_optab->start = optab; 2566 } 2567 } 2568 } 2569 2570 /* Initialize reg_hash hash table. */ 2571 reg_hash = hash_new (); 2572 { 2573 const reg_entry *regtab; 2574 unsigned int regtab_size = i386_regtab_size; 2575 2576 for (regtab = i386_regtab; regtab_size--; regtab++) 2577 { 2578 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); 2579 if (hash_err) 2580 as_fatal (_("can't hash %s: %s"), 2581 regtab->reg_name, 2582 hash_err); 2583 } 2584 } 2585 2586 /* Fill in lexical tables: mnemonic_chars, operand_chars. */ 2587 { 2588 int c; 2589 char *p; 2590 2591 for (c = 0; c < 256; c++) 2592 { 2593 if (ISDIGIT (c)) 2594 { 2595 digit_chars[c] = c; 2596 mnemonic_chars[c] = c; 2597 register_chars[c] = c; 2598 operand_chars[c] = c; 2599 } 2600 else if (ISLOWER (c)) 2601 { 2602 mnemonic_chars[c] = c; 2603 register_chars[c] = c; 2604 operand_chars[c] = c; 2605 } 2606 else if (ISUPPER (c)) 2607 { 2608 mnemonic_chars[c] = TOLOWER (c); 2609 register_chars[c] = mnemonic_chars[c]; 2610 operand_chars[c] = c; 2611 } 2612 else if (c == '{' || c == '}') 2613 operand_chars[c] = c; 2614 2615 if (ISALPHA (c) || ISDIGIT (c)) 2616 identifier_chars[c] = c; 2617 else if (c >= 128) 2618 { 2619 identifier_chars[c] = c; 2620 operand_chars[c] = c; 2621 } 2622 } 2623 2624 #ifdef LEX_AT 2625 identifier_chars['@'] = '@'; 2626 #endif 2627 #ifdef LEX_QM 2628 identifier_chars['?'] = '?'; 2629 operand_chars['?'] = '?'; 2630 #endif 2631 digit_chars['-'] = '-'; 2632 mnemonic_chars['_'] = '_'; 2633 mnemonic_chars['-'] = '-'; 2634 mnemonic_chars['.'] = '.'; 2635 identifier_chars['_'] = '_'; 2636 identifier_chars['.'] = '.'; 2637 2638 for (p = operand_special_chars; *p != '\0'; p++) 2639 operand_chars[(unsigned char) *p] = *p; 2640 } 2641 2642 if (flag_code == CODE_64BIT) 2643 { 2644 #if defined (OBJ_COFF) && defined (TE_PE) 2645 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour 2646 ? 32 : 16); 2647 #else 2648 x86_dwarf2_return_column = 16; 2649 #endif 2650 x86_cie_data_alignment = -8; 2651 } 2652 else 2653 { 2654 x86_dwarf2_return_column = 8; 2655 x86_cie_data_alignment = -4; 2656 } 2657 } 2658 2659 void 2660 i386_print_statistics (FILE *file) 2661 { 2662 hash_print_statistics (file, "i386 opcode", op_hash); 2663 hash_print_statistics (file, "i386 register", reg_hash); 2664 } 2665 2666 #ifdef DEBUG386 2668 2669 /* Debugging routines for md_assemble. */ 2670 static void pte (insn_template *); 2671 static void pt (i386_operand_type); 2672 static void pe (expressionS *); 2673 static void ps (symbolS *); 2674 2675 static void 2676 pi (char *line, i386_insn *x) 2677 { 2678 unsigned int j; 2679 2680 fprintf (stdout, "%s: template ", line); 2681 pte (&x->tm); 2682 fprintf (stdout, " address: base %s index %s scale %x\n", 2683 x->base_reg ? x->base_reg->reg_name : "none", 2684 x->index_reg ? x->index_reg->reg_name : "none", 2685 x->log2_scale_factor); 2686 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", 2687 x->rm.mode, x->rm.reg, x->rm.regmem); 2688 fprintf (stdout, " sib: base %x index %x scale %x\n", 2689 x->sib.base, x->sib.index, x->sib.scale); 2690 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", 2691 (x->rex & REX_W) != 0, 2692 (x->rex & REX_R) != 0, 2693 (x->rex & REX_X) != 0, 2694 (x->rex & REX_B) != 0); 2695 for (j = 0; j < x->operands; j++) 2696 { 2697 fprintf (stdout, " #%d: ", j + 1); 2698 pt (x->types[j]); 2699 fprintf (stdout, "\n"); 2700 if (x->types[j].bitfield.reg8 2701 || x->types[j].bitfield.reg16 2702 || x->types[j].bitfield.reg32 2703 || x->types[j].bitfield.reg64 2704 || x->types[j].bitfield.regmmx 2705 || x->types[j].bitfield.regxmm 2706 || x->types[j].bitfield.regymm 2707 || x->types[j].bitfield.regzmm 2708 || x->types[j].bitfield.sreg2 2709 || x->types[j].bitfield.sreg3 2710 || x->types[j].bitfield.control 2711 || x->types[j].bitfield.debug 2712 || x->types[j].bitfield.test) 2713 fprintf (stdout, "%s\n", x->op[j].regs->reg_name); 2714 if (operand_type_check (x->types[j], imm)) 2715 pe (x->op[j].imms); 2716 if (operand_type_check (x->types[j], disp)) 2717 pe (x->op[j].disps); 2718 } 2719 } 2720 2721 static void 2722 pte (insn_template *t) 2723 { 2724 unsigned int j; 2725 fprintf (stdout, " %d operands ", t->operands); 2726 fprintf (stdout, "opcode %x ", t->base_opcode); 2727 if (t->extension_opcode != None) 2728 fprintf (stdout, "ext %x ", t->extension_opcode); 2729 if (t->opcode_modifier.d) 2730 fprintf (stdout, "D"); 2731 if (t->opcode_modifier.w) 2732 fprintf (stdout, "W"); 2733 fprintf (stdout, "\n"); 2734 for (j = 0; j < t->operands; j++) 2735 { 2736 fprintf (stdout, " #%d type ", j + 1); 2737 pt (t->operand_types[j]); 2738 fprintf (stdout, "\n"); 2739 } 2740 } 2741 2742 static void 2743 pe (expressionS *e) 2744 { 2745 fprintf (stdout, " operation %d\n", e->X_op); 2746 fprintf (stdout, " add_number %ld (%lx)\n", 2747 (long) e->X_add_number, (long) e->X_add_number); 2748 if (e->X_add_symbol) 2749 { 2750 fprintf (stdout, " add_symbol "); 2751 ps (e->X_add_symbol); 2752 fprintf (stdout, "\n"); 2753 } 2754 if (e->X_op_symbol) 2755 { 2756 fprintf (stdout, " op_symbol "); 2757 ps (e->X_op_symbol); 2758 fprintf (stdout, "\n"); 2759 } 2760 } 2761 2762 static void 2763 ps (symbolS *s) 2764 { 2765 fprintf (stdout, "%s type %s%s", 2766 S_GET_NAME (s), 2767 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 2768 segment_name (S_GET_SEGMENT (s))); 2769 } 2770 2771 static struct type_name 2772 { 2773 i386_operand_type mask; 2774 const char *name; 2775 } 2776 const type_names[] = 2777 { 2778 { OPERAND_TYPE_REG8, "r8" }, 2779 { OPERAND_TYPE_REG16, "r16" }, 2780 { OPERAND_TYPE_REG32, "r32" }, 2781 { OPERAND_TYPE_REG64, "r64" }, 2782 { OPERAND_TYPE_IMM8, "i8" }, 2783 { OPERAND_TYPE_IMM8, "i8s" }, 2784 { OPERAND_TYPE_IMM16, "i16" }, 2785 { OPERAND_TYPE_IMM32, "i32" }, 2786 { OPERAND_TYPE_IMM32S, "i32s" }, 2787 { OPERAND_TYPE_IMM64, "i64" }, 2788 { OPERAND_TYPE_IMM1, "i1" }, 2789 { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, 2790 { OPERAND_TYPE_DISP8, "d8" }, 2791 { OPERAND_TYPE_DISP16, "d16" }, 2792 { OPERAND_TYPE_DISP32, "d32" }, 2793 { OPERAND_TYPE_DISP32S, "d32s" }, 2794 { OPERAND_TYPE_DISP64, "d64" }, 2795 { OPERAND_TYPE_VEC_DISP8, "Vector d8" }, 2796 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, 2797 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, 2798 { OPERAND_TYPE_CONTROL, "control reg" }, 2799 { OPERAND_TYPE_TEST, "test reg" }, 2800 { OPERAND_TYPE_DEBUG, "debug reg" }, 2801 { OPERAND_TYPE_FLOATREG, "FReg" }, 2802 { OPERAND_TYPE_FLOATACC, "FAcc" }, 2803 { OPERAND_TYPE_SREG2, "SReg2" }, 2804 { OPERAND_TYPE_SREG3, "SReg3" }, 2805 { OPERAND_TYPE_ACC, "Acc" }, 2806 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, 2807 { OPERAND_TYPE_REGMMX, "rMMX" }, 2808 { OPERAND_TYPE_REGXMM, "rXMM" }, 2809 { OPERAND_TYPE_REGYMM, "rYMM" }, 2810 { OPERAND_TYPE_REGZMM, "rZMM" }, 2811 { OPERAND_TYPE_REGMASK, "Mask reg" }, 2812 { OPERAND_TYPE_ESSEG, "es" }, 2813 }; 2814 2815 static void 2816 pt (i386_operand_type t) 2817 { 2818 unsigned int j; 2819 i386_operand_type a; 2820 2821 for (j = 0; j < ARRAY_SIZE (type_names); j++) 2822 { 2823 a = operand_type_and (t, type_names[j].mask); 2824 if (!operand_type_all_zero (&a)) 2825 fprintf (stdout, "%s, ", type_names[j].name); 2826 } 2827 fflush (stdout); 2828 } 2829 2830 #endif /* DEBUG386 */ 2831 2832 static bfd_reloc_code_real_type 2834 reloc (unsigned int size, 2835 int pcrel, 2836 int sign, 2837 int bnd_prefix, 2838 bfd_reloc_code_real_type other) 2839 { 2840 if (other != NO_RELOC) 2841 { 2842 reloc_howto_type *rel; 2843 2844 if (size == 8) 2845 switch (other) 2846 { 2847 case BFD_RELOC_X86_64_GOT32: 2848 return BFD_RELOC_X86_64_GOT64; 2849 break; 2850 case BFD_RELOC_X86_64_GOTPLT64: 2851 return BFD_RELOC_X86_64_GOTPLT64; 2852 break; 2853 case BFD_RELOC_X86_64_PLTOFF64: 2854 return BFD_RELOC_X86_64_PLTOFF64; 2855 break; 2856 case BFD_RELOC_X86_64_GOTPC32: 2857 other = BFD_RELOC_X86_64_GOTPC64; 2858 break; 2859 case BFD_RELOC_X86_64_GOTPCREL: 2860 other = BFD_RELOC_X86_64_GOTPCREL64; 2861 break; 2862 case BFD_RELOC_X86_64_TPOFF32: 2863 other = BFD_RELOC_X86_64_TPOFF64; 2864 break; 2865 case BFD_RELOC_X86_64_DTPOFF32: 2866 other = BFD_RELOC_X86_64_DTPOFF64; 2867 break; 2868 default: 2869 break; 2870 } 2871 2872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2873 if (other == BFD_RELOC_SIZE32) 2874 { 2875 if (size == 8) 2876 other = BFD_RELOC_SIZE64; 2877 if (pcrel) 2878 { 2879 as_bad (_("there are no pc-relative size relocations")); 2880 return NO_RELOC; 2881 } 2882 } 2883 #endif 2884 2885 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ 2886 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) 2887 sign = -1; 2888 2889 rel = bfd_reloc_type_lookup (stdoutput, other); 2890 if (!rel) 2891 as_bad (_("unknown relocation (%u)"), other); 2892 else if (size != bfd_get_reloc_size (rel)) 2893 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), 2894 bfd_get_reloc_size (rel), 2895 size); 2896 else if (pcrel && !rel->pc_relative) 2897 as_bad (_("non-pc-relative relocation for pc-relative field")); 2898 else if ((rel->complain_on_overflow == complain_overflow_signed 2899 && !sign) 2900 || (rel->complain_on_overflow == complain_overflow_unsigned 2901 && sign > 0)) 2902 as_bad (_("relocated field and relocation type differ in signedness")); 2903 else 2904 return other; 2905 return NO_RELOC; 2906 } 2907 2908 if (pcrel) 2909 { 2910 if (!sign) 2911 as_bad (_("there are no unsigned pc-relative relocations")); 2912 switch (size) 2913 { 2914 case 1: return BFD_RELOC_8_PCREL; 2915 case 2: return BFD_RELOC_16_PCREL; 2916 case 4: return (bnd_prefix && object_64bit 2917 ? BFD_RELOC_X86_64_PC32_BND 2918 : BFD_RELOC_32_PCREL); 2919 case 8: return BFD_RELOC_64_PCREL; 2920 } 2921 as_bad (_("cannot do %u byte pc-relative relocation"), size); 2922 } 2923 else 2924 { 2925 if (sign > 0) 2926 switch (size) 2927 { 2928 case 4: return BFD_RELOC_X86_64_32S; 2929 } 2930 else 2931 switch (size) 2932 { 2933 case 1: return BFD_RELOC_8; 2934 case 2: return BFD_RELOC_16; 2935 case 4: return BFD_RELOC_32; 2936 case 8: return BFD_RELOC_64; 2937 } 2938 as_bad (_("cannot do %s %u byte relocation"), 2939 sign > 0 ? "signed" : "unsigned", size); 2940 } 2941 2942 return NO_RELOC; 2943 } 2944 2945 /* Here we decide which fixups can be adjusted to make them relative to 2946 the beginning of the section instead of the symbol. Basically we need 2947 to make sure that the dynamic relocations are done correctly, so in 2948 some cases we force the original symbol to be used. */ 2949 2950 int 2951 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) 2952 { 2953 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2954 if (!IS_ELF) 2955 return 1; 2956 2957 /* Don't adjust pc-relative references to merge sections in 64-bit 2958 mode. */ 2959 if (use_rela_relocations 2960 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 2961 && fixP->fx_pcrel) 2962 return 0; 2963 2964 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations 2965 and changed later by validate_fix. */ 2966 if (GOT_symbol && fixP->fx_subsy == GOT_symbol 2967 && fixP->fx_r_type == BFD_RELOC_32_PCREL) 2968 return 0; 2969 2970 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol 2971 for size relocations. */ 2972 if (fixP->fx_r_type == BFD_RELOC_SIZE32 2973 || fixP->fx_r_type == BFD_RELOC_SIZE64 2974 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF 2975 || fixP->fx_r_type == BFD_RELOC_386_PLT32 2976 || fixP->fx_r_type == BFD_RELOC_386_GOT32 2977 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD 2978 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM 2979 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 2980 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 2981 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE 2982 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE 2983 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 2984 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE 2985 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC 2986 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL 2987 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 2988 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 2989 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL 2990 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD 2991 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD 2992 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 2993 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 2994 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF 2995 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 2996 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 2997 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 2998 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC 2999 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL 3000 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3001 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3002 return 0; 3003 #endif 3004 return 1; 3005 } 3006 3007 static int 3008 intel_float_operand (const char *mnemonic) 3009 { 3010 /* Note that the value returned is meaningful only for opcodes with (memory) 3011 operands, hence the code here is free to improperly handle opcodes that 3012 have no operands (for better performance and smaller code). */ 3013 3014 if (mnemonic[0] != 'f') 3015 return 0; /* non-math */ 3016 3017 switch (mnemonic[1]) 3018 { 3019 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and 3020 the fs segment override prefix not currently handled because no 3021 call path can make opcodes without operands get here */ 3022 case 'i': 3023 return 2 /* integer op */; 3024 case 'l': 3025 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) 3026 return 3; /* fldcw/fldenv */ 3027 break; 3028 case 'n': 3029 if (mnemonic[2] != 'o' /* fnop */) 3030 return 3; /* non-waiting control op */ 3031 break; 3032 case 'r': 3033 if (mnemonic[2] == 's') 3034 return 3; /* frstor/frstpm */ 3035 break; 3036 case 's': 3037 if (mnemonic[2] == 'a') 3038 return 3; /* fsave */ 3039 if (mnemonic[2] == 't') 3040 { 3041 switch (mnemonic[3]) 3042 { 3043 case 'c': /* fstcw */ 3044 case 'd': /* fstdw */ 3045 case 'e': /* fstenv */ 3046 case 's': /* fsts[gw] */ 3047 return 3; 3048 } 3049 } 3050 break; 3051 case 'x': 3052 if (mnemonic[2] == 'r' || mnemonic[2] == 's') 3053 return 0; /* fxsave/fxrstor are not really math ops */ 3054 break; 3055 } 3056 3057 return 1; 3058 } 3059 3060 /* Build the VEX prefix. */ 3061 3062 static void 3063 build_vex_prefix (const insn_template *t) 3064 { 3065 unsigned int register_specifier; 3066 unsigned int implied_prefix; 3067 unsigned int vector_length; 3068 3069 /* Check register specifier. */ 3070 if (i.vex.register_specifier) 3071 { 3072 register_specifier = 3073 ~register_number (i.vex.register_specifier) & 0xf; 3074 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); 3075 } 3076 else 3077 register_specifier = 0xf; 3078 3079 /* Use 2-byte VEX prefix by swappping destination and source 3080 operand. */ 3081 if (!i.swap_operand 3082 && i.operands == i.reg_operands 3083 && i.tm.opcode_modifier.vexopcode == VEX0F 3084 && i.tm.opcode_modifier.s 3085 && i.rex == REX_B) 3086 { 3087 unsigned int xchg = i.operands - 1; 3088 union i386_op temp_op; 3089 i386_operand_type temp_type; 3090 3091 temp_type = i.types[xchg]; 3092 i.types[xchg] = i.types[0]; 3093 i.types[0] = temp_type; 3094 temp_op = i.op[xchg]; 3095 i.op[xchg] = i.op[0]; 3096 i.op[0] = temp_op; 3097 3098 gas_assert (i.rm.mode == 3); 3099 3100 i.rex = REX_R; 3101 xchg = i.rm.regmem; 3102 i.rm.regmem = i.rm.reg; 3103 i.rm.reg = xchg; 3104 3105 /* Use the next insn. */ 3106 i.tm = t[1]; 3107 } 3108 3109 if (i.tm.opcode_modifier.vex == VEXScalar) 3110 vector_length = avxscalar; 3111 else 3112 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; 3113 3114 switch ((i.tm.base_opcode >> 8) & 0xff) 3115 { 3116 case 0: 3117 implied_prefix = 0; 3118 break; 3119 case DATA_PREFIX_OPCODE: 3120 implied_prefix = 1; 3121 break; 3122 case REPE_PREFIX_OPCODE: 3123 implied_prefix = 2; 3124 break; 3125 case REPNE_PREFIX_OPCODE: 3126 implied_prefix = 3; 3127 break; 3128 default: 3129 abort (); 3130 } 3131 3132 /* Use 2-byte VEX prefix if possible. */ 3133 if (i.tm.opcode_modifier.vexopcode == VEX0F 3134 && i.tm.opcode_modifier.vexw != VEXW1 3135 && (i.rex & (REX_W | REX_X | REX_B)) == 0) 3136 { 3137 /* 2-byte VEX prefix. */ 3138 unsigned int r; 3139 3140 i.vex.length = 2; 3141 i.vex.bytes[0] = 0xc5; 3142 3143 /* Check the REX.R bit. */ 3144 r = (i.rex & REX_R) ? 0 : 1; 3145 i.vex.bytes[1] = (r << 7 3146 | register_specifier << 3 3147 | vector_length << 2 3148 | implied_prefix); 3149 } 3150 else 3151 { 3152 /* 3-byte VEX prefix. */ 3153 unsigned int m, w; 3154 3155 i.vex.length = 3; 3156 3157 switch (i.tm.opcode_modifier.vexopcode) 3158 { 3159 case VEX0F: 3160 m = 0x1; 3161 i.vex.bytes[0] = 0xc4; 3162 break; 3163 case VEX0F38: 3164 m = 0x2; 3165 i.vex.bytes[0] = 0xc4; 3166 break; 3167 case VEX0F3A: 3168 m = 0x3; 3169 i.vex.bytes[0] = 0xc4; 3170 break; 3171 case XOP08: 3172 m = 0x8; 3173 i.vex.bytes[0] = 0x8f; 3174 break; 3175 case XOP09: 3176 m = 0x9; 3177 i.vex.bytes[0] = 0x8f; 3178 break; 3179 case XOP0A: 3180 m = 0xa; 3181 i.vex.bytes[0] = 0x8f; 3182 break; 3183 default: 3184 abort (); 3185 } 3186 3187 /* The high 3 bits of the second VEX byte are 1's compliment 3188 of RXB bits from REX. */ 3189 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; 3190 3191 /* Check the REX.W bit. */ 3192 w = (i.rex & REX_W) ? 1 : 0; 3193 if (i.tm.opcode_modifier.vexw == VEXW1) 3194 w = 1; 3195 3196 i.vex.bytes[2] = (w << 7 3197 | register_specifier << 3 3198 | vector_length << 2 3199 | implied_prefix); 3200 } 3201 } 3202 3203 /* Build the EVEX prefix. */ 3204 3205 static void 3206 build_evex_prefix (void) 3207 { 3208 unsigned int register_specifier; 3209 unsigned int implied_prefix; 3210 unsigned int m, w; 3211 rex_byte vrex_used = 0; 3212 3213 /* Check register specifier. */ 3214 if (i.vex.register_specifier) 3215 { 3216 gas_assert ((i.vrex & REX_X) == 0); 3217 3218 register_specifier = i.vex.register_specifier->reg_num; 3219 if ((i.vex.register_specifier->reg_flags & RegRex)) 3220 register_specifier += 8; 3221 /* The upper 16 registers are encoded in the fourth byte of the 3222 EVEX prefix. */ 3223 if (!(i.vex.register_specifier->reg_flags & RegVRex)) 3224 i.vex.bytes[3] = 0x8; 3225 register_specifier = ~register_specifier & 0xf; 3226 } 3227 else 3228 { 3229 register_specifier = 0xf; 3230 3231 /* Encode upper 16 vector index register in the fourth byte of 3232 the EVEX prefix. */ 3233 if (!(i.vrex & REX_X)) 3234 i.vex.bytes[3] = 0x8; 3235 else 3236 vrex_used |= REX_X; 3237 } 3238 3239 switch ((i.tm.base_opcode >> 8) & 0xff) 3240 { 3241 case 0: 3242 implied_prefix = 0; 3243 break; 3244 case DATA_PREFIX_OPCODE: 3245 implied_prefix = 1; 3246 break; 3247 case REPE_PREFIX_OPCODE: 3248 implied_prefix = 2; 3249 break; 3250 case REPNE_PREFIX_OPCODE: 3251 implied_prefix = 3; 3252 break; 3253 default: 3254 abort (); 3255 } 3256 3257 /* 4 byte EVEX prefix. */ 3258 i.vex.length = 4; 3259 i.vex.bytes[0] = 0x62; 3260 3261 /* mmmm bits. */ 3262 switch (i.tm.opcode_modifier.vexopcode) 3263 { 3264 case VEX0F: 3265 m = 1; 3266 break; 3267 case VEX0F38: 3268 m = 2; 3269 break; 3270 case VEX0F3A: 3271 m = 3; 3272 break; 3273 default: 3274 abort (); 3275 break; 3276 } 3277 3278 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB 3279 bits from REX. */ 3280 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; 3281 3282 /* The fifth bit of the second EVEX byte is 1's compliment of the 3283 REX_R bit in VREX. */ 3284 if (!(i.vrex & REX_R)) 3285 i.vex.bytes[1] |= 0x10; 3286 else 3287 vrex_used |= REX_R; 3288 3289 if ((i.reg_operands + i.imm_operands) == i.operands) 3290 { 3291 /* When all operands are registers, the REX_X bit in REX is not 3292 used. We reuse it to encode the upper 16 registers, which is 3293 indicated by the REX_B bit in VREX. The REX_X bit is encoded 3294 as 1's compliment. */ 3295 if ((i.vrex & REX_B)) 3296 { 3297 vrex_used |= REX_B; 3298 i.vex.bytes[1] &= ~0x40; 3299 } 3300 } 3301 3302 /* EVEX instructions shouldn't need the REX prefix. */ 3303 i.vrex &= ~vrex_used; 3304 gas_assert (i.vrex == 0); 3305 3306 /* Check the REX.W bit. */ 3307 w = (i.rex & REX_W) ? 1 : 0; 3308 if (i.tm.opcode_modifier.vexw) 3309 { 3310 if (i.tm.opcode_modifier.vexw == VEXW1) 3311 w = 1; 3312 } 3313 /* If w is not set it means we are dealing with WIG instruction. */ 3314 else if (!w) 3315 { 3316 if (evexwig == evexw1) 3317 w = 1; 3318 } 3319 3320 /* Encode the U bit. */ 3321 implied_prefix |= 0x4; 3322 3323 /* The third byte of the EVEX prefix. */ 3324 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); 3325 3326 /* The fourth byte of the EVEX prefix. */ 3327 /* The zeroing-masking bit. */ 3328 if (i.mask && i.mask->zeroing) 3329 i.vex.bytes[3] |= 0x80; 3330 3331 /* Don't always set the broadcast bit if there is no RC. */ 3332 if (!i.rounding) 3333 { 3334 /* Encode the vector length. */ 3335 unsigned int vec_length; 3336 3337 switch (i.tm.opcode_modifier.evex) 3338 { 3339 case EVEXLIG: /* LL' is ignored */ 3340 vec_length = evexlig << 5; 3341 break; 3342 case EVEX128: 3343 vec_length = 0 << 5; 3344 break; 3345 case EVEX256: 3346 vec_length = 1 << 5; 3347 break; 3348 case EVEX512: 3349 vec_length = 2 << 5; 3350 break; 3351 default: 3352 abort (); 3353 break; 3354 } 3355 i.vex.bytes[3] |= vec_length; 3356 /* Encode the broadcast bit. */ 3357 if (i.broadcast) 3358 i.vex.bytes[3] |= 0x10; 3359 } 3360 else 3361 { 3362 if (i.rounding->type != saeonly) 3363 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); 3364 else 3365 i.vex.bytes[3] |= 0x10 | (evexrcig << 5); 3366 } 3367 3368 if (i.mask && i.mask->mask) 3369 i.vex.bytes[3] |= i.mask->mask->reg_num; 3370 } 3371 3372 static void 3373 process_immext (void) 3374 { 3375 expressionS *exp; 3376 3377 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) 3378 && i.operands > 0) 3379 { 3380 /* MONITOR/MWAIT as well as SVME instructions have fixed operands 3381 with an opcode suffix which is coded in the same place as an 3382 8-bit immediate field would be. 3383 Here we check those operands and remove them afterwards. */ 3384 unsigned int x; 3385 3386 for (x = 0; x < i.operands; x++) 3387 if (register_number (i.op[x].regs) != x) 3388 as_bad (_("can't use register '%s%s' as operand %d in '%s'."), 3389 register_prefix, i.op[x].regs->reg_name, x + 1, 3390 i.tm.name); 3391 3392 i.operands = 0; 3393 } 3394 3395 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix 3396 which is coded in the same place as an 8-bit immediate field 3397 would be. Here we fake an 8-bit immediate operand from the 3398 opcode suffix stored in tm.extension_opcode. 3399 3400 AVX instructions also use this encoding, for some of 3401 3 argument instructions. */ 3402 3403 gas_assert (i.imm_operands <= 1 3404 && (i.operands <= 2 3405 || ((i.tm.opcode_modifier.vex 3406 || i.tm.opcode_modifier.evex) 3407 && i.operands <= 4))); 3408 3409 exp = &im_expressions[i.imm_operands++]; 3410 i.op[i.operands].imms = exp; 3411 i.types[i.operands] = imm8; 3412 i.operands++; 3413 exp->X_op = O_constant; 3414 exp->X_add_number = i.tm.extension_opcode; 3415 i.tm.extension_opcode = None; 3416 } 3417 3418 3419 static int 3420 check_hle (void) 3421 { 3422 switch (i.tm.opcode_modifier.hleprefixok) 3423 { 3424 default: 3425 abort (); 3426 case HLEPrefixNone: 3427 as_bad (_("invalid instruction `%s' after `%s'"), 3428 i.tm.name, i.hle_prefix); 3429 return 0; 3430 case HLEPrefixLock: 3431 if (i.prefix[LOCK_PREFIX]) 3432 return 1; 3433 as_bad (_("missing `lock' with `%s'"), i.hle_prefix); 3434 return 0; 3435 case HLEPrefixAny: 3436 return 1; 3437 case HLEPrefixRelease: 3438 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) 3439 { 3440 as_bad (_("instruction `%s' after `xacquire' not allowed"), 3441 i.tm.name); 3442 return 0; 3443 } 3444 if (i.mem_operands == 0 3445 || !operand_type_check (i.types[i.operands - 1], anymem)) 3446 { 3447 as_bad (_("memory destination needed for instruction `%s'" 3448 " after `xrelease'"), i.tm.name); 3449 return 0; 3450 } 3451 return 1; 3452 } 3453 } 3454 3455 /* This is the guts of the machine-dependent assembler. LINE points to a 3456 machine dependent instruction. This function is supposed to emit 3457 the frags/bytes it assembles to. */ 3458 3459 void 3460 md_assemble (char *line) 3461 { 3462 unsigned int j; 3463 char mnemonic[MAX_MNEM_SIZE]; 3464 const insn_template *t; 3465 3466 /* Initialize globals. */ 3467 memset (&i, '\0', sizeof (i)); 3468 for (j = 0; j < MAX_OPERANDS; j++) 3469 i.reloc[j] = NO_RELOC; 3470 memset (disp_expressions, '\0', sizeof (disp_expressions)); 3471 memset (im_expressions, '\0', sizeof (im_expressions)); 3472 save_stack_p = save_stack; 3473 3474 /* First parse an instruction mnemonic & call i386_operand for the operands. 3475 We assume that the scrubber has arranged it so that line[0] is the valid 3476 start of a (possibly prefixed) mnemonic. */ 3477 3478 line = parse_insn (line, mnemonic); 3479 if (line == NULL) 3480 return; 3481 3482 line = parse_operands (line, mnemonic); 3483 this_operand = -1; 3484 if (line == NULL) 3485 return; 3486 3487 /* Now we've parsed the mnemonic into a set of templates, and have the 3488 operands at hand. */ 3489 3490 /* All intel opcodes have reversed operands except for "bound" and 3491 "enter". We also don't reverse intersegment "jmp" and "call" 3492 instructions with 2 immediate operands so that the immediate segment 3493 precedes the offset, as it does when in AT&T mode. */ 3494 if (intel_syntax 3495 && i.operands > 1 3496 && (strcmp (mnemonic, "bound") != 0) 3497 && (strcmp (mnemonic, "invlpga") != 0) 3498 && !(operand_type_check (i.types[0], imm) 3499 && operand_type_check (i.types[1], imm))) 3500 swap_operands (); 3501 3502 /* The order of the immediates should be reversed 3503 for 2 immediates extrq and insertq instructions */ 3504 if (i.imm_operands == 2 3505 && (strcmp (mnemonic, "extrq") == 0 3506 || strcmp (mnemonic, "insertq") == 0)) 3507 swap_2_operands (0, 1); 3508 3509 if (i.imm_operands) 3510 optimize_imm (); 3511 3512 /* Don't optimize displacement for movabs since it only takes 64bit 3513 displacement. */ 3514 if (i.disp_operands 3515 && i.disp_encoding != disp_encoding_32bit 3516 && (flag_code != CODE_64BIT 3517 || strcmp (mnemonic, "movabs") != 0)) 3518 optimize_disp (); 3519 3520 /* Next, we find a template that matches the given insn, 3521 making sure the overlap of the given operands types is consistent 3522 with the template operand types. */ 3523 3524 if (!(t = match_template ())) 3525 return; 3526 3527 if (sse_check != check_none 3528 && !i.tm.opcode_modifier.noavx 3529 && (i.tm.cpu_flags.bitfield.cpusse 3530 || i.tm.cpu_flags.bitfield.cpusse2 3531 || i.tm.cpu_flags.bitfield.cpusse3 3532 || i.tm.cpu_flags.bitfield.cpussse3 3533 || i.tm.cpu_flags.bitfield.cpusse4_1 3534 || i.tm.cpu_flags.bitfield.cpusse4_2)) 3535 { 3536 (sse_check == check_warning 3537 ? as_warn 3538 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); 3539 } 3540 3541 /* Zap movzx and movsx suffix. The suffix has been set from 3542 "word ptr" or "byte ptr" on the source operand in Intel syntax 3543 or extracted from mnemonic in AT&T syntax. But we'll use 3544 the destination register to choose the suffix for encoding. */ 3545 if ((i.tm.base_opcode & ~9) == 0x0fb6) 3546 { 3547 /* In Intel syntax, there must be a suffix. In AT&T syntax, if 3548 there is no suffix, the default will be byte extension. */ 3549 if (i.reg_operands != 2 3550 && !i.suffix 3551 && intel_syntax) 3552 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 3553 3554 i.suffix = 0; 3555 } 3556 3557 if (i.tm.opcode_modifier.fwait) 3558 if (!add_prefix (FWAIT_OPCODE)) 3559 return; 3560 3561 /* Check if REP prefix is OK. */ 3562 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) 3563 { 3564 as_bad (_("invalid instruction `%s' after `%s'"), 3565 i.tm.name, i.rep_prefix); 3566 return; 3567 } 3568 3569 /* Check for lock without a lockable instruction. Destination operand 3570 must be memory unless it is xchg (0x86). */ 3571 if (i.prefix[LOCK_PREFIX] 3572 && (!i.tm.opcode_modifier.islockable 3573 || i.mem_operands == 0 3574 || (i.tm.base_opcode != 0x86 3575 && !operand_type_check (i.types[i.operands - 1], anymem)))) 3576 { 3577 as_bad (_("expecting lockable instruction after `lock'")); 3578 return; 3579 } 3580 3581 /* Check if HLE prefix is OK. */ 3582 if (i.hle_prefix && !check_hle ()) 3583 return; 3584 3585 /* Check BND prefix. */ 3586 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) 3587 as_bad (_("expecting valid branch instruction after `bnd'")); 3588 3589 if (i.tm.cpu_flags.bitfield.cpumpx 3590 && flag_code == CODE_64BIT 3591 && i.prefix[ADDR_PREFIX]) 3592 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); 3593 3594 /* Insert BND prefix. */ 3595 if (add_bnd_prefix 3596 && i.tm.opcode_modifier.bndprefixok 3597 && !i.prefix[BND_PREFIX]) 3598 add_prefix (BND_PREFIX_OPCODE); 3599 3600 /* Check string instruction segment overrides. */ 3601 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) 3602 { 3603 if (!check_string ()) 3604 return; 3605 i.disp_operands = 0; 3606 } 3607 3608 if (!process_suffix ()) 3609 return; 3610 3611 /* Update operand types. */ 3612 for (j = 0; j < i.operands; j++) 3613 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); 3614 3615 /* Make still unresolved immediate matches conform to size of immediate 3616 given in i.suffix. */ 3617 if (!finalize_imm ()) 3618 return; 3619 3620 if (i.types[0].bitfield.imm1) 3621 i.imm_operands = 0; /* kludge for shift insns. */ 3622 3623 /* We only need to check those implicit registers for instructions 3624 with 3 operands or less. */ 3625 if (i.operands <= 3) 3626 for (j = 0; j < i.operands; j++) 3627 if (i.types[j].bitfield.inoutportreg 3628 || i.types[j].bitfield.shiftcount 3629 || i.types[j].bitfield.acc 3630 || i.types[j].bitfield.floatacc) 3631 i.reg_operands--; 3632 3633 /* ImmExt should be processed after SSE2AVX. */ 3634 if (!i.tm.opcode_modifier.sse2avx 3635 && i.tm.opcode_modifier.immext) 3636 process_immext (); 3637 3638 /* For insns with operands there are more diddles to do to the opcode. */ 3639 if (i.operands) 3640 { 3641 if (!process_operands ()) 3642 return; 3643 } 3644 else if (!quiet_warnings && i.tm.opcode_modifier.ugh) 3645 { 3646 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 3647 as_warn (_("translating to `%sp'"), i.tm.name); 3648 } 3649 3650 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) 3651 { 3652 if (flag_code == CODE_16BIT) 3653 { 3654 as_bad (_("instruction `%s' isn't supported in 16-bit mode."), 3655 i.tm.name); 3656 return; 3657 } 3658 3659 if (i.tm.opcode_modifier.vex) 3660 build_vex_prefix (t); 3661 else 3662 build_evex_prefix (); 3663 } 3664 3665 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 3666 instructions may define INT_OPCODE as well, so avoid this corner 3667 case for those instructions that use MODRM. */ 3668 if (i.tm.base_opcode == INT_OPCODE 3669 && !i.tm.opcode_modifier.modrm 3670 && i.op[0].imms->X_add_number == 3) 3671 { 3672 i.tm.base_opcode = INT3_OPCODE; 3673 i.imm_operands = 0; 3674 } 3675 3676 if ((i.tm.opcode_modifier.jump 3677 || i.tm.opcode_modifier.jumpbyte 3678 || i.tm.opcode_modifier.jumpdword) 3679 && i.op[0].disps->X_op == O_constant) 3680 { 3681 /* Convert "jmp constant" (and "call constant") to a jump (call) to 3682 the absolute address given by the constant. Since ix86 jumps and 3683 calls are pc relative, we need to generate a reloc. */ 3684 i.op[0].disps->X_add_symbol = &abs_symbol; 3685 i.op[0].disps->X_op = O_symbol; 3686 } 3687 3688 if (i.tm.opcode_modifier.rex64) 3689 i.rex |= REX_W; 3690 3691 /* For 8 bit registers we need an empty rex prefix. Also if the 3692 instruction already has a prefix, we need to convert old 3693 registers to new ones. */ 3694 3695 if ((i.types[0].bitfield.reg8 3696 && (i.op[0].regs->reg_flags & RegRex64) != 0) 3697 || (i.types[1].bitfield.reg8 3698 && (i.op[1].regs->reg_flags & RegRex64) != 0) 3699 || ((i.types[0].bitfield.reg8 3700 || i.types[1].bitfield.reg8) 3701 && i.rex != 0)) 3702 { 3703 int x; 3704 3705 i.rex |= REX_OPCODE; 3706 for (x = 0; x < 2; x++) 3707 { 3708 /* Look for 8 bit operand that uses old registers. */ 3709 if (i.types[x].bitfield.reg8 3710 && (i.op[x].regs->reg_flags & RegRex64) == 0) 3711 { 3712 /* In case it is "hi" register, give up. */ 3713 if (i.op[x].regs->reg_num > 3) 3714 as_bad (_("can't encode register '%s%s' in an " 3715 "instruction requiring REX prefix."), 3716 register_prefix, i.op[x].regs->reg_name); 3717 3718 /* Otherwise it is equivalent to the extended register. 3719 Since the encoding doesn't change this is merely 3720 cosmetic cleanup for debug output. */ 3721 3722 i.op[x].regs = i.op[x].regs + 8; 3723 } 3724 } 3725 } 3726 3727 if (i.rex != 0) 3728 add_prefix (REX_OPCODE | i.rex); 3729 3730 /* We are ready to output the insn. */ 3731 output_insn (); 3732 } 3733 3734 static char * 3735 parse_insn (char *line, char *mnemonic) 3736 { 3737 char *l = line; 3738 char *token_start = l; 3739 char *mnem_p; 3740 int supported; 3741 const insn_template *t; 3742 char *dot_p = NULL; 3743 3744 while (1) 3745 { 3746 mnem_p = mnemonic; 3747 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 3748 { 3749 if (*mnem_p == '.') 3750 dot_p = mnem_p; 3751 mnem_p++; 3752 if (mnem_p >= mnemonic + MAX_MNEM_SIZE) 3753 { 3754 as_bad (_("no such instruction: `%s'"), token_start); 3755 return NULL; 3756 } 3757 l++; 3758 } 3759 if (!is_space_char (*l) 3760 && *l != END_OF_INSN 3761 && (intel_syntax 3762 || (*l != PREFIX_SEPARATOR 3763 && *l != ','))) 3764 { 3765 as_bad (_("invalid character %s in mnemonic"), 3766 output_invalid (*l)); 3767 return NULL; 3768 } 3769 if (token_start == l) 3770 { 3771 if (!intel_syntax && *l == PREFIX_SEPARATOR) 3772 as_bad (_("expecting prefix; got nothing")); 3773 else 3774 as_bad (_("expecting mnemonic; got nothing")); 3775 return NULL; 3776 } 3777 3778 /* Look up instruction (or prefix) via hash table. */ 3779 current_templates = (const templates *) hash_find (op_hash, mnemonic); 3780 3781 if (*l != END_OF_INSN 3782 && (!is_space_char (*l) || l[1] != END_OF_INSN) 3783 && current_templates 3784 && current_templates->start->opcode_modifier.isprefix) 3785 { 3786 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) 3787 { 3788 as_bad ((flag_code != CODE_64BIT 3789 ? _("`%s' is only supported in 64-bit mode") 3790 : _("`%s' is not supported in 64-bit mode")), 3791 current_templates->start->name); 3792 return NULL; 3793 } 3794 /* If we are in 16-bit mode, do not allow addr16 or data16. 3795 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 3796 if ((current_templates->start->opcode_modifier.size16 3797 || current_templates->start->opcode_modifier.size32) 3798 && flag_code != CODE_64BIT 3799 && (current_templates->start->opcode_modifier.size32 3800 ^ (flag_code == CODE_16BIT))) 3801 { 3802 as_bad (_("redundant %s prefix"), 3803 current_templates->start->name); 3804 return NULL; 3805 } 3806 /* Add prefix, checking for repeated prefixes. */ 3807 switch (add_prefix (current_templates->start->base_opcode)) 3808 { 3809 case PREFIX_EXIST: 3810 return NULL; 3811 case PREFIX_REP: 3812 if (current_templates->start->cpu_flags.bitfield.cpuhle) 3813 i.hle_prefix = current_templates->start->name; 3814 else if (current_templates->start->cpu_flags.bitfield.cpumpx) 3815 i.bnd_prefix = current_templates->start->name; 3816 else 3817 i.rep_prefix = current_templates->start->name; 3818 break; 3819 default: 3820 break; 3821 } 3822 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 3823 token_start = ++l; 3824 } 3825 else 3826 break; 3827 } 3828 3829 if (!current_templates) 3830 { 3831 /* Check if we should swap operand or force 32bit displacement in 3832 encoding. */ 3833 if (mnem_p - 2 == dot_p && dot_p[1] == 's') 3834 i.swap_operand = 1; 3835 else if (mnem_p - 3 == dot_p 3836 && dot_p[1] == 'd' 3837 && dot_p[2] == '8') 3838 i.disp_encoding = disp_encoding_8bit; 3839 else if (mnem_p - 4 == dot_p 3840 && dot_p[1] == 'd' 3841 && dot_p[2] == '3' 3842 && dot_p[3] == '2') 3843 i.disp_encoding = disp_encoding_32bit; 3844 else 3845 goto check_suffix; 3846 mnem_p = dot_p; 3847 *dot_p = '\0'; 3848 current_templates = (const templates *) hash_find (op_hash, mnemonic); 3849 } 3850 3851 if (!current_templates) 3852 { 3853 check_suffix: 3854 /* See if we can get a match by trimming off a suffix. */ 3855 switch (mnem_p[-1]) 3856 { 3857 case WORD_MNEM_SUFFIX: 3858 if (intel_syntax && (intel_float_operand (mnemonic) & 2)) 3859 i.suffix = SHORT_MNEM_SUFFIX; 3860 else 3861 case BYTE_MNEM_SUFFIX: 3862 case QWORD_MNEM_SUFFIX: 3863 i.suffix = mnem_p[-1]; 3864 mnem_p[-1] = '\0'; 3865 current_templates = (const templates *) hash_find (op_hash, 3866 mnemonic); 3867 break; 3868 case SHORT_MNEM_SUFFIX: 3869 case LONG_MNEM_SUFFIX: 3870 if (!intel_syntax) 3871 { 3872 i.suffix = mnem_p[-1]; 3873 mnem_p[-1] = '\0'; 3874 current_templates = (const templates *) hash_find (op_hash, 3875 mnemonic); 3876 } 3877 break; 3878 3879 /* Intel Syntax. */ 3880 case 'd': 3881 if (intel_syntax) 3882 { 3883 if (intel_float_operand (mnemonic) == 1) 3884 i.suffix = SHORT_MNEM_SUFFIX; 3885 else 3886 i.suffix = LONG_MNEM_SUFFIX; 3887 mnem_p[-1] = '\0'; 3888 current_templates = (const templates *) hash_find (op_hash, 3889 mnemonic); 3890 } 3891 break; 3892 } 3893 if (!current_templates) 3894 { 3895 as_bad (_("no such instruction: `%s'"), token_start); 3896 return NULL; 3897 } 3898 } 3899 3900 if (current_templates->start->opcode_modifier.jump 3901 || current_templates->start->opcode_modifier.jumpbyte) 3902 { 3903 /* Check for a branch hint. We allow ",pt" and ",pn" for 3904 predict taken and predict not taken respectively. 3905 I'm not sure that branch hints actually do anything on loop 3906 and jcxz insns (JumpByte) for current Pentium4 chips. They 3907 may work in the future and it doesn't hurt to accept them 3908 now. */ 3909 if (l[0] == ',' && l[1] == 'p') 3910 { 3911 if (l[2] == 't') 3912 { 3913 if (!add_prefix (DS_PREFIX_OPCODE)) 3914 return NULL; 3915 l += 3; 3916 } 3917 else if (l[2] == 'n') 3918 { 3919 if (!add_prefix (CS_PREFIX_OPCODE)) 3920 return NULL; 3921 l += 3; 3922 } 3923 } 3924 } 3925 /* Any other comma loses. */ 3926 if (*l == ',') 3927 { 3928 as_bad (_("invalid character %s in mnemonic"), 3929 output_invalid (*l)); 3930 return NULL; 3931 } 3932 3933 /* Check if instruction is supported on specified architecture. */ 3934 supported = 0; 3935 for (t = current_templates->start; t < current_templates->end; ++t) 3936 { 3937 supported |= cpu_flags_match (t); 3938 if (supported == CPU_FLAGS_PERFECT_MATCH) 3939 goto skip; 3940 } 3941 3942 if (!(supported & CPU_FLAGS_64BIT_MATCH)) 3943 { 3944 as_bad (flag_code == CODE_64BIT 3945 ? _("`%s' is not supported in 64-bit mode") 3946 : _("`%s' is only supported in 64-bit mode"), 3947 current_templates->start->name); 3948 return NULL; 3949 } 3950 if (supported != CPU_FLAGS_PERFECT_MATCH) 3951 { 3952 as_bad (_("`%s' is not supported on `%s%s'"), 3953 current_templates->start->name, 3954 cpu_arch_name ? cpu_arch_name : default_arch, 3955 cpu_sub_arch_name ? cpu_sub_arch_name : ""); 3956 return NULL; 3957 } 3958 3959 skip: 3960 if (!cpu_arch_flags.bitfield.cpui386 3961 && (flag_code != CODE_16BIT)) 3962 { 3963 as_warn (_("use .code16 to ensure correct addressing mode")); 3964 } 3965 3966 return l; 3967 } 3968 3969 static char * 3970 parse_operands (char *l, const char *mnemonic) 3971 { 3972 char *token_start; 3973 3974 /* 1 if operand is pending after ','. */ 3975 unsigned int expecting_operand = 0; 3976 3977 /* Non-zero if operand parens not balanced. */ 3978 unsigned int paren_not_balanced; 3979 3980 while (*l != END_OF_INSN) 3981 { 3982 /* Skip optional white space before operand. */ 3983 if (is_space_char (*l)) 3984 ++l; 3985 if (!is_operand_char (*l) && *l != END_OF_INSN) 3986 { 3987 as_bad (_("invalid character %s before operand %d"), 3988 output_invalid (*l), 3989 i.operands + 1); 3990 return NULL; 3991 } 3992 token_start = l; /* after white space */ 3993 paren_not_balanced = 0; 3994 while (paren_not_balanced || *l != ',') 3995 { 3996 if (*l == END_OF_INSN) 3997 { 3998 if (paren_not_balanced) 3999 { 4000 if (!intel_syntax) 4001 as_bad (_("unbalanced parenthesis in operand %d."), 4002 i.operands + 1); 4003 else 4004 as_bad (_("unbalanced brackets in operand %d."), 4005 i.operands + 1); 4006 return NULL; 4007 } 4008 else 4009 break; /* we are done */ 4010 } 4011 else if (!is_operand_char (*l) && !is_space_char (*l)) 4012 { 4013 as_bad (_("invalid character %s in operand %d"), 4014 output_invalid (*l), 4015 i.operands + 1); 4016 return NULL; 4017 } 4018 if (!intel_syntax) 4019 { 4020 if (*l == '(') 4021 ++paren_not_balanced; 4022 if (*l == ')') 4023 --paren_not_balanced; 4024 } 4025 else 4026 { 4027 if (*l == '[') 4028 ++paren_not_balanced; 4029 if (*l == ']') 4030 --paren_not_balanced; 4031 } 4032 l++; 4033 } 4034 if (l != token_start) 4035 { /* Yes, we've read in another operand. */ 4036 unsigned int operand_ok; 4037 this_operand = i.operands++; 4038 i.types[this_operand].bitfield.unspecified = 1; 4039 if (i.operands > MAX_OPERANDS) 4040 { 4041 as_bad (_("spurious operands; (%d operands/instruction max)"), 4042 MAX_OPERANDS); 4043 return NULL; 4044 } 4045 /* Now parse operand adding info to 'i' as we go along. */ 4046 END_STRING_AND_SAVE (l); 4047 4048 if (intel_syntax) 4049 operand_ok = 4050 i386_intel_operand (token_start, 4051 intel_float_operand (mnemonic)); 4052 else 4053 operand_ok = i386_att_operand (token_start); 4054 4055 RESTORE_END_STRING (l); 4056 if (!operand_ok) 4057 return NULL; 4058 } 4059 else 4060 { 4061 if (expecting_operand) 4062 { 4063 expecting_operand_after_comma: 4064 as_bad (_("expecting operand after ','; got nothing")); 4065 return NULL; 4066 } 4067 if (*l == ',') 4068 { 4069 as_bad (_("expecting operand before ','; got nothing")); 4070 return NULL; 4071 } 4072 } 4073 4074 /* Now *l must be either ',' or END_OF_INSN. */ 4075 if (*l == ',') 4076 { 4077 if (*++l == END_OF_INSN) 4078 { 4079 /* Just skip it, if it's \n complain. */ 4080 goto expecting_operand_after_comma; 4081 } 4082 expecting_operand = 1; 4083 } 4084 } 4085 return l; 4086 } 4087 4088 static void 4089 swap_2_operands (int xchg1, int xchg2) 4090 { 4091 union i386_op temp_op; 4092 i386_operand_type temp_type; 4093 enum bfd_reloc_code_real temp_reloc; 4094 4095 temp_type = i.types[xchg2]; 4096 i.types[xchg2] = i.types[xchg1]; 4097 i.types[xchg1] = temp_type; 4098 temp_op = i.op[xchg2]; 4099 i.op[xchg2] = i.op[xchg1]; 4100 i.op[xchg1] = temp_op; 4101 temp_reloc = i.reloc[xchg2]; 4102 i.reloc[xchg2] = i.reloc[xchg1]; 4103 i.reloc[xchg1] = temp_reloc; 4104 4105 if (i.mask) 4106 { 4107 if (i.mask->operand == xchg1) 4108 i.mask->operand = xchg2; 4109 else if (i.mask->operand == xchg2) 4110 i.mask->operand = xchg1; 4111 } 4112 if (i.broadcast) 4113 { 4114 if (i.broadcast->operand == xchg1) 4115 i.broadcast->operand = xchg2; 4116 else if (i.broadcast->operand == xchg2) 4117 i.broadcast->operand = xchg1; 4118 } 4119 if (i.rounding) 4120 { 4121 if (i.rounding->operand == xchg1) 4122 i.rounding->operand = xchg2; 4123 else if (i.rounding->operand == xchg2) 4124 i.rounding->operand = xchg1; 4125 } 4126 } 4127 4128 static void 4129 swap_operands (void) 4130 { 4131 switch (i.operands) 4132 { 4133 case 5: 4134 case 4: 4135 swap_2_operands (1, i.operands - 2); 4136 case 3: 4137 case 2: 4138 swap_2_operands (0, i.operands - 1); 4139 break; 4140 default: 4141 abort (); 4142 } 4143 4144 if (i.mem_operands == 2) 4145 { 4146 const seg_entry *temp_seg; 4147 temp_seg = i.seg[0]; 4148 i.seg[0] = i.seg[1]; 4149 i.seg[1] = temp_seg; 4150 } 4151 } 4152 4153 /* Try to ensure constant immediates are represented in the smallest 4154 opcode possible. */ 4155 static void 4156 optimize_imm (void) 4157 { 4158 char guess_suffix = 0; 4159 int op; 4160 4161 if (i.suffix) 4162 guess_suffix = i.suffix; 4163 else if (i.reg_operands) 4164 { 4165 /* Figure out a suffix from the last register operand specified. 4166 We can't do this properly yet, ie. excluding InOutPortReg, 4167 but the following works for instructions with immediates. 4168 In any case, we can't set i.suffix yet. */ 4169 for (op = i.operands; --op >= 0;) 4170 if (i.types[op].bitfield.reg8) 4171 { 4172 guess_suffix = BYTE_MNEM_SUFFIX; 4173 break; 4174 } 4175 else if (i.types[op].bitfield.reg16) 4176 { 4177 guess_suffix = WORD_MNEM_SUFFIX; 4178 break; 4179 } 4180 else if (i.types[op].bitfield.reg32) 4181 { 4182 guess_suffix = LONG_MNEM_SUFFIX; 4183 break; 4184 } 4185 else if (i.types[op].bitfield.reg64) 4186 { 4187 guess_suffix = QWORD_MNEM_SUFFIX; 4188 break; 4189 } 4190 } 4191 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 4192 guess_suffix = WORD_MNEM_SUFFIX; 4193 4194 for (op = i.operands; --op >= 0;) 4195 if (operand_type_check (i.types[op], imm)) 4196 { 4197 switch (i.op[op].imms->X_op) 4198 { 4199 case O_constant: 4200 /* If a suffix is given, this operand may be shortened. */ 4201 switch (guess_suffix) 4202 { 4203 case LONG_MNEM_SUFFIX: 4204 i.types[op].bitfield.imm32 = 1; 4205 i.types[op].bitfield.imm64 = 1; 4206 break; 4207 case WORD_MNEM_SUFFIX: 4208 i.types[op].bitfield.imm16 = 1; 4209 i.types[op].bitfield.imm32 = 1; 4210 i.types[op].bitfield.imm32s = 1; 4211 i.types[op].bitfield.imm64 = 1; 4212 break; 4213 case BYTE_MNEM_SUFFIX: 4214 i.types[op].bitfield.imm8 = 1; 4215 i.types[op].bitfield.imm8s = 1; 4216 i.types[op].bitfield.imm16 = 1; 4217 i.types[op].bitfield.imm32 = 1; 4218 i.types[op].bitfield.imm32s = 1; 4219 i.types[op].bitfield.imm64 = 1; 4220 break; 4221 } 4222 4223 /* If this operand is at most 16 bits, convert it 4224 to a signed 16 bit number before trying to see 4225 whether it will fit in an even smaller size. 4226 This allows a 16-bit operand such as $0xffe0 to 4227 be recognised as within Imm8S range. */ 4228 if ((i.types[op].bitfield.imm16) 4229 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) 4230 { 4231 i.op[op].imms->X_add_number = 4232 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 4233 } 4234 if ((i.types[op].bitfield.imm32) 4235 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) 4236 == 0)) 4237 { 4238 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number 4239 ^ ((offsetT) 1 << 31)) 4240 - ((offsetT) 1 << 31)); 4241 } 4242 i.types[op] 4243 = operand_type_or (i.types[op], 4244 smallest_imm_type (i.op[op].imms->X_add_number)); 4245 4246 /* We must avoid matching of Imm32 templates when 64bit 4247 only immediate is available. */ 4248 if (guess_suffix == QWORD_MNEM_SUFFIX) 4249 i.types[op].bitfield.imm32 = 0; 4250 break; 4251 4252 case O_absent: 4253 case O_register: 4254 abort (); 4255 4256 /* Symbols and expressions. */ 4257 default: 4258 /* Convert symbolic operand to proper sizes for matching, but don't 4259 prevent matching a set of insns that only supports sizes other 4260 than those matching the insn suffix. */ 4261 { 4262 i386_operand_type mask, allowed; 4263 const insn_template *t; 4264 4265 operand_type_set (&mask, 0); 4266 operand_type_set (&allowed, 0); 4267 4268 for (t = current_templates->start; 4269 t < current_templates->end; 4270 ++t) 4271 allowed = operand_type_or (allowed, 4272 t->operand_types[op]); 4273 switch (guess_suffix) 4274 { 4275 case QWORD_MNEM_SUFFIX: 4276 mask.bitfield.imm64 = 1; 4277 mask.bitfield.imm32s = 1; 4278 break; 4279 case LONG_MNEM_SUFFIX: 4280 mask.bitfield.imm32 = 1; 4281 break; 4282 case WORD_MNEM_SUFFIX: 4283 mask.bitfield.imm16 = 1; 4284 break; 4285 case BYTE_MNEM_SUFFIX: 4286 mask.bitfield.imm8 = 1; 4287 break; 4288 default: 4289 break; 4290 } 4291 allowed = operand_type_and (mask, allowed); 4292 if (!operand_type_all_zero (&allowed)) 4293 i.types[op] = operand_type_and (i.types[op], mask); 4294 } 4295 break; 4296 } 4297 } 4298 } 4299 4300 /* Try to use the smallest displacement type too. */ 4301 static void 4302 optimize_disp (void) 4303 { 4304 int op; 4305 4306 for (op = i.operands; --op >= 0;) 4307 if (operand_type_check (i.types[op], disp)) 4308 { 4309 if (i.op[op].disps->X_op == O_constant) 4310 { 4311 offsetT op_disp = i.op[op].disps->X_add_number; 4312 4313 if (i.types[op].bitfield.disp16 4314 && (op_disp & ~(offsetT) 0xffff) == 0) 4315 { 4316 /* If this operand is at most 16 bits, convert 4317 to a signed 16 bit number and don't use 64bit 4318 displacement. */ 4319 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); 4320 i.types[op].bitfield.disp64 = 0; 4321 } 4322 if (i.types[op].bitfield.disp32 4323 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) 4324 { 4325 /* If this operand is at most 32 bits, convert 4326 to a signed 32 bit number and don't use 64bit 4327 displacement. */ 4328 op_disp &= (((offsetT) 2 << 31) - 1); 4329 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); 4330 i.types[op].bitfield.disp64 = 0; 4331 } 4332 if (!op_disp && i.types[op].bitfield.baseindex) 4333 { 4334 i.types[op].bitfield.disp8 = 0; 4335 i.types[op].bitfield.disp16 = 0; 4336 i.types[op].bitfield.disp32 = 0; 4337 i.types[op].bitfield.disp32s = 0; 4338 i.types[op].bitfield.disp64 = 0; 4339 i.op[op].disps = 0; 4340 i.disp_operands--; 4341 } 4342 else if (flag_code == CODE_64BIT) 4343 { 4344 if (fits_in_signed_long (op_disp)) 4345 { 4346 i.types[op].bitfield.disp64 = 0; 4347 i.types[op].bitfield.disp32s = 1; 4348 } 4349 if (i.prefix[ADDR_PREFIX] 4350 && fits_in_unsigned_long (op_disp)) 4351 i.types[op].bitfield.disp32 = 1; 4352 } 4353 if ((i.types[op].bitfield.disp32 4354 || i.types[op].bitfield.disp32s 4355 || i.types[op].bitfield.disp16) 4356 && fits_in_signed_byte (op_disp)) 4357 i.types[op].bitfield.disp8 = 1; 4358 } 4359 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 4360 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) 4361 { 4362 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, 4363 i.op[op].disps, 0, i.reloc[op]); 4364 i.types[op].bitfield.disp8 = 0; 4365 i.types[op].bitfield.disp16 = 0; 4366 i.types[op].bitfield.disp32 = 0; 4367 i.types[op].bitfield.disp32s = 0; 4368 i.types[op].bitfield.disp64 = 0; 4369 } 4370 else 4371 /* We only support 64bit displacement on constants. */ 4372 i.types[op].bitfield.disp64 = 0; 4373 } 4374 } 4375 4376 /* Check if operands are valid for the instruction. */ 4377 4378 static int 4379 check_VecOperands (const insn_template *t) 4380 { 4381 unsigned int op; 4382 4383 /* Without VSIB byte, we can't have a vector register for index. */ 4384 if (!t->opcode_modifier.vecsib 4385 && i.index_reg 4386 && (i.index_reg->reg_type.bitfield.regxmm 4387 || i.index_reg->reg_type.bitfield.regymm 4388 || i.index_reg->reg_type.bitfield.regzmm)) 4389 { 4390 i.error = unsupported_vector_index_register; 4391 return 1; 4392 } 4393 4394 /* Check if default mask is allowed. */ 4395 if (t->opcode_modifier.nodefmask 4396 && (!i.mask || i.mask->mask->reg_num == 0)) 4397 { 4398 i.error = no_default_mask; 4399 return 1; 4400 } 4401 4402 /* For VSIB byte, we need a vector register for index, and all vector 4403 registers must be distinct. */ 4404 if (t->opcode_modifier.vecsib) 4405 { 4406 if (!i.index_reg 4407 || !((t->opcode_modifier.vecsib == VecSIB128 4408 && i.index_reg->reg_type.bitfield.regxmm) 4409 || (t->opcode_modifier.vecsib == VecSIB256 4410 && i.index_reg->reg_type.bitfield.regymm) 4411 || (t->opcode_modifier.vecsib == VecSIB512 4412 && i.index_reg->reg_type.bitfield.regzmm))) 4413 { 4414 i.error = invalid_vsib_address; 4415 return 1; 4416 } 4417 4418 gas_assert (i.reg_operands == 2 || i.mask); 4419 if (i.reg_operands == 2 && !i.mask) 4420 { 4421 gas_assert (i.types[0].bitfield.regxmm 4422 || i.types[0].bitfield.regymm); 4423 gas_assert (i.types[2].bitfield.regxmm 4424 || i.types[2].bitfield.regymm); 4425 if (operand_check == check_none) 4426 return 0; 4427 if (register_number (i.op[0].regs) 4428 != register_number (i.index_reg) 4429 && register_number (i.op[2].regs) 4430 != register_number (i.index_reg) 4431 && register_number (i.op[0].regs) 4432 != register_number (i.op[2].regs)) 4433 return 0; 4434 if (operand_check == check_error) 4435 { 4436 i.error = invalid_vector_register_set; 4437 return 1; 4438 } 4439 as_warn (_("mask, index, and destination registers should be distinct")); 4440 } 4441 else if (i.reg_operands == 1 && i.mask) 4442 { 4443 if ((i.types[1].bitfield.regymm 4444 || i.types[1].bitfield.regzmm) 4445 && (register_number (i.op[1].regs) 4446 == register_number (i.index_reg))) 4447 { 4448 if (operand_check == check_error) 4449 { 4450 i.error = invalid_vector_register_set; 4451 return 1; 4452 } 4453 if (operand_check != check_none) 4454 as_warn (_("index and destination registers should be distinct")); 4455 } 4456 } 4457 } 4458 4459 /* Check if broadcast is supported by the instruction and is applied 4460 to the memory operand. */ 4461 if (i.broadcast) 4462 { 4463 int broadcasted_opnd_size; 4464 4465 /* Check if specified broadcast is supported in this instruction, 4466 and it's applied to memory operand of DWORD or QWORD type, 4467 depending on VecESize. */ 4468 if (i.broadcast->type != t->opcode_modifier.broadcast 4469 || !i.types[i.broadcast->operand].bitfield.mem 4470 || (t->opcode_modifier.vecesize == 0 4471 && !i.types[i.broadcast->operand].bitfield.dword 4472 && !i.types[i.broadcast->operand].bitfield.unspecified) 4473 || (t->opcode_modifier.vecesize == 1 4474 && !i.types[i.broadcast->operand].bitfield.qword 4475 && !i.types[i.broadcast->operand].bitfield.unspecified)) 4476 goto bad_broadcast; 4477 4478 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; 4479 if (i.broadcast->type == BROADCAST_1TO16) 4480 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ 4481 else if (i.broadcast->type == BROADCAST_1TO8) 4482 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ 4483 else if (i.broadcast->type == BROADCAST_1TO4) 4484 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ 4485 else if (i.broadcast->type == BROADCAST_1TO2) 4486 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ 4487 else 4488 goto bad_broadcast; 4489 4490 if ((broadcasted_opnd_size == 256 4491 && !t->operand_types[i.broadcast->operand].bitfield.ymmword) 4492 || (broadcasted_opnd_size == 512 4493 && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) 4494 { 4495 bad_broadcast: 4496 i.error = unsupported_broadcast; 4497 return 1; 4498 } 4499 } 4500 /* If broadcast is supported in this instruction, we need to check if 4501 operand of one-element size isn't specified without broadcast. */ 4502 else if (t->opcode_modifier.broadcast && i.mem_operands) 4503 { 4504 /* Find memory operand. */ 4505 for (op = 0; op < i.operands; op++) 4506 if (operand_type_check (i.types[op], anymem)) 4507 break; 4508 gas_assert (op < i.operands); 4509 /* Check size of the memory operand. */ 4510 if ((t->opcode_modifier.vecesize == 0 4511 && i.types[op].bitfield.dword) 4512 || (t->opcode_modifier.vecesize == 1 4513 && i.types[op].bitfield.qword)) 4514 { 4515 i.error = broadcast_needed; 4516 return 1; 4517 } 4518 } 4519 4520 /* Check if requested masking is supported. */ 4521 if (i.mask 4522 && (!t->opcode_modifier.masking 4523 || (i.mask->zeroing 4524 && t->opcode_modifier.masking == MERGING_MASKING))) 4525 { 4526 i.error = unsupported_masking; 4527 return 1; 4528 } 4529 4530 /* Check if masking is applied to dest operand. */ 4531 if (i.mask && (i.mask->operand != (int) (i.operands - 1))) 4532 { 4533 i.error = mask_not_on_destination; 4534 return 1; 4535 } 4536 4537 /* Check RC/SAE. */ 4538 if (i.rounding) 4539 { 4540 if ((i.rounding->type != saeonly 4541 && !t->opcode_modifier.staticrounding) 4542 || (i.rounding->type == saeonly 4543 && (t->opcode_modifier.staticrounding 4544 || !t->opcode_modifier.sae))) 4545 { 4546 i.error = unsupported_rc_sae; 4547 return 1; 4548 } 4549 /* If the instruction has several immediate operands and one of 4550 them is rounding, the rounding operand should be the last 4551 immediate operand. */ 4552 if (i.imm_operands > 1 4553 && i.rounding->operand != (int) (i.imm_operands - 1)) 4554 { 4555 i.error = rc_sae_operand_not_last_imm; 4556 return 1; 4557 } 4558 } 4559 4560 /* Check vector Disp8 operand. */ 4561 if (t->opcode_modifier.disp8memshift) 4562 { 4563 if (i.broadcast) 4564 i.memshift = t->opcode_modifier.vecesize ? 3 : 2; 4565 else 4566 i.memshift = t->opcode_modifier.disp8memshift; 4567 4568 for (op = 0; op < i.operands; op++) 4569 if (operand_type_check (i.types[op], disp) 4570 && i.op[op].disps->X_op == O_constant) 4571 { 4572 offsetT value = i.op[op].disps->X_add_number; 4573 int vec_disp8_ok = fits_in_vec_disp8 (value); 4574 if (t->operand_types [op].bitfield.vec_disp8) 4575 { 4576 if (vec_disp8_ok) 4577 i.types[op].bitfield.vec_disp8 = 1; 4578 else 4579 { 4580 /* Vector insn can only have Vec_Disp8/Disp32 in 4581 32/64bit modes, and Vec_Disp8/Disp16 in 16bit 4582 mode. */ 4583 i.types[op].bitfield.disp8 = 0; 4584 if (flag_code != CODE_16BIT) 4585 i.types[op].bitfield.disp16 = 0; 4586 } 4587 } 4588 else if (flag_code != CODE_16BIT) 4589 { 4590 /* One form of this instruction supports vector Disp8. 4591 Try vector Disp8 if we need to use Disp32. */ 4592 if (vec_disp8_ok && !fits_in_signed_byte (value)) 4593 { 4594 i.error = try_vector_disp8; 4595 return 1; 4596 } 4597 } 4598 } 4599 } 4600 else 4601 i.memshift = -1; 4602 4603 return 0; 4604 } 4605 4606 /* Check if operands are valid for the instruction. Update VEX 4607 operand types. */ 4608 4609 static int 4610 VEX_check_operands (const insn_template *t) 4611 { 4612 /* VREX is only valid with EVEX prefix. */ 4613 if (i.need_vrex && !t->opcode_modifier.evex) 4614 { 4615 i.error = invalid_register_operand; 4616 return 1; 4617 } 4618 4619 if (!t->opcode_modifier.vex) 4620 return 0; 4621 4622 /* Only check VEX_Imm4, which must be the first operand. */ 4623 if (t->operand_types[0].bitfield.vec_imm4) 4624 { 4625 if (i.op[0].imms->X_op != O_constant 4626 || !fits_in_imm4 (i.op[0].imms->X_add_number)) 4627 { 4628 i.error = bad_imm4; 4629 return 1; 4630 } 4631 4632 /* Turn off Imm8 so that update_imm won't complain. */ 4633 i.types[0] = vec_imm4; 4634 } 4635 4636 return 0; 4637 } 4638 4639 static const insn_template * 4640 match_template (void) 4641 { 4642 /* Points to template once we've found it. */ 4643 const insn_template *t; 4644 i386_operand_type overlap0, overlap1, overlap2, overlap3; 4645 i386_operand_type overlap4; 4646 unsigned int found_reverse_match; 4647 i386_opcode_modifier suffix_check; 4648 i386_operand_type operand_types [MAX_OPERANDS]; 4649 int addr_prefix_disp; 4650 unsigned int j; 4651 unsigned int found_cpu_match; 4652 unsigned int check_register; 4653 enum i386_error specific_error = 0; 4654 4655 #if MAX_OPERANDS != 5 4656 # error "MAX_OPERANDS must be 5." 4657 #endif 4658 4659 found_reverse_match = 0; 4660 addr_prefix_disp = -1; 4661 4662 memset (&suffix_check, 0, sizeof (suffix_check)); 4663 if (i.suffix == BYTE_MNEM_SUFFIX) 4664 suffix_check.no_bsuf = 1; 4665 else if (i.suffix == WORD_MNEM_SUFFIX) 4666 suffix_check.no_wsuf = 1; 4667 else if (i.suffix == SHORT_MNEM_SUFFIX) 4668 suffix_check.no_ssuf = 1; 4669 else if (i.suffix == LONG_MNEM_SUFFIX) 4670 suffix_check.no_lsuf = 1; 4671 else if (i.suffix == QWORD_MNEM_SUFFIX) 4672 suffix_check.no_qsuf = 1; 4673 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) 4674 suffix_check.no_ldsuf = 1; 4675 4676 /* Must have right number of operands. */ 4677 i.error = number_of_operands_mismatch; 4678 4679 for (t = current_templates->start; t < current_templates->end; t++) 4680 { 4681 addr_prefix_disp = -1; 4682 4683 if (i.operands != t->operands) 4684 continue; 4685 4686 /* Check processor support. */ 4687 i.error = unsupported; 4688 found_cpu_match = (cpu_flags_match (t) 4689 == CPU_FLAGS_PERFECT_MATCH); 4690 if (!found_cpu_match) 4691 continue; 4692 4693 /* Check old gcc support. */ 4694 i.error = old_gcc_only; 4695 if (!old_gcc && t->opcode_modifier.oldgcc) 4696 continue; 4697 4698 /* Check AT&T mnemonic. */ 4699 i.error = unsupported_with_intel_mnemonic; 4700 if (intel_mnemonic && t->opcode_modifier.attmnemonic) 4701 continue; 4702 4703 /* Check AT&T/Intel syntax. */ 4704 i.error = unsupported_syntax; 4705 if ((intel_syntax && t->opcode_modifier.attsyntax) 4706 || (!intel_syntax && t->opcode_modifier.intelsyntax)) 4707 continue; 4708 4709 /* Check the suffix, except for some instructions in intel mode. */ 4710 i.error = invalid_instruction_suffix; 4711 if ((!intel_syntax || !t->opcode_modifier.ignoresize) 4712 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) 4713 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) 4714 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) 4715 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) 4716 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) 4717 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) 4718 continue; 4719 4720 if (!operand_size_match (t)) 4721 continue; 4722 4723 for (j = 0; j < MAX_OPERANDS; j++) 4724 operand_types[j] = t->operand_types[j]; 4725 4726 /* In general, don't allow 64-bit operands in 32-bit mode. */ 4727 if (i.suffix == QWORD_MNEM_SUFFIX 4728 && flag_code != CODE_64BIT 4729 && (intel_syntax 4730 ? (!t->opcode_modifier.ignoresize 4731 && !intel_float_operand (t->name)) 4732 : intel_float_operand (t->name) != 2) 4733 && ((!operand_types[0].bitfield.regmmx 4734 && !operand_types[0].bitfield.regxmm 4735 && !operand_types[0].bitfield.regymm 4736 && !operand_types[0].bitfield.regzmm) 4737 || (!operand_types[t->operands > 1].bitfield.regmmx 4738 && operand_types[t->operands > 1].bitfield.regxmm 4739 && operand_types[t->operands > 1].bitfield.regymm 4740 && operand_types[t->operands > 1].bitfield.regzmm)) 4741 && (t->base_opcode != 0x0fc7 4742 || t->extension_opcode != 1 /* cmpxchg8b */)) 4743 continue; 4744 4745 /* In general, don't allow 32-bit operands on pre-386. */ 4746 else if (i.suffix == LONG_MNEM_SUFFIX 4747 && !cpu_arch_flags.bitfield.cpui386 4748 && (intel_syntax 4749 ? (!t->opcode_modifier.ignoresize 4750 && !intel_float_operand (t->name)) 4751 : intel_float_operand (t->name) != 2) 4752 && ((!operand_types[0].bitfield.regmmx 4753 && !operand_types[0].bitfield.regxmm) 4754 || (!operand_types[t->operands > 1].bitfield.regmmx 4755 && operand_types[t->operands > 1].bitfield.regxmm))) 4756 continue; 4757 4758 /* Do not verify operands when there are none. */ 4759 else 4760 { 4761 if (!t->operands) 4762 /* We've found a match; break out of loop. */ 4763 break; 4764 } 4765 4766 /* Address size prefix will turn Disp64/Disp32/Disp16 operand 4767 into Disp32/Disp16/Disp32 operand. */ 4768 if (i.prefix[ADDR_PREFIX] != 0) 4769 { 4770 /* There should be only one Disp operand. */ 4771 switch (flag_code) 4772 { 4773 case CODE_16BIT: 4774 for (j = 0; j < MAX_OPERANDS; j++) 4775 { 4776 if (operand_types[j].bitfield.disp16) 4777 { 4778 addr_prefix_disp = j; 4779 operand_types[j].bitfield.disp32 = 1; 4780 operand_types[j].bitfield.disp16 = 0; 4781 break; 4782 } 4783 } 4784 break; 4785 case CODE_32BIT: 4786 for (j = 0; j < MAX_OPERANDS; j++) 4787 { 4788 if (operand_types[j].bitfield.disp32) 4789 { 4790 addr_prefix_disp = j; 4791 operand_types[j].bitfield.disp32 = 0; 4792 operand_types[j].bitfield.disp16 = 1; 4793 break; 4794 } 4795 } 4796 break; 4797 case CODE_64BIT: 4798 for (j = 0; j < MAX_OPERANDS; j++) 4799 { 4800 if (operand_types[j].bitfield.disp64) 4801 { 4802 addr_prefix_disp = j; 4803 operand_types[j].bitfield.disp64 = 0; 4804 operand_types[j].bitfield.disp32 = 1; 4805 break; 4806 } 4807 } 4808 break; 4809 } 4810 } 4811 4812 /* We check register size if needed. */ 4813 check_register = t->opcode_modifier.checkregsize; 4814 overlap0 = operand_type_and (i.types[0], operand_types[0]); 4815 switch (t->operands) 4816 { 4817 case 1: 4818 if (!operand_type_match (overlap0, i.types[0])) 4819 continue; 4820 break; 4821 case 2: 4822 /* xchg %eax, %eax is a special case. It is an aliase for nop 4823 only in 32bit mode and we can use opcode 0x90. In 64bit 4824 mode, we can't use 0x90 for xchg %eax, %eax since it should 4825 zero-extend %eax to %rax. */ 4826 if (flag_code == CODE_64BIT 4827 && t->base_opcode == 0x90 4828 && operand_type_equal (&i.types [0], &acc32) 4829 && operand_type_equal (&i.types [1], &acc32)) 4830 continue; 4831 if (i.swap_operand) 4832 { 4833 /* If we swap operand in encoding, we either match 4834 the next one or reverse direction of operands. */ 4835 if (t->opcode_modifier.s) 4836 continue; 4837 else if (t->opcode_modifier.d) 4838 goto check_reverse; 4839 } 4840 4841 case 3: 4842 /* If we swap operand in encoding, we match the next one. */ 4843 if (i.swap_operand && t->opcode_modifier.s) 4844 continue; 4845 case 4: 4846 case 5: 4847 overlap1 = operand_type_and (i.types[1], operand_types[1]); 4848 if (!operand_type_match (overlap0, i.types[0]) 4849 || !operand_type_match (overlap1, i.types[1]) 4850 || (check_register 4851 && !operand_type_register_match (overlap0, i.types[0], 4852 operand_types[0], 4853 overlap1, i.types[1], 4854 operand_types[1]))) 4855 { 4856 /* Check if other direction is valid ... */ 4857 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) 4858 continue; 4859 4860 check_reverse: 4861 /* Try reversing direction of operands. */ 4862 overlap0 = operand_type_and (i.types[0], operand_types[1]); 4863 overlap1 = operand_type_and (i.types[1], operand_types[0]); 4864 if (!operand_type_match (overlap0, i.types[0]) 4865 || !operand_type_match (overlap1, i.types[1]) 4866 || (check_register 4867 && !operand_type_register_match (overlap0, 4868 i.types[0], 4869 operand_types[1], 4870 overlap1, 4871 i.types[1], 4872 operand_types[0]))) 4873 { 4874 /* Does not match either direction. */ 4875 continue; 4876 } 4877 /* found_reverse_match holds which of D or FloatDR 4878 we've found. */ 4879 if (t->opcode_modifier.d) 4880 found_reverse_match = Opcode_D; 4881 else if (t->opcode_modifier.floatd) 4882 found_reverse_match = Opcode_FloatD; 4883 else 4884 found_reverse_match = 0; 4885 if (t->opcode_modifier.floatr) 4886 found_reverse_match |= Opcode_FloatR; 4887 } 4888 else 4889 { 4890 /* Found a forward 2 operand match here. */ 4891 switch (t->operands) 4892 { 4893 case 5: 4894 overlap4 = operand_type_and (i.types[4], 4895 operand_types[4]); 4896 case 4: 4897 overlap3 = operand_type_and (i.types[3], 4898 operand_types[3]); 4899 case 3: 4900 overlap2 = operand_type_and (i.types[2], 4901 operand_types[2]); 4902 break; 4903 } 4904 4905 switch (t->operands) 4906 { 4907 case 5: 4908 if (!operand_type_match (overlap4, i.types[4]) 4909 || !operand_type_register_match (overlap3, 4910 i.types[3], 4911 operand_types[3], 4912 overlap4, 4913 i.types[4], 4914 operand_types[4])) 4915 continue; 4916 case 4: 4917 if (!operand_type_match (overlap3, i.types[3]) 4918 || (check_register 4919 && !operand_type_register_match (overlap2, 4920 i.types[2], 4921 operand_types[2], 4922 overlap3, 4923 i.types[3], 4924 operand_types[3]))) 4925 continue; 4926 case 3: 4927 /* Here we make use of the fact that there are no 4928 reverse match 3 operand instructions, and all 3 4929 operand instructions only need to be checked for 4930 register consistency between operands 2 and 3. */ 4931 if (!operand_type_match (overlap2, i.types[2]) 4932 || (check_register 4933 && !operand_type_register_match (overlap1, 4934 i.types[1], 4935 operand_types[1], 4936 overlap2, 4937 i.types[2], 4938 operand_types[2]))) 4939 continue; 4940 break; 4941 } 4942 } 4943 /* Found either forward/reverse 2, 3 or 4 operand match here: 4944 slip through to break. */ 4945 } 4946 if (!found_cpu_match) 4947 { 4948 found_reverse_match = 0; 4949 continue; 4950 } 4951 4952 /* Check if vector and VEX operands are valid. */ 4953 if (check_VecOperands (t) || VEX_check_operands (t)) 4954 { 4955 specific_error = i.error; 4956 continue; 4957 } 4958 4959 /* We've found a match; break out of loop. */ 4960 break; 4961 } 4962 4963 if (t == current_templates->end) 4964 { 4965 /* We found no match. */ 4966 const char *err_msg; 4967 switch (specific_error ? specific_error : i.error) 4968 { 4969 default: 4970 abort (); 4971 case operand_size_mismatch: 4972 err_msg = _("operand size mismatch"); 4973 break; 4974 case operand_type_mismatch: 4975 err_msg = _("operand type mismatch"); 4976 break; 4977 case register_type_mismatch: 4978 err_msg = _("register type mismatch"); 4979 break; 4980 case number_of_operands_mismatch: 4981 err_msg = _("number of operands mismatch"); 4982 break; 4983 case invalid_instruction_suffix: 4984 err_msg = _("invalid instruction suffix"); 4985 break; 4986 case bad_imm4: 4987 err_msg = _("constant doesn't fit in 4 bits"); 4988 break; 4989 case old_gcc_only: 4990 err_msg = _("only supported with old gcc"); 4991 break; 4992 case unsupported_with_intel_mnemonic: 4993 err_msg = _("unsupported with Intel mnemonic"); 4994 break; 4995 case unsupported_syntax: 4996 err_msg = _("unsupported syntax"); 4997 break; 4998 case unsupported: 4999 as_bad (_("unsupported instruction `%s'"), 5000 current_templates->start->name); 5001 return NULL; 5002 case invalid_vsib_address: 5003 err_msg = _("invalid VSIB address"); 5004 break; 5005 case invalid_vector_register_set: 5006 err_msg = _("mask, index, and destination registers must be distinct"); 5007 break; 5008 case unsupported_vector_index_register: 5009 err_msg = _("unsupported vector index register"); 5010 break; 5011 case unsupported_broadcast: 5012 err_msg = _("unsupported broadcast"); 5013 break; 5014 case broadcast_not_on_src_operand: 5015 err_msg = _("broadcast not on source memory operand"); 5016 break; 5017 case broadcast_needed: 5018 err_msg = _("broadcast is needed for operand of such type"); 5019 break; 5020 case unsupported_masking: 5021 err_msg = _("unsupported masking"); 5022 break; 5023 case mask_not_on_destination: 5024 err_msg = _("mask not on destination operand"); 5025 break; 5026 case no_default_mask: 5027 err_msg = _("default mask isn't allowed"); 5028 break; 5029 case unsupported_rc_sae: 5030 err_msg = _("unsupported static rounding/sae"); 5031 break; 5032 case rc_sae_operand_not_last_imm: 5033 if (intel_syntax) 5034 err_msg = _("RC/SAE operand must precede immediate operands"); 5035 else 5036 err_msg = _("RC/SAE operand must follow immediate operands"); 5037 break; 5038 case invalid_register_operand: 5039 err_msg = _("invalid register operand"); 5040 break; 5041 } 5042 as_bad (_("%s for `%s'"), err_msg, 5043 current_templates->start->name); 5044 return NULL; 5045 } 5046 5047 if (!quiet_warnings) 5048 { 5049 if (!intel_syntax 5050 && (i.types[0].bitfield.jumpabsolute 5051 != operand_types[0].bitfield.jumpabsolute)) 5052 { 5053 as_warn (_("indirect %s without `*'"), t->name); 5054 } 5055 5056 if (t->opcode_modifier.isprefix 5057 && t->opcode_modifier.ignoresize) 5058 { 5059 /* Warn them that a data or address size prefix doesn't 5060 affect assembly of the next line of code. */ 5061 as_warn (_("stand-alone `%s' prefix"), t->name); 5062 } 5063 } 5064 5065 /* Copy the template we found. */ 5066 i.tm = *t; 5067 5068 if (addr_prefix_disp != -1) 5069 i.tm.operand_types[addr_prefix_disp] 5070 = operand_types[addr_prefix_disp]; 5071 5072 if (found_reverse_match) 5073 { 5074 /* If we found a reverse match we must alter the opcode 5075 direction bit. found_reverse_match holds bits to change 5076 (different for int & float insns). */ 5077 5078 i.tm.base_opcode ^= found_reverse_match; 5079 5080 i.tm.operand_types[0] = operand_types[1]; 5081 i.tm.operand_types[1] = operand_types[0]; 5082 } 5083 5084 return t; 5085 } 5086 5087 static int 5088 check_string (void) 5089 { 5090 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; 5091 if (i.tm.operand_types[mem_op].bitfield.esseg) 5092 { 5093 if (i.seg[0] != NULL && i.seg[0] != &es) 5094 { 5095 as_bad (_("`%s' operand %d must use `%ses' segment"), 5096 i.tm.name, 5097 mem_op + 1, 5098 register_prefix); 5099 return 0; 5100 } 5101 /* There's only ever one segment override allowed per instruction. 5102 This instruction possibly has a legal segment override on the 5103 second operand, so copy the segment to where non-string 5104 instructions store it, allowing common code. */ 5105 i.seg[0] = i.seg[1]; 5106 } 5107 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) 5108 { 5109 if (i.seg[1] != NULL && i.seg[1] != &es) 5110 { 5111 as_bad (_("`%s' operand %d must use `%ses' segment"), 5112 i.tm.name, 5113 mem_op + 2, 5114 register_prefix); 5115 return 0; 5116 } 5117 } 5118 return 1; 5119 } 5120 5121 static int 5122 process_suffix (void) 5123 { 5124 /* If matched instruction specifies an explicit instruction mnemonic 5125 suffix, use it. */ 5126 if (i.tm.opcode_modifier.size16) 5127 i.suffix = WORD_MNEM_SUFFIX; 5128 else if (i.tm.opcode_modifier.size32) 5129 i.suffix = LONG_MNEM_SUFFIX; 5130 else if (i.tm.opcode_modifier.size64) 5131 i.suffix = QWORD_MNEM_SUFFIX; 5132 else if (i.reg_operands) 5133 { 5134 /* If there's no instruction mnemonic suffix we try to invent one 5135 based on register operands. */ 5136 if (!i.suffix) 5137 { 5138 /* We take i.suffix from the last register operand specified, 5139 Destination register type is more significant than source 5140 register type. crc32 in SSE4.2 prefers source register 5141 type. */ 5142 if (i.tm.base_opcode == 0xf20f38f1) 5143 { 5144 if (i.types[0].bitfield.reg16) 5145 i.suffix = WORD_MNEM_SUFFIX; 5146 else if (i.types[0].bitfield.reg32) 5147 i.suffix = LONG_MNEM_SUFFIX; 5148 else if (i.types[0].bitfield.reg64) 5149 i.suffix = QWORD_MNEM_SUFFIX; 5150 } 5151 else if (i.tm.base_opcode == 0xf20f38f0) 5152 { 5153 if (i.types[0].bitfield.reg8) 5154 i.suffix = BYTE_MNEM_SUFFIX; 5155 } 5156 5157 if (!i.suffix) 5158 { 5159 int op; 5160 5161 if (i.tm.base_opcode == 0xf20f38f1 5162 || i.tm.base_opcode == 0xf20f38f0) 5163 { 5164 /* We have to know the operand size for crc32. */ 5165 as_bad (_("ambiguous memory operand size for `%s`"), 5166 i.tm.name); 5167 return 0; 5168 } 5169 5170 for (op = i.operands; --op >= 0;) 5171 if (!i.tm.operand_types[op].bitfield.inoutportreg) 5172 { 5173 if (i.types[op].bitfield.reg8) 5174 { 5175 i.suffix = BYTE_MNEM_SUFFIX; 5176 break; 5177 } 5178 else if (i.types[op].bitfield.reg16) 5179 { 5180 i.suffix = WORD_MNEM_SUFFIX; 5181 break; 5182 } 5183 else if (i.types[op].bitfield.reg32) 5184 { 5185 i.suffix = LONG_MNEM_SUFFIX; 5186 break; 5187 } 5188 else if (i.types[op].bitfield.reg64) 5189 { 5190 i.suffix = QWORD_MNEM_SUFFIX; 5191 break; 5192 } 5193 } 5194 } 5195 } 5196 else if (i.suffix == BYTE_MNEM_SUFFIX) 5197 { 5198 if (intel_syntax 5199 && i.tm.opcode_modifier.ignoresize 5200 && i.tm.opcode_modifier.no_bsuf) 5201 i.suffix = 0; 5202 else if (!check_byte_reg ()) 5203 return 0; 5204 } 5205 else if (i.suffix == LONG_MNEM_SUFFIX) 5206 { 5207 if (intel_syntax 5208 && i.tm.opcode_modifier.ignoresize 5209 && i.tm.opcode_modifier.no_lsuf) 5210 i.suffix = 0; 5211 else if (!check_long_reg ()) 5212 return 0; 5213 } 5214 else if (i.suffix == QWORD_MNEM_SUFFIX) 5215 { 5216 if (intel_syntax 5217 && i.tm.opcode_modifier.ignoresize 5218 && i.tm.opcode_modifier.no_qsuf) 5219 i.suffix = 0; 5220 else if (!check_qword_reg ()) 5221 return 0; 5222 } 5223 else if (i.suffix == WORD_MNEM_SUFFIX) 5224 { 5225 if (intel_syntax 5226 && i.tm.opcode_modifier.ignoresize 5227 && i.tm.opcode_modifier.no_wsuf) 5228 i.suffix = 0; 5229 else if (!check_word_reg ()) 5230 return 0; 5231 } 5232 else if (i.suffix == XMMWORD_MNEM_SUFFIX 5233 || i.suffix == YMMWORD_MNEM_SUFFIX 5234 || i.suffix == ZMMWORD_MNEM_SUFFIX) 5235 { 5236 /* Skip if the instruction has x/y/z suffix. match_template 5237 should check if it is a valid suffix. */ 5238 } 5239 else if (intel_syntax && i.tm.opcode_modifier.ignoresize) 5240 /* Do nothing if the instruction is going to ignore the prefix. */ 5241 ; 5242 else 5243 abort (); 5244 } 5245 else if (i.tm.opcode_modifier.defaultsize 5246 && !i.suffix 5247 /* exclude fldenv/frstor/fsave/fstenv */ 5248 && i.tm.opcode_modifier.no_ssuf) 5249 { 5250 i.suffix = stackop_size; 5251 } 5252 else if (intel_syntax 5253 && !i.suffix 5254 && (i.tm.operand_types[0].bitfield.jumpabsolute 5255 || i.tm.opcode_modifier.jumpbyte 5256 || i.tm.opcode_modifier.jumpintersegment 5257 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ 5258 && i.tm.extension_opcode <= 3))) 5259 { 5260 switch (flag_code) 5261 { 5262 case CODE_64BIT: 5263 if (!i.tm.opcode_modifier.no_qsuf) 5264 { 5265 i.suffix = QWORD_MNEM_SUFFIX; 5266 break; 5267 } 5268 case CODE_32BIT: 5269 if (!i.tm.opcode_modifier.no_lsuf) 5270 i.suffix = LONG_MNEM_SUFFIX; 5271 break; 5272 case CODE_16BIT: 5273 if (!i.tm.opcode_modifier.no_wsuf) 5274 i.suffix = WORD_MNEM_SUFFIX; 5275 break; 5276 } 5277 } 5278 5279 if (!i.suffix) 5280 { 5281 if (!intel_syntax) 5282 { 5283 if (i.tm.opcode_modifier.w) 5284 { 5285 as_bad (_("no instruction mnemonic suffix given and " 5286 "no register operands; can't size instruction")); 5287 return 0; 5288 } 5289 } 5290 else 5291 { 5292 unsigned int suffixes; 5293 5294 suffixes = !i.tm.opcode_modifier.no_bsuf; 5295 if (!i.tm.opcode_modifier.no_wsuf) 5296 suffixes |= 1 << 1; 5297 if (!i.tm.opcode_modifier.no_lsuf) 5298 suffixes |= 1 << 2; 5299 if (!i.tm.opcode_modifier.no_ldsuf) 5300 suffixes |= 1 << 3; 5301 if (!i.tm.opcode_modifier.no_ssuf) 5302 suffixes |= 1 << 4; 5303 if (!i.tm.opcode_modifier.no_qsuf) 5304 suffixes |= 1 << 5; 5305 5306 /* There are more than suffix matches. */ 5307 if (i.tm.opcode_modifier.w 5308 || ((suffixes & (suffixes - 1)) 5309 && !i.tm.opcode_modifier.defaultsize 5310 && !i.tm.opcode_modifier.ignoresize)) 5311 { 5312 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 5313 return 0; 5314 } 5315 } 5316 } 5317 5318 /* Change the opcode based on the operand size given by i.suffix; 5319 We don't need to change things for byte insns. */ 5320 5321 if (i.suffix 5322 && i.suffix != BYTE_MNEM_SUFFIX 5323 && i.suffix != XMMWORD_MNEM_SUFFIX 5324 && i.suffix != YMMWORD_MNEM_SUFFIX 5325 && i.suffix != ZMMWORD_MNEM_SUFFIX) 5326 { 5327 /* It's not a byte, select word/dword operation. */ 5328 if (i.tm.opcode_modifier.w) 5329 { 5330 if (i.tm.opcode_modifier.shortform) 5331 i.tm.base_opcode |= 8; 5332 else 5333 i.tm.base_opcode |= 1; 5334 } 5335 5336 /* Now select between word & dword operations via the operand 5337 size prefix, except for instructions that will ignore this 5338 prefix anyway. */ 5339 if (i.tm.opcode_modifier.addrprefixop0) 5340 { 5341 /* The address size override prefix changes the size of the 5342 first operand. */ 5343 if ((flag_code == CODE_32BIT 5344 && i.op->regs[0].reg_type.bitfield.reg16) 5345 || (flag_code != CODE_32BIT 5346 && i.op->regs[0].reg_type.bitfield.reg32)) 5347 if (!add_prefix (ADDR_PREFIX_OPCODE)) 5348 return 0; 5349 } 5350 else if (i.suffix != QWORD_MNEM_SUFFIX 5351 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX 5352 && !i.tm.opcode_modifier.ignoresize 5353 && !i.tm.opcode_modifier.floatmf 5354 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) 5355 || (flag_code == CODE_64BIT 5356 && i.tm.opcode_modifier.jumpbyte))) 5357 { 5358 unsigned int prefix = DATA_PREFIX_OPCODE; 5359 5360 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ 5361 prefix = ADDR_PREFIX_OPCODE; 5362 5363 if (!add_prefix (prefix)) 5364 return 0; 5365 } 5366 5367 /* Set mode64 for an operand. */ 5368 if (i.suffix == QWORD_MNEM_SUFFIX 5369 && flag_code == CODE_64BIT 5370 && !i.tm.opcode_modifier.norex64) 5371 { 5372 /* Special case for xchg %rax,%rax. It is NOP and doesn't 5373 need rex64. cmpxchg8b is also a special case. */ 5374 if (! (i.operands == 2 5375 && i.tm.base_opcode == 0x90 5376 && i.tm.extension_opcode == None 5377 && operand_type_equal (&i.types [0], &acc64) 5378 && operand_type_equal (&i.types [1], &acc64)) 5379 && ! (i.operands == 1 5380 && i.tm.base_opcode == 0xfc7 5381 && i.tm.extension_opcode == 1 5382 && !operand_type_check (i.types [0], reg) 5383 && operand_type_check (i.types [0], anymem))) 5384 i.rex |= REX_W; 5385 } 5386 5387 /* Size floating point instruction. */ 5388 if (i.suffix == LONG_MNEM_SUFFIX) 5389 if (i.tm.opcode_modifier.floatmf) 5390 i.tm.base_opcode ^= 4; 5391 } 5392 5393 return 1; 5394 } 5395 5396 static int 5397 check_byte_reg (void) 5398 { 5399 int op; 5400 5401 for (op = i.operands; --op >= 0;) 5402 { 5403 /* If this is an eight bit register, it's OK. If it's the 16 or 5404 32 bit version of an eight bit register, we will just use the 5405 low portion, and that's OK too. */ 5406 if (i.types[op].bitfield.reg8) 5407 continue; 5408 5409 /* I/O port address operands are OK too. */ 5410 if (i.tm.operand_types[op].bitfield.inoutportreg) 5411 continue; 5412 5413 /* crc32 doesn't generate this warning. */ 5414 if (i.tm.base_opcode == 0xf20f38f0) 5415 continue; 5416 5417 if ((i.types[op].bitfield.reg16 5418 || i.types[op].bitfield.reg32 5419 || i.types[op].bitfield.reg64) 5420 && i.op[op].regs->reg_num < 4 5421 /* Prohibit these changes in 64bit mode, since the lowering 5422 would be more complicated. */ 5423 && flag_code != CODE_64BIT) 5424 { 5425 #if REGISTER_WARNINGS 5426 if (!quiet_warnings) 5427 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 5428 register_prefix, 5429 (i.op[op].regs + (i.types[op].bitfield.reg16 5430 ? REGNAM_AL - REGNAM_AX 5431 : REGNAM_AL - REGNAM_EAX))->reg_name, 5432 register_prefix, 5433 i.op[op].regs->reg_name, 5434 i.suffix); 5435 #endif 5436 continue; 5437 } 5438 /* Any other register is bad. */ 5439 if (i.types[op].bitfield.reg16 5440 || i.types[op].bitfield.reg32 5441 || i.types[op].bitfield.reg64 5442 || i.types[op].bitfield.regmmx 5443 || i.types[op].bitfield.regxmm 5444 || i.types[op].bitfield.regymm 5445 || i.types[op].bitfield.regzmm 5446 || i.types[op].bitfield.sreg2 5447 || i.types[op].bitfield.sreg3 5448 || i.types[op].bitfield.control 5449 || i.types[op].bitfield.debug 5450 || i.types[op].bitfield.test 5451 || i.types[op].bitfield.floatreg 5452 || i.types[op].bitfield.floatacc) 5453 { 5454 as_bad (_("`%s%s' not allowed with `%s%c'"), 5455 register_prefix, 5456 i.op[op].regs->reg_name, 5457 i.tm.name, 5458 i.suffix); 5459 return 0; 5460 } 5461 } 5462 return 1; 5463 } 5464 5465 static int 5466 check_long_reg (void) 5467 { 5468 int op; 5469 5470 for (op = i.operands; --op >= 0;) 5471 /* Reject eight bit registers, except where the template requires 5472 them. (eg. movzb) */ 5473 if (i.types[op].bitfield.reg8 5474 && (i.tm.operand_types[op].bitfield.reg16 5475 || i.tm.operand_types[op].bitfield.reg32 5476 || i.tm.operand_types[op].bitfield.acc)) 5477 { 5478 as_bad (_("`%s%s' not allowed with `%s%c'"), 5479 register_prefix, 5480 i.op[op].regs->reg_name, 5481 i.tm.name, 5482 i.suffix); 5483 return 0; 5484 } 5485 /* Warn if the e prefix on a general reg is missing. */ 5486 else if ((!quiet_warnings || flag_code == CODE_64BIT) 5487 && i.types[op].bitfield.reg16 5488 && (i.tm.operand_types[op].bitfield.reg32 5489 || i.tm.operand_types[op].bitfield.acc)) 5490 { 5491 /* Prohibit these changes in the 64bit mode, since the 5492 lowering is more complicated. */ 5493 if (flag_code == CODE_64BIT) 5494 { 5495 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5496 register_prefix, i.op[op].regs->reg_name, 5497 i.suffix); 5498 return 0; 5499 } 5500 #if REGISTER_WARNINGS 5501 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 5502 register_prefix, 5503 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, 5504 register_prefix, i.op[op].regs->reg_name, i.suffix); 5505 #endif 5506 } 5507 /* Warn if the r prefix on a general reg is present. */ 5508 else if (i.types[op].bitfield.reg64 5509 && (i.tm.operand_types[op].bitfield.reg32 5510 || i.tm.operand_types[op].bitfield.acc)) 5511 { 5512 if (intel_syntax 5513 && i.tm.opcode_modifier.toqword 5514 && !i.types[0].bitfield.regxmm) 5515 { 5516 /* Convert to QWORD. We want REX byte. */ 5517 i.suffix = QWORD_MNEM_SUFFIX; 5518 } 5519 else 5520 { 5521 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5522 register_prefix, i.op[op].regs->reg_name, 5523 i.suffix); 5524 return 0; 5525 } 5526 } 5527 return 1; 5528 } 5529 5530 static int 5531 check_qword_reg (void) 5532 { 5533 int op; 5534 5535 for (op = i.operands; --op >= 0; ) 5536 /* Reject eight bit registers, except where the template requires 5537 them. (eg. movzb) */ 5538 if (i.types[op].bitfield.reg8 5539 && (i.tm.operand_types[op].bitfield.reg16 5540 || i.tm.operand_types[op].bitfield.reg32 5541 || i.tm.operand_types[op].bitfield.acc)) 5542 { 5543 as_bad (_("`%s%s' not allowed with `%s%c'"), 5544 register_prefix, 5545 i.op[op].regs->reg_name, 5546 i.tm.name, 5547 i.suffix); 5548 return 0; 5549 } 5550 /* Warn if the r prefix on a general reg is missing. */ 5551 else if ((i.types[op].bitfield.reg16 5552 || i.types[op].bitfield.reg32) 5553 && (i.tm.operand_types[op].bitfield.reg32 5554 || i.tm.operand_types[op].bitfield.acc)) 5555 { 5556 /* Prohibit these changes in the 64bit mode, since the 5557 lowering is more complicated. */ 5558 if (intel_syntax 5559 && i.tm.opcode_modifier.todword 5560 && !i.types[0].bitfield.regxmm) 5561 { 5562 /* Convert to DWORD. We don't want REX byte. */ 5563 i.suffix = LONG_MNEM_SUFFIX; 5564 } 5565 else 5566 { 5567 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5568 register_prefix, i.op[op].regs->reg_name, 5569 i.suffix); 5570 return 0; 5571 } 5572 } 5573 return 1; 5574 } 5575 5576 static int 5577 check_word_reg (void) 5578 { 5579 int op; 5580 for (op = i.operands; --op >= 0;) 5581 /* Reject eight bit registers, except where the template requires 5582 them. (eg. movzb) */ 5583 if (i.types[op].bitfield.reg8 5584 && (i.tm.operand_types[op].bitfield.reg16 5585 || i.tm.operand_types[op].bitfield.reg32 5586 || i.tm.operand_types[op].bitfield.acc)) 5587 { 5588 as_bad (_("`%s%s' not allowed with `%s%c'"), 5589 register_prefix, 5590 i.op[op].regs->reg_name, 5591 i.tm.name, 5592 i.suffix); 5593 return 0; 5594 } 5595 /* Warn if the e or r prefix on a general reg is present. */ 5596 else if ((!quiet_warnings || flag_code == CODE_64BIT) 5597 && (i.types[op].bitfield.reg32 5598 || i.types[op].bitfield.reg64) 5599 && (i.tm.operand_types[op].bitfield.reg16 5600 || i.tm.operand_types[op].bitfield.acc)) 5601 { 5602 /* Prohibit these changes in the 64bit mode, since the 5603 lowering is more complicated. */ 5604 if (flag_code == CODE_64BIT) 5605 { 5606 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 5607 register_prefix, i.op[op].regs->reg_name, 5608 i.suffix); 5609 return 0; 5610 } 5611 #if REGISTER_WARNINGS 5612 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 5613 register_prefix, 5614 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, 5615 register_prefix, i.op[op].regs->reg_name, i.suffix); 5616 #endif 5617 } 5618 return 1; 5619 } 5620 5621 static int 5622 update_imm (unsigned int j) 5623 { 5624 i386_operand_type overlap = i.types[j]; 5625 if ((overlap.bitfield.imm8 5626 || overlap.bitfield.imm8s 5627 || overlap.bitfield.imm16 5628 || overlap.bitfield.imm32 5629 || overlap.bitfield.imm32s 5630 || overlap.bitfield.imm64) 5631 && !operand_type_equal (&overlap, &imm8) 5632 && !operand_type_equal (&overlap, &imm8s) 5633 && !operand_type_equal (&overlap, &imm16) 5634 && !operand_type_equal (&overlap, &imm32) 5635 && !operand_type_equal (&overlap, &imm32s) 5636 && !operand_type_equal (&overlap, &imm64)) 5637 { 5638 if (i.suffix) 5639 { 5640 i386_operand_type temp; 5641 5642 operand_type_set (&temp, 0); 5643 if (i.suffix == BYTE_MNEM_SUFFIX) 5644 { 5645 temp.bitfield.imm8 = overlap.bitfield.imm8; 5646 temp.bitfield.imm8s = overlap.bitfield.imm8s; 5647 } 5648 else if (i.suffix == WORD_MNEM_SUFFIX) 5649 temp.bitfield.imm16 = overlap.bitfield.imm16; 5650 else if (i.suffix == QWORD_MNEM_SUFFIX) 5651 { 5652 temp.bitfield.imm64 = overlap.bitfield.imm64; 5653 temp.bitfield.imm32s = overlap.bitfield.imm32s; 5654 } 5655 else 5656 temp.bitfield.imm32 = overlap.bitfield.imm32; 5657 overlap = temp; 5658 } 5659 else if (operand_type_equal (&overlap, &imm16_32_32s) 5660 || operand_type_equal (&overlap, &imm16_32) 5661 || operand_type_equal (&overlap, &imm16_32s)) 5662 { 5663 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 5664 overlap = imm16; 5665 else 5666 overlap = imm32s; 5667 } 5668 if (!operand_type_equal (&overlap, &imm8) 5669 && !operand_type_equal (&overlap, &imm8s) 5670 && !operand_type_equal (&overlap, &imm16) 5671 && !operand_type_equal (&overlap, &imm32) 5672 && !operand_type_equal (&overlap, &imm32s) 5673 && !operand_type_equal (&overlap, &imm64)) 5674 { 5675 as_bad (_("no instruction mnemonic suffix given; " 5676 "can't determine immediate size")); 5677 return 0; 5678 } 5679 } 5680 i.types[j] = overlap; 5681 5682 return 1; 5683 } 5684 5685 static int 5686 finalize_imm (void) 5687 { 5688 unsigned int j, n; 5689 5690 /* Update the first 2 immediate operands. */ 5691 n = i.operands > 2 ? 2 : i.operands; 5692 if (n) 5693 { 5694 for (j = 0; j < n; j++) 5695 if (update_imm (j) == 0) 5696 return 0; 5697 5698 /* The 3rd operand can't be immediate operand. */ 5699 gas_assert (operand_type_check (i.types[2], imm) == 0); 5700 } 5701 5702 return 1; 5703 } 5704 5705 static int 5706 bad_implicit_operand (int xmm) 5707 { 5708 const char *ireg = xmm ? "xmm0" : "ymm0"; 5709 5710 if (intel_syntax) 5711 as_bad (_("the last operand of `%s' must be `%s%s'"), 5712 i.tm.name, register_prefix, ireg); 5713 else 5714 as_bad (_("the first operand of `%s' must be `%s%s'"), 5715 i.tm.name, register_prefix, ireg); 5716 return 0; 5717 } 5718 5719 static int 5720 process_operands (void) 5721 { 5722 /* Default segment register this instruction will use for memory 5723 accesses. 0 means unknown. This is only for optimizing out 5724 unnecessary segment overrides. */ 5725 const seg_entry *default_seg = 0; 5726 5727 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) 5728 { 5729 unsigned int dupl = i.operands; 5730 unsigned int dest = dupl - 1; 5731 unsigned int j; 5732 5733 /* The destination must be an xmm register. */ 5734 gas_assert (i.reg_operands 5735 && MAX_OPERANDS > dupl 5736 && operand_type_equal (&i.types[dest], ®xmm)); 5737 5738 if (i.tm.opcode_modifier.firstxmm0) 5739 { 5740 /* The first operand is implicit and must be xmm0. */ 5741 gas_assert (operand_type_equal (&i.types[0], ®xmm)); 5742 if (register_number (i.op[0].regs) != 0) 5743 return bad_implicit_operand (1); 5744 5745 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) 5746 { 5747 /* Keep xmm0 for instructions with VEX prefix and 3 5748 sources. */ 5749 goto duplicate; 5750 } 5751 else 5752 { 5753 /* We remove the first xmm0 and keep the number of 5754 operands unchanged, which in fact duplicates the 5755 destination. */ 5756 for (j = 1; j < i.operands; j++) 5757 { 5758 i.op[j - 1] = i.op[j]; 5759 i.types[j - 1] = i.types[j]; 5760 i.tm.operand_types[j - 1] = i.tm.operand_types[j]; 5761 } 5762 } 5763 } 5764 else if (i.tm.opcode_modifier.implicit1stxmm0) 5765 { 5766 gas_assert ((MAX_OPERANDS - 1) > dupl 5767 && (i.tm.opcode_modifier.vexsources 5768 == VEX3SOURCES)); 5769 5770 /* Add the implicit xmm0 for instructions with VEX prefix 5771 and 3 sources. */ 5772 for (j = i.operands; j > 0; j--) 5773 { 5774 i.op[j] = i.op[j - 1]; 5775 i.types[j] = i.types[j - 1]; 5776 i.tm.operand_types[j] = i.tm.operand_types[j - 1]; 5777 } 5778 i.op[0].regs 5779 = (const reg_entry *) hash_find (reg_hash, "xmm0"); 5780 i.types[0] = regxmm; 5781 i.tm.operand_types[0] = regxmm; 5782 5783 i.operands += 2; 5784 i.reg_operands += 2; 5785 i.tm.operands += 2; 5786 5787 dupl++; 5788 dest++; 5789 i.op[dupl] = i.op[dest]; 5790 i.types[dupl] = i.types[dest]; 5791 i.tm.operand_types[dupl] = i.tm.operand_types[dest]; 5792 } 5793 else 5794 { 5795 duplicate: 5796 i.operands++; 5797 i.reg_operands++; 5798 i.tm.operands++; 5799 5800 i.op[dupl] = i.op[dest]; 5801 i.types[dupl] = i.types[dest]; 5802 i.tm.operand_types[dupl] = i.tm.operand_types[dest]; 5803 } 5804 5805 if (i.tm.opcode_modifier.immext) 5806 process_immext (); 5807 } 5808 else if (i.tm.opcode_modifier.firstxmm0) 5809 { 5810 unsigned int j; 5811 5812 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */ 5813 gas_assert (i.reg_operands 5814 && (operand_type_equal (&i.types[0], ®xmm) 5815 || operand_type_equal (&i.types[0], ®ymm) 5816 || operand_type_equal (&i.types[0], ®zmm))); 5817 if (register_number (i.op[0].regs) != 0) 5818 return bad_implicit_operand (i.types[0].bitfield.regxmm); 5819 5820 for (j = 1; j < i.operands; j++) 5821 { 5822 i.op[j - 1] = i.op[j]; 5823 i.types[j - 1] = i.types[j]; 5824 5825 /* We need to adjust fields in i.tm since they are used by 5826 build_modrm_byte. */ 5827 i.tm.operand_types [j - 1] = i.tm.operand_types [j]; 5828 } 5829 5830 i.operands--; 5831 i.reg_operands--; 5832 i.tm.operands--; 5833 } 5834 else if (i.tm.opcode_modifier.regkludge) 5835 { 5836 /* The imul $imm, %reg instruction is converted into 5837 imul $imm, %reg, %reg, and the clr %reg instruction 5838 is converted into xor %reg, %reg. */ 5839 5840 unsigned int first_reg_op; 5841 5842 if (operand_type_check (i.types[0], reg)) 5843 first_reg_op = 0; 5844 else 5845 first_reg_op = 1; 5846 /* Pretend we saw the extra register operand. */ 5847 gas_assert (i.reg_operands == 1 5848 && i.op[first_reg_op + 1].regs == 0); 5849 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; 5850 i.types[first_reg_op + 1] = i.types[first_reg_op]; 5851 i.operands++; 5852 i.reg_operands++; 5853 } 5854 5855 if (i.tm.opcode_modifier.shortform) 5856 { 5857 if (i.types[0].bitfield.sreg2 5858 || i.types[0].bitfield.sreg3) 5859 { 5860 if (i.tm.base_opcode == POP_SEG_SHORT 5861 && i.op[0].regs->reg_num == 1) 5862 { 5863 as_bad (_("you can't `pop %scs'"), register_prefix); 5864 return 0; 5865 } 5866 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 5867 if ((i.op[0].regs->reg_flags & RegRex) != 0) 5868 i.rex |= REX_B; 5869 } 5870 else 5871 { 5872 /* The register or float register operand is in operand 5873 0 or 1. */ 5874 unsigned int op; 5875 5876 if (i.types[0].bitfield.floatreg 5877 || operand_type_check (i.types[0], reg)) 5878 op = 0; 5879 else 5880 op = 1; 5881 /* Register goes in low 3 bits of opcode. */ 5882 i.tm.base_opcode |= i.op[op].regs->reg_num; 5883 if ((i.op[op].regs->reg_flags & RegRex) != 0) 5884 i.rex |= REX_B; 5885 if (!quiet_warnings && i.tm.opcode_modifier.ugh) 5886 { 5887 /* Warn about some common errors, but press on regardless. 5888 The first case can be generated by gcc (<= 2.8.1). */ 5889 if (i.operands == 2) 5890 { 5891 /* Reversed arguments on faddp, fsubp, etc. */ 5892 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, 5893 register_prefix, i.op[!intel_syntax].regs->reg_name, 5894 register_prefix, i.op[intel_syntax].regs->reg_name); 5895 } 5896 else 5897 { 5898 /* Extraneous `l' suffix on fp insn. */ 5899 as_warn (_("translating to `%s %s%s'"), i.tm.name, 5900 register_prefix, i.op[0].regs->reg_name); 5901 } 5902 } 5903 } 5904 } 5905 else if (i.tm.opcode_modifier.modrm) 5906 { 5907 /* The opcode is completed (modulo i.tm.extension_opcode which 5908 must be put into the modrm byte). Now, we make the modrm and 5909 index base bytes based on all the info we've collected. */ 5910 5911 default_seg = build_modrm_byte (); 5912 } 5913 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) 5914 { 5915 default_seg = &ds; 5916 } 5917 else if (i.tm.opcode_modifier.isstring) 5918 { 5919 /* For the string instructions that allow a segment override 5920 on one of their operands, the default segment is ds. */ 5921 default_seg = &ds; 5922 } 5923 5924 if (i.tm.base_opcode == 0x8d /* lea */ 5925 && i.seg[0] 5926 && !quiet_warnings) 5927 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); 5928 5929 /* If a segment was explicitly specified, and the specified segment 5930 is not the default, use an opcode prefix to select it. If we 5931 never figured out what the default segment is, then default_seg 5932 will be zero at this point, and the specified segment prefix will 5933 always be used. */ 5934 if ((i.seg[0]) && (i.seg[0] != default_seg)) 5935 { 5936 if (!add_prefix (i.seg[0]->seg_prefix)) 5937 return 0; 5938 } 5939 return 1; 5940 } 5941 5942 static const seg_entry * 5943 build_modrm_byte (void) 5944 { 5945 const seg_entry *default_seg = 0; 5946 unsigned int source, dest; 5947 int vex_3_sources; 5948 5949 /* The first operand of instructions with VEX prefix and 3 sources 5950 must be VEX_Imm4. */ 5951 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; 5952 if (vex_3_sources) 5953 { 5954 unsigned int nds, reg_slot; 5955 expressionS *exp; 5956 5957 if (i.tm.opcode_modifier.veximmext 5958 && i.tm.opcode_modifier.immext) 5959 { 5960 dest = i.operands - 2; 5961 gas_assert (dest == 3); 5962 } 5963 else 5964 dest = i.operands - 1; 5965 nds = dest - 1; 5966 5967 /* There are 2 kinds of instructions: 5968 1. 5 operands: 4 register operands or 3 register operands 5969 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and 5970 VexW0 or VexW1. The destination must be either XMM, YMM or 5971 ZMM register. 5972 2. 4 operands: 4 register operands or 3 register operands 5973 plus 1 memory operand, VexXDS, and VexImmExt */ 5974 gas_assert ((i.reg_operands == 4 5975 || (i.reg_operands == 3 && i.mem_operands == 1)) 5976 && i.tm.opcode_modifier.vexvvvv == VEXXDS 5977 && (i.tm.opcode_modifier.veximmext 5978 || (i.imm_operands == 1 5979 && i.types[0].bitfield.vec_imm4 5980 && (i.tm.opcode_modifier.vexw == VEXW0 5981 || i.tm.opcode_modifier.vexw == VEXW1) 5982 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) 5983 || operand_type_equal (&i.tm.operand_types[dest], ®ymm) 5984 || operand_type_equal (&i.tm.operand_types[dest], ®zmm))))); 5985 5986 if (i.imm_operands == 0) 5987 { 5988 /* When there is no immediate operand, generate an 8bit 5989 immediate operand to encode the first operand. */ 5990 exp = &im_expressions[i.imm_operands++]; 5991 i.op[i.operands].imms = exp; 5992 i.types[i.operands] = imm8; 5993 i.operands++; 5994 /* If VexW1 is set, the first operand is the source and 5995 the second operand is encoded in the immediate operand. */ 5996 if (i.tm.opcode_modifier.vexw == VEXW1) 5997 { 5998 source = 0; 5999 reg_slot = 1; 6000 } 6001 else 6002 { 6003 source = 1; 6004 reg_slot = 0; 6005 } 6006 6007 /* FMA swaps REG and NDS. */ 6008 if (i.tm.cpu_flags.bitfield.cpufma) 6009 { 6010 unsigned int tmp; 6011 tmp = reg_slot; 6012 reg_slot = nds; 6013 nds = tmp; 6014 } 6015 6016 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], 6017 ®xmm) 6018 || operand_type_equal (&i.tm.operand_types[reg_slot], 6019 ®ymm) 6020 || operand_type_equal (&i.tm.operand_types[reg_slot], 6021 ®zmm)); 6022 exp->X_op = O_constant; 6023 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; 6024 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); 6025 } 6026 else 6027 { 6028 unsigned int imm_slot; 6029 6030 if (i.tm.opcode_modifier.vexw == VEXW0) 6031 { 6032 /* If VexW0 is set, the third operand is the source and 6033 the second operand is encoded in the immediate 6034 operand. */ 6035 source = 2; 6036 reg_slot = 1; 6037 } 6038 else 6039 { 6040 /* VexW1 is set, the second operand is the source and 6041 the third operand is encoded in the immediate 6042 operand. */ 6043 source = 1; 6044 reg_slot = 2; 6045 } 6046 6047 if (i.tm.opcode_modifier.immext) 6048 { 6049 /* When ImmExt is set, the immdiate byte is the last 6050 operand. */ 6051 imm_slot = i.operands - 1; 6052 source--; 6053 reg_slot--; 6054 } 6055 else 6056 { 6057 imm_slot = 0; 6058 6059 /* Turn on Imm8 so that output_imm will generate it. */ 6060 i.types[imm_slot].bitfield.imm8 = 1; 6061 } 6062 6063 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], 6064 ®xmm) 6065 || operand_type_equal (&i.tm.operand_types[reg_slot], 6066 ®ymm) 6067 || operand_type_equal (&i.tm.operand_types[reg_slot], 6068 ®zmm)); 6069 i.op[imm_slot].imms->X_add_number 6070 |= register_number (i.op[reg_slot].regs) << 4; 6071 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); 6072 } 6073 6074 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) 6075 || operand_type_equal (&i.tm.operand_types[nds], 6076 ®ymm) 6077 || operand_type_equal (&i.tm.operand_types[nds], 6078 ®zmm)); 6079 i.vex.register_specifier = i.op[nds].regs; 6080 } 6081 else 6082 source = dest = 0; 6083 6084 /* i.reg_operands MUST be the number of real register operands; 6085 implicit registers do not count. If there are 3 register 6086 operands, it must be a instruction with VexNDS. For a 6087 instruction with VexNDD, the destination register is encoded 6088 in VEX prefix. If there are 4 register operands, it must be 6089 a instruction with VEX prefix and 3 sources. */ 6090 if (i.mem_operands == 0 6091 && ((i.reg_operands == 2 6092 && i.tm.opcode_modifier.vexvvvv <= VEXXDS) 6093 || (i.reg_operands == 3 6094 && i.tm.opcode_modifier.vexvvvv == VEXXDS) 6095 || (i.reg_operands == 4 && vex_3_sources))) 6096 { 6097 switch (i.operands) 6098 { 6099 case 2: 6100 source = 0; 6101 break; 6102 case 3: 6103 /* When there are 3 operands, one of them may be immediate, 6104 which may be the first or the last operand. Otherwise, 6105 the first operand must be shift count register (cl) or it 6106 is an instruction with VexNDS. */ 6107 gas_assert (i.imm_operands == 1 6108 || (i.imm_operands == 0 6109 && (i.tm.opcode_modifier.vexvvvv == VEXXDS 6110 || i.types[0].bitfield.shiftcount))); 6111 if (operand_type_check (i.types[0], imm) 6112 || i.types[0].bitfield.shiftcount) 6113 source = 1; 6114 else 6115 source = 0; 6116 break; 6117 case 4: 6118 /* When there are 4 operands, the first two must be 8bit 6119 immediate operands. The source operand will be the 3rd 6120 one. 6121 6122 For instructions with VexNDS, if the first operand 6123 an imm8, the source operand is the 2nd one. If the last 6124 operand is imm8, the source operand is the first one. */ 6125 gas_assert ((i.imm_operands == 2 6126 && i.types[0].bitfield.imm8 6127 && i.types[1].bitfield.imm8) 6128 || (i.tm.opcode_modifier.vexvvvv == VEXXDS 6129 && i.imm_operands == 1 6130 && (i.types[0].bitfield.imm8 6131 || i.types[i.operands - 1].bitfield.imm8 6132 || i.rounding))); 6133 if (i.imm_operands == 2) 6134 source = 2; 6135 else 6136 { 6137 if (i.types[0].bitfield.imm8) 6138 source = 1; 6139 else 6140 source = 0; 6141 } 6142 break; 6143 case 5: 6144 if (i.tm.opcode_modifier.evex) 6145 { 6146 /* For EVEX instructions, when there are 5 operands, the 6147 first one must be immediate operand. If the second one 6148 is immediate operand, the source operand is the 3th 6149 one. If the last one is immediate operand, the source 6150 operand is the 2nd one. */ 6151 gas_assert (i.imm_operands == 2 6152 && i.tm.opcode_modifier.sae 6153 && operand_type_check (i.types[0], imm)); 6154 if (operand_type_check (i.types[1], imm)) 6155 source = 2; 6156 else if (operand_type_check (i.types[4], imm)) 6157 source = 1; 6158 else 6159 abort (); 6160 } 6161 break; 6162 default: 6163 abort (); 6164 } 6165 6166 if (!vex_3_sources) 6167 { 6168 dest = source + 1; 6169 6170 /* RC/SAE operand could be between DEST and SRC. That happens 6171 when one operand is GPR and the other one is XMM/YMM/ZMM 6172 register. */ 6173 if (i.rounding && i.rounding->operand == (int) dest) 6174 dest++; 6175 6176 if (i.tm.opcode_modifier.vexvvvv == VEXXDS) 6177 { 6178 /* For instructions with VexNDS, the register-only source 6179 operand must be 32/64bit integer, XMM, YMM or ZMM 6180 register. It is encoded in VEX prefix. We need to 6181 clear RegMem bit before calling operand_type_equal. */ 6182 6183 i386_operand_type op; 6184 unsigned int vvvv; 6185 6186 /* Check register-only source operand when two source 6187 operands are swapped. */ 6188 if (!i.tm.operand_types[source].bitfield.baseindex 6189 && i.tm.operand_types[dest].bitfield.baseindex) 6190 { 6191 vvvv = source; 6192 source = dest; 6193 } 6194 else 6195 vvvv = dest; 6196 6197 op = i.tm.operand_types[vvvv]; 6198 op.bitfield.regmem = 0; 6199 if ((dest + 1) >= i.operands 6200 || (!op.bitfield.reg32 6201 && op.bitfield.reg64 6202 && !operand_type_equal (&op, ®xmm) 6203 && !operand_type_equal (&op, ®ymm) 6204 && !operand_type_equal (&op, ®zmm) 6205 && !operand_type_equal (&op, ®mask))) 6206 abort (); 6207 i.vex.register_specifier = i.op[vvvv].regs; 6208 dest++; 6209 } 6210 } 6211 6212 i.rm.mode = 3; 6213 /* One of the register operands will be encoded in the i.tm.reg 6214 field, the other in the combined i.tm.mode and i.tm.regmem 6215 fields. If no form of this instruction supports a memory 6216 destination operand, then we assume the source operand may 6217 sometimes be a memory operand and so we need to store the 6218 destination in the i.rm.reg field. */ 6219 if (!i.tm.operand_types[dest].bitfield.regmem 6220 && operand_type_check (i.tm.operand_types[dest], anymem) == 0) 6221 { 6222 i.rm.reg = i.op[dest].regs->reg_num; 6223 i.rm.regmem = i.op[source].regs->reg_num; 6224 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 6225 i.rex |= REX_R; 6226 if ((i.op[dest].regs->reg_flags & RegVRex) != 0) 6227 i.vrex |= REX_R; 6228 if ((i.op[source].regs->reg_flags & RegRex) != 0) 6229 i.rex |= REX_B; 6230 if ((i.op[source].regs->reg_flags & RegVRex) != 0) 6231 i.vrex |= REX_B; 6232 } 6233 else 6234 { 6235 i.rm.reg = i.op[source].regs->reg_num; 6236 i.rm.regmem = i.op[dest].regs->reg_num; 6237 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 6238 i.rex |= REX_B; 6239 if ((i.op[dest].regs->reg_flags & RegVRex) != 0) 6240 i.vrex |= REX_B; 6241 if ((i.op[source].regs->reg_flags & RegRex) != 0) 6242 i.rex |= REX_R; 6243 if ((i.op[source].regs->reg_flags & RegVRex) != 0) 6244 i.vrex |= REX_R; 6245 } 6246 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) 6247 { 6248 if (!i.types[0].bitfield.control 6249 && !i.types[1].bitfield.control) 6250 abort (); 6251 i.rex &= ~(REX_R | REX_B); 6252 add_prefix (LOCK_PREFIX_OPCODE); 6253 } 6254 } 6255 else 6256 { /* If it's not 2 reg operands... */ 6257 unsigned int mem; 6258 6259 if (i.mem_operands) 6260 { 6261 unsigned int fake_zero_displacement = 0; 6262 unsigned int op; 6263 6264 for (op = 0; op < i.operands; op++) 6265 if (operand_type_check (i.types[op], anymem)) 6266 break; 6267 gas_assert (op < i.operands); 6268 6269 if (i.tm.opcode_modifier.vecsib) 6270 { 6271 if (i.index_reg->reg_num == RegEiz 6272 || i.index_reg->reg_num == RegRiz) 6273 abort (); 6274 6275 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6276 if (!i.base_reg) 6277 { 6278 i.sib.base = NO_BASE_REGISTER; 6279 i.sib.scale = i.log2_scale_factor; 6280 /* No Vec_Disp8 if there is no base. */ 6281 i.types[op].bitfield.vec_disp8 = 0; 6282 i.types[op].bitfield.disp8 = 0; 6283 i.types[op].bitfield.disp16 = 0; 6284 i.types[op].bitfield.disp64 = 0; 6285 if (flag_code != CODE_64BIT) 6286 { 6287 /* Must be 32 bit */ 6288 i.types[op].bitfield.disp32 = 1; 6289 i.types[op].bitfield.disp32s = 0; 6290 } 6291 else 6292 { 6293 i.types[op].bitfield.disp32 = 0; 6294 i.types[op].bitfield.disp32s = 1; 6295 } 6296 } 6297 i.sib.index = i.index_reg->reg_num; 6298 if ((i.index_reg->reg_flags & RegRex) != 0) 6299 i.rex |= REX_X; 6300 if ((i.index_reg->reg_flags & RegVRex) != 0) 6301 i.vrex |= REX_X; 6302 } 6303 6304 default_seg = &ds; 6305 6306 if (i.base_reg == 0) 6307 { 6308 i.rm.mode = 0; 6309 if (!i.disp_operands) 6310 { 6311 fake_zero_displacement = 1; 6312 /* Instructions with VSIB byte need 32bit displacement 6313 if there is no base register. */ 6314 if (i.tm.opcode_modifier.vecsib) 6315 i.types[op].bitfield.disp32 = 1; 6316 } 6317 if (i.index_reg == 0) 6318 { 6319 gas_assert (!i.tm.opcode_modifier.vecsib); 6320 /* Operand is just <disp> */ 6321 if (flag_code == CODE_64BIT) 6322 { 6323 /* 64bit mode overwrites the 32bit absolute 6324 addressing by RIP relative addressing and 6325 absolute addressing is encoded by one of the 6326 redundant SIB forms. */ 6327 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6328 i.sib.base = NO_BASE_REGISTER; 6329 i.sib.index = NO_INDEX_REGISTER; 6330 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) 6331 ? disp32s : disp32); 6332 } 6333 else if ((flag_code == CODE_16BIT) 6334 ^ (i.prefix[ADDR_PREFIX] != 0)) 6335 { 6336 i.rm.regmem = NO_BASE_REGISTER_16; 6337 i.types[op] = disp16; 6338 } 6339 else 6340 { 6341 i.rm.regmem = NO_BASE_REGISTER; 6342 i.types[op] = disp32; 6343 } 6344 } 6345 else if (!i.tm.opcode_modifier.vecsib) 6346 { 6347 /* !i.base_reg && i.index_reg */ 6348 if (i.index_reg->reg_num == RegEiz 6349 || i.index_reg->reg_num == RegRiz) 6350 i.sib.index = NO_INDEX_REGISTER; 6351 else 6352 i.sib.index = i.index_reg->reg_num; 6353 i.sib.base = NO_BASE_REGISTER; 6354 i.sib.scale = i.log2_scale_factor; 6355 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6356 /* No Vec_Disp8 if there is no base. */ 6357 i.types[op].bitfield.vec_disp8 = 0; 6358 i.types[op].bitfield.disp8 = 0; 6359 i.types[op].bitfield.disp16 = 0; 6360 i.types[op].bitfield.disp64 = 0; 6361 if (flag_code != CODE_64BIT) 6362 { 6363 /* Must be 32 bit */ 6364 i.types[op].bitfield.disp32 = 1; 6365 i.types[op].bitfield.disp32s = 0; 6366 } 6367 else 6368 { 6369 i.types[op].bitfield.disp32 = 0; 6370 i.types[op].bitfield.disp32s = 1; 6371 } 6372 if ((i.index_reg->reg_flags & RegRex) != 0) 6373 i.rex |= REX_X; 6374 } 6375 } 6376 /* RIP addressing for 64bit mode. */ 6377 else if (i.base_reg->reg_num == RegRip || 6378 i.base_reg->reg_num == RegEip) 6379 { 6380 gas_assert (!i.tm.opcode_modifier.vecsib); 6381 i.rm.regmem = NO_BASE_REGISTER; 6382 i.types[op].bitfield.disp8 = 0; 6383 i.types[op].bitfield.disp16 = 0; 6384 i.types[op].bitfield.disp32 = 0; 6385 i.types[op].bitfield.disp32s = 1; 6386 i.types[op].bitfield.disp64 = 0; 6387 i.types[op].bitfield.vec_disp8 = 0; 6388 i.flags[op] |= Operand_PCrel; 6389 if (! i.disp_operands) 6390 fake_zero_displacement = 1; 6391 } 6392 else if (i.base_reg->reg_type.bitfield.reg16) 6393 { 6394 gas_assert (!i.tm.opcode_modifier.vecsib); 6395 switch (i.base_reg->reg_num) 6396 { 6397 case 3: /* (%bx) */ 6398 if (i.index_reg == 0) 6399 i.rm.regmem = 7; 6400 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 6401 i.rm.regmem = i.index_reg->reg_num - 6; 6402 break; 6403 case 5: /* (%bp) */ 6404 default_seg = &ss; 6405 if (i.index_reg == 0) 6406 { 6407 i.rm.regmem = 6; 6408 if (operand_type_check (i.types[op], disp) == 0) 6409 { 6410 /* fake (%bp) into 0(%bp) */ 6411 if (i.tm.operand_types[op].bitfield.vec_disp8) 6412 i.types[op].bitfield.vec_disp8 = 1; 6413 else 6414 i.types[op].bitfield.disp8 = 1; 6415 fake_zero_displacement = 1; 6416 } 6417 } 6418 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 6419 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 6420 break; 6421 default: /* (%si) -> 4 or (%di) -> 5 */ 6422 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 6423 } 6424 i.rm.mode = mode_from_disp_size (i.types[op]); 6425 } 6426 else /* i.base_reg and 32/64 bit mode */ 6427 { 6428 if (flag_code == CODE_64BIT 6429 && operand_type_check (i.types[op], disp)) 6430 { 6431 i386_operand_type temp; 6432 operand_type_set (&temp, 0); 6433 temp.bitfield.disp8 = i.types[op].bitfield.disp8; 6434 temp.bitfield.vec_disp8 6435 = i.types[op].bitfield.vec_disp8; 6436 i.types[op] = temp; 6437 if (i.prefix[ADDR_PREFIX] == 0) 6438 i.types[op].bitfield.disp32s = 1; 6439 else 6440 i.types[op].bitfield.disp32 = 1; 6441 } 6442 6443 if (!i.tm.opcode_modifier.vecsib) 6444 i.rm.regmem = i.base_reg->reg_num; 6445 if ((i.base_reg->reg_flags & RegRex) != 0) 6446 i.rex |= REX_B; 6447 i.sib.base = i.base_reg->reg_num; 6448 /* x86-64 ignores REX prefix bit here to avoid decoder 6449 complications. */ 6450 if (!(i.base_reg->reg_flags & RegRex) 6451 && (i.base_reg->reg_num == EBP_REG_NUM 6452 || i.base_reg->reg_num == ESP_REG_NUM)) 6453 default_seg = &ss; 6454 if (i.base_reg->reg_num == 5 && i.disp_operands == 0) 6455 { 6456 fake_zero_displacement = 1; 6457 if (i.tm.operand_types [op].bitfield.vec_disp8) 6458 i.types[op].bitfield.vec_disp8 = 1; 6459 else 6460 i.types[op].bitfield.disp8 = 1; 6461 } 6462 i.sib.scale = i.log2_scale_factor; 6463 if (i.index_reg == 0) 6464 { 6465 gas_assert (!i.tm.opcode_modifier.vecsib); 6466 /* <disp>(%esp) becomes two byte modrm with no index 6467 register. We've already stored the code for esp 6468 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. 6469 Any base register besides %esp will not use the 6470 extra modrm byte. */ 6471 i.sib.index = NO_INDEX_REGISTER; 6472 } 6473 else if (!i.tm.opcode_modifier.vecsib) 6474 { 6475 if (i.index_reg->reg_num == RegEiz 6476 || i.index_reg->reg_num == RegRiz) 6477 i.sib.index = NO_INDEX_REGISTER; 6478 else 6479 i.sib.index = i.index_reg->reg_num; 6480 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 6481 if ((i.index_reg->reg_flags & RegRex) != 0) 6482 i.rex |= REX_X; 6483 } 6484 6485 if (i.disp_operands 6486 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 6487 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) 6488 i.rm.mode = 0; 6489 else 6490 { 6491 if (!fake_zero_displacement 6492 && !i.disp_operands 6493 && i.disp_encoding) 6494 { 6495 fake_zero_displacement = 1; 6496 if (i.disp_encoding == disp_encoding_8bit) 6497 i.types[op].bitfield.disp8 = 1; 6498 else 6499 i.types[op].bitfield.disp32 = 1; 6500 } 6501 i.rm.mode = mode_from_disp_size (i.types[op]); 6502 } 6503 } 6504 6505 if (fake_zero_displacement) 6506 { 6507 /* Fakes a zero displacement assuming that i.types[op] 6508 holds the correct displacement size. */ 6509 expressionS *exp; 6510 6511 gas_assert (i.op[op].disps == 0); 6512 exp = &disp_expressions[i.disp_operands++]; 6513 i.op[op].disps = exp; 6514 exp->X_op = O_constant; 6515 exp->X_add_number = 0; 6516 exp->X_add_symbol = (symbolS *) 0; 6517 exp->X_op_symbol = (symbolS *) 0; 6518 } 6519 6520 mem = op; 6521 } 6522 else 6523 mem = ~0; 6524 6525 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) 6526 { 6527 if (operand_type_check (i.types[0], imm)) 6528 i.vex.register_specifier = NULL; 6529 else 6530 { 6531 /* VEX.vvvv encodes one of the sources when the first 6532 operand is not an immediate. */ 6533 if (i.tm.opcode_modifier.vexw == VEXW0) 6534 i.vex.register_specifier = i.op[0].regs; 6535 else 6536 i.vex.register_specifier = i.op[1].regs; 6537 } 6538 6539 /* Destination is a XMM register encoded in the ModRM.reg 6540 and VEX.R bit. */ 6541 i.rm.reg = i.op[2].regs->reg_num; 6542 if ((i.op[2].regs->reg_flags & RegRex) != 0) 6543 i.rex |= REX_R; 6544 6545 /* ModRM.rm and VEX.B encodes the other source. */ 6546 if (!i.mem_operands) 6547 { 6548 i.rm.mode = 3; 6549 6550 if (i.tm.opcode_modifier.vexw == VEXW0) 6551 i.rm.regmem = i.op[1].regs->reg_num; 6552 else 6553 i.rm.regmem = i.op[0].regs->reg_num; 6554 6555 if ((i.op[1].regs->reg_flags & RegRex) != 0) 6556 i.rex |= REX_B; 6557 } 6558 } 6559 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) 6560 { 6561 i.vex.register_specifier = i.op[2].regs; 6562 if (!i.mem_operands) 6563 { 6564 i.rm.mode = 3; 6565 i.rm.regmem = i.op[1].regs->reg_num; 6566 if ((i.op[1].regs->reg_flags & RegRex) != 0) 6567 i.rex |= REX_B; 6568 } 6569 } 6570 /* Fill in i.rm.reg or i.rm.regmem field with register operand 6571 (if any) based on i.tm.extension_opcode. Again, we must be 6572 careful to make sure that segment/control/debug/test/MMX 6573 registers are coded into the i.rm.reg field. */ 6574 else if (i.reg_operands) 6575 { 6576 unsigned int op; 6577 unsigned int vex_reg = ~0; 6578 6579 for (op = 0; op < i.operands; op++) 6580 if (i.types[op].bitfield.reg8 6581 || i.types[op].bitfield.reg16 6582 || i.types[op].bitfield.reg32 6583 || i.types[op].bitfield.reg64 6584 || i.types[op].bitfield.regmmx 6585 || i.types[op].bitfield.regxmm 6586 || i.types[op].bitfield.regymm 6587 || i.types[op].bitfield.regbnd 6588 || i.types[op].bitfield.regzmm 6589 || i.types[op].bitfield.regmask 6590 || i.types[op].bitfield.sreg2 6591 || i.types[op].bitfield.sreg3 6592 || i.types[op].bitfield.control 6593 || i.types[op].bitfield.debug 6594 || i.types[op].bitfield.test) 6595 break; 6596 6597 if (vex_3_sources) 6598 op = dest; 6599 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) 6600 { 6601 /* For instructions with VexNDS, the register-only 6602 source operand is encoded in VEX prefix. */ 6603 gas_assert (mem != (unsigned int) ~0); 6604 6605 if (op > mem) 6606 { 6607 vex_reg = op++; 6608 gas_assert (op < i.operands); 6609 } 6610 else 6611 { 6612 /* Check register-only source operand when two source 6613 operands are swapped. */ 6614 if (!i.tm.operand_types[op].bitfield.baseindex 6615 && i.tm.operand_types[op + 1].bitfield.baseindex) 6616 { 6617 vex_reg = op; 6618 op += 2; 6619 gas_assert (mem == (vex_reg + 1) 6620 && op < i.operands); 6621 } 6622 else 6623 { 6624 vex_reg = op + 1; 6625 gas_assert (vex_reg < i.operands); 6626 } 6627 } 6628 } 6629 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) 6630 { 6631 /* For instructions with VexNDD, the register destination 6632 is encoded in VEX prefix. */ 6633 if (i.mem_operands == 0) 6634 { 6635 /* There is no memory operand. */ 6636 gas_assert ((op + 2) == i.operands); 6637 vex_reg = op + 1; 6638 } 6639 else 6640 { 6641 /* There are only 2 operands. */ 6642 gas_assert (op < 2 && i.operands == 2); 6643 vex_reg = 1; 6644 } 6645 } 6646 else 6647 gas_assert (op < i.operands); 6648 6649 if (vex_reg != (unsigned int) ~0) 6650 { 6651 i386_operand_type *type = &i.tm.operand_types[vex_reg]; 6652 6653 if (type->bitfield.reg32 != 1 6654 && type->bitfield.reg64 != 1 6655 && !operand_type_equal (type, ®xmm) 6656 && !operand_type_equal (type, ®ymm) 6657 && !operand_type_equal (type, ®zmm) 6658 && !operand_type_equal (type, ®mask)) 6659 abort (); 6660 6661 i.vex.register_specifier = i.op[vex_reg].regs; 6662 } 6663 6664 /* Don't set OP operand twice. */ 6665 if (vex_reg != op) 6666 { 6667 /* If there is an extension opcode to put here, the 6668 register number must be put into the regmem field. */ 6669 if (i.tm.extension_opcode != None) 6670 { 6671 i.rm.regmem = i.op[op].regs->reg_num; 6672 if ((i.op[op].regs->reg_flags & RegRex) != 0) 6673 i.rex |= REX_B; 6674 if ((i.op[op].regs->reg_flags & RegVRex) != 0) 6675 i.vrex |= REX_B; 6676 } 6677 else 6678 { 6679 i.rm.reg = i.op[op].regs->reg_num; 6680 if ((i.op[op].regs->reg_flags & RegRex) != 0) 6681 i.rex |= REX_R; 6682 if ((i.op[op].regs->reg_flags & RegVRex) != 0) 6683 i.vrex |= REX_R; 6684 } 6685 } 6686 6687 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we 6688 must set it to 3 to indicate this is a register operand 6689 in the regmem field. */ 6690 if (!i.mem_operands) 6691 i.rm.mode = 3; 6692 } 6693 6694 /* Fill in i.rm.reg field with extension opcode (if any). */ 6695 if (i.tm.extension_opcode != None) 6696 i.rm.reg = i.tm.extension_opcode; 6697 } 6698 return default_seg; 6699 } 6700 6701 static void 6702 output_branch (void) 6703 { 6704 char *p; 6705 int size; 6706 int code16; 6707 int prefix; 6708 relax_substateT subtype; 6709 symbolS *sym; 6710 offsetT off; 6711 6712 code16 = flag_code == CODE_16BIT ? CODE16 : 0; 6713 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; 6714 6715 prefix = 0; 6716 if (i.prefix[DATA_PREFIX] != 0) 6717 { 6718 prefix = 1; 6719 i.prefixes -= 1; 6720 code16 ^= CODE16; 6721 } 6722 /* Pentium4 branch hints. */ 6723 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 6724 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 6725 { 6726 prefix++; 6727 i.prefixes--; 6728 } 6729 if (i.prefix[REX_PREFIX] != 0) 6730 { 6731 prefix++; 6732 i.prefixes--; 6733 } 6734 6735 /* BND prefixed jump. */ 6736 if (i.prefix[BND_PREFIX] != 0) 6737 { 6738 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); 6739 i.prefixes -= 1; 6740 } 6741 6742 if (i.prefixes != 0 && !intel_syntax) 6743 as_warn (_("skipping prefixes on this instruction")); 6744 6745 /* It's always a symbol; End frag & setup for relax. 6746 Make sure there is enough room in this frag for the largest 6747 instruction we may generate in md_convert_frag. This is 2 6748 bytes for the opcode and room for the prefix and largest 6749 displacement. */ 6750 frag_grow (prefix + 2 + 4); 6751 /* Prefix and 1 opcode byte go in fr_fix. */ 6752 p = frag_more (prefix + 1); 6753 if (i.prefix[DATA_PREFIX] != 0) 6754 *p++ = DATA_PREFIX_OPCODE; 6755 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE 6756 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) 6757 *p++ = i.prefix[SEG_PREFIX]; 6758 if (i.prefix[REX_PREFIX] != 0) 6759 *p++ = i.prefix[REX_PREFIX]; 6760 *p = i.tm.base_opcode; 6761 6762 if ((unsigned char) *p == JUMP_PC_RELATIVE) 6763 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); 6764 else if (cpu_arch_flags.bitfield.cpui386) 6765 subtype = ENCODE_RELAX_STATE (COND_JUMP, size); 6766 else 6767 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); 6768 subtype |= code16; 6769 6770 sym = i.op[0].disps->X_add_symbol; 6771 off = i.op[0].disps->X_add_number; 6772 6773 if (i.op[0].disps->X_op != O_constant 6774 && i.op[0].disps->X_op != O_symbol) 6775 { 6776 /* Handle complex expressions. */ 6777 sym = make_expr_symbol (i.op[0].disps); 6778 off = 0; 6779 } 6780 6781 /* 1 possible extra opcode + 4 byte displacement go in var part. 6782 Pass reloc in fr_var. */ 6783 frag_var (rs_machine_dependent, 5, 6784 ((!object_64bit 6785 || i.reloc[0] != NO_RELOC 6786 || (i.bnd_prefix == NULL && !add_bnd_prefix)) 6787 ? i.reloc[0] 6788 : BFD_RELOC_X86_64_PC32_BND), 6789 subtype, sym, off, p); 6790 } 6791 6792 static void 6793 output_jump (void) 6794 { 6795 char *p; 6796 int size; 6797 fixS *fixP; 6798 6799 if (i.tm.opcode_modifier.jumpbyte) 6800 { 6801 /* This is a loop or jecxz type instruction. */ 6802 size = 1; 6803 if (i.prefix[ADDR_PREFIX] != 0) 6804 { 6805 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 6806 i.prefixes -= 1; 6807 } 6808 /* Pentium4 branch hints. */ 6809 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 6810 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 6811 { 6812 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); 6813 i.prefixes--; 6814 } 6815 } 6816 else 6817 { 6818 int code16; 6819 6820 code16 = 0; 6821 if (flag_code == CODE_16BIT) 6822 code16 = CODE16; 6823 6824 if (i.prefix[DATA_PREFIX] != 0) 6825 { 6826 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 6827 i.prefixes -= 1; 6828 code16 ^= CODE16; 6829 } 6830 6831 size = 4; 6832 if (code16) 6833 size = 2; 6834 } 6835 6836 if (i.prefix[REX_PREFIX] != 0) 6837 { 6838 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); 6839 i.prefixes -= 1; 6840 } 6841 6842 /* BND prefixed jump. */ 6843 if (i.prefix[BND_PREFIX] != 0) 6844 { 6845 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); 6846 i.prefixes -= 1; 6847 } 6848 6849 if (i.prefixes != 0 && !intel_syntax) 6850 as_warn (_("skipping prefixes on this instruction")); 6851 6852 p = frag_more (i.tm.opcode_length + size); 6853 switch (i.tm.opcode_length) 6854 { 6855 case 2: 6856 *p++ = i.tm.base_opcode >> 8; 6857 case 1: 6858 *p++ = i.tm.base_opcode; 6859 break; 6860 default: 6861 abort (); 6862 } 6863 6864 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, 6865 i.op[0].disps, 1, reloc (size, 1, 1, 6866 (i.bnd_prefix != NULL 6867 || add_bnd_prefix), 6868 i.reloc[0])); 6869 6870 /* All jumps handled here are signed, but don't use a signed limit 6871 check for 32 and 16 bit jumps as we want to allow wrap around at 6872 4G and 64k respectively. */ 6873 if (size == 1) 6874 fixP->fx_signed = 1; 6875 } 6876 6877 static void 6878 output_interseg_jump (void) 6879 { 6880 char *p; 6881 int size; 6882 int prefix; 6883 int code16; 6884 6885 code16 = 0; 6886 if (flag_code == CODE_16BIT) 6887 code16 = CODE16; 6888 6889 prefix = 0; 6890 if (i.prefix[DATA_PREFIX] != 0) 6891 { 6892 prefix = 1; 6893 i.prefixes -= 1; 6894 code16 ^= CODE16; 6895 } 6896 if (i.prefix[REX_PREFIX] != 0) 6897 { 6898 prefix++; 6899 i.prefixes -= 1; 6900 } 6901 6902 size = 4; 6903 if (code16) 6904 size = 2; 6905 6906 if (i.prefixes != 0 && !intel_syntax) 6907 as_warn (_("skipping prefixes on this instruction")); 6908 6909 /* 1 opcode; 2 segment; offset */ 6910 p = frag_more (prefix + 1 + 2 + size); 6911 6912 if (i.prefix[DATA_PREFIX] != 0) 6913 *p++ = DATA_PREFIX_OPCODE; 6914 6915 if (i.prefix[REX_PREFIX] != 0) 6916 *p++ = i.prefix[REX_PREFIX]; 6917 6918 *p++ = i.tm.base_opcode; 6919 if (i.op[1].imms->X_op == O_constant) 6920 { 6921 offsetT n = i.op[1].imms->X_add_number; 6922 6923 if (size == 2 6924 && !fits_in_unsigned_word (n) 6925 && !fits_in_signed_word (n)) 6926 { 6927 as_bad (_("16-bit jump out of range")); 6928 return; 6929 } 6930 md_number_to_chars (p, n, size); 6931 } 6932 else 6933 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 6934 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1])); 6935 if (i.op[0].imms->X_op != O_constant) 6936 as_bad (_("can't handle non absolute segment in `%s'"), 6937 i.tm.name); 6938 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 6939 } 6940 6941 static void 6942 output_insn (void) 6943 { 6944 fragS *insn_start_frag; 6945 offsetT insn_start_off; 6946 6947 /* Tie dwarf2 debug info to the address at the start of the insn. 6948 We can't do this after the insn has been output as the current 6949 frag may have been closed off. eg. by frag_var. */ 6950 dwarf2_emit_insn (0); 6951 6952 insn_start_frag = frag_now; 6953 insn_start_off = frag_now_fix (); 6954 6955 /* Output jumps. */ 6956 if (i.tm.opcode_modifier.jump) 6957 output_branch (); 6958 else if (i.tm.opcode_modifier.jumpbyte 6959 || i.tm.opcode_modifier.jumpdword) 6960 output_jump (); 6961 else if (i.tm.opcode_modifier.jumpintersegment) 6962 output_interseg_jump (); 6963 else 6964 { 6965 /* Output normal instructions here. */ 6966 char *p; 6967 unsigned char *q; 6968 unsigned int j; 6969 unsigned int prefix; 6970 6971 /* Some processors fail on LOCK prefix. This options makes 6972 assembler ignore LOCK prefix and serves as a workaround. */ 6973 if (omit_lock_prefix) 6974 { 6975 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) 6976 return; 6977 i.prefix[LOCK_PREFIX] = 0; 6978 } 6979 6980 /* Since the VEX/EVEX prefix contains the implicit prefix, we 6981 don't need the explicit prefix. */ 6982 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) 6983 { 6984 switch (i.tm.opcode_length) 6985 { 6986 case 3: 6987 if (i.tm.base_opcode & 0xff000000) 6988 { 6989 prefix = (i.tm.base_opcode >> 24) & 0xff; 6990 goto check_prefix; 6991 } 6992 break; 6993 case 2: 6994 if ((i.tm.base_opcode & 0xff0000) != 0) 6995 { 6996 prefix = (i.tm.base_opcode >> 16) & 0xff; 6997 if (i.tm.cpu_flags.bitfield.cpupadlock) 6998 { 6999 check_prefix: 7000 if (prefix != REPE_PREFIX_OPCODE 7001 || (i.prefix[REP_PREFIX] 7002 != REPE_PREFIX_OPCODE)) 7003 add_prefix (prefix); 7004 } 7005 else 7006 add_prefix (prefix); 7007 } 7008 break; 7009 case 1: 7010 break; 7011 default: 7012 abort (); 7013 } 7014 7015 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 7016 /* For x32, add a dummy REX_OPCODE prefix for mov/add with 7017 R_X86_64_GOTTPOFF relocation so that linker can safely 7018 perform IE->LE optimization. */ 7019 if (x86_elf_abi == X86_64_X32_ABI 7020 && i.operands == 2 7021 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF 7022 && i.prefix[REX_PREFIX] == 0) 7023 add_prefix (REX_OPCODE); 7024 #endif 7025 7026 /* The prefix bytes. */ 7027 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) 7028 if (*q) 7029 FRAG_APPEND_1_CHAR (*q); 7030 } 7031 else 7032 { 7033 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) 7034 if (*q) 7035 switch (j) 7036 { 7037 case REX_PREFIX: 7038 /* REX byte is encoded in VEX prefix. */ 7039 break; 7040 case SEG_PREFIX: 7041 case ADDR_PREFIX: 7042 FRAG_APPEND_1_CHAR (*q); 7043 break; 7044 default: 7045 /* There should be no other prefixes for instructions 7046 with VEX prefix. */ 7047 abort (); 7048 } 7049 7050 /* For EVEX instructions i.vrex should become 0 after 7051 build_evex_prefix. For VEX instructions upper 16 registers 7052 aren't available, so VREX should be 0. */ 7053 if (i.vrex) 7054 abort (); 7055 /* Now the VEX prefix. */ 7056 p = frag_more (i.vex.length); 7057 for (j = 0; j < i.vex.length; j++) 7058 p[j] = i.vex.bytes[j]; 7059 } 7060 7061 /* Now the opcode; be careful about word order here! */ 7062 if (i.tm.opcode_length == 1) 7063 { 7064 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 7065 } 7066 else 7067 { 7068 switch (i.tm.opcode_length) 7069 { 7070 case 4: 7071 p = frag_more (4); 7072 *p++ = (i.tm.base_opcode >> 24) & 0xff; 7073 *p++ = (i.tm.base_opcode >> 16) & 0xff; 7074 break; 7075 case 3: 7076 p = frag_more (3); 7077 *p++ = (i.tm.base_opcode >> 16) & 0xff; 7078 break; 7079 case 2: 7080 p = frag_more (2); 7081 break; 7082 default: 7083 abort (); 7084 break; 7085 } 7086 7087 /* Put out high byte first: can't use md_number_to_chars! */ 7088 *p++ = (i.tm.base_opcode >> 8) & 0xff; 7089 *p = i.tm.base_opcode & 0xff; 7090 } 7091 7092 /* Now the modrm byte and sib byte (if present). */ 7093 if (i.tm.opcode_modifier.modrm) 7094 { 7095 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 7096 | i.rm.reg << 3 7097 | i.rm.mode << 6)); 7098 /* If i.rm.regmem == ESP (4) 7099 && i.rm.mode != (Register mode) 7100 && not 16 bit 7101 ==> need second modrm byte. */ 7102 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 7103 && i.rm.mode != 3 7104 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) 7105 FRAG_APPEND_1_CHAR ((i.sib.base << 0 7106 | i.sib.index << 3 7107 | i.sib.scale << 6)); 7108 } 7109 7110 if (i.disp_operands) 7111 output_disp (insn_start_frag, insn_start_off); 7112 7113 if (i.imm_operands) 7114 output_imm (insn_start_frag, insn_start_off); 7115 } 7116 7117 #ifdef DEBUG386 7118 if (flag_debug) 7119 { 7120 pi ("" /*line*/, &i); 7121 } 7122 #endif /* DEBUG386 */ 7123 } 7124 7125 /* Return the size of the displacement operand N. */ 7126 7127 static int 7128 disp_size (unsigned int n) 7129 { 7130 int size = 4; 7131 7132 /* Vec_Disp8 has to be 8bit. */ 7133 if (i.types[n].bitfield.vec_disp8) 7134 size = 1; 7135 else if (i.types[n].bitfield.disp64) 7136 size = 8; 7137 else if (i.types[n].bitfield.disp8) 7138 size = 1; 7139 else if (i.types[n].bitfield.disp16) 7140 size = 2; 7141 return size; 7142 } 7143 7144 /* Return the size of the immediate operand N. */ 7145 7146 static int 7147 imm_size (unsigned int n) 7148 { 7149 int size = 4; 7150 if (i.types[n].bitfield.imm64) 7151 size = 8; 7152 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) 7153 size = 1; 7154 else if (i.types[n].bitfield.imm16) 7155 size = 2; 7156 return size; 7157 } 7158 7159 static void 7160 output_disp (fragS *insn_start_frag, offsetT insn_start_off) 7161 { 7162 char *p; 7163 unsigned int n; 7164 7165 for (n = 0; n < i.operands; n++) 7166 { 7167 if (i.types[n].bitfield.vec_disp8 7168 || operand_type_check (i.types[n], disp)) 7169 { 7170 if (i.op[n].disps->X_op == O_constant) 7171 { 7172 int size = disp_size (n); 7173 offsetT val = i.op[n].disps->X_add_number; 7174 7175 if (i.types[n].bitfield.vec_disp8) 7176 val >>= i.memshift; 7177 val = offset_in_range (val, size); 7178 p = frag_more (size); 7179 md_number_to_chars (p, val, size); 7180 } 7181 else 7182 { 7183 enum bfd_reloc_code_real reloc_type; 7184 int size = disp_size (n); 7185 int sign = i.types[n].bitfield.disp32s; 7186 int pcrel = (i.flags[n] & Operand_PCrel) != 0; 7187 7188 /* We can't have 8 bit displacement here. */ 7189 gas_assert (!i.types[n].bitfield.disp8); 7190 7191 /* The PC relative address is computed relative 7192 to the instruction boundary, so in case immediate 7193 fields follows, we need to adjust the value. */ 7194 if (pcrel && i.imm_operands) 7195 { 7196 unsigned int n1; 7197 int sz = 0; 7198 7199 for (n1 = 0; n1 < i.operands; n1++) 7200 if (operand_type_check (i.types[n1], imm)) 7201 { 7202 /* Only one immediate is allowed for PC 7203 relative address. */ 7204 gas_assert (sz == 0); 7205 sz = imm_size (n1); 7206 i.op[n].disps->X_add_number -= sz; 7207 } 7208 /* We should find the immediate. */ 7209 gas_assert (sz != 0); 7210 } 7211 7212 p = frag_more (size); 7213 reloc_type = reloc (size, pcrel, sign, 7214 (i.bnd_prefix != NULL 7215 || add_bnd_prefix), 7216 i.reloc[n]); 7217 if (GOT_symbol 7218 && GOT_symbol == i.op[n].disps->X_add_symbol 7219 && (((reloc_type == BFD_RELOC_32 7220 || reloc_type == BFD_RELOC_X86_64_32S 7221 || (reloc_type == BFD_RELOC_64 7222 && object_64bit)) 7223 && (i.op[n].disps->X_op == O_symbol 7224 || (i.op[n].disps->X_op == O_add 7225 && ((symbol_get_value_expression 7226 (i.op[n].disps->X_op_symbol)->X_op) 7227 == O_subtract)))) 7228 || reloc_type == BFD_RELOC_32_PCREL)) 7229 { 7230 offsetT add; 7231 7232 if (insn_start_frag == frag_now) 7233 add = (p - frag_now->fr_literal) - insn_start_off; 7234 else 7235 { 7236 fragS *fr; 7237 7238 add = insn_start_frag->fr_fix - insn_start_off; 7239 for (fr = insn_start_frag->fr_next; 7240 fr && fr != frag_now; fr = fr->fr_next) 7241 add += fr->fr_fix; 7242 add += p - frag_now->fr_literal; 7243 } 7244 7245 if (!object_64bit) 7246 { 7247 reloc_type = BFD_RELOC_386_GOTPC; 7248 i.op[n].imms->X_add_number += add; 7249 } 7250 else if (reloc_type == BFD_RELOC_64) 7251 reloc_type = BFD_RELOC_X86_64_GOTPC64; 7252 else 7253 /* Don't do the adjustment for x86-64, as there 7254 the pcrel addressing is relative to the _next_ 7255 insn, and that is taken care of in other code. */ 7256 reloc_type = BFD_RELOC_X86_64_GOTPC32; 7257 } 7258 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 7259 i.op[n].disps, pcrel, reloc_type); 7260 } 7261 } 7262 } 7263 } 7264 7265 static void 7266 output_imm (fragS *insn_start_frag, offsetT insn_start_off) 7267 { 7268 char *p; 7269 unsigned int n; 7270 7271 for (n = 0; n < i.operands; n++) 7272 { 7273 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ 7274 if (i.rounding && (int) n == i.rounding->operand) 7275 continue; 7276 7277 if (operand_type_check (i.types[n], imm)) 7278 { 7279 if (i.op[n].imms->X_op == O_constant) 7280 { 7281 int size = imm_size (n); 7282 offsetT val; 7283 7284 val = offset_in_range (i.op[n].imms->X_add_number, 7285 size); 7286 p = frag_more (size); 7287 md_number_to_chars (p, val, size); 7288 } 7289 else 7290 { 7291 /* Not absolute_section. 7292 Need a 32-bit fixup (don't support 8bit 7293 non-absolute imms). Try to support other 7294 sizes ... */ 7295 enum bfd_reloc_code_real reloc_type; 7296 int size = imm_size (n); 7297 int sign; 7298 7299 if (i.types[n].bitfield.imm32s 7300 && (i.suffix == QWORD_MNEM_SUFFIX 7301 || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) 7302 sign = 1; 7303 else 7304 sign = 0; 7305 7306 p = frag_more (size); 7307 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]); 7308 7309 /* This is tough to explain. We end up with this one if we 7310 * have operands that look like 7311 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to 7312 * obtain the absolute address of the GOT, and it is strongly 7313 * preferable from a performance point of view to avoid using 7314 * a runtime relocation for this. The actual sequence of 7315 * instructions often look something like: 7316 * 7317 * call .L66 7318 * .L66: 7319 * popl %ebx 7320 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 7321 * 7322 * The call and pop essentially return the absolute address 7323 * of the label .L66 and store it in %ebx. The linker itself 7324 * will ultimately change the first operand of the addl so 7325 * that %ebx points to the GOT, but to keep things simple, the 7326 * .o file must have this operand set so that it generates not 7327 * the absolute address of .L66, but the absolute address of 7328 * itself. This allows the linker itself simply treat a GOTPC 7329 * relocation as asking for a pcrel offset to the GOT to be 7330 * added in, and the addend of the relocation is stored in the 7331 * operand field for the instruction itself. 7332 * 7333 * Our job here is to fix the operand so that it would add 7334 * the correct offset so that %ebx would point to itself. The 7335 * thing that is tricky is that .-.L66 will point to the 7336 * beginning of the instruction, so we need to further modify 7337 * the operand so that it will point to itself. There are 7338 * other cases where you have something like: 7339 * 7340 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 7341 * 7342 * and here no correction would be required. Internally in 7343 * the assembler we treat operands of this form as not being 7344 * pcrel since the '.' is explicitly mentioned, and I wonder 7345 * whether it would simplify matters to do it this way. Who 7346 * knows. In earlier versions of the PIC patches, the 7347 * pcrel_adjust field was used to store the correction, but 7348 * since the expression is not pcrel, I felt it would be 7349 * confusing to do it this way. */ 7350 7351 if ((reloc_type == BFD_RELOC_32 7352 || reloc_type == BFD_RELOC_X86_64_32S 7353 || reloc_type == BFD_RELOC_64) 7354 && GOT_symbol 7355 && GOT_symbol == i.op[n].imms->X_add_symbol 7356 && (i.op[n].imms->X_op == O_symbol 7357 || (i.op[n].imms->X_op == O_add 7358 && ((symbol_get_value_expression 7359 (i.op[n].imms->X_op_symbol)->X_op) 7360 == O_subtract)))) 7361 { 7362 offsetT add; 7363 7364 if (insn_start_frag == frag_now) 7365 add = (p - frag_now->fr_literal) - insn_start_off; 7366 else 7367 { 7368 fragS *fr; 7369 7370 add = insn_start_frag->fr_fix - insn_start_off; 7371 for (fr = insn_start_frag->fr_next; 7372 fr && fr != frag_now; fr = fr->fr_next) 7373 add += fr->fr_fix; 7374 add += p - frag_now->fr_literal; 7375 } 7376 7377 if (!object_64bit) 7378 reloc_type = BFD_RELOC_386_GOTPC; 7379 else if (size == 4) 7380 reloc_type = BFD_RELOC_X86_64_GOTPC32; 7381 else if (size == 8) 7382 reloc_type = BFD_RELOC_X86_64_GOTPC64; 7383 i.op[n].imms->X_add_number += add; 7384 } 7385 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 7386 i.op[n].imms, 0, reloc_type); 7387 } 7388 } 7389 } 7390 } 7391 7392 /* x86_cons_fix_new is called via the expression parsing code when a 7394 reloc is needed. We use this hook to get the correct .got reloc. */ 7395 static int cons_sign = -1; 7396 7397 void 7398 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, 7399 expressionS *exp, bfd_reloc_code_real_type r) 7400 { 7401 r = reloc (len, 0, cons_sign, 0, r); 7402 7403 #ifdef TE_PE 7404 if (exp->X_op == O_secrel) 7405 { 7406 exp->X_op = O_symbol; 7407 r = BFD_RELOC_32_SECREL; 7408 } 7409 #endif 7410 7411 fix_new_exp (frag, off, len, exp, 0, r); 7412 } 7413 7414 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the 7415 purpose of the `.dc.a' internal pseudo-op. */ 7416 7417 int 7418 x86_address_bytes (void) 7419 { 7420 if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) 7421 return 4; 7422 return stdoutput->arch_info->bits_per_address / 8; 7423 } 7424 7425 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ 7426 || defined (LEX_AT) 7427 # define lex_got(reloc, adjust, types, bnd_prefix) NULL 7428 #else 7429 /* Parse operands of the form 7430 <symbol>@GOTOFF+<nnn> 7431 and similar .plt or .got references. 7432 7433 If we find one, set up the correct relocation in RELOC and copy the 7434 input string, minus the `@GOTOFF' into a malloc'd buffer for 7435 parsing by the calling routine. Return this buffer, and if ADJUST 7436 is non-null set it to the length of the string we removed from the 7437 input line. Otherwise return NULL. */ 7438 static char * 7439 lex_got (enum bfd_reloc_code_real *rel, 7440 int *adjust, 7441 i386_operand_type *types, 7442 int bnd_prefix) 7443 { 7444 /* Some of the relocations depend on the size of what field is to 7445 be relocated. But in our callers i386_immediate and i386_displacement 7446 we don't yet know the operand size (this will be set by insn 7447 matching). Hence we record the word32 relocation here, 7448 and adjust the reloc according to the real size in reloc(). */ 7449 static const struct { 7450 const char *str; 7451 int len; 7452 const enum bfd_reloc_code_real rel[2]; 7453 const i386_operand_type types64; 7454 } gotrel[] = { 7455 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 7456 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, 7457 BFD_RELOC_SIZE32 }, 7458 OPERAND_TYPE_IMM32_64 }, 7459 #endif 7460 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, 7461 BFD_RELOC_X86_64_PLTOFF64 }, 7462 OPERAND_TYPE_IMM64 }, 7463 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, 7464 BFD_RELOC_X86_64_PLT32 }, 7465 OPERAND_TYPE_IMM32_32S_DISP32 }, 7466 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, 7467 BFD_RELOC_X86_64_GOTPLT64 }, 7468 OPERAND_TYPE_IMM64_DISP64 }, 7469 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, 7470 BFD_RELOC_X86_64_GOTOFF64 }, 7471 OPERAND_TYPE_IMM64_DISP64 }, 7472 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, 7473 BFD_RELOC_X86_64_GOTPCREL }, 7474 OPERAND_TYPE_IMM32_32S_DISP32 }, 7475 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, 7476 BFD_RELOC_X86_64_TLSGD }, 7477 OPERAND_TYPE_IMM32_32S_DISP32 }, 7478 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, 7479 _dummy_first_bfd_reloc_code_real }, 7480 OPERAND_TYPE_NONE }, 7481 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, 7482 BFD_RELOC_X86_64_TLSLD }, 7483 OPERAND_TYPE_IMM32_32S_DISP32 }, 7484 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, 7485 BFD_RELOC_X86_64_GOTTPOFF }, 7486 OPERAND_TYPE_IMM32_32S_DISP32 }, 7487 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, 7488 BFD_RELOC_X86_64_TPOFF32 }, 7489 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 7490 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, 7491 _dummy_first_bfd_reloc_code_real }, 7492 OPERAND_TYPE_NONE }, 7493 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, 7494 BFD_RELOC_X86_64_DTPOFF32 }, 7495 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 7496 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, 7497 _dummy_first_bfd_reloc_code_real }, 7498 OPERAND_TYPE_NONE }, 7499 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, 7500 _dummy_first_bfd_reloc_code_real }, 7501 OPERAND_TYPE_NONE }, 7502 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, 7503 BFD_RELOC_X86_64_GOT32 }, 7504 OPERAND_TYPE_IMM32_32S_64_DISP32 }, 7505 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, 7506 BFD_RELOC_X86_64_GOTPC32_TLSDESC }, 7507 OPERAND_TYPE_IMM32_32S_DISP32 }, 7508 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, 7509 BFD_RELOC_X86_64_TLSDESC_CALL }, 7510 OPERAND_TYPE_IMM32_32S_DISP32 }, 7511 }; 7512 char *cp; 7513 unsigned int j; 7514 7515 #if defined (OBJ_MAYBE_ELF) 7516 if (!IS_ELF) 7517 return NULL; 7518 #endif 7519 7520 for (cp = input_line_pointer; *cp != '@'; cp++) 7521 if (is_end_of_line[(unsigned char) *cp] || *cp == ',') 7522 return NULL; 7523 7524 for (j = 0; j < ARRAY_SIZE (gotrel); j++) 7525 { 7526 int len = gotrel[j].len; 7527 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 7528 { 7529 if (gotrel[j].rel[object_64bit] != 0) 7530 { 7531 int first, second; 7532 char *tmpbuf, *past_reloc; 7533 7534 *rel = gotrel[j].rel[object_64bit]; 7535 7536 if (types) 7537 { 7538 if (flag_code != CODE_64BIT) 7539 { 7540 types->bitfield.imm32 = 1; 7541 types->bitfield.disp32 = 1; 7542 } 7543 else 7544 *types = gotrel[j].types64; 7545 } 7546 7547 if (j != 0 && GOT_symbol == NULL) 7548 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 7549 7550 /* The length of the first part of our input line. */ 7551 first = cp - input_line_pointer; 7552 7553 /* The second part goes from after the reloc token until 7554 (and including) an end_of_line char or comma. */ 7555 past_reloc = cp + 1 + len; 7556 cp = past_reloc; 7557 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') 7558 ++cp; 7559 second = cp + 1 - past_reloc; 7560 7561 /* Allocate and copy string. The trailing NUL shouldn't 7562 be necessary, but be safe. */ 7563 tmpbuf = (char *) xmalloc (first + second + 2); 7564 memcpy (tmpbuf, input_line_pointer, first); 7565 if (second != 0 && *past_reloc != ' ') 7566 /* Replace the relocation token with ' ', so that 7567 errors like foo@GOTOFF1 will be detected. */ 7568 tmpbuf[first++] = ' '; 7569 else 7570 /* Increment length by 1 if the relocation token is 7571 removed. */ 7572 len++; 7573 if (adjust) 7574 *adjust = len; 7575 memcpy (tmpbuf + first, past_reloc, second); 7576 tmpbuf[first + second] = '\0'; 7577 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32) 7578 *rel = BFD_RELOC_X86_64_PLT32_BND; 7579 return tmpbuf; 7580 } 7581 7582 as_bad (_("@%s reloc is not supported with %d-bit output format"), 7583 gotrel[j].str, 1 << (5 + object_64bit)); 7584 return NULL; 7585 } 7586 } 7587 7588 /* Might be a symbol version string. Don't as_bad here. */ 7589 return NULL; 7590 } 7591 #endif 7592 7593 #ifdef TE_PE 7594 #ifdef lex_got 7595 #undef lex_got 7596 #endif 7597 /* Parse operands of the form 7598 <symbol>@SECREL32+<nnn> 7599 7600 If we find one, set up the correct relocation in RELOC and copy the 7601 input string, minus the `@SECREL32' into a malloc'd buffer for 7602 parsing by the calling routine. Return this buffer, and if ADJUST 7603 is non-null set it to the length of the string we removed from the 7604 input line. Otherwise return NULL. 7605 7606 This function is copied from the ELF version above adjusted for PE targets. */ 7607 7608 static char * 7609 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, 7610 int *adjust ATTRIBUTE_UNUSED, 7611 i386_operand_type *types, 7612 int bnd_prefix ATTRIBUTE_UNUSED) 7613 { 7614 static const struct 7615 { 7616 const char *str; 7617 int len; 7618 const enum bfd_reloc_code_real rel[2]; 7619 const i386_operand_type types64; 7620 } 7621 gotrel[] = 7622 { 7623 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, 7624 BFD_RELOC_32_SECREL }, 7625 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 7626 }; 7627 7628 char *cp; 7629 unsigned j; 7630 7631 for (cp = input_line_pointer; *cp != '@'; cp++) 7632 if (is_end_of_line[(unsigned char) *cp] || *cp == ',') 7633 return NULL; 7634 7635 for (j = 0; j < ARRAY_SIZE (gotrel); j++) 7636 { 7637 int len = gotrel[j].len; 7638 7639 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 7640 { 7641 if (gotrel[j].rel[object_64bit] != 0) 7642 { 7643 int first, second; 7644 char *tmpbuf, *past_reloc; 7645 7646 *rel = gotrel[j].rel[object_64bit]; 7647 if (adjust) 7648 *adjust = len; 7649 7650 if (types) 7651 { 7652 if (flag_code != CODE_64BIT) 7653 { 7654 types->bitfield.imm32 = 1; 7655 types->bitfield.disp32 = 1; 7656 } 7657 else 7658 *types = gotrel[j].types64; 7659 } 7660 7661 /* The length of the first part of our input line. */ 7662 first = cp - input_line_pointer; 7663 7664 /* The second part goes from after the reloc token until 7665 (and including) an end_of_line char or comma. */ 7666 past_reloc = cp + 1 + len; 7667 cp = past_reloc; 7668 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') 7669 ++cp; 7670 second = cp + 1 - past_reloc; 7671 7672 /* Allocate and copy string. The trailing NUL shouldn't 7673 be necessary, but be safe. */ 7674 tmpbuf = (char *) xmalloc (first + second + 2); 7675 memcpy (tmpbuf, input_line_pointer, first); 7676 if (second != 0 && *past_reloc != ' ') 7677 /* Replace the relocation token with ' ', so that 7678 errors like foo@SECLREL321 will be detected. */ 7679 tmpbuf[first++] = ' '; 7680 memcpy (tmpbuf + first, past_reloc, second); 7681 tmpbuf[first + second] = '\0'; 7682 return tmpbuf; 7683 } 7684 7685 as_bad (_("@%s reloc is not supported with %d-bit output format"), 7686 gotrel[j].str, 1 << (5 + object_64bit)); 7687 return NULL; 7688 } 7689 } 7690 7691 /* Might be a symbol version string. Don't as_bad here. */ 7692 return NULL; 7693 } 7694 7695 #endif /* TE_PE */ 7696 7697 bfd_reloc_code_real_type 7698 x86_cons (expressionS *exp, int size) 7699 { 7700 bfd_reloc_code_real_type got_reloc = NO_RELOC; 7701 7702 intel_syntax = -intel_syntax; 7703 7704 exp->X_md = 0; 7705 if (size == 4 || (object_64bit && size == 8)) 7706 { 7707 /* Handle @GOTOFF and the like in an expression. */ 7708 char *save; 7709 char *gotfree_input_line; 7710 int adjust = 0; 7711 7712 save = input_line_pointer; 7713 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0); 7714 if (gotfree_input_line) 7715 input_line_pointer = gotfree_input_line; 7716 7717 expression (exp); 7718 7719 if (gotfree_input_line) 7720 { 7721 /* expression () has merrily parsed up to the end of line, 7722 or a comma - in the wrong buffer. Transfer how far 7723 input_line_pointer has moved to the right buffer. */ 7724 input_line_pointer = (save 7725 + (input_line_pointer - gotfree_input_line) 7726 + adjust); 7727 free (gotfree_input_line); 7728 if (exp->X_op == O_constant 7729 || exp->X_op == O_absent 7730 || exp->X_op == O_illegal 7731 || exp->X_op == O_register 7732 || exp->X_op == O_big) 7733 { 7734 char c = *input_line_pointer; 7735 *input_line_pointer = 0; 7736 as_bad (_("missing or invalid expression `%s'"), save); 7737 *input_line_pointer = c; 7738 } 7739 } 7740 } 7741 else 7742 expression (exp); 7743 7744 intel_syntax = -intel_syntax; 7745 7746 if (intel_syntax) 7747 i386_intel_simplify (exp); 7748 7749 return got_reloc; 7750 } 7751 7752 static void 7753 signed_cons (int size) 7754 { 7755 if (flag_code == CODE_64BIT) 7756 cons_sign = 1; 7757 cons (size); 7758 cons_sign = -1; 7759 } 7760 7761 #ifdef TE_PE 7762 static void 7763 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 7764 { 7765 expressionS exp; 7766 7767 do 7768 { 7769 expression (&exp); 7770 if (exp.X_op == O_symbol) 7771 exp.X_op = O_secrel; 7772 7773 emit_expr (&exp, 4); 7774 } 7775 while (*input_line_pointer++ == ','); 7776 7777 input_line_pointer--; 7778 demand_empty_rest_of_line (); 7779 } 7780 #endif 7781 7782 /* Handle Vector operations. */ 7783 7784 static char * 7785 check_VecOperations (char *op_string, char *op_end) 7786 { 7787 const reg_entry *mask; 7788 const char *saved; 7789 char *end_op; 7790 7791 while (*op_string 7792 && (op_end == NULL || op_string < op_end)) 7793 { 7794 saved = op_string; 7795 if (*op_string == '{') 7796 { 7797 op_string++; 7798 7799 /* Check broadcasts. */ 7800 if (strncmp (op_string, "1to", 3) == 0) 7801 { 7802 int bcst_type; 7803 7804 if (i.broadcast) 7805 goto duplicated_vec_op; 7806 7807 op_string += 3; 7808 if (*op_string == '8') 7809 bcst_type = BROADCAST_1TO8; 7810 else if (*op_string == '4') 7811 bcst_type = BROADCAST_1TO4; 7812 else if (*op_string == '2') 7813 bcst_type = BROADCAST_1TO2; 7814 else if (*op_string == '1' 7815 && *(op_string+1) == '6') 7816 { 7817 bcst_type = BROADCAST_1TO16; 7818 op_string++; 7819 } 7820 else 7821 { 7822 as_bad (_("Unsupported broadcast: `%s'"), saved); 7823 return NULL; 7824 } 7825 op_string++; 7826 7827 broadcast_op.type = bcst_type; 7828 broadcast_op.operand = this_operand; 7829 i.broadcast = &broadcast_op; 7830 } 7831 /* Check masking operation. */ 7832 else if ((mask = parse_register (op_string, &end_op)) != NULL) 7833 { 7834 /* k0 can't be used for write mask. */ 7835 if (mask->reg_num == 0) 7836 { 7837 as_bad (_("`%s' can't be used for write mask"), 7838 op_string); 7839 return NULL; 7840 } 7841 7842 if (!i.mask) 7843 { 7844 mask_op.mask = mask; 7845 mask_op.zeroing = 0; 7846 mask_op.operand = this_operand; 7847 i.mask = &mask_op; 7848 } 7849 else 7850 { 7851 if (i.mask->mask) 7852 goto duplicated_vec_op; 7853 7854 i.mask->mask = mask; 7855 7856 /* Only "{z}" is allowed here. No need to check 7857 zeroing mask explicitly. */ 7858 if (i.mask->operand != this_operand) 7859 { 7860 as_bad (_("invalid write mask `%s'"), saved); 7861 return NULL; 7862 } 7863 } 7864 7865 op_string = end_op; 7866 } 7867 /* Check zeroing-flag for masking operation. */ 7868 else if (*op_string == 'z') 7869 { 7870 if (!i.mask) 7871 { 7872 mask_op.mask = NULL; 7873 mask_op.zeroing = 1; 7874 mask_op.operand = this_operand; 7875 i.mask = &mask_op; 7876 } 7877 else 7878 { 7879 if (i.mask->zeroing) 7880 { 7881 duplicated_vec_op: 7882 as_bad (_("duplicated `%s'"), saved); 7883 return NULL; 7884 } 7885 7886 i.mask->zeroing = 1; 7887 7888 /* Only "{%k}" is allowed here. No need to check mask 7889 register explicitly. */ 7890 if (i.mask->operand != this_operand) 7891 { 7892 as_bad (_("invalid zeroing-masking `%s'"), 7893 saved); 7894 return NULL; 7895 } 7896 } 7897 7898 op_string++; 7899 } 7900 else 7901 goto unknown_vec_op; 7902 7903 if (*op_string != '}') 7904 { 7905 as_bad (_("missing `}' in `%s'"), saved); 7906 return NULL; 7907 } 7908 op_string++; 7909 continue; 7910 } 7911 unknown_vec_op: 7912 /* We don't know this one. */ 7913 as_bad (_("unknown vector operation: `%s'"), saved); 7914 return NULL; 7915 } 7916 7917 return op_string; 7918 } 7919 7920 static int 7921 i386_immediate (char *imm_start) 7922 { 7923 char *save_input_line_pointer; 7924 char *gotfree_input_line; 7925 segT exp_seg = 0; 7926 expressionS *exp; 7927 i386_operand_type types; 7928 7929 operand_type_set (&types, ~0); 7930 7931 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 7932 { 7933 as_bad (_("at most %d immediate operands are allowed"), 7934 MAX_IMMEDIATE_OPERANDS); 7935 return 0; 7936 } 7937 7938 exp = &im_expressions[i.imm_operands++]; 7939 i.op[this_operand].imms = exp; 7940 7941 if (is_space_char (*imm_start)) 7942 ++imm_start; 7943 7944 save_input_line_pointer = input_line_pointer; 7945 input_line_pointer = imm_start; 7946 7947 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types, 7948 (i.bnd_prefix != NULL 7949 || add_bnd_prefix)); 7950 if (gotfree_input_line) 7951 input_line_pointer = gotfree_input_line; 7952 7953 exp_seg = expression (exp); 7954 7955 SKIP_WHITESPACE (); 7956 7957 /* Handle vector operations. */ 7958 if (*input_line_pointer == '{') 7959 { 7960 input_line_pointer = check_VecOperations (input_line_pointer, 7961 NULL); 7962 if (input_line_pointer == NULL) 7963 return 0; 7964 } 7965 7966 if (*input_line_pointer) 7967 as_bad (_("junk `%s' after expression"), input_line_pointer); 7968 7969 input_line_pointer = save_input_line_pointer; 7970 if (gotfree_input_line) 7971 { 7972 free (gotfree_input_line); 7973 7974 if (exp->X_op == O_constant || exp->X_op == O_register) 7975 exp->X_op = O_illegal; 7976 } 7977 7978 return i386_finalize_immediate (exp_seg, exp, types, imm_start); 7979 } 7980 7981 static int 7982 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, 7983 i386_operand_type types, const char *imm_start) 7984 { 7985 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) 7986 { 7987 if (imm_start) 7988 as_bad (_("missing or invalid immediate expression `%s'"), 7989 imm_start); 7990 return 0; 7991 } 7992 else if (exp->X_op == O_constant) 7993 { 7994 /* Size it properly later. */ 7995 i.types[this_operand].bitfield.imm64 = 1; 7996 /* If not 64bit, sign extend val. */ 7997 if (flag_code != CODE_64BIT 7998 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) 7999 exp->X_add_number 8000 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 8001 } 8002 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 8003 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour 8004 && exp_seg != absolute_section 8005 && exp_seg != text_section 8006 && exp_seg != data_section 8007 && exp_seg != bss_section 8008 && exp_seg != undefined_section 8009 && !bfd_is_com_section (exp_seg)) 8010 { 8011 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 8012 return 0; 8013 } 8014 #endif 8015 else if (!intel_syntax && exp_seg == reg_section) 8016 { 8017 if (imm_start) 8018 as_bad (_("illegal immediate register operand %s"), imm_start); 8019 return 0; 8020 } 8021 else 8022 { 8023 /* This is an address. The size of the address will be 8024 determined later, depending on destination register, 8025 suffix, or the default for the section. */ 8026 i.types[this_operand].bitfield.imm8 = 1; 8027 i.types[this_operand].bitfield.imm16 = 1; 8028 i.types[this_operand].bitfield.imm32 = 1; 8029 i.types[this_operand].bitfield.imm32s = 1; 8030 i.types[this_operand].bitfield.imm64 = 1; 8031 i.types[this_operand] = operand_type_and (i.types[this_operand], 8032 types); 8033 } 8034 8035 return 1; 8036 } 8037 8038 static char * 8039 i386_scale (char *scale) 8040 { 8041 offsetT val; 8042 char *save = input_line_pointer; 8043 8044 input_line_pointer = scale; 8045 val = get_absolute_expression (); 8046 8047 switch (val) 8048 { 8049 case 1: 8050 i.log2_scale_factor = 0; 8051 break; 8052 case 2: 8053 i.log2_scale_factor = 1; 8054 break; 8055 case 4: 8056 i.log2_scale_factor = 2; 8057 break; 8058 case 8: 8059 i.log2_scale_factor = 3; 8060 break; 8061 default: 8062 { 8063 char sep = *input_line_pointer; 8064 8065 *input_line_pointer = '\0'; 8066 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 8067 scale); 8068 *input_line_pointer = sep; 8069 input_line_pointer = save; 8070 return NULL; 8071 } 8072 } 8073 if (i.log2_scale_factor != 0 && i.index_reg == 0) 8074 { 8075 as_warn (_("scale factor of %d without an index register"), 8076 1 << i.log2_scale_factor); 8077 i.log2_scale_factor = 0; 8078 } 8079 scale = input_line_pointer; 8080 input_line_pointer = save; 8081 return scale; 8082 } 8083 8084 static int 8085 i386_displacement (char *disp_start, char *disp_end) 8086 { 8087 expressionS *exp; 8088 segT exp_seg = 0; 8089 char *save_input_line_pointer; 8090 char *gotfree_input_line; 8091 int override; 8092 i386_operand_type bigdisp, types = anydisp; 8093 int ret; 8094 8095 if (i.disp_operands == MAX_MEMORY_OPERANDS) 8096 { 8097 as_bad (_("at most %d displacement operands are allowed"), 8098 MAX_MEMORY_OPERANDS); 8099 return 0; 8100 } 8101 8102 operand_type_set (&bigdisp, 0); 8103 if ((i.types[this_operand].bitfield.jumpabsolute) 8104 || (!current_templates->start->opcode_modifier.jump 8105 && !current_templates->start->opcode_modifier.jumpdword)) 8106 { 8107 bigdisp.bitfield.disp32 = 1; 8108 override = (i.prefix[ADDR_PREFIX] != 0); 8109 if (flag_code == CODE_64BIT) 8110 { 8111 if (!override) 8112 { 8113 bigdisp.bitfield.disp32s = 1; 8114 bigdisp.bitfield.disp64 = 1; 8115 } 8116 } 8117 else if ((flag_code == CODE_16BIT) ^ override) 8118 { 8119 bigdisp.bitfield.disp32 = 0; 8120 bigdisp.bitfield.disp16 = 1; 8121 } 8122 } 8123 else 8124 { 8125 /* For PC-relative branches, the width of the displacement 8126 is dependent upon data size, not address size. */ 8127 override = (i.prefix[DATA_PREFIX] != 0); 8128 if (flag_code == CODE_64BIT) 8129 { 8130 if (override || i.suffix == WORD_MNEM_SUFFIX) 8131 bigdisp.bitfield.disp16 = 1; 8132 else 8133 { 8134 bigdisp.bitfield.disp32 = 1; 8135 bigdisp.bitfield.disp32s = 1; 8136 } 8137 } 8138 else 8139 { 8140 if (!override) 8141 override = (i.suffix == (flag_code != CODE_16BIT 8142 ? WORD_MNEM_SUFFIX 8143 : LONG_MNEM_SUFFIX)); 8144 bigdisp.bitfield.disp32 = 1; 8145 if ((flag_code == CODE_16BIT) ^ override) 8146 { 8147 bigdisp.bitfield.disp32 = 0; 8148 bigdisp.bitfield.disp16 = 1; 8149 } 8150 } 8151 } 8152 i.types[this_operand] = operand_type_or (i.types[this_operand], 8153 bigdisp); 8154 8155 exp = &disp_expressions[i.disp_operands]; 8156 i.op[this_operand].disps = exp; 8157 i.disp_operands++; 8158 save_input_line_pointer = input_line_pointer; 8159 input_line_pointer = disp_start; 8160 END_STRING_AND_SAVE (disp_end); 8161 8162 #ifndef GCC_ASM_O_HACK 8163 #define GCC_ASM_O_HACK 0 8164 #endif 8165 #if GCC_ASM_O_HACK 8166 END_STRING_AND_SAVE (disp_end + 1); 8167 if (i.types[this_operand].bitfield.baseIndex 8168 && displacement_string_end[-1] == '+') 8169 { 8170 /* This hack is to avoid a warning when using the "o" 8171 constraint within gcc asm statements. 8172 For instance: 8173 8174 #define _set_tssldt_desc(n,addr,limit,type) \ 8175 __asm__ __volatile__ ( \ 8176 "movw %w2,%0\n\t" \ 8177 "movw %w1,2+%0\n\t" \ 8178 "rorl $16,%1\n\t" \ 8179 "movb %b1,4+%0\n\t" \ 8180 "movb %4,5+%0\n\t" \ 8181 "movb $0,6+%0\n\t" \ 8182 "movb %h1,7+%0\n\t" \ 8183 "rorl $16,%1" \ 8184 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 8185 8186 This works great except that the output assembler ends 8187 up looking a bit weird if it turns out that there is 8188 no offset. You end up producing code that looks like: 8189 8190 #APP 8191 movw $235,(%eax) 8192 movw %dx,2+(%eax) 8193 rorl $16,%edx 8194 movb %dl,4+(%eax) 8195 movb $137,5+(%eax) 8196 movb $0,6+(%eax) 8197 movb %dh,7+(%eax) 8198 rorl $16,%edx 8199 #NO_APP 8200 8201 So here we provide the missing zero. */ 8202 8203 *displacement_string_end = '0'; 8204 } 8205 #endif 8206 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types, 8207 (i.bnd_prefix != NULL 8208 || add_bnd_prefix)); 8209 if (gotfree_input_line) 8210 input_line_pointer = gotfree_input_line; 8211 8212 exp_seg = expression (exp); 8213 8214 SKIP_WHITESPACE (); 8215 if (*input_line_pointer) 8216 as_bad (_("junk `%s' after expression"), input_line_pointer); 8217 #if GCC_ASM_O_HACK 8218 RESTORE_END_STRING (disp_end + 1); 8219 #endif 8220 input_line_pointer = save_input_line_pointer; 8221 if (gotfree_input_line) 8222 { 8223 free (gotfree_input_line); 8224 8225 if (exp->X_op == O_constant || exp->X_op == O_register) 8226 exp->X_op = O_illegal; 8227 } 8228 8229 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); 8230 8231 RESTORE_END_STRING (disp_end); 8232 8233 return ret; 8234 } 8235 8236 static int 8237 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, 8238 i386_operand_type types, const char *disp_start) 8239 { 8240 i386_operand_type bigdisp; 8241 int ret = 1; 8242 8243 /* We do this to make sure that the section symbol is in 8244 the symbol table. We will ultimately change the relocation 8245 to be relative to the beginning of the section. */ 8246 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF 8247 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 8248 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 8249 { 8250 if (exp->X_op != O_symbol) 8251 goto inv_disp; 8252 8253 if (S_IS_LOCAL (exp->X_add_symbol) 8254 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section 8255 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) 8256 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 8257 exp->X_op = O_subtract; 8258 exp->X_op_symbol = GOT_symbol; 8259 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 8260 i.reloc[this_operand] = BFD_RELOC_32_PCREL; 8261 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 8262 i.reloc[this_operand] = BFD_RELOC_64; 8263 else 8264 i.reloc[this_operand] = BFD_RELOC_32; 8265 } 8266 8267 else if (exp->X_op == O_absent 8268 || exp->X_op == O_illegal 8269 || exp->X_op == O_big) 8270 { 8271 inv_disp: 8272 as_bad (_("missing or invalid displacement expression `%s'"), 8273 disp_start); 8274 ret = 0; 8275 } 8276 8277 else if (flag_code == CODE_64BIT 8278 && !i.prefix[ADDR_PREFIX] 8279 && exp->X_op == O_constant) 8280 { 8281 /* Since displacement is signed extended to 64bit, don't allow 8282 disp32 and turn off disp32s if they are out of range. */ 8283 i.types[this_operand].bitfield.disp32 = 0; 8284 if (!fits_in_signed_long (exp->X_add_number)) 8285 { 8286 i.types[this_operand].bitfield.disp32s = 0; 8287 if (i.types[this_operand].bitfield.baseindex) 8288 { 8289 as_bad (_("0x%lx out range of signed 32bit displacement"), 8290 (long) exp->X_add_number); 8291 ret = 0; 8292 } 8293 } 8294 } 8295 8296 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 8297 else if (exp->X_op != O_constant 8298 && OUTPUT_FLAVOR == bfd_target_aout_flavour 8299 && exp_seg != absolute_section 8300 && exp_seg != text_section 8301 && exp_seg != data_section 8302 && exp_seg != bss_section 8303 && exp_seg != undefined_section 8304 && !bfd_is_com_section (exp_seg)) 8305 { 8306 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 8307 ret = 0; 8308 } 8309 #endif 8310 8311 /* Check if this is a displacement only operand. */ 8312 bigdisp = i.types[this_operand]; 8313 bigdisp.bitfield.disp8 = 0; 8314 bigdisp.bitfield.disp16 = 0; 8315 bigdisp.bitfield.disp32 = 0; 8316 bigdisp.bitfield.disp32s = 0; 8317 bigdisp.bitfield.disp64 = 0; 8318 if (operand_type_all_zero (&bigdisp)) 8319 i.types[this_operand] = operand_type_and (i.types[this_operand], 8320 types); 8321 8322 return ret; 8323 } 8324 8325 /* Make sure the memory operand we've been dealt is valid. 8326 Return 1 on success, 0 on a failure. */ 8327 8328 static int 8329 i386_index_check (const char *operand_string) 8330 { 8331 const char *kind = "base/index"; 8332 enum flag_code addr_mode; 8333 8334 if (i.prefix[ADDR_PREFIX]) 8335 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; 8336 else 8337 { 8338 addr_mode = flag_code; 8339 8340 #if INFER_ADDR_PREFIX 8341 if (i.mem_operands == 0) 8342 { 8343 /* Infer address prefix from the first memory operand. */ 8344 const reg_entry *addr_reg = i.base_reg; 8345 8346 if (addr_reg == NULL) 8347 addr_reg = i.index_reg; 8348 8349 if (addr_reg) 8350 { 8351 if (addr_reg->reg_num == RegEip 8352 || addr_reg->reg_num == RegEiz 8353 || addr_reg->reg_type.bitfield.reg32) 8354 addr_mode = CODE_32BIT; 8355 else if (flag_code != CODE_64BIT 8356 && addr_reg->reg_type.bitfield.reg16) 8357 addr_mode = CODE_16BIT; 8358 8359 if (addr_mode != flag_code) 8360 { 8361 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 8362 i.prefixes += 1; 8363 /* Change the size of any displacement too. At most one 8364 of Disp16 or Disp32 is set. 8365 FIXME. There doesn't seem to be any real need for 8366 separate Disp16 and Disp32 flags. The same goes for 8367 Imm16 and Imm32. Removing them would probably clean 8368 up the code quite a lot. */ 8369 if (flag_code != CODE_64BIT 8370 && (i.types[this_operand].bitfield.disp16 8371 || i.types[this_operand].bitfield.disp32)) 8372 i.types[this_operand] 8373 = operand_type_xor (i.types[this_operand], disp16_32); 8374 } 8375 } 8376 } 8377 #endif 8378 } 8379 8380 if (current_templates->start->opcode_modifier.isstring 8381 && !current_templates->start->opcode_modifier.immext 8382 && (current_templates->end[-1].opcode_modifier.isstring 8383 || i.mem_operands)) 8384 { 8385 /* Memory operands of string insns are special in that they only allow 8386 a single register (rDI, rSI, or rBX) as their memory address. */ 8387 const reg_entry *expected_reg; 8388 static const char *di_si[][2] = 8389 { 8390 { "esi", "edi" }, 8391 { "si", "di" }, 8392 { "rsi", "rdi" } 8393 }; 8394 static const char *bx[] = { "ebx", "bx", "rbx" }; 8395 8396 kind = "string address"; 8397 8398 if (current_templates->start->opcode_modifier.w) 8399 { 8400 i386_operand_type type = current_templates->end[-1].operand_types[0]; 8401 8402 if (!type.bitfield.baseindex 8403 || ((!i.mem_operands != !intel_syntax) 8404 && current_templates->end[-1].operand_types[1] 8405 .bitfield.baseindex)) 8406 type = current_templates->end[-1].operand_types[1]; 8407 expected_reg = hash_find (reg_hash, 8408 di_si[addr_mode][type.bitfield.esseg]); 8409 8410 } 8411 else 8412 expected_reg = hash_find (reg_hash, bx[addr_mode]); 8413 8414 if (i.base_reg != expected_reg 8415 || i.index_reg 8416 || operand_type_check (i.types[this_operand], disp)) 8417 { 8418 /* The second memory operand must have the same size as 8419 the first one. */ 8420 if (i.mem_operands 8421 && i.base_reg 8422 && !((addr_mode == CODE_64BIT 8423 && i.base_reg->reg_type.bitfield.reg64) 8424 || (addr_mode == CODE_32BIT 8425 ? i.base_reg->reg_type.bitfield.reg32 8426 : i.base_reg->reg_type.bitfield.reg16))) 8427 goto bad_address; 8428 8429 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), 8430 operand_string, 8431 intel_syntax ? '[' : '(', 8432 register_prefix, 8433 expected_reg->reg_name, 8434 intel_syntax ? ']' : ')'); 8435 return 1; 8436 } 8437 else 8438 return 1; 8439 8440 bad_address: 8441 as_bad (_("`%s' is not a valid %s expression"), 8442 operand_string, kind); 8443 return 0; 8444 } 8445 else 8446 { 8447 if (addr_mode != CODE_16BIT) 8448 { 8449 /* 32-bit/64-bit checks. */ 8450 if ((i.base_reg 8451 && (addr_mode == CODE_64BIT 8452 ? !i.base_reg->reg_type.bitfield.reg64 8453 : !i.base_reg->reg_type.bitfield.reg32) 8454 && (i.index_reg 8455 || (i.base_reg->reg_num 8456 != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) 8457 || (i.index_reg 8458 && !i.index_reg->reg_type.bitfield.regxmm 8459 && !i.index_reg->reg_type.bitfield.regymm 8460 && !i.index_reg->reg_type.bitfield.regzmm 8461 && ((addr_mode == CODE_64BIT 8462 ? !(i.index_reg->reg_type.bitfield.reg64 8463 || i.index_reg->reg_num == RegRiz) 8464 : !(i.index_reg->reg_type.bitfield.reg32 8465 || i.index_reg->reg_num == RegEiz)) 8466 || !i.index_reg->reg_type.bitfield.baseindex))) 8467 goto bad_address; 8468 } 8469 else 8470 { 8471 /* 16-bit checks. */ 8472 if ((i.base_reg 8473 && (!i.base_reg->reg_type.bitfield.reg16 8474 || !i.base_reg->reg_type.bitfield.baseindex)) 8475 || (i.index_reg 8476 && (!i.index_reg->reg_type.bitfield.reg16 8477 || !i.index_reg->reg_type.bitfield.baseindex 8478 || !(i.base_reg 8479 && i.base_reg->reg_num < 6 8480 && i.index_reg->reg_num >= 6 8481 && i.log2_scale_factor == 0)))) 8482 goto bad_address; 8483 } 8484 } 8485 return 1; 8486 } 8487 8488 /* Handle vector immediates. */ 8489 8490 static int 8491 RC_SAE_immediate (const char *imm_start) 8492 { 8493 unsigned int match_found, j; 8494 const char *pstr = imm_start; 8495 expressionS *exp; 8496 8497 if (*pstr != '{') 8498 return 0; 8499 8500 pstr++; 8501 match_found = 0; 8502 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) 8503 { 8504 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) 8505 { 8506 if (!i.rounding) 8507 { 8508 rc_op.type = RC_NamesTable[j].type; 8509 rc_op.operand = this_operand; 8510 i.rounding = &rc_op; 8511 } 8512 else 8513 { 8514 as_bad (_("duplicated `%s'"), imm_start); 8515 return 0; 8516 } 8517 pstr += RC_NamesTable[j].len; 8518 match_found = 1; 8519 break; 8520 } 8521 } 8522 if (!match_found) 8523 return 0; 8524 8525 if (*pstr++ != '}') 8526 { 8527 as_bad (_("Missing '}': '%s'"), imm_start); 8528 return 0; 8529 } 8530 /* RC/SAE immediate string should contain nothing more. */; 8531 if (*pstr != 0) 8532 { 8533 as_bad (_("Junk after '}': '%s'"), imm_start); 8534 return 0; 8535 } 8536 8537 exp = &im_expressions[i.imm_operands++]; 8538 i.op[this_operand].imms = exp; 8539 8540 exp->X_op = O_constant; 8541 exp->X_add_number = 0; 8542 exp->X_add_symbol = (symbolS *) 0; 8543 exp->X_op_symbol = (symbolS *) 0; 8544 8545 i.types[this_operand].bitfield.imm8 = 1; 8546 return 1; 8547 } 8548 8549 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero 8550 on error. */ 8551 8552 static int 8553 i386_att_operand (char *operand_string) 8554 { 8555 const reg_entry *r; 8556 char *end_op; 8557 char *op_string = operand_string; 8558 8559 if (is_space_char (*op_string)) 8560 ++op_string; 8561 8562 /* We check for an absolute prefix (differentiating, 8563 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 8564 if (*op_string == ABSOLUTE_PREFIX) 8565 { 8566 ++op_string; 8567 if (is_space_char (*op_string)) 8568 ++op_string; 8569 i.types[this_operand].bitfield.jumpabsolute = 1; 8570 } 8571 8572 /* Check if operand is a register. */ 8573 if ((r = parse_register (op_string, &end_op)) != NULL) 8574 { 8575 i386_operand_type temp; 8576 8577 /* Check for a segment override by searching for ':' after a 8578 segment register. */ 8579 op_string = end_op; 8580 if (is_space_char (*op_string)) 8581 ++op_string; 8582 if (*op_string == ':' 8583 && (r->reg_type.bitfield.sreg2 8584 || r->reg_type.bitfield.sreg3)) 8585 { 8586 switch (r->reg_num) 8587 { 8588 case 0: 8589 i.seg[i.mem_operands] = &es; 8590 break; 8591 case 1: 8592 i.seg[i.mem_operands] = &cs; 8593 break; 8594 case 2: 8595 i.seg[i.mem_operands] = &ss; 8596 break; 8597 case 3: 8598 i.seg[i.mem_operands] = &ds; 8599 break; 8600 case 4: 8601 i.seg[i.mem_operands] = &fs; 8602 break; 8603 case 5: 8604 i.seg[i.mem_operands] = &gs; 8605 break; 8606 } 8607 8608 /* Skip the ':' and whitespace. */ 8609 ++op_string; 8610 if (is_space_char (*op_string)) 8611 ++op_string; 8612 8613 if (!is_digit_char (*op_string) 8614 && !is_identifier_char (*op_string) 8615 && *op_string != '(' 8616 && *op_string != ABSOLUTE_PREFIX) 8617 { 8618 as_bad (_("bad memory operand `%s'"), op_string); 8619 return 0; 8620 } 8621 /* Handle case of %es:*foo. */ 8622 if (*op_string == ABSOLUTE_PREFIX) 8623 { 8624 ++op_string; 8625 if (is_space_char (*op_string)) 8626 ++op_string; 8627 i.types[this_operand].bitfield.jumpabsolute = 1; 8628 } 8629 goto do_memory_reference; 8630 } 8631 8632 /* Handle vector operations. */ 8633 if (*op_string == '{') 8634 { 8635 op_string = check_VecOperations (op_string, NULL); 8636 if (op_string == NULL) 8637 return 0; 8638 } 8639 8640 if (*op_string) 8641 { 8642 as_bad (_("junk `%s' after register"), op_string); 8643 return 0; 8644 } 8645 temp = r->reg_type; 8646 temp.bitfield.baseindex = 0; 8647 i.types[this_operand] = operand_type_or (i.types[this_operand], 8648 temp); 8649 i.types[this_operand].bitfield.unspecified = 0; 8650 i.op[this_operand].regs = r; 8651 i.reg_operands++; 8652 } 8653 else if (*op_string == REGISTER_PREFIX) 8654 { 8655 as_bad (_("bad register name `%s'"), op_string); 8656 return 0; 8657 } 8658 else if (*op_string == IMMEDIATE_PREFIX) 8659 { 8660 ++op_string; 8661 if (i.types[this_operand].bitfield.jumpabsolute) 8662 { 8663 as_bad (_("immediate operand illegal with absolute jump")); 8664 return 0; 8665 } 8666 if (!i386_immediate (op_string)) 8667 return 0; 8668 } 8669 else if (RC_SAE_immediate (operand_string)) 8670 { 8671 /* If it is a RC or SAE immediate, do nothing. */ 8672 ; 8673 } 8674 else if (is_digit_char (*op_string) 8675 || is_identifier_char (*op_string) 8676 || *op_string == '(') 8677 { 8678 /* This is a memory reference of some sort. */ 8679 char *base_string; 8680 8681 /* Start and end of displacement string expression (if found). */ 8682 char *displacement_string_start; 8683 char *displacement_string_end; 8684 char *vop_start; 8685 8686 do_memory_reference: 8687 if ((i.mem_operands == 1 8688 && !current_templates->start->opcode_modifier.isstring) 8689 || i.mem_operands == 2) 8690 { 8691 as_bad (_("too many memory references for `%s'"), 8692 current_templates->start->name); 8693 return 0; 8694 } 8695 8696 /* Check for base index form. We detect the base index form by 8697 looking for an ')' at the end of the operand, searching 8698 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 8699 after the '('. */ 8700 base_string = op_string + strlen (op_string); 8701 8702 /* Handle vector operations. */ 8703 vop_start = strchr (op_string, '{'); 8704 if (vop_start && vop_start < base_string) 8705 { 8706 if (check_VecOperations (vop_start, base_string) == NULL) 8707 return 0; 8708 base_string = vop_start; 8709 } 8710 8711 --base_string; 8712 if (is_space_char (*base_string)) 8713 --base_string; 8714 8715 /* If we only have a displacement, set-up for it to be parsed later. */ 8716 displacement_string_start = op_string; 8717 displacement_string_end = base_string + 1; 8718 8719 if (*base_string == ')') 8720 { 8721 char *temp_string; 8722 unsigned int parens_balanced = 1; 8723 /* We've already checked that the number of left & right ()'s are 8724 equal, so this loop will not be infinite. */ 8725 do 8726 { 8727 base_string--; 8728 if (*base_string == ')') 8729 parens_balanced++; 8730 if (*base_string == '(') 8731 parens_balanced--; 8732 } 8733 while (parens_balanced); 8734 8735 temp_string = base_string; 8736 8737 /* Skip past '(' and whitespace. */ 8738 ++base_string; 8739 if (is_space_char (*base_string)) 8740 ++base_string; 8741 8742 if (*base_string == ',' 8743 || ((i.base_reg = parse_register (base_string, &end_op)) 8744 != NULL)) 8745 { 8746 displacement_string_end = temp_string; 8747 8748 i.types[this_operand].bitfield.baseindex = 1; 8749 8750 if (i.base_reg) 8751 { 8752 base_string = end_op; 8753 if (is_space_char (*base_string)) 8754 ++base_string; 8755 } 8756 8757 /* There may be an index reg or scale factor here. */ 8758 if (*base_string == ',') 8759 { 8760 ++base_string; 8761 if (is_space_char (*base_string)) 8762 ++base_string; 8763 8764 if ((i.index_reg = parse_register (base_string, &end_op)) 8765 != NULL) 8766 { 8767 base_string = end_op; 8768 if (is_space_char (*base_string)) 8769 ++base_string; 8770 if (*base_string == ',') 8771 { 8772 ++base_string; 8773 if (is_space_char (*base_string)) 8774 ++base_string; 8775 } 8776 else if (*base_string != ')') 8777 { 8778 as_bad (_("expecting `,' or `)' " 8779 "after index register in `%s'"), 8780 operand_string); 8781 return 0; 8782 } 8783 } 8784 else if (*base_string == REGISTER_PREFIX) 8785 { 8786 end_op = strchr (base_string, ','); 8787 if (end_op) 8788 *end_op = '\0'; 8789 as_bad (_("bad register name `%s'"), base_string); 8790 return 0; 8791 } 8792 8793 /* Check for scale factor. */ 8794 if (*base_string != ')') 8795 { 8796 char *end_scale = i386_scale (base_string); 8797 8798 if (!end_scale) 8799 return 0; 8800 8801 base_string = end_scale; 8802 if (is_space_char (*base_string)) 8803 ++base_string; 8804 if (*base_string != ')') 8805 { 8806 as_bad (_("expecting `)' " 8807 "after scale factor in `%s'"), 8808 operand_string); 8809 return 0; 8810 } 8811 } 8812 else if (!i.index_reg) 8813 { 8814 as_bad (_("expecting index register or scale factor " 8815 "after `,'; got '%c'"), 8816 *base_string); 8817 return 0; 8818 } 8819 } 8820 else if (*base_string != ')') 8821 { 8822 as_bad (_("expecting `,' or `)' " 8823 "after base register in `%s'"), 8824 operand_string); 8825 return 0; 8826 } 8827 } 8828 else if (*base_string == REGISTER_PREFIX) 8829 { 8830 end_op = strchr (base_string, ','); 8831 if (end_op) 8832 *end_op = '\0'; 8833 as_bad (_("bad register name `%s'"), base_string); 8834 return 0; 8835 } 8836 } 8837 8838 /* If there's an expression beginning the operand, parse it, 8839 assuming displacement_string_start and 8840 displacement_string_end are meaningful. */ 8841 if (displacement_string_start != displacement_string_end) 8842 { 8843 if (!i386_displacement (displacement_string_start, 8844 displacement_string_end)) 8845 return 0; 8846 } 8847 8848 /* Special case for (%dx) while doing input/output op. */ 8849 if (i.base_reg 8850 && operand_type_equal (&i.base_reg->reg_type, 8851 ®16_inoutportreg) 8852 && i.index_reg == 0 8853 && i.log2_scale_factor == 0 8854 && i.seg[i.mem_operands] == 0 8855 && !operand_type_check (i.types[this_operand], disp)) 8856 { 8857 i.types[this_operand] = inoutportreg; 8858 return 1; 8859 } 8860 8861 if (i386_index_check (operand_string) == 0) 8862 return 0; 8863 i.types[this_operand].bitfield.mem = 1; 8864 i.mem_operands++; 8865 } 8866 else 8867 { 8868 /* It's not a memory operand; argh! */ 8869 as_bad (_("invalid char %s beginning operand %d `%s'"), 8870 output_invalid (*op_string), 8871 this_operand + 1, 8872 op_string); 8873 return 0; 8874 } 8875 return 1; /* Normal return. */ 8876 } 8877 8878 /* Calculate the maximum variable size (i.e., excluding fr_fix) 8880 that an rs_machine_dependent frag may reach. */ 8881 8882 unsigned int 8883 i386_frag_max_var (fragS *frag) 8884 { 8885 /* The only relaxable frags are for jumps. 8886 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ 8887 gas_assert (frag->fr_type == rs_machine_dependent); 8888 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; 8889 } 8890 8891 /* md_estimate_size_before_relax() 8892 8893 Called just before relax() for rs_machine_dependent frags. The x86 8894 assembler uses these frags to handle variable size jump 8895 instructions. 8896 8897 Any symbol that is now undefined will not become defined. 8898 Return the correct fr_subtype in the frag. 8899 Return the initial "guess for variable size of frag" to caller. 8900 The guess is actually the growth beyond the fixed part. Whatever 8901 we do to grow the fixed or variable part contributes to our 8902 returned value. */ 8903 8904 int 8905 md_estimate_size_before_relax (fragS *fragP, segT segment) 8906 { 8907 /* We've already got fragP->fr_subtype right; all we have to do is 8908 check for un-relaxable symbols. On an ELF system, we can't relax 8909 an externally visible symbol, because it may be overridden by a 8910 shared library. */ 8911 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 8912 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8913 || (IS_ELF 8914 && (S_IS_EXTERNAL (fragP->fr_symbol) 8915 || S_IS_WEAK (fragP->fr_symbol) 8916 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags 8917 & BSF_GNU_INDIRECT_FUNCTION)))) 8918 #endif 8919 #if defined (OBJ_COFF) && defined (TE_PE) 8920 || (OUTPUT_FLAVOR == bfd_target_coff_flavour 8921 && S_IS_WEAK (fragP->fr_symbol)) 8922 #endif 8923 ) 8924 { 8925 /* Symbol is undefined in this segment, or we need to keep a 8926 reloc so that weak symbols can be overridden. */ 8927 int size = (fragP->fr_subtype & CODE16) ? 2 : 4; 8928 enum bfd_reloc_code_real reloc_type; 8929 unsigned char *opcode; 8930 int old_fr_fix; 8931 8932 if (fragP->fr_var != NO_RELOC) 8933 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; 8934 else if (size == 2) 8935 reloc_type = BFD_RELOC_16_PCREL; 8936 else 8937 reloc_type = BFD_RELOC_32_PCREL; 8938 8939 old_fr_fix = fragP->fr_fix; 8940 opcode = (unsigned char *) fragP->fr_opcode; 8941 8942 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) 8943 { 8944 case UNCOND_JUMP: 8945 /* Make jmp (0xeb) a (d)word displacement jump. */ 8946 opcode[0] = 0xe9; 8947 fragP->fr_fix += size; 8948 fix_new (fragP, old_fr_fix, size, 8949 fragP->fr_symbol, 8950 fragP->fr_offset, 1, 8951 reloc_type); 8952 break; 8953 8954 case COND_JUMP86: 8955 if (size == 2 8956 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) 8957 { 8958 /* Negate the condition, and branch past an 8959 unconditional jump. */ 8960 opcode[0] ^= 1; 8961 opcode[1] = 3; 8962 /* Insert an unconditional jump. */ 8963 opcode[2] = 0xe9; 8964 /* We added two extra opcode bytes, and have a two byte 8965 offset. */ 8966 fragP->fr_fix += 2 + 2; 8967 fix_new (fragP, old_fr_fix + 2, 2, 8968 fragP->fr_symbol, 8969 fragP->fr_offset, 1, 8970 reloc_type); 8971 break; 8972 } 8973 /* Fall through. */ 8974 8975 case COND_JUMP: 8976 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) 8977 { 8978 fixS *fixP; 8979 8980 fragP->fr_fix += 1; 8981 fixP = fix_new (fragP, old_fr_fix, 1, 8982 fragP->fr_symbol, 8983 fragP->fr_offset, 1, 8984 BFD_RELOC_8_PCREL); 8985 fixP->fx_signed = 1; 8986 break; 8987 } 8988 8989 /* This changes the byte-displacement jump 0x7N 8990 to the (d)word-displacement jump 0x0f,0x8N. */ 8991 opcode[1] = opcode[0] + 0x10; 8992 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 8993 /* We've added an opcode byte. */ 8994 fragP->fr_fix += 1 + size; 8995 fix_new (fragP, old_fr_fix + 1, size, 8996 fragP->fr_symbol, 8997 fragP->fr_offset, 1, 8998 reloc_type); 8999 break; 9000 9001 default: 9002 BAD_CASE (fragP->fr_subtype); 9003 break; 9004 } 9005 frag_wane (fragP); 9006 return fragP->fr_fix - old_fr_fix; 9007 } 9008 9009 /* Guess size depending on current relax state. Initially the relax 9010 state will correspond to a short jump and we return 1, because 9011 the variable part of the frag (the branch offset) is one byte 9012 long. However, we can relax a section more than once and in that 9013 case we must either set fr_subtype back to the unrelaxed state, 9014 or return the value for the appropriate branch. */ 9015 return md_relax_table[fragP->fr_subtype].rlx_length; 9016 } 9017 9018 /* Called after relax() is finished. 9019 9020 In: Address of frag. 9021 fr_type == rs_machine_dependent. 9022 fr_subtype is what the address relaxed to. 9023 9024 Out: Any fixSs and constants are set up. 9025 Caller will turn frag into a ".space 0". */ 9026 9027 void 9028 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, 9029 fragS *fragP) 9030 { 9031 unsigned char *opcode; 9032 unsigned char *where_to_put_displacement = NULL; 9033 offsetT target_address; 9034 offsetT opcode_address; 9035 unsigned int extension = 0; 9036 offsetT displacement_from_opcode_start; 9037 9038 opcode = (unsigned char *) fragP->fr_opcode; 9039 9040 /* Address we want to reach in file space. */ 9041 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 9042 9043 /* Address opcode resides at in file space. */ 9044 opcode_address = fragP->fr_address + fragP->fr_fix; 9045 9046 /* Displacement from opcode start to fill into instruction. */ 9047 displacement_from_opcode_start = target_address - opcode_address; 9048 9049 if ((fragP->fr_subtype & BIG) == 0) 9050 { 9051 /* Don't have to change opcode. */ 9052 extension = 1; /* 1 opcode + 1 displacement */ 9053 where_to_put_displacement = &opcode[1]; 9054 } 9055 else 9056 { 9057 if (no_cond_jump_promotion 9058 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) 9059 as_warn_where (fragP->fr_file, fragP->fr_line, 9060 _("long jump required")); 9061 9062 switch (fragP->fr_subtype) 9063 { 9064 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 9065 extension = 4; /* 1 opcode + 4 displacement */ 9066 opcode[0] = 0xe9; 9067 where_to_put_displacement = &opcode[1]; 9068 break; 9069 9070 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 9071 extension = 2; /* 1 opcode + 2 displacement */ 9072 opcode[0] = 0xe9; 9073 where_to_put_displacement = &opcode[1]; 9074 break; 9075 9076 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 9077 case ENCODE_RELAX_STATE (COND_JUMP86, BIG): 9078 extension = 5; /* 2 opcode + 4 displacement */ 9079 opcode[1] = opcode[0] + 0x10; 9080 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 9081 where_to_put_displacement = &opcode[2]; 9082 break; 9083 9084 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 9085 extension = 3; /* 2 opcode + 2 displacement */ 9086 opcode[1] = opcode[0] + 0x10; 9087 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 9088 where_to_put_displacement = &opcode[2]; 9089 break; 9090 9091 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): 9092 extension = 4; 9093 opcode[0] ^= 1; 9094 opcode[1] = 3; 9095 opcode[2] = 0xe9; 9096 where_to_put_displacement = &opcode[3]; 9097 break; 9098 9099 default: 9100 BAD_CASE (fragP->fr_subtype); 9101 break; 9102 } 9103 } 9104 9105 /* If size if less then four we are sure that the operand fits, 9106 but if it's 4, then it could be that the displacement is larger 9107 then -/+ 2GB. */ 9108 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 9109 && object_64bit 9110 && ((addressT) (displacement_from_opcode_start - extension 9111 + ((addressT) 1 << 31)) 9112 > (((addressT) 2 << 31) - 1))) 9113 { 9114 as_bad_where (fragP->fr_file, fragP->fr_line, 9115 _("jump target out of range")); 9116 /* Make us emit 0. */ 9117 displacement_from_opcode_start = extension; 9118 } 9119 /* Now put displacement after opcode. */ 9120 md_number_to_chars ((char *) where_to_put_displacement, 9121 (valueT) (displacement_from_opcode_start - extension), 9122 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 9123 fragP->fr_fix += extension; 9124 } 9125 9126 /* Apply a fixup (fixP) to segment data, once it has been determined 9128 by our caller that we have all the info we need to fix it up. 9129 9130 Parameter valP is the pointer to the value of the bits. 9131 9132 On the 386, immediates, displacements, and data pointers are all in 9133 the same (little-endian) format, so we don't need to care about which 9134 we are handling. */ 9135 9136 void 9137 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 9138 { 9139 char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 9140 valueT value = *valP; 9141 9142 #if !defined (TE_Mach) 9143 if (fixP->fx_pcrel) 9144 { 9145 switch (fixP->fx_r_type) 9146 { 9147 default: 9148 break; 9149 9150 case BFD_RELOC_64: 9151 fixP->fx_r_type = BFD_RELOC_64_PCREL; 9152 break; 9153 case BFD_RELOC_32: 9154 case BFD_RELOC_X86_64_32S: 9155 fixP->fx_r_type = BFD_RELOC_32_PCREL; 9156 break; 9157 case BFD_RELOC_16: 9158 fixP->fx_r_type = BFD_RELOC_16_PCREL; 9159 break; 9160 case BFD_RELOC_8: 9161 fixP->fx_r_type = BFD_RELOC_8_PCREL; 9162 break; 9163 } 9164 } 9165 9166 if (fixP->fx_addsy != NULL 9167 && (fixP->fx_r_type == BFD_RELOC_32_PCREL 9168 || fixP->fx_r_type == BFD_RELOC_64_PCREL 9169 || fixP->fx_r_type == BFD_RELOC_16_PCREL 9170 || fixP->fx_r_type == BFD_RELOC_8_PCREL 9171 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND) 9172 && !use_rela_relocations) 9173 { 9174 /* This is a hack. There should be a better way to handle this. 9175 This covers for the fact that bfd_install_relocation will 9176 subtract the current location (for partial_inplace, PC relative 9177 relocations); see more below. */ 9178 #ifndef OBJ_AOUT 9179 if (IS_ELF 9180 #ifdef TE_PE 9181 || OUTPUT_FLAVOR == bfd_target_coff_flavour 9182 #endif 9183 ) 9184 value += fixP->fx_where + fixP->fx_frag->fr_address; 9185 #endif 9186 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9187 if (IS_ELF) 9188 { 9189 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); 9190 9191 if ((sym_seg == seg 9192 || (symbol_section_p (fixP->fx_addsy) 9193 && sym_seg != absolute_section)) 9194 && !generic_force_reloc (fixP)) 9195 { 9196 /* Yes, we add the values in twice. This is because 9197 bfd_install_relocation subtracts them out again. I think 9198 bfd_install_relocation is broken, but I don't dare change 9199 it. FIXME. */ 9200 value += fixP->fx_where + fixP->fx_frag->fr_address; 9201 } 9202 } 9203 #endif 9204 #if defined (OBJ_COFF) && defined (TE_PE) 9205 /* For some reason, the PE format does not store a 9206 section address offset for a PC relative symbol. */ 9207 if (S_GET_SEGMENT (fixP->fx_addsy) != seg 9208 || S_IS_WEAK (fixP->fx_addsy)) 9209 value += md_pcrel_from (fixP); 9210 #endif 9211 } 9212 #if defined (OBJ_COFF) && defined (TE_PE) 9213 if (fixP->fx_addsy != NULL 9214 && S_IS_WEAK (fixP->fx_addsy) 9215 /* PR 16858: Do not modify weak function references. */ 9216 && ! fixP->fx_pcrel) 9217 { 9218 #if !defined (TE_PEP) 9219 /* For x86 PE weak function symbols are neither PC-relative 9220 nor do they set S_IS_FUNCTION. So the only reliable way 9221 to detect them is to check the flags of their containing 9222 section. */ 9223 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL 9224 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) 9225 ; 9226 else 9227 #endif 9228 value -= S_GET_VALUE (fixP->fx_addsy); 9229 } 9230 #endif 9231 9232 /* Fix a few things - the dynamic linker expects certain values here, 9233 and we must not disappoint it. */ 9234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9235 if (IS_ELF && fixP->fx_addsy) 9236 switch (fixP->fx_r_type) 9237 { 9238 case BFD_RELOC_386_PLT32: 9239 case BFD_RELOC_X86_64_PLT32: 9240 case BFD_RELOC_X86_64_PLT32_BND: 9241 /* Make the jump instruction point to the address of the operand. At 9242 runtime we merely add the offset to the actual PLT entry. */ 9243 value = -4; 9244 break; 9245 9246 case BFD_RELOC_386_TLS_GD: 9247 case BFD_RELOC_386_TLS_LDM: 9248 case BFD_RELOC_386_TLS_IE_32: 9249 case BFD_RELOC_386_TLS_IE: 9250 case BFD_RELOC_386_TLS_GOTIE: 9251 case BFD_RELOC_386_TLS_GOTDESC: 9252 case BFD_RELOC_X86_64_TLSGD: 9253 case BFD_RELOC_X86_64_TLSLD: 9254 case BFD_RELOC_X86_64_GOTTPOFF: 9255 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 9256 value = 0; /* Fully resolved at runtime. No addend. */ 9257 /* Fallthrough */ 9258 case BFD_RELOC_386_TLS_LE: 9259 case BFD_RELOC_386_TLS_LDO_32: 9260 case BFD_RELOC_386_TLS_LE_32: 9261 case BFD_RELOC_X86_64_DTPOFF32: 9262 case BFD_RELOC_X86_64_DTPOFF64: 9263 case BFD_RELOC_X86_64_TPOFF32: 9264 case BFD_RELOC_X86_64_TPOFF64: 9265 S_SET_THREAD_LOCAL (fixP->fx_addsy); 9266 break; 9267 9268 case BFD_RELOC_386_TLS_DESC_CALL: 9269 case BFD_RELOC_X86_64_TLSDESC_CALL: 9270 value = 0; /* Fully resolved at runtime. No addend. */ 9271 S_SET_THREAD_LOCAL (fixP->fx_addsy); 9272 fixP->fx_done = 0; 9273 return; 9274 9275 case BFD_RELOC_386_GOT32: 9276 case BFD_RELOC_X86_64_GOT32: 9277 value = 0; /* Fully resolved at runtime. No addend. */ 9278 break; 9279 9280 case BFD_RELOC_VTABLE_INHERIT: 9281 case BFD_RELOC_VTABLE_ENTRY: 9282 fixP->fx_done = 0; 9283 return; 9284 9285 default: 9286 break; 9287 } 9288 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 9289 *valP = value; 9290 #endif /* !defined (TE_Mach) */ 9291 9292 /* Are we finished with this relocation now? */ 9293 if (fixP->fx_addsy == NULL) 9294 fixP->fx_done = 1; 9295 #if defined (OBJ_COFF) && defined (TE_PE) 9296 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) 9297 { 9298 fixP->fx_done = 0; 9299 /* Remember value for tc_gen_reloc. */ 9300 fixP->fx_addnumber = value; 9301 /* Clear out the frag for now. */ 9302 value = 0; 9303 } 9304 #endif 9305 else if (use_rela_relocations) 9306 { 9307 fixP->fx_no_overflow = 1; 9308 /* Remember value for tc_gen_reloc. */ 9309 fixP->fx_addnumber = value; 9310 value = 0; 9311 } 9312 9313 md_number_to_chars (p, value, fixP->fx_size); 9314 } 9315 9316 char * 9318 md_atof (int type, char *litP, int *sizeP) 9319 { 9320 /* This outputs the LITTLENUMs in REVERSE order; 9321 in accord with the bigendian 386. */ 9322 return ieee_md_atof (type, litP, sizeP, FALSE); 9323 } 9324 9325 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; 9327 9328 static char * 9329 output_invalid (int c) 9330 { 9331 if (ISPRINT (c)) 9332 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 9333 "'%c'", c); 9334 else 9335 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 9336 "(0x%x)", (unsigned char) c); 9337 return output_invalid_buf; 9338 } 9339 9340 /* REG_STRING starts *before* REGISTER_PREFIX. */ 9341 9342 static const reg_entry * 9343 parse_real_register (char *reg_string, char **end_op) 9344 { 9345 char *s = reg_string; 9346 char *p; 9347 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 9348 const reg_entry *r; 9349 9350 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 9351 if (*s == REGISTER_PREFIX) 9352 ++s; 9353 9354 if (is_space_char (*s)) 9355 ++s; 9356 9357 p = reg_name_given; 9358 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 9359 { 9360 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 9361 return (const reg_entry *) NULL; 9362 s++; 9363 } 9364 9365 /* For naked regs, make sure that we are not dealing with an identifier. 9366 This prevents confusing an identifier like `eax_var' with register 9367 `eax'. */ 9368 if (allow_naked_reg && identifier_chars[(unsigned char) *s]) 9369 return (const reg_entry *) NULL; 9370 9371 *end_op = s; 9372 9373 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 9374 9375 /* Handle floating point regs, allowing spaces in the (i) part. */ 9376 if (r == i386_regtab /* %st is first entry of table */) 9377 { 9378 if (is_space_char (*s)) 9379 ++s; 9380 if (*s == '(') 9381 { 9382 ++s; 9383 if (is_space_char (*s)) 9384 ++s; 9385 if (*s >= '0' && *s <= '7') 9386 { 9387 int fpr = *s - '0'; 9388 ++s; 9389 if (is_space_char (*s)) 9390 ++s; 9391 if (*s == ')') 9392 { 9393 *end_op = s + 1; 9394 r = (const reg_entry *) hash_find (reg_hash, "st(0)"); 9395 know (r); 9396 return r + fpr; 9397 } 9398 } 9399 /* We have "%st(" then garbage. */ 9400 return (const reg_entry *) NULL; 9401 } 9402 } 9403 9404 if (r == NULL || allow_pseudo_reg) 9405 return r; 9406 9407 if (operand_type_all_zero (&r->reg_type)) 9408 return (const reg_entry *) NULL; 9409 9410 if ((r->reg_type.bitfield.reg32 9411 || r->reg_type.bitfield.sreg3 9412 || r->reg_type.bitfield.control 9413 || r->reg_type.bitfield.debug 9414 || r->reg_type.bitfield.test) 9415 && !cpu_arch_flags.bitfield.cpui386) 9416 return (const reg_entry *) NULL; 9417 9418 if (r->reg_type.bitfield.floatreg 9419 && !cpu_arch_flags.bitfield.cpu8087 9420 && !cpu_arch_flags.bitfield.cpu287 9421 && !cpu_arch_flags.bitfield.cpu387) 9422 return (const reg_entry *) NULL; 9423 9424 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) 9425 return (const reg_entry *) NULL; 9426 9427 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) 9428 return (const reg_entry *) NULL; 9429 9430 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) 9431 return (const reg_entry *) NULL; 9432 9433 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask) 9434 && !cpu_arch_flags.bitfield.cpuavx512f) 9435 return (const reg_entry *) NULL; 9436 9437 /* Don't allow fake index register unless allow_index_reg isn't 0. */ 9438 if (!allow_index_reg 9439 && (r->reg_num == RegEiz || r->reg_num == RegRiz)) 9440 return (const reg_entry *) NULL; 9441 9442 /* Upper 16 vector register is only available with VREX in 64bit 9443 mode. */ 9444 if ((r->reg_flags & RegVRex)) 9445 { 9446 if (!cpu_arch_flags.bitfield.cpuvrex 9447 || flag_code != CODE_64BIT) 9448 return (const reg_entry *) NULL; 9449 9450 i.need_vrex = 1; 9451 } 9452 9453 if (((r->reg_flags & (RegRex64 | RegRex)) 9454 || r->reg_type.bitfield.reg64) 9455 && (!cpu_arch_flags.bitfield.cpulm 9456 || !operand_type_equal (&r->reg_type, &control)) 9457 && flag_code != CODE_64BIT) 9458 return (const reg_entry *) NULL; 9459 9460 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) 9461 return (const reg_entry *) NULL; 9462 9463 return r; 9464 } 9465 9466 /* REG_STRING starts *before* REGISTER_PREFIX. */ 9467 9468 static const reg_entry * 9469 parse_register (char *reg_string, char **end_op) 9470 { 9471 const reg_entry *r; 9472 9473 if (*reg_string == REGISTER_PREFIX || allow_naked_reg) 9474 r = parse_real_register (reg_string, end_op); 9475 else 9476 r = NULL; 9477 if (!r) 9478 { 9479 char *save = input_line_pointer; 9480 char c; 9481 symbolS *symbolP; 9482 9483 input_line_pointer = reg_string; 9484 c = get_symbol_end (); 9485 symbolP = symbol_find (reg_string); 9486 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) 9487 { 9488 const expressionS *e = symbol_get_value_expression (symbolP); 9489 9490 know (e->X_op == O_register); 9491 know (e->X_add_number >= 0 9492 && (valueT) e->X_add_number < i386_regtab_size); 9493 r = i386_regtab + e->X_add_number; 9494 if ((r->reg_flags & RegVRex)) 9495 i.need_vrex = 1; 9496 *end_op = input_line_pointer; 9497 } 9498 *input_line_pointer = c; 9499 input_line_pointer = save; 9500 } 9501 return r; 9502 } 9503 9504 int 9505 i386_parse_name (char *name, expressionS *e, char *nextcharP) 9506 { 9507 const reg_entry *r; 9508 char *end = input_line_pointer; 9509 9510 *end = *nextcharP; 9511 r = parse_register (name, &input_line_pointer); 9512 if (r && end <= input_line_pointer) 9513 { 9514 *nextcharP = *input_line_pointer; 9515 *input_line_pointer = 0; 9516 e->X_op = O_register; 9517 e->X_add_number = r - i386_regtab; 9518 return 1; 9519 } 9520 input_line_pointer = end; 9521 *end = 0; 9522 return intel_syntax ? i386_intel_parse_name (name, e) : 0; 9523 } 9524 9525 void 9526 md_operand (expressionS *e) 9527 { 9528 char *end; 9529 const reg_entry *r; 9530 9531 switch (*input_line_pointer) 9532 { 9533 case REGISTER_PREFIX: 9534 r = parse_real_register (input_line_pointer, &end); 9535 if (r) 9536 { 9537 e->X_op = O_register; 9538 e->X_add_number = r - i386_regtab; 9539 input_line_pointer = end; 9540 } 9541 break; 9542 9543 case '[': 9544 gas_assert (intel_syntax); 9545 end = input_line_pointer++; 9546 expression (e); 9547 if (*input_line_pointer == ']') 9548 { 9549 ++input_line_pointer; 9550 e->X_op_symbol = make_expr_symbol (e); 9551 e->X_add_symbol = NULL; 9552 e->X_add_number = 0; 9553 e->X_op = O_index; 9554 } 9555 else 9556 { 9557 e->X_op = O_absent; 9558 input_line_pointer = end; 9559 } 9560 break; 9561 } 9562 } 9563 9564 9565 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9567 const char *md_shortopts = "kVQ:sqn"; 9568 #else 9569 const char *md_shortopts = "qn"; 9570 #endif 9571 9572 #define OPTION_32 (OPTION_MD_BASE + 0) 9573 #define OPTION_64 (OPTION_MD_BASE + 1) 9574 #define OPTION_DIVIDE (OPTION_MD_BASE + 2) 9575 #define OPTION_MARCH (OPTION_MD_BASE + 3) 9576 #define OPTION_MTUNE (OPTION_MD_BASE + 4) 9577 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) 9578 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) 9579 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) 9580 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) 9581 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) 9582 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) 9583 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) 9584 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) 9585 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) 9586 #define OPTION_X32 (OPTION_MD_BASE + 14) 9587 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) 9588 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) 9589 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) 9590 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) 9591 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) 9592 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) 9593 9594 struct option md_longopts[] = 9595 { 9596 {"32", no_argument, NULL, OPTION_32}, 9597 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 9598 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 9599 {"64", no_argument, NULL, OPTION_64}, 9600 #endif 9601 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9602 {"x32", no_argument, NULL, OPTION_X32}, 9603 #endif 9604 {"divide", no_argument, NULL, OPTION_DIVIDE}, 9605 {"march", required_argument, NULL, OPTION_MARCH}, 9606 {"mtune", required_argument, NULL, OPTION_MTUNE}, 9607 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, 9608 {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, 9609 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, 9610 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, 9611 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, 9612 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, 9613 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, 9614 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, 9615 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, 9616 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, 9617 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, 9618 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, 9619 # if defined (TE_PE) || defined (TE_PEP) 9620 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, 9621 #endif 9622 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX}, 9623 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, 9624 {NULL, no_argument, NULL, 0} 9625 }; 9626 size_t md_longopts_size = sizeof (md_longopts); 9627 9628 int 9629 md_parse_option (int c, char *arg) 9630 { 9631 unsigned int j; 9632 char *arch, *next; 9633 9634 switch (c) 9635 { 9636 case 'n': 9637 optimize_align_code = 0; 9638 break; 9639 9640 case 'q': 9641 quiet_warnings = 1; 9642 break; 9643 9644 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9645 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 9646 should be emitted or not. FIXME: Not implemented. */ 9647 case 'Q': 9648 break; 9649 9650 /* -V: SVR4 argument to print version ID. */ 9651 case 'V': 9652 print_version_id (); 9653 break; 9654 9655 /* -k: Ignore for FreeBSD compatibility. */ 9656 case 'k': 9657 break; 9658 9659 case 's': 9660 /* -s: On i386 Solaris, this tells the native assembler to use 9661 .stab instead of .stab.excl. We always use .stab anyhow. */ 9662 break; 9663 #endif 9664 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 9665 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 9666 case OPTION_64: 9667 { 9668 const char **list, **l; 9669 9670 list = bfd_target_list (); 9671 for (l = list; *l != NULL; l++) 9672 if (CONST_STRNEQ (*l, "elf64-x86-64") 9673 || strcmp (*l, "coff-x86-64") == 0 9674 || strcmp (*l, "pe-x86-64") == 0 9675 || strcmp (*l, "pei-x86-64") == 0 9676 || strcmp (*l, "mach-o-x86-64") == 0) 9677 { 9678 default_arch = "x86_64"; 9679 break; 9680 } 9681 if (*l == NULL) 9682 as_fatal (_("no compiled in support for x86_64")); 9683 free (list); 9684 } 9685 break; 9686 #endif 9687 9688 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9689 case OPTION_X32: 9690 if (IS_ELF) 9691 { 9692 const char **list, **l; 9693 9694 list = bfd_target_list (); 9695 for (l = list; *l != NULL; l++) 9696 if (CONST_STRNEQ (*l, "elf32-x86-64")) 9697 { 9698 default_arch = "x86_64:32"; 9699 break; 9700 } 9701 if (*l == NULL) 9702 as_fatal (_("no compiled in support for 32bit x86_64")); 9703 free (list); 9704 } 9705 else 9706 as_fatal (_("32bit x86_64 is only supported for ELF")); 9707 break; 9708 #endif 9709 9710 case OPTION_32: 9711 default_arch = "i386"; 9712 break; 9713 9714 case OPTION_DIVIDE: 9715 #ifdef SVR4_COMMENT_CHARS 9716 { 9717 char *n, *t; 9718 const char *s; 9719 9720 n = (char *) xmalloc (strlen (i386_comment_chars) + 1); 9721 t = n; 9722 for (s = i386_comment_chars; *s != '\0'; s++) 9723 if (*s != '/') 9724 *t++ = *s; 9725 *t = '\0'; 9726 i386_comment_chars = n; 9727 } 9728 #endif 9729 break; 9730 9731 case OPTION_MARCH: 9732 arch = xstrdup (arg); 9733 do 9734 { 9735 if (*arch == '.') 9736 as_fatal (_("invalid -march= option: `%s'"), arg); 9737 next = strchr (arch, '+'); 9738 if (next) 9739 *next++ = '\0'; 9740 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 9741 { 9742 if (strcmp (arch, cpu_arch [j].name) == 0) 9743 { 9744 /* Processor. */ 9745 if (! cpu_arch[j].flags.bitfield.cpui386) 9746 continue; 9747 9748 cpu_arch_name = cpu_arch[j].name; 9749 cpu_sub_arch_name = NULL; 9750 cpu_arch_flags = cpu_arch[j].flags; 9751 cpu_arch_isa = cpu_arch[j].type; 9752 cpu_arch_isa_flags = cpu_arch[j].flags; 9753 if (!cpu_arch_tune_set) 9754 { 9755 cpu_arch_tune = cpu_arch_isa; 9756 cpu_arch_tune_flags = cpu_arch_isa_flags; 9757 } 9758 break; 9759 } 9760 else if (*cpu_arch [j].name == '.' 9761 && strcmp (arch, cpu_arch [j].name + 1) == 0) 9762 { 9763 /* ISA entension. */ 9764 i386_cpu_flags flags; 9765 9766 if (!cpu_arch[j].negated) 9767 flags = cpu_flags_or (cpu_arch_flags, 9768 cpu_arch[j].flags); 9769 else 9770 flags = cpu_flags_and_not (cpu_arch_flags, 9771 cpu_arch[j].flags); 9772 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 9773 { 9774 if (cpu_sub_arch_name) 9775 { 9776 char *name = cpu_sub_arch_name; 9777 cpu_sub_arch_name = concat (name, 9778 cpu_arch[j].name, 9779 (const char *) NULL); 9780 free (name); 9781 } 9782 else 9783 cpu_sub_arch_name = xstrdup (cpu_arch[j].name); 9784 cpu_arch_flags = flags; 9785 cpu_arch_isa_flags = flags; 9786 } 9787 break; 9788 } 9789 } 9790 9791 if (j >= ARRAY_SIZE (cpu_arch)) 9792 as_fatal (_("invalid -march= option: `%s'"), arg); 9793 9794 arch = next; 9795 } 9796 while (next != NULL ); 9797 break; 9798 9799 case OPTION_MTUNE: 9800 if (*arg == '.') 9801 as_fatal (_("invalid -mtune= option: `%s'"), arg); 9802 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 9803 { 9804 if (strcmp (arg, cpu_arch [j].name) == 0) 9805 { 9806 cpu_arch_tune_set = 1; 9807 cpu_arch_tune = cpu_arch [j].type; 9808 cpu_arch_tune_flags = cpu_arch[j].flags; 9809 break; 9810 } 9811 } 9812 if (j >= ARRAY_SIZE (cpu_arch)) 9813 as_fatal (_("invalid -mtune= option: `%s'"), arg); 9814 break; 9815 9816 case OPTION_MMNEMONIC: 9817 if (strcasecmp (arg, "att") == 0) 9818 intel_mnemonic = 0; 9819 else if (strcasecmp (arg, "intel") == 0) 9820 intel_mnemonic = 1; 9821 else 9822 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); 9823 break; 9824 9825 case OPTION_MSYNTAX: 9826 if (strcasecmp (arg, "att") == 0) 9827 intel_syntax = 0; 9828 else if (strcasecmp (arg, "intel") == 0) 9829 intel_syntax = 1; 9830 else 9831 as_fatal (_("invalid -msyntax= option: `%s'"), arg); 9832 break; 9833 9834 case OPTION_MINDEX_REG: 9835 allow_index_reg = 1; 9836 break; 9837 9838 case OPTION_MNAKED_REG: 9839 allow_naked_reg = 1; 9840 break; 9841 9842 case OPTION_MOLD_GCC: 9843 old_gcc = 1; 9844 break; 9845 9846 case OPTION_MSSE2AVX: 9847 sse2avx = 1; 9848 break; 9849 9850 case OPTION_MSSE_CHECK: 9851 if (strcasecmp (arg, "error") == 0) 9852 sse_check = check_error; 9853 else if (strcasecmp (arg, "warning") == 0) 9854 sse_check = check_warning; 9855 else if (strcasecmp (arg, "none") == 0) 9856 sse_check = check_none; 9857 else 9858 as_fatal (_("invalid -msse-check= option: `%s'"), arg); 9859 break; 9860 9861 case OPTION_MOPERAND_CHECK: 9862 if (strcasecmp (arg, "error") == 0) 9863 operand_check = check_error; 9864 else if (strcasecmp (arg, "warning") == 0) 9865 operand_check = check_warning; 9866 else if (strcasecmp (arg, "none") == 0) 9867 operand_check = check_none; 9868 else 9869 as_fatal (_("invalid -moperand-check= option: `%s'"), arg); 9870 break; 9871 9872 case OPTION_MAVXSCALAR: 9873 if (strcasecmp (arg, "128") == 0) 9874 avxscalar = vex128; 9875 else if (strcasecmp (arg, "256") == 0) 9876 avxscalar = vex256; 9877 else 9878 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); 9879 break; 9880 9881 case OPTION_MADD_BND_PREFIX: 9882 add_bnd_prefix = 1; 9883 break; 9884 9885 case OPTION_MEVEXLIG: 9886 if (strcmp (arg, "128") == 0) 9887 evexlig = evexl128; 9888 else if (strcmp (arg, "256") == 0) 9889 evexlig = evexl256; 9890 else if (strcmp (arg, "512") == 0) 9891 evexlig = evexl512; 9892 else 9893 as_fatal (_("invalid -mevexlig= option: `%s'"), arg); 9894 break; 9895 9896 case OPTION_MEVEXRCIG: 9897 if (strcmp (arg, "rne") == 0) 9898 evexrcig = rne; 9899 else if (strcmp (arg, "rd") == 0) 9900 evexrcig = rd; 9901 else if (strcmp (arg, "ru") == 0) 9902 evexrcig = ru; 9903 else if (strcmp (arg, "rz") == 0) 9904 evexrcig = rz; 9905 else 9906 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); 9907 break; 9908 9909 case OPTION_MEVEXWIG: 9910 if (strcmp (arg, "0") == 0) 9911 evexwig = evexw0; 9912 else if (strcmp (arg, "1") == 0) 9913 evexwig = evexw1; 9914 else 9915 as_fatal (_("invalid -mevexwig= option: `%s'"), arg); 9916 break; 9917 9918 # if defined (TE_PE) || defined (TE_PEP) 9919 case OPTION_MBIG_OBJ: 9920 use_big_obj = 1; 9921 break; 9922 #endif 9923 9924 case OPTION_OMIT_LOCK_PREFIX: 9925 if (strcasecmp (arg, "yes") == 0) 9926 omit_lock_prefix = 1; 9927 else if (strcasecmp (arg, "no") == 0) 9928 omit_lock_prefix = 0; 9929 else 9930 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); 9931 break; 9932 9933 default: 9934 return 0; 9935 } 9936 return 1; 9937 } 9938 9939 #define MESSAGE_TEMPLATE \ 9940 " " 9941 9942 static void 9943 show_arch (FILE *stream, int ext, int check) 9944 { 9945 static char message[] = MESSAGE_TEMPLATE; 9946 char *start = message + 27; 9947 char *p; 9948 int size = sizeof (MESSAGE_TEMPLATE); 9949 int left; 9950 const char *name; 9951 int len; 9952 unsigned int j; 9953 9954 p = start; 9955 left = size - (start - message); 9956 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 9957 { 9958 /* Should it be skipped? */ 9959 if (cpu_arch [j].skip) 9960 continue; 9961 9962 name = cpu_arch [j].name; 9963 len = cpu_arch [j].len; 9964 if (*name == '.') 9965 { 9966 /* It is an extension. Skip if we aren't asked to show it. */ 9967 if (ext) 9968 { 9969 name++; 9970 len--; 9971 } 9972 else 9973 continue; 9974 } 9975 else if (ext) 9976 { 9977 /* It is an processor. Skip if we show only extension. */ 9978 continue; 9979 } 9980 else if (check && ! cpu_arch[j].flags.bitfield.cpui386) 9981 { 9982 /* It is an impossible processor - skip. */ 9983 continue; 9984 } 9985 9986 /* Reserve 2 spaces for ", " or ",\0" */ 9987 left -= len + 2; 9988 9989 /* Check if there is any room. */ 9990 if (left >= 0) 9991 { 9992 if (p != start) 9993 { 9994 *p++ = ','; 9995 *p++ = ' '; 9996 } 9997 p = mempcpy (p, name, len); 9998 } 9999 else 10000 { 10001 /* Output the current message now and start a new one. */ 10002 *p++ = ','; 10003 *p = '\0'; 10004 fprintf (stream, "%s\n", message); 10005 p = start; 10006 left = size - (start - message) - len - 2; 10007 10008 gas_assert (left >= 0); 10009 10010 p = mempcpy (p, name, len); 10011 } 10012 } 10013 10014 *p = '\0'; 10015 fprintf (stream, "%s\n", message); 10016 } 10017 10018 void 10019 md_show_usage (FILE *stream) 10020 { 10021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10022 fprintf (stream, _("\ 10023 -Q ignored\n\ 10024 -V print assembler version number\n\ 10025 -k ignored\n")); 10026 #endif 10027 fprintf (stream, _("\ 10028 -n Do not optimize code alignment\n\ 10029 -q quieten some warnings\n")); 10030 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10031 fprintf (stream, _("\ 10032 -s ignored\n")); 10033 #endif 10034 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 10035 || defined (TE_PE) || defined (TE_PEP)) 10036 fprintf (stream, _("\ 10037 --32/--64/--x32 generate 32bit/64bit/x32 code\n")); 10038 #endif 10039 #ifdef SVR4_COMMENT_CHARS 10040 fprintf (stream, _("\ 10041 --divide do not treat `/' as a comment character\n")); 10042 #else 10043 fprintf (stream, _("\ 10044 --divide ignored\n")); 10045 #endif 10046 fprintf (stream, _("\ 10047 -march=CPU[,+EXTENSION...]\n\ 10048 generate code for CPU and EXTENSION, CPU is one of:\n")); 10049 show_arch (stream, 0, 1); 10050 fprintf (stream, _("\ 10051 EXTENSION is combination of:\n")); 10052 show_arch (stream, 1, 0); 10053 fprintf (stream, _("\ 10054 -mtune=CPU optimize for CPU, CPU is one of:\n")); 10055 show_arch (stream, 0, 0); 10056 fprintf (stream, _("\ 10057 -msse2avx encode SSE instructions with VEX prefix\n")); 10058 fprintf (stream, _("\ 10059 -msse-check=[none|error|warning]\n\ 10060 check SSE instructions\n")); 10061 fprintf (stream, _("\ 10062 -moperand-check=[none|error|warning]\n\ 10063 check operand combinations for validity\n")); 10064 fprintf (stream, _("\ 10065 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ 10066 length\n")); 10067 fprintf (stream, _("\ 10068 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ 10069 length\n")); 10070 fprintf (stream, _("\ 10071 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ 10072 for EVEX.W bit ignored instructions\n")); 10073 fprintf (stream, _("\ 10074 -mevexrcig=[rne|rd|ru|rz]\n\ 10075 encode EVEX instructions with specific EVEX.RC value\n\ 10076 for SAE-only ignored instructions\n")); 10077 fprintf (stream, _("\ 10078 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); 10079 fprintf (stream, _("\ 10080 -msyntax=[att|intel] use AT&T/Intel syntax\n")); 10081 fprintf (stream, _("\ 10082 -mindex-reg support pseudo index registers\n")); 10083 fprintf (stream, _("\ 10084 -mnaked-reg don't require `%%' prefix for registers\n")); 10085 fprintf (stream, _("\ 10086 -mold-gcc support old (<= 2.8.1) versions of gcc\n")); 10087 fprintf (stream, _("\ 10088 -madd-bnd-prefix add BND prefix for all valid branches\n")); 10089 # if defined (TE_PE) || defined (TE_PEP) 10090 fprintf (stream, _("\ 10091 -mbig-obj generate big object files\n")); 10092 #endif 10093 fprintf (stream, _("\ 10094 -momit-lock-prefix=[no|yes]\n\ 10095 strip all lock prefixes\n")); 10096 } 10097 10098 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 10099 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 10100 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 10101 10102 /* Pick the target format to use. */ 10103 10104 const char * 10105 i386_target_format (void) 10106 { 10107 if (!strncmp (default_arch, "x86_64", 6)) 10108 { 10109 update_code_flag (CODE_64BIT, 1); 10110 if (default_arch[6] == '\0') 10111 x86_elf_abi = X86_64_ABI; 10112 else 10113 x86_elf_abi = X86_64_X32_ABI; 10114 } 10115 else if (!strcmp (default_arch, "i386")) 10116 update_code_flag (CODE_32BIT, 1); 10117 else 10118 as_fatal (_("unknown architecture")); 10119 10120 if (cpu_flags_all_zero (&cpu_arch_isa_flags)) 10121 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; 10122 if (cpu_flags_all_zero (&cpu_arch_tune_flags)) 10123 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; 10124 10125 switch (OUTPUT_FLAVOR) 10126 { 10127 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) 10128 case bfd_target_aout_flavour: 10129 return AOUT_TARGET_FORMAT; 10130 #endif 10131 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) 10132 # if defined (TE_PE) || defined (TE_PEP) 10133 case bfd_target_coff_flavour: 10134 if (flag_code == CODE_64BIT) 10135 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; 10136 else 10137 return "pe-i386"; 10138 # elif defined (TE_GO32) 10139 case bfd_target_coff_flavour: 10140 return "coff-go32"; 10141 # else 10142 case bfd_target_coff_flavour: 10143 return "coff-i386"; 10144 # endif 10145 #endif 10146 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 10147 case bfd_target_elf_flavour: 10148 { 10149 const char *format; 10150 10151 switch (x86_elf_abi) 10152 { 10153 default: 10154 format = ELF_TARGET_FORMAT; 10155 break; 10156 case X86_64_ABI: 10157 use_rela_relocations = 1; 10158 object_64bit = 1; 10159 format = ELF_TARGET_FORMAT64; 10160 break; 10161 case X86_64_X32_ABI: 10162 use_rela_relocations = 1; 10163 object_64bit = 1; 10164 disallow_64bit_reloc = 1; 10165 format = ELF_TARGET_FORMAT32; 10166 break; 10167 } 10168 if (cpu_arch_isa == PROCESSOR_L1OM) 10169 { 10170 if (x86_elf_abi != X86_64_ABI) 10171 as_fatal (_("Intel L1OM is 64bit only")); 10172 return ELF_TARGET_L1OM_FORMAT; 10173 } 10174 if (cpu_arch_isa == PROCESSOR_K1OM) 10175 { 10176 if (x86_elf_abi != X86_64_ABI) 10177 as_fatal (_("Intel K1OM is 64bit only")); 10178 return ELF_TARGET_K1OM_FORMAT; 10179 } 10180 else 10181 return format; 10182 } 10183 #endif 10184 #if defined (OBJ_MACH_O) 10185 case bfd_target_mach_o_flavour: 10186 if (flag_code == CODE_64BIT) 10187 { 10188 use_rela_relocations = 1; 10189 object_64bit = 1; 10190 return "mach-o-x86-64"; 10191 } 10192 else 10193 return "mach-o-i386"; 10194 #endif 10195 default: 10196 abort (); 10197 return NULL; 10198 } 10199 } 10200 10201 #endif /* OBJ_MAYBE_ more than one */ 10202 10203 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 10204 void 10205 i386_elf_emit_arch_note (void) 10206 { 10207 if (IS_ELF && cpu_arch_name != NULL) 10208 { 10209 char *p; 10210 asection *seg = now_seg; 10211 subsegT subseg = now_subseg; 10212 Elf_Internal_Note i_note; 10213 Elf_External_Note e_note; 10214 asection *note_secp; 10215 int len; 10216 10217 /* Create the .note section. */ 10218 note_secp = subseg_new (".note", 0); 10219 bfd_set_section_flags (stdoutput, 10220 note_secp, 10221 SEC_HAS_CONTENTS | SEC_READONLY); 10222 10223 /* Process the arch string. */ 10224 len = strlen (cpu_arch_name); 10225 10226 i_note.namesz = len + 1; 10227 i_note.descsz = 0; 10228 i_note.type = NT_ARCH; 10229 p = frag_more (sizeof (e_note.namesz)); 10230 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); 10231 p = frag_more (sizeof (e_note.descsz)); 10232 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); 10233 p = frag_more (sizeof (e_note.type)); 10234 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); 10235 p = frag_more (len + 1); 10236 strcpy (p, cpu_arch_name); 10237 10238 frag_align (2, 0, 0); 10239 10240 subseg_set (seg, subseg); 10241 } 10242 } 10243 #endif 10244 10245 symbolS * 10247 md_undefined_symbol (char *name) 10248 { 10249 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 10250 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 10251 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 10252 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 10253 { 10254 if (!GOT_symbol) 10255 { 10256 if (symbol_find (name)) 10257 as_bad (_("GOT already in symbol table")); 10258 GOT_symbol = symbol_new (name, undefined_section, 10259 (valueT) 0, &zero_address_frag); 10260 }; 10261 return GOT_symbol; 10262 } 10263 return 0; 10264 } 10265 10266 /* Round up a section size to the appropriate boundary. */ 10267 10268 valueT 10269 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 10270 { 10271 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 10272 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 10273 { 10274 /* For a.out, force the section size to be aligned. If we don't do 10275 this, BFD will align it for us, but it will not write out the 10276 final bytes of the section. This may be a bug in BFD, but it is 10277 easier to fix it here since that is how the other a.out targets 10278 work. */ 10279 int align; 10280 10281 align = bfd_get_section_alignment (stdoutput, segment); 10282 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 10283 } 10284 #endif 10285 10286 return size; 10287 } 10288 10289 /* On the i386, PC-relative offsets are relative to the start of the 10290 next instruction. That is, the address of the offset, plus its 10291 size, since the offset is always the last part of the insn. */ 10292 10293 long 10294 md_pcrel_from (fixS *fixP) 10295 { 10296 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 10297 } 10298 10299 #ifndef I386COFF 10300 10301 static void 10302 s_bss (int ignore ATTRIBUTE_UNUSED) 10303 { 10304 int temp; 10305 10306 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10307 if (IS_ELF) 10308 obj_elf_section_change_hook (); 10309 #endif 10310 temp = get_absolute_expression (); 10311 subseg_set (bss_section, (subsegT) temp); 10312 demand_empty_rest_of_line (); 10313 } 10314 10315 #endif 10316 10317 void 10318 i386_validate_fix (fixS *fixp) 10319 { 10320 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) 10321 { 10322 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 10323 { 10324 if (!object_64bit) 10325 abort (); 10326 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; 10327 } 10328 else 10329 { 10330 if (!object_64bit) 10331 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 10332 else 10333 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; 10334 } 10335 fixp->fx_subsy = 0; 10336 } 10337 } 10338 10339 arelent * 10340 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 10341 { 10342 arelent *rel; 10343 bfd_reloc_code_real_type code; 10344 10345 switch (fixp->fx_r_type) 10346 { 10347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10348 case BFD_RELOC_SIZE32: 10349 case BFD_RELOC_SIZE64: 10350 if (S_IS_DEFINED (fixp->fx_addsy) 10351 && !S_IS_EXTERNAL (fixp->fx_addsy)) 10352 { 10353 /* Resolve size relocation against local symbol to size of 10354 the symbol plus addend. */ 10355 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; 10356 if (fixp->fx_r_type == BFD_RELOC_SIZE32 10357 && !fits_in_unsigned_long (value)) 10358 as_bad_where (fixp->fx_file, fixp->fx_line, 10359 _("symbol size computation overflow")); 10360 fixp->fx_addsy = NULL; 10361 fixp->fx_subsy = NULL; 10362 md_apply_fix (fixp, (valueT *) &value, NULL); 10363 return NULL; 10364 } 10365 #endif 10366 10367 case BFD_RELOC_X86_64_PLT32: 10368 case BFD_RELOC_X86_64_PLT32_BND: 10369 case BFD_RELOC_X86_64_GOT32: 10370 case BFD_RELOC_X86_64_GOTPCREL: 10371 case BFD_RELOC_386_PLT32: 10372 case BFD_RELOC_386_GOT32: 10373 case BFD_RELOC_386_GOTOFF: 10374 case BFD_RELOC_386_GOTPC: 10375 case BFD_RELOC_386_TLS_GD: 10376 case BFD_RELOC_386_TLS_LDM: 10377 case BFD_RELOC_386_TLS_LDO_32: 10378 case BFD_RELOC_386_TLS_IE_32: 10379 case BFD_RELOC_386_TLS_IE: 10380 case BFD_RELOC_386_TLS_GOTIE: 10381 case BFD_RELOC_386_TLS_LE_32: 10382 case BFD_RELOC_386_TLS_LE: 10383 case BFD_RELOC_386_TLS_GOTDESC: 10384 case BFD_RELOC_386_TLS_DESC_CALL: 10385 case BFD_RELOC_X86_64_TLSGD: 10386 case BFD_RELOC_X86_64_TLSLD: 10387 case BFD_RELOC_X86_64_DTPOFF32: 10388 case BFD_RELOC_X86_64_DTPOFF64: 10389 case BFD_RELOC_X86_64_GOTTPOFF: 10390 case BFD_RELOC_X86_64_TPOFF32: 10391 case BFD_RELOC_X86_64_TPOFF64: 10392 case BFD_RELOC_X86_64_GOTOFF64: 10393 case BFD_RELOC_X86_64_GOTPC32: 10394 case BFD_RELOC_X86_64_GOT64: 10395 case BFD_RELOC_X86_64_GOTPCREL64: 10396 case BFD_RELOC_X86_64_GOTPC64: 10397 case BFD_RELOC_X86_64_GOTPLT64: 10398 case BFD_RELOC_X86_64_PLTOFF64: 10399 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 10400 case BFD_RELOC_X86_64_TLSDESC_CALL: 10401 case BFD_RELOC_RVA: 10402 case BFD_RELOC_VTABLE_ENTRY: 10403 case BFD_RELOC_VTABLE_INHERIT: 10404 #ifdef TE_PE 10405 case BFD_RELOC_32_SECREL: 10406 #endif 10407 code = fixp->fx_r_type; 10408 break; 10409 case BFD_RELOC_X86_64_32S: 10410 if (!fixp->fx_pcrel) 10411 { 10412 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ 10413 code = fixp->fx_r_type; 10414 break; 10415 } 10416 default: 10417 if (fixp->fx_pcrel) 10418 { 10419 switch (fixp->fx_size) 10420 { 10421 default: 10422 as_bad_where (fixp->fx_file, fixp->fx_line, 10423 _("can not do %d byte pc-relative relocation"), 10424 fixp->fx_size); 10425 code = BFD_RELOC_32_PCREL; 10426 break; 10427 case 1: code = BFD_RELOC_8_PCREL; break; 10428 case 2: code = BFD_RELOC_16_PCREL; break; 10429 case 4: 10430 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND 10431 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL); 10432 break; 10433 #ifdef BFD64 10434 case 8: code = BFD_RELOC_64_PCREL; break; 10435 #endif 10436 } 10437 } 10438 else 10439 { 10440 switch (fixp->fx_size) 10441 { 10442 default: 10443 as_bad_where (fixp->fx_file, fixp->fx_line, 10444 _("can not do %d byte relocation"), 10445 fixp->fx_size); 10446 code = BFD_RELOC_32; 10447 break; 10448 case 1: code = BFD_RELOC_8; break; 10449 case 2: code = BFD_RELOC_16; break; 10450 case 4: code = BFD_RELOC_32; break; 10451 #ifdef BFD64 10452 case 8: code = BFD_RELOC_64; break; 10453 #endif 10454 } 10455 } 10456 break; 10457 } 10458 10459 if ((code == BFD_RELOC_32 10460 || code == BFD_RELOC_32_PCREL 10461 || code == BFD_RELOC_X86_64_32S) 10462 && GOT_symbol 10463 && fixp->fx_addsy == GOT_symbol) 10464 { 10465 if (!object_64bit) 10466 code = BFD_RELOC_386_GOTPC; 10467 else 10468 code = BFD_RELOC_X86_64_GOTPC32; 10469 } 10470 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) 10471 && GOT_symbol 10472 && fixp->fx_addsy == GOT_symbol) 10473 { 10474 code = BFD_RELOC_X86_64_GOTPC64; 10475 } 10476 10477 rel = (arelent *) xmalloc (sizeof (arelent)); 10478 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 10479 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 10480 10481 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 10482 10483 if (!use_rela_relocations) 10484 { 10485 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 10486 vtable entry to be used in the relocation's section offset. */ 10487 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 10488 rel->address = fixp->fx_offset; 10489 #if defined (OBJ_COFF) && defined (TE_PE) 10490 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) 10491 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); 10492 else 10493 #endif 10494 rel->addend = 0; 10495 } 10496 /* Use the rela in 64bit mode. */ 10497 else 10498 { 10499 if (disallow_64bit_reloc) 10500 switch (code) 10501 { 10502 case BFD_RELOC_X86_64_DTPOFF64: 10503 case BFD_RELOC_X86_64_TPOFF64: 10504 case BFD_RELOC_64_PCREL: 10505 case BFD_RELOC_X86_64_GOTOFF64: 10506 case BFD_RELOC_X86_64_GOT64: 10507 case BFD_RELOC_X86_64_GOTPCREL64: 10508 case BFD_RELOC_X86_64_GOTPC64: 10509 case BFD_RELOC_X86_64_GOTPLT64: 10510 case BFD_RELOC_X86_64_PLTOFF64: 10511 as_bad_where (fixp->fx_file, fixp->fx_line, 10512 _("cannot represent relocation type %s in x32 mode"), 10513 bfd_get_reloc_code_name (code)); 10514 break; 10515 default: 10516 break; 10517 } 10518 10519 if (!fixp->fx_pcrel) 10520 rel->addend = fixp->fx_offset; 10521 else 10522 switch (code) 10523 { 10524 case BFD_RELOC_X86_64_PLT32: 10525 case BFD_RELOC_X86_64_PLT32_BND: 10526 case BFD_RELOC_X86_64_GOT32: 10527 case BFD_RELOC_X86_64_GOTPCREL: 10528 case BFD_RELOC_X86_64_TLSGD: 10529 case BFD_RELOC_X86_64_TLSLD: 10530 case BFD_RELOC_X86_64_GOTTPOFF: 10531 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 10532 case BFD_RELOC_X86_64_TLSDESC_CALL: 10533 rel->addend = fixp->fx_offset - fixp->fx_size; 10534 break; 10535 default: 10536 rel->addend = (section->vma 10537 - fixp->fx_size 10538 + fixp->fx_addnumber 10539 + md_pcrel_from (fixp)); 10540 break; 10541 } 10542 } 10543 10544 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 10545 if (rel->howto == NULL) 10546 { 10547 as_bad_where (fixp->fx_file, fixp->fx_line, 10548 _("cannot represent relocation type %s"), 10549 bfd_get_reloc_code_name (code)); 10550 /* Set howto to a garbage value so that we can keep going. */ 10551 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 10552 gas_assert (rel->howto != NULL); 10553 } 10554 10555 return rel; 10556 } 10557 10558 #include "tc-i386-intel.c" 10559 10560 void 10561 tc_x86_parse_to_dw2regnum (expressionS *exp) 10562 { 10563 int saved_naked_reg; 10564 char saved_register_dot; 10565 10566 saved_naked_reg = allow_naked_reg; 10567 allow_naked_reg = 1; 10568 saved_register_dot = register_chars['.']; 10569 register_chars['.'] = '.'; 10570 allow_pseudo_reg = 1; 10571 expression_and_evaluate (exp); 10572 allow_pseudo_reg = 0; 10573 register_chars['.'] = saved_register_dot; 10574 allow_naked_reg = saved_naked_reg; 10575 10576 if (exp->X_op == O_register && exp->X_add_number >= 0) 10577 { 10578 if ((addressT) exp->X_add_number < i386_regtab_size) 10579 { 10580 exp->X_op = O_constant; 10581 exp->X_add_number = i386_regtab[exp->X_add_number] 10582 .dw2_regnum[flag_code >> 1]; 10583 } 10584 else 10585 exp->X_op = O_illegal; 10586 } 10587 } 10588 10589 void 10590 tc_x86_frame_initial_instructions (void) 10591 { 10592 static unsigned int sp_regno[2]; 10593 10594 if (!sp_regno[flag_code >> 1]) 10595 { 10596 char *saved_input = input_line_pointer; 10597 char sp[][4] = {"esp", "rsp"}; 10598 expressionS exp; 10599 10600 input_line_pointer = sp[flag_code >> 1]; 10601 tc_x86_parse_to_dw2regnum (&exp); 10602 gas_assert (exp.X_op == O_constant); 10603 sp_regno[flag_code >> 1] = exp.X_add_number; 10604 input_line_pointer = saved_input; 10605 } 10606 10607 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); 10608 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); 10609 } 10610 10611 int 10612 x86_dwarf2_addr_size (void) 10613 { 10614 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 10615 if (x86_elf_abi == X86_64_X32_ABI) 10616 return 4; 10617 #endif 10618 return bfd_arch_bits_per_address (stdoutput) / 8; 10619 } 10620 10621 int 10622 i386_elf_section_type (const char *str, size_t len) 10623 { 10624 if (flag_code == CODE_64BIT 10625 && len == sizeof ("unwind") - 1 10626 && strncmp (str, "unwind", 6) == 0) 10627 return SHT_X86_64_UNWIND; 10628 10629 return -1; 10630 } 10631 10632 #ifdef TE_SOLARIS 10633 void 10634 i386_solaris_fix_up_eh_frame (segT sec) 10635 { 10636 if (flag_code == CODE_64BIT) 10637 elf_section_type (sec) = SHT_X86_64_UNWIND; 10638 } 10639 #endif 10640 10641 #ifdef TE_PE 10642 void 10643 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 10644 { 10645 expressionS exp; 10646 10647 exp.X_op = O_secrel; 10648 exp.X_add_symbol = symbol; 10649 exp.X_add_number = 0; 10650 emit_expr (&exp, size); 10651 } 10652 #endif 10653 10654 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 10655 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ 10656 10657 bfd_vma 10658 x86_64_section_letter (int letter, char **ptr_msg) 10659 { 10660 if (flag_code == CODE_64BIT) 10661 { 10662 if (letter == 'l') 10663 return SHF_X86_64_LARGE; 10664 10665 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); 10666 } 10667 else 10668 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); 10669 return -1; 10670 } 10671 10672 bfd_vma 10673 x86_64_section_word (char *str, size_t len) 10674 { 10675 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) 10676 return SHF_X86_64_LARGE; 10677 10678 return -1; 10679 } 10680 10681 static void 10682 handle_large_common (int small ATTRIBUTE_UNUSED) 10683 { 10684 if (flag_code != CODE_64BIT) 10685 { 10686 s_comm_internal (0, elf_common_parse); 10687 as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); 10688 } 10689 else 10690 { 10691 static segT lbss_section; 10692 asection *saved_com_section_ptr = elf_com_section_ptr; 10693 asection *saved_bss_section = bss_section; 10694 10695 if (lbss_section == NULL) 10696 { 10697 flagword applicable; 10698 segT seg = now_seg; 10699 subsegT subseg = now_subseg; 10700 10701 /* The .lbss section is for local .largecomm symbols. */ 10702 lbss_section = subseg_new (".lbss", 0); 10703 applicable = bfd_applicable_section_flags (stdoutput); 10704 bfd_set_section_flags (stdoutput, lbss_section, 10705 applicable & SEC_ALLOC); 10706 seg_info (lbss_section)->bss = 1; 10707 10708 subseg_set (seg, subseg); 10709 } 10710 10711 elf_com_section_ptr = &_bfd_elf_large_com_section; 10712 bss_section = lbss_section; 10713 10714 s_comm_internal (0, elf_common_parse); 10715 10716 elf_com_section_ptr = saved_com_section_ptr; 10717 bss_section = saved_bss_section; 10718 } 10719 } 10720 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 10721
