| /external/syslinux/com32/modules/ |
| kontron_wdt.c | 141 uint8_t index_reg = ioread8(pld.io_index); local
142 if ((index_reg == 0xff) && (ioread8(pld.io_data) == 0xff)) {
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-i386.c | 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
314 const reg_entry *index_reg; member in struct:_i386_insn
[all...] |
| tc-i386-intel.c | 971 i.index_reg = intel_state.base;
976 i.index_reg = intel_state.index;
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_asm.h | 249 unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */ member in struct:r600_bytecode
|
| eg_asm.c | 162 alu.src[0].sel = bc->index_reg[id];
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| /toolchain/binutils/binutils-2.25/include/opcode/ |
| pyr.h | 37 unsigned int index_reg :6; member in struct:pyr_insn_format
|
| /external/mesa3d/src/mesa/program/ |
| ir_to_mesa.cpp | 1515 src_reg index_reg; local
[all...] |
| /art/runtime/arch/mips/ |
| quick_entrypoints_mips.S | 861 .macro LOAD_WORD_TO_REG reg, next_arg, index_reg, label
864 addiu $\index_reg, 16
868 .macro LOAD_LONG_TO_REG reg1, reg2, next_arg, index_reg, next_index, label
872 li $\index_reg, \next_index
876 .macro LOAD_FLOAT_TO_REG reg, next_arg, index_reg, label
879 addiu $\index_reg, 16
884 // LDu expands into 3 instructions for 64-bit FPU, so index_reg cannot be updated here.
885 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, label
894 // LDu expands into 2 instructions for 32-bit FPU, so index_reg is updated here.
895 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, labe
[all...] |
| /art/compiler/optimizing/ |
| code_generator_mips64.cc | 841 GpuRegister index_reg = index_.AsRegister<GpuRegister>(); variable
[all...] |
| code_generator_vector_mips.cc | 878 Register index_reg = index.AsRegister<Register>(); local
880 __ Lsa(AT, index_reg, base, scale);
882 __ Addu(AT, base, index_reg);
[all...] |
| code_generator_vector_mips64.cc | 882 GpuRegister index_reg = index.AsRegister<GpuRegister>(); local
884 __ Dlsa(AT, index_reg, base, scale);
886 __ Daddu(AT, base, index_reg);
[all...] |
| code_generator_arm64.cc | 1229 Register index_reg = RegisterFrom(index_, Primitive::kPrimInt); variable
2691 Register index_reg = InputRegisterAt(instruction, 0); local
2696 __ Add(OutputRegister(instruction), index_reg, offset); local
[all...] |
| code_generator_mips.cc | 901 Register index_reg = index_.AsRegister<Register>(); variable
2644 Register index_reg = index.AsRegister<Register>(); local
6634 Register index_reg = index.IsRegisterPair() local
[all...] |
| code_generator_arm_vixl.cc | 1294 vixl32::Register index_reg = RegisterFrom(index_); variable
8765 vixl32::Register index_reg = RegisterFrom(index, Primitive::kPrimInt); local
8935 vixl32::Register index_reg = index.IsRegisterPair() local
[all...] |
| code_generator_x86.cc | 746 Register index_reg = index_.AsRegister<Register>(); variable
747 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_reg));
748 if (codegen->IsCoreCalleeSaveRegister(index_reg)) {
749 // We are about to change the value of `index_reg` (see the
759 // register, `index_reg` _would_ eventually be saved onto
772 __ movl(free_reg, index_reg);
773 index_reg = free_reg;
774 index = Location::RegisterLocation(index_reg);
781 // Shifting the index value contained in `index_reg` by the scale
785 __ shll(index_reg, Immediate(TIMES_4))
5660 Register index_reg = index_loc.AsRegister<Register>(); local
[all...] |
| code_generator_x86_64.cc | 769 Register index_reg = index_.AsRegister<CpuRegister>().AsRegister(); variable
770 DCHECK(locations->GetLiveRegisters()->ContainsCoreRegister(index_reg));
771 if (codegen->IsCoreCalleeSaveRegister(index_reg)) {
772 // We are about to change the value of `index_reg` (see the
782 // register, `index_reg` _would_ eventually be saved onto
5106 CpuRegister index_reg = index_loc.AsRegister<CpuRegister>(); local
[all...] |
| /external/vixl/src/aarch64/ |
| logic-aarch64.cc | 4359 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); local
4364 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); local
4379 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); local
4384 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); local
4399 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); local
4404 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); local
4419 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); local
4424 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); local
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_glsl_to_tgsi.cpp | 2087 st_src_reg index_reg = get_temp(glsl_type::uint_type); local
2688 st_src_reg index_reg; local
[all...] |
| /external/v8/src/interpreter/ |
| interpreter.cc | 3218 Node* index_reg = __ BytecodeOperandReg(1); local
3262 Node* index_reg = __ BytecodeOperandReg(0); local
3289 Node* index_reg = __ BytecodeOperandReg(0); local
[all...] |
| /art/compiler/linker/arm/ |
| relative_patcher_thumb2_test.cc | [all...] |
| /art/compiler/linker/arm64/ |
| relative_patcher_arm64_test.cc | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_visitor.cpp | 787 dst_reg index_reg = retype(byte_offset(dst_reg(header), REG_SIZE), local
789 pull = MOV(writemask(index_reg, WRITEMASK_X), offset_reg);
[all...] |
| brw_vec4_generator.cpp | 825 struct brw_reg index_reg = brw_vec1_grf( local
829 retype(index_reg, BRW_REGISTER_TYPE_UD));
[all...] |
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | [all...] |
| /art/runtime/arch/arm64/ |
| quick_entrypoints_arm64.S | [all...] |
