| /external/v8/src/x64/ |
| codegen-x64.h | 39 Register base_reg,
44 : base_reg_(base_reg),
52 Register base_reg,
57 : base_reg_(base_reg),
65 Register base_reg,
70 : base_reg_(base_reg),
|
| code-stubs-x64.cc | 2992 Register base_reg = r15; local
[all...] |
| disasm-x64.cc | 347 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| /art/compiler/linker/arm/ |
| relative_patcher_thumb2.h | 38 static uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg,
41 CheckValidReg(base_reg);
43 DCHECK(!narrow || base_reg < 8u) << base_reg;
47 BakerReadBarrierFirstRegField::Encode(base_reg) |
52 static uint32_t EncodeBakerReadBarrierArrayData(uint32_t base_reg) {
53 CheckValidReg(base_reg);
55 BakerReadBarrierFirstRegField::Encode(base_reg) |
|
| relative_patcher_thumb2.cc | 120 // LDR (immediate), encoding T3, with correct base_reg.
122 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
123 CHECK_EQ(next_insn & 0xffff0000u, 0xf8d00000u | (base_reg << 16));
127 // LDR (immediate), encoding T1, with correct base_reg.
129 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
130 CHECK_EQ(next_insn & 0xf838u, 0x6800u | (base_reg << 3));
137 // LDR (register) with correct base_reg, S=1 and option=011 (LDR Wt, [Xn, Xm, LSL #2]).
139 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
140 CHECK_EQ(next_insn & 0xffff0ff0u, 0xf8500020u | (base_reg << 16));
181 vixl::aarch32::Register base_reg,
[all...] |
| relative_patcher_thumb2_test.cc | 229 std::vector<uint8_t> CompileBakerOffsetThunk(uint32_t base_reg,
233 0u, Thumb2RelativePatcher::EncodeBakerReadBarrierFieldData(base_reg, holder_reg, narrow));
238 std::vector<uint8_t> CompileBakerArrayThunk(uint32_t base_reg) {
240 0u, Thumb2RelativePatcher::EncodeBakerReadBarrierArrayData(base_reg));
588 for (uint32_t base_reg : valid_regs) {
590 uint32_t ldr = kLdrWInsn | offset | (base_reg << 16) | (ref_reg << 12);
595 base_reg, holder_reg, /* narrow */ false);
608 for (uint32_t base_reg : valid_regs) {
612 uint32_t ldr = kLdrWInsn | offset | (base_reg << 16) | (ref_reg << 12);
619 CompileBakerOffsetThunk(base_reg, holder_reg, /* narrow */ false)
[all...] |
| /art/compiler/linker/arm64/ |
| relative_patcher_arm64.h | 35 static uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg, uint32_t holder_reg) {
36 CheckValidReg(base_reg);
39 BakerReadBarrierFirstRegField::Encode(base_reg) |
43 static uint32_t EncodeBakerReadBarrierArrayData(uint32_t base_reg) {
44 CheckValidReg(base_reg);
46 BakerReadBarrierFirstRegField::Encode(base_reg) |
|
| relative_patcher_arm64.cc | 317 // LDR (immediate) with correct base_reg.
319 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
320 CHECK_EQ(next_insn & 0xffc003e0u, 0xb9400000u | (base_reg << 5));
326 // LDR (register) with the correct base_reg, size=10 (32-bit), option=011 (extend = LSL),
329 const uint32_t base_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); local
330 CHECK_EQ(next_insn & 0xffe0ffe0u, 0xb8607800u | (base_reg << 5));
358 vixl::aarch64::Register base_reg,
379 __ Add(base_reg, base_reg, Operand(ip0, LSR, 32));
409 auto base_reg local
445 auto base_reg = local
[all...] |
| relative_patcher_arm64_test.cc | 475 std::vector<uint8_t> CompileBakerOffsetThunk(uint32_t base_reg, uint32_t holder_reg) {
477 0u, Arm64RelativePatcher::EncodeBakerReadBarrierFieldData(base_reg, holder_reg));
482 std::vector<uint8_t> CompileBakerArrayThunk(uint32_t base_reg) {
484 0u, Arm64RelativePatcher::EncodeBakerReadBarrierArrayData(base_reg));
[all...] |
| /external/mesa3d/src/util/ |
| register_allocate.h | 54 unsigned int base_reg, unsigned int reg);
|
| register_allocate.c | 257 * Adds a conflict between base_reg and reg, and also between reg and
258 * anything that base_reg conflicts with.
266 unsigned int base_reg, unsigned int reg)
270 ra_add_reg_conflict(regs, reg, base_reg);
272 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
273 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| metag-dis.c | 472 const char *base_reg; local
481 base_reg = lookup_reg_name (base_unit, base_no);
491 snprintf (buf, buf_size, "[%s]", base_reg);
498 snprintf (buf, buf_size, "[%s++]", base_reg);
500 snprintf (buf, buf_size, "[++%s]", base_reg);
507 snprintf (buf, buf_size, "[%s--]", base_reg);
509 snprintf (buf, buf_size, "[--%s]", base_reg);
519 snprintf (buf, buf_size, "[%s+#%d++]", base_reg, offset);
521 snprintf (buf, buf_size, "[%s++#%d]", base_reg, offset);
524 snprintf (buf, buf_size, "[%s+#%d]", base_reg, offset)
552 const char *base_reg; local
582 const char *base_reg; local
598 const char *base_reg; local
614 const char *base_reg; local
909 const char *base_reg; local
2330 const char *base_reg = "?"; local
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Scripts/Ds5/ |
| cmd_load_symbols.py | 40 base_reg = re.compile("(.*)")
variable
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-metag.c | 186 const metag_reg *base_reg; member in struct:__anon115747
736 if (regs[0]->unit != addr->base_reg->unit)
768 addr->base_reg = regs[0];
1063 (regs[0]->unit == addr.base_reg->unit ||
1064 (size == 8 && is_unit_pair (regs[0], addr.base_reg))))
1087 if (!is_short_unit (addr.base_reg->unit))
1093 insn->bits |= ((addr.base_reg->no << 14) |
1094 ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5));
1188 if (!is_short_unit (addr.base_reg->unit))
1194 if (addr.base_reg->no > 1
[all...] |
| tc-i386.c | 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
313 const reg_entry *base_reg; member in struct:_i386_insn
[all...] |
| tc-tic6x.c | 1143 tic6x_register base_reg; member in struct:__anon115807
1425 tic6x_register base_reg; local
[all...] |
| tc-i386-intel.c | 970 i.base_reg = intel_state.index;
975 i.base_reg = intel_state.base;
|
| tc-arm.c | 1748 int base_reg; local
1893 mask >>= base_reg; local
1951 int base_reg = -1; local
8501 int base_reg = inst.operands[0].reg; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_reg_allocate.cpp | 138 for (int base_reg = j;
139 base_reg < j + class_sizes[i];
140 base_reg++) {
141 ra_add_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg);
|
| brw_fs_reg_allocate.cpp | 217 for (int base_reg = j;
218 base_reg < j + (class_sizes[i] + 1) / 2;
219 base_reg++) {
220 ra_add_reg_conflict(regs, base_reg, reg);
231 for (int base_reg = j;
232 base_reg < j + class_sizes[i];
233 base_reg++) {
234 ra_add_reg_conflict(regs, base_reg, reg);
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 426 uint32_t base_reg; local
439 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
440 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
442 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
448 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /art/compiler/optimizing/ |
| code_generator_mips64.cc | [all...] |
| code_generator_mips.cc | 2840 Register base_reg = index.IsConstant() ? obj : TMP; local
7199 Register base_reg = (invoke->HasPcRelativeMethodLoadKind() && !is_r6) local
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | [all...] |
| assembler_mips.cc | 3789 branches_.emplace_back(IsR6(), buffer_.Size(), dest_reg, base_reg, Branch::kLabel); local
3804 branches_.emplace_back(IsR6(), buffer_.Size(), dest_reg, base_reg, Branch::kLiteral); local
[all...] |
