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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
bitfield-bfm.s 50 .macro op_bfm signed, reg, immr, imms
51 \signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15
54 .macro ext2bfm signed, reg, imms
55 op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms
59 .macro sr2bfm signed, reg, shift, imms
60 op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms
66 op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)"
68 op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)
    [all...]
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_dataflow_swizzles.c 106 float imms[4] = {0.0f, 0.0f, 0.0f, 0.0f}; local
389 imms[new_swz] = 0.0f;
393 imms[new_swz] = -0.5f;
395 imms[new_swz] = 0.5f;
400 imms[new_swz] = -1.0f;
402 imms[new_swz] = 1.0f;
406 imms[new_swz] = rc_get_constant_value(c, reg->Index,
412 imms);
  /frameworks/base/packages/SettingsLib/src/com/android/settingslib/inputmethod/
InputMethodSettingValuesWrapper.java 85 final List<InputMethodInfo> imms = mImm.getInputMethodList(); local
86 mMethodList.addAll(imms);
87 for (InputMethodInfo imi : imms) {
  /art/compiler/utils/
assembler_test.h 155 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
159 for (int64_t imm : imms) {
208 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
213 for (int64_t imm : imms) {
265 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
267 WarnOnCombinations(reg1_registers.size() * reg2_registers.size() * imms.size());
272 for (int64_t imm : imms) {
317 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
320 for (int64_t imm : imms) {
518 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes, as_uint) local
987 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); local
1089 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); local
    [all...]
  /external/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AddressingModes.h 212 /// the form N:immr:imms.
290 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
293 // Extract the N, imms, and immr fields.
296 unsigned imms = val & 0x3f; local
299 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
303 unsigned S = imms & (size - 1);
318 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
322 // Extract the N and imms fields needed for checking
324 unsigned imms = val & 0x3f; local
    [all...]
  /system/core/libpixelflinger/codeflinger/
Arm64Assembler.cpp     [all...]
Arm64Assembler.h 236 uint32_t immr, uint32_t imms);
238 uint32_t immr, uint32_t imms);
240 uint32_t immr, uint32_t imms);
  /external/mesa3d/src/gallium/auxiliary/translate/
translate_sse.c 473 unsigned imms[2] = { 0, 0x3f800000 }; local
682 imms[swizzle[0] - PIPE_SWIZZLE_0]);
692 imms[swizzle[1] - PIPE_SWIZZLE_0]);
710 imms[swizzle[2] - PIPE_SWIZZLE_0]);
720 imms[swizzle[3] - PIPE_SWIZZLE_0]);
742 unsigned imms[2] = { 0, 1 }; local
798 imms[1] =
826 imms[swizzle[1] - PIPE_SWIZZLE_0]);
833 (imms[swizzle[1] - PIPE_SWIZZLE_0] << 16) |
834 imms[swizzle[0] - PIPE_SWIZZLE_0])
    [all...]
  /toolchain/binutils/binutils-2.25/opcodes/
aarch64-dis.c 565 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
728 /* value is N:immr:imms. */
1521 int64_t imms, val; local
1557 int64_t immr, imms; local
1584 int64_t immr, imms, val; local
1612 int64_t imms = inst->operands[3].imm.value; local
    [all...]
  /external/mesa3d/src/gallium/drivers/nouveau/codegen/
nv50_ir_build_util.cpp 47 memset(imms, 0, sizeof(imms));
59 while (imms[pos])
61 imms[pos] = imm;
361 while (imms[pos] && imms[pos]->reg.data.u32 != u)
364 ImmediateValue *imm = imms[pos];
nv50_ir_build_util.h 192 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; member in class:nv50_ir::BuildUtil
  /external/mesa3d/src/gallium/drivers/radeonsi/
si_shader_internal.h 94 LLVMValueRef *imms; member in struct:si_shader_context
si_shader_tgsi_setup.c 698 ctx->imms[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle],
701 ctx->imms[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle + 1],
705 return LLVMConstBitCast(ctx->imms[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle], ctype);
    [all...]
  /external/llvm/lib/Target/AArch64/InstPrinter/
AArch64InstPrinter.cpp 114 int64_t imms = Op3.getImm(); local
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
117 shift = 31 - imms;
118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
119 ((imms + 1 == immr))) {
121 shift = 63 - imms;
122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
125 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
128 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
    [all...]
  /external/v8/src/arm64/
assembler-arm64-inl.h 1026 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
1027 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1028 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1030 return imms << ImmS_offset;
1043 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
1045 DCHECK(is_uint6(imms));
1046 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
1048 return imms << ImmSetBits_offset;
    [all...]
assembler-arm64.h     [all...]
assembler-arm64.cc     [all...]
  /art/compiler/utils/mips64/
assembler_mips64_test.cc 1325 std::vector<int64_t> imms = CreateImmediateValuesBits(\/* imm_bits *\/ 16, \/* as_uint *\/ true); local
2707 const uint16_t imms[] = { local
    [all...]
  /toolchain/binutils/binutils-2.25/gas/config/
tc-i386-intel.c 769 i.op[this_operand].imms = expP;
843 if (i386_finalize_immediate (exp_seg, i.op[0].imms,
849 i.op[this_operand].imms = expP;
996 i.op[this_operand].imms = expP;
tc-i386.c 248 expressionS *imms; member in union:i386_op
    [all...]
  /external/vixl/src/aarch64/
assembler-aarch64.h 687 unsigned imms);
693 unsigned imms);
699 unsigned imms);
    [all...]
macro-assembler-aarch64.h     [all...]
assembler-aarch64.cc 594 unsigned imms) {
598 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
605 unsigned imms) {
609 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
616 unsigned imms) {
620 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
631 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.GetSizeInBits()) | Rn(rn)
    [all...]
  /external/mesa3d/src/gallium/auxiliary/gallivm/
lp_bld_tgsi_soa.c 3054 LLVMValueRef imms[4]; local
    [all...]
  /frameworks/base/services/core/java/com/android/server/
InputMethodManagerService.java     [all...]

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