1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __GIC_V2_H__ 32 #define __GIC_V2_H__ 33 34 35 #define GIC400_NUM_SPIS 480 36 #define MAX_PPIS 14 37 #define MAX_SGIS 16 38 39 #define MIN_SGI_ID 0 40 #define MIN_PPI_ID 16 41 #define MIN_SPI_ID 32 42 43 #define GRP0 0 44 #define GRP1 1 45 #define GIC_PRI_MASK 0xff 46 #define GIC_HIGHEST_SEC_PRIORITY 0 47 #define GIC_LOWEST_SEC_PRIORITY 127 48 #define GIC_HIGHEST_NS_PRIORITY 128 49 #define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ 50 #define GIC_SPURIOUS_INTERRUPT 1023 51 #define GIC_TARGET_CPU_MASK 0xff 52 53 #define ENABLE_GRP0 (1 << 0) 54 #define ENABLE_GRP1 (1 << 1) 55 56 /* Distributor interface definitions */ 57 #define GICD_CTLR 0x0 58 #define GICD_TYPER 0x4 59 #define GICD_IGROUPR 0x80 60 #define GICD_ISENABLER 0x100 61 #define GICD_ICENABLER 0x180 62 #define GICD_ISPENDR 0x200 63 #define GICD_ICPENDR 0x280 64 #define GICD_ISACTIVER 0x300 65 #define GICD_ICACTIVER 0x380 66 #define GICD_IPRIORITYR 0x400 67 #define GICD_ITARGETSR 0x800 68 #define GICD_ICFGR 0xC00 69 #define GICD_SGIR 0xF00 70 #define GICD_CPENDSGIR 0xF10 71 #define GICD_SPENDSGIR 0xF20 72 73 #define IGROUPR_SHIFT 5 74 #define ISENABLER_SHIFT 5 75 #define ICENABLER_SHIFT ISENABLER_SHIFT 76 #define ISPENDR_SHIFT 5 77 #define ICPENDR_SHIFT ISPENDR_SHIFT 78 #define ISACTIVER_SHIFT 5 79 #define ICACTIVER_SHIFT ISACTIVER_SHIFT 80 #define IPRIORITYR_SHIFT 2 81 #define ITARGETSR_SHIFT 2 82 #define ICFGR_SHIFT 4 83 #define CPENDSGIR_SHIFT 2 84 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 85 86 /* GICD_TYPER bit definitions */ 87 #define IT_LINES_NO_MASK 0x1f 88 89 /* Physical CPU Interface registers */ 90 #define GICC_CTLR 0x0 91 #define GICC_PMR 0x4 92 #define GICC_BPR 0x8 93 #define GICC_IAR 0xC 94 #define GICC_EOIR 0x10 95 #define GICC_RPR 0x14 96 #define GICC_HPPIR 0x18 97 #define GICC_AHPPIR 0x28 98 #define GICC_IIDR 0xFC 99 #define GICC_DIR 0x1000 100 #define GICC_PRIODROP GICC_EOIR 101 102 /* GICC_CTLR bit definitions */ 103 #define EOI_MODE_NS (1 << 10) 104 #define EOI_MODE_S (1 << 9) 105 #define IRQ_BYP_DIS_GRP1 (1 << 8) 106 #define FIQ_BYP_DIS_GRP1 (1 << 7) 107 #define IRQ_BYP_DIS_GRP0 (1 << 6) 108 #define FIQ_BYP_DIS_GRP0 (1 << 5) 109 #define CBPR (1 << 4) 110 #define FIQ_EN (1 << 3) 111 #define ACK_CTL (1 << 2) 112 113 /* GICC_IIDR bit masks and shifts */ 114 #define GICC_IIDR_PID_SHIFT 20 115 #define GICC_IIDR_ARCH_SHIFT 16 116 #define GICC_IIDR_REV_SHIFT 12 117 #define GICC_IIDR_IMP_SHIFT 0 118 119 #define GICC_IIDR_PID_MASK 0xfff 120 #define GICC_IIDR_ARCH_MASK 0xf 121 #define GICC_IIDR_REV_MASK 0xf 122 #define GICC_IIDR_IMP_MASK 0xfff 123 124 /* HYP view virtual CPU Interface registers */ 125 #define GICH_CTL 0x0 126 #define GICH_VTR 0x4 127 #define GICH_ELRSR0 0x30 128 #define GICH_ELRSR1 0x34 129 #define GICH_APR0 0xF0 130 #define GICH_LR_BASE 0x100 131 132 /* Virtual CPU Interface registers */ 133 #define GICV_CTL 0x0 134 #define GICV_PRIMASK 0x4 135 #define GICV_BP 0x8 136 #define GICV_INTACK 0xC 137 #define GICV_EOI 0x10 138 #define GICV_RUNNINGPRI 0x14 139 #define GICV_HIGHESTPEND 0x18 140 #define GICV_DEACTIVATE 0x1000 141 142 #ifndef __ASSEMBLY__ 143 144 #include <mmio.h> 145 146 147 /******************************************************************************* 148 * GIC Distributor function prototypes 149 ******************************************************************************/ 150 151 unsigned int gicd_read_igroupr(unsigned int, unsigned int); 152 unsigned int gicd_read_isenabler(unsigned int, unsigned int); 153 unsigned int gicd_read_icenabler(unsigned int, unsigned int); 154 unsigned int gicd_read_ispendr(unsigned int, unsigned int); 155 unsigned int gicd_read_icpendr(unsigned int, unsigned int); 156 unsigned int gicd_read_isactiver(unsigned int, unsigned int); 157 unsigned int gicd_read_icactiver(unsigned int, unsigned int); 158 unsigned int gicd_read_ipriorityr(unsigned int, unsigned int); 159 unsigned int gicd_read_itargetsr(unsigned int, unsigned int); 160 unsigned int gicd_read_icfgr(unsigned int, unsigned int); 161 unsigned int gicd_read_cpendsgir(unsigned int, unsigned int); 162 unsigned int gicd_read_spendsgir(unsigned int, unsigned int); 163 void gicd_write_igroupr(unsigned int, unsigned int, unsigned int); 164 void gicd_write_isenabler(unsigned int, unsigned int, unsigned int); 165 void gicd_write_icenabler(unsigned int, unsigned int, unsigned int); 166 void gicd_write_ispendr(unsigned int, unsigned int, unsigned int); 167 void gicd_write_icpendr(unsigned int, unsigned int, unsigned int); 168 void gicd_write_isactiver(unsigned int, unsigned int, unsigned int); 169 void gicd_write_icactiver(unsigned int, unsigned int, unsigned int); 170 void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int); 171 void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int); 172 void gicd_write_icfgr(unsigned int, unsigned int, unsigned int); 173 void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int); 174 void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int); 175 unsigned int gicd_get_igroupr(unsigned int, unsigned int); 176 void gicd_set_igroupr(unsigned int, unsigned int); 177 void gicd_clr_igroupr(unsigned int, unsigned int); 178 void gicd_set_isenabler(unsigned int, unsigned int); 179 void gicd_set_icenabler(unsigned int, unsigned int); 180 void gicd_set_ispendr(unsigned int, unsigned int); 181 void gicd_set_icpendr(unsigned int, unsigned int); 182 void gicd_set_isactiver(unsigned int, unsigned int); 183 void gicd_set_icactiver(unsigned int, unsigned int); 184 void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int); 185 void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int); 186 187 188 /******************************************************************************* 189 * GIC Distributor interface accessors for reading entire registers 190 ******************************************************************************/ 191 192 static inline unsigned int gicd_read_ctlr(unsigned int base) 193 { 194 return mmio_read_32(base + GICD_CTLR); 195 } 196 197 static inline unsigned int gicd_read_typer(unsigned int base) 198 { 199 return mmio_read_32(base + GICD_TYPER); 200 } 201 202 static inline unsigned int gicd_read_sgir(unsigned int base) 203 { 204 return mmio_read_32(base + GICD_SGIR); 205 } 206 207 208 /******************************************************************************* 209 * GIC Distributor interface accessors for writing entire registers 210 ******************************************************************************/ 211 212 static inline void gicd_write_ctlr(unsigned int base, unsigned int val) 213 { 214 mmio_write_32(base + GICD_CTLR, val); 215 } 216 217 static inline void gicd_write_sgir(unsigned int base, unsigned int val) 218 { 219 mmio_write_32(base + GICD_SGIR, val); 220 } 221 222 223 /******************************************************************************* 224 * GIC CPU interface accessors for reading entire registers 225 ******************************************************************************/ 226 227 static inline unsigned int gicc_read_ctlr(unsigned int base) 228 { 229 return mmio_read_32(base + GICC_CTLR); 230 } 231 232 static inline unsigned int gicc_read_pmr(unsigned int base) 233 { 234 return mmio_read_32(base + GICC_PMR); 235 } 236 237 static inline unsigned int gicc_read_BPR(unsigned int base) 238 { 239 return mmio_read_32(base + GICC_BPR); 240 } 241 242 static inline unsigned int gicc_read_IAR(unsigned int base) 243 { 244 return mmio_read_32(base + GICC_IAR); 245 } 246 247 static inline unsigned int gicc_read_EOIR(unsigned int base) 248 { 249 return mmio_read_32(base + GICC_EOIR); 250 } 251 252 static inline unsigned int gicc_read_hppir(unsigned int base) 253 { 254 return mmio_read_32(base + GICC_HPPIR); 255 } 256 257 static inline unsigned int gicc_read_ahppir(unsigned int base) 258 { 259 return mmio_read_32(base + GICC_AHPPIR); 260 } 261 262 static inline unsigned int gicc_read_dir(unsigned int base) 263 { 264 return mmio_read_32(base + GICC_DIR); 265 } 266 267 static inline unsigned int gicc_read_iidr(unsigned int base) 268 { 269 return mmio_read_32(base + GICC_IIDR); 270 } 271 272 273 /******************************************************************************* 274 * GIC CPU interface accessors for writing entire registers 275 ******************************************************************************/ 276 277 static inline void gicc_write_ctlr(unsigned int base, unsigned int val) 278 { 279 mmio_write_32(base + GICC_CTLR, val); 280 } 281 282 static inline void gicc_write_pmr(unsigned int base, unsigned int val) 283 { 284 mmio_write_32(base + GICC_PMR, val); 285 } 286 287 static inline void gicc_write_BPR(unsigned int base, unsigned int val) 288 { 289 mmio_write_32(base + GICC_BPR, val); 290 } 291 292 293 static inline void gicc_write_IAR(unsigned int base, unsigned int val) 294 { 295 mmio_write_32(base + GICC_IAR, val); 296 } 297 298 static inline void gicc_write_EOIR(unsigned int base, unsigned int val) 299 { 300 mmio_write_32(base + GICC_EOIR, val); 301 } 302 303 static inline void gicc_write_hppir(unsigned int base, unsigned int val) 304 { 305 mmio_write_32(base + GICC_HPPIR, val); 306 } 307 308 static inline void gicc_write_dir(unsigned int base, unsigned int val) 309 { 310 mmio_write_32(base + GICC_DIR, val); 311 } 312 313 /******************************************************************************* 314 * Prototype of function to map an interrupt type to the interrupt line used to 315 * signal it. 316 ******************************************************************************/ 317 uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type); 318 319 #endif /*__ASSEMBLY__*/ 320 321 #endif /* __GIC_V2_H__ */ 322
