| /external/v8/tools/clang/rewrite_to_chrome_style/tests/ |
| operators-expected.cc | 11 struct Op2 {};
13 inline bool operator==(const Op2&, const Op2) {
23 blink::Op2 a2, b2;
|
| operators-original.cc | 11 struct Op2 {};
13 inline bool operator==(const Op2&, const Op2) {
23 blink::Op2 a2, b2;
|
| /external/llvm/lib/IR/ |
| ProfileSummary.cpp | 134 ConstantAsMetadata *Op2 =
137 if (!Op0 || !Op1 || !Op2)
141 cast<ConstantInt>(Op2->getValue())->getZExtValue());
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 162 MCOperand Op2 = MI.getOperand(2);
163 assert(Op2.isImm() && "Second operand is not immediate.");
164 Encoding |= Op2.getImm() & 0xffff;
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyPeephole.cpp | 151 const auto &Op2 = MI.getOperand(2);
152 if (!Op2.isReg())
157 unsigned NewReg = Op2.getReg();
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| PTXInstPrinter.cpp | 143 const MCOperand &Op2 = MI->getOperand(OpNo+1);
145 if (Op2.getImm() == 0)
147 O << "+" << Op2.getImm();
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 85 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
99 Ops[5].getAsInteger(10, Op2);
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
111 uint32_t Op2 = Bits & 0x7;
114 utostr(CRm) + "_" + utostr(Op2);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 286 MachineOperand Op2 = MI.getOperand(S2);
287 ChangeOpInto(MI.getOperand(S1), Op2);
|
| HexagonSplitDouble.cpp | 688 MachineOperand &Op2 = MI->getOperand(2);
706 if (Op2.isImm()) {
708 .addImm(Op2.getImm());
709 } else if (Op2.isReg()) {
711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
742 MachineOperand &Op2 = MI->getOperand(2);
743 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
744 int64_t Sh64 = Op2.getImm()
[all...] |
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCCodeEmitter.cpp | 145 const MCOperand Op2 = Inst.getOperand(2);
148 ((Op2.isImm() && Op2.getImm() != 0) ||
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
157 (Op2.isReg() && Op2.getReg() != Lanai::R0))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.cpp | 151 SDValue Op2 = Op.getOperand(2);
166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
171 if (Op1.getType() != Op2.getType())
176 return Op1.getReg() == Op2.getReg();
178 return Op1.getImm() == Op2.getImm();
295 MachineOperand &Op2 = AluIter->getOperand(2);
302 if (Op2.isImm()) {
313 // Check that the Op2 would fit in the immediate field of the
315 ((IsSpls && isInt<10>(Op2.getImm())) ||
316 (!IsSpls && isInt<16>(Op2.getImm())))) ||
317 Offset.getImm() == Op2.getImm())
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 368 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp);
370 assert(isSimilarDispOp(Op1, Op2) &&
378 return Op1.isImm() ? Op1.getImm() - Op2.getImm()
379 : Op1.getOffset() - Op2.getOffset();
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
347 unsigned Op1, Op2;
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
360 unsigned Op1, Op2;
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 273 SDValue Op2 = Op.getOperand(2);
288 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
295 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
296 return DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 246 SDValue Op2 = Node->getOperand(1);
251 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
|
| /external/llvm/lib/Analysis/ |
| CFLGraph.h | 251 auto *Op2 = Inst.getOperand(1);
253 addAssignEdge(Op2, &Inst);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 322 const MachineOperand &Op2 = I->getOperand(2);
324 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
347 unsigned N = Op2.getImm();
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 405 Scatterer Op2 = scatter(&SI, SI.getOperand(2));
407 assert(Op2.size() == NumElems && "Mismatched select");
415 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I],
420 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I],
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/ |
| EbcExecute.c | 42 IN UINT64 Op2
877 @param Op2 Operand 2 from the instruction
879 @return ~Op2
886 IN UINT64 Op2
897 @param Op2 Operand 2 from the instruction
899 @return Op2 * -1
906 IN UINT64 Op2
917 @param Op2 Operand 2 from the instruction
919 @return Op1 + Op2
926 IN UINT64 Op2
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 718 SDValue Op2 = Op.getOperand(2);
721 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
755 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
762 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
763 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 565 const MachineOperand &Op2 = Inst.getOperand(2);
574 if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
575 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 69 const MCOperand &Op2 = MI->getOperand(2);
74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
110 if (Op2.isImm() && Op3.isImm()) {
113 int64_t immr = Op2.getImm();
144 if (Op2.getImm() > Op3.getImm()) {
147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
162 const MCOperand &Op2 = MI->getOperand(2)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 816 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
817 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
821 delete &Op2;
829 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
830 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
834 delete &Op2;
843 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
844 if (isSrcOp(Op) && isDstOp(Op2)) {
848 delete &Op2;
[all...] |
