| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd;
21 Inst(unsigned Opc, unsigned ImmOpnd);
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| MipsInstrInfo.cpp | 71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
74 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
80 Cond.push_back(MachineOperand::CreateImm(Opc));
100 unsigned Opc = Cond[0].getImm();
101 const MCInstrDesc &MCID = get(Opc);
125 // Floating point branches: 1 (opc)
126 // Int BranchZero: 2 (opc, reg)
127 // Int Branch: 3 (opc, reg0, reg1)
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FrameLowering.cpp | 103 unsigned Opc = MBBI->getOpcode();
104 switch (Opc) {
148 unsigned Opc = isSub ?
162 Opc = isSub
165 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 unsigned Opc = PI->getOpcode();
193 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
194 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RedundantCopyElimination.cpp | 71 unsigned Opc = MI.getOpcode();
74 if ((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
77 else if ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
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| /external/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.cpp | 162 int Opc = (isSub) ? ARM::tSUBrr
164 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
165 if (Opc != ARM::tADDhirr)
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| /external/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 170 unsigned Opc = BPF::MOV_rr;
172 CurDAG->SelectNodeTo(Node, Opc, VT, TFI);
175 ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonCFGOptimizer.cpp | 61 static bool IsConditionalBranch(int Opc) {
62 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
63 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);
67 static bool IsUnconditionalJump(int Opc) {
68 return (Opc == Hexagon::J2_jump);
115 int Opc = MI.getOpcode();
116 if (IsConditionalBranch(Opc)) {
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| HexagonSplitConst32AndConst64.cpp | 90 int Opc = MI.getOpcode();
91 if (Opc == Hexagon::CONST32_Int_Real &&
106 else if (Opc == Hexagon::CONST32_Int_Real ||
107 Opc == Hexagon::CONST32_Float_Real) {
113 if (Opc == Hexagon::CONST32_Float_Real) {
126 else if (Opc == Hexagon::CONST64_Int_Real ||
127 Opc == Hexagon::CONST64_Float_Real) {
133 if (Opc == Hexagon::CONST64_Float_Real) {
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| HexagonRegisterInfo.cpp | 181 unsigned Opc = MI.getOpcode();
182 switch (Opc) {
194 if (!HII.isValidOffset(Opc, RealOffset)) {
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| RDFCopy.cpp | 30 unsigned Opc = MI->getOpcode();
31 switch (Opc) {
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelDAGToDAG.cpp | 305 unsigned Opc = Lanai::ADD_I_LO;
307 CurDAG->SelectNodeTo(Node, Opc, VT, TFI, Imm);
310 ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VT, TFI, Imm));
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| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 95 unsigned Opc;
97 Opc = MSP430::MOV16rr;
99 Opc = MSP430::MOV8rr;
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
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| MSP430FrameLowering.cpp | 143 unsigned Opc = PI->getOpcode();
144 if (Opc != MSP430::POP16r && !PI->isTerminator())
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| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 159 unsigned Opc = MBBI->getOpcode();
160 switch (Opc) {
271 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
272 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
274 Opc = isSub
277 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
293 unsigned Opc = isSub
296 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
356 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
358 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 196 unsigned Opc = MBlaze::BRID;
198 Opc = (unsigned)Cond[0].getImm();
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
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| MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode();
102 if (Opc != ISD::Constant)
213 unsigned Opc = MBlaze::ADDIK;
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 142 unsigned Opc = PI->getOpcode();
143 if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
|
| MSP430InstrInfo.cpp | 95 unsigned Opc;
97 Opc = MSP430::MOV16rr;
99 Opc = MSP430::MOV8rr;
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 51 unsigned Opc = 0;
54 Opc = SystemZ::MOV32mr;
57 Opc = SystemZ::MOV64mr;
59 Opc = SystemZ::FMOV32mr;
61 Opc = SystemZ::FMOV64mr;
63 Opc = SystemZ::MOV64Pmr;
65 Opc = SystemZ::MOV128mr;
69 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
81 unsigned Opc = 0;
84 Opc = SystemZ::MOV32rm
[all...] |
| SystemZFrameLowering.cpp | 69 unsigned Opc; uint64_t Chunk;
74 Opc = SystemZ::ADD64ri32;
77 Opc = SystemZ::ADD64ri16;
86 BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D)
|
| /external/llvm/lib/Target/AVR/ |
| AVRInstrInfo.cpp | 45 unsigned Opc;
48 Opc = AVR::MOVRdRr;
50 Opc = AVR::MOVWRdRr;
52 Opc = AVR::SPREAD;
54 Opc = AVR::SPWRITE;
59 BuildMI(MBB, MI, DL, get(Opc), DestReg)
195 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
196 switch (Opc) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
131 if (Opc != ARM::tADDhirr)
142 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
147 if (Opc == ARM::tADDrSPi) {
181 int Opc = 0;
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
202 Opc = ARM::tADDrSPi;
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
216 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 33 unsigned opc = I->getOpcode(); local
35 return (opc == SPU::BR
36 || opc == SPU::BRA
37 || opc == SPU::BI);
42 unsigned opc = I->getOpcode(); local
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
46 || opc == SPU::BRZr32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr1
145 unsigned opc; local
180 unsigned opc; local
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 51 unsigned Opc = MI->getOpcode();
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
56 (Opc == Mips::LDC164_P8))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
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