/prebuilts/go/darwin-x86/src/crypto/rc4/ |
rc4_arm.s | 12 #define Rn R2 26 MOVW n+8(FP), Rn 56 CMP Rk, Rn
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/prebuilts/go/linux-x86/src/crypto/rc4/ |
rc4_arm.s | 12 #define Rn R2 26 MOVW n+8(FP), Rn 56 CMP Rk, Rn
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/prebuilts/go/darwin-x86/src/runtime/ |
vlop_arm.s | 207 #define Rn R8 229 MOVW Rn, Rr /* numerator */ 247 MOVW Rn, Rr /* numerator */ 264 MOVW Rn, Rr /* numerator */ 297 MOVW Rn, Rr /* numerator */
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/prebuilts/go/linux-x86/src/runtime/ |
vlop_arm.s | 207 #define Rn R8 229 MOVW Rn, Rr /* numerator */ 247 MOVW Rn, Rr /* numerator */ 264 MOVW Rn, Rr /* numerator */ 297 MOVW Rn, Rr /* numerator */
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
ArmDisassembler.c | 171 UINT32 Rn, Rd, Rm;
184 Rn = (OpCode >> 16) & 0xf;
198 // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
199 AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
201 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
202 AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
210 // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
211 // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
212 // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^ [all...] |
ThumbDisassembler.c | 149 { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
150 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
154 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
157 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
187 { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
188 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
190 { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
191 { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
192 { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]
193 { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>] [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
AArch64Disassembler.cpp | 653 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 658 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 661 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb2SizeReduction.cpp | 438 unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); 443 assert(isARMLowRegister(Rn)); 451 .addReg(Rn, RegState::Define) 452 .addReg(Rn) [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/toolchain/binutils/binutils-2.25/include/opcode/ |
tic30.h | 190 #define Rn 0x0001 209 #define GAddr1 Rn | Direct | Indirect | Imm16 211 #define TAddr1 op3T1 | Rn | Indirect 212 #define TAddr2 op3T2 | Rn | Indirect 213 #define Reg Rn | ARn 247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, 251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, 252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, 347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, 408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt } [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 687 // [Rn, Rm] 689 // {2-0} = Rn 692 unsigned Rn = getARMRegisterNumbering(MO1.getReg()); 694 return (Rm << 3) | Rn; 709 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. 788 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC. [all...] |
/external/v8/src/arm/ |
disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm); 305 if (format[1] == 'n') { // 'rn: Rn register 418 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { 420 "[r%d", Rn); 734 // Rn field to encode it. 735 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 739 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 740 // Rn field to encode the Rd register and the Rd field to encode 741 // the Rn register [all...] |
simulator-arm.cc | 695 FPSCR_rounding_mode_ = RN; 1580 int rn = instr->RnValue(); local 2100 int rn = instr->RnValue(); local 2176 int rn = instr->RnValue(); local 2206 int rn = instr->RnValue(); local 2242 int rn = instr->RnValue(); local 2438 int rn = instr->RnValue(); local 2668 int rn = instr->RnValue(); local 2732 int rn = instr->RnValue(); local 3891 int rn = instr->RnValue(); local 3931 int rn = instr->RnValue(); local 3948 int rn = instr->RnValue(); local [all...] |
/system/core/libpixelflinger/tests/arch-arm64/assembler/ |
arm64_assembler_test.cpp | 414 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3) 428 regs[Rn] = test.RnValue; 449 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break; 450 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break; 451 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break; 452 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break; 453 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break; 454 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break; 456 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break; 457 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/vixl/src/aarch64/ |
assembler-aarch64.h | 601 void add(const Register& rd, const Register& rn, const Operand& operand); 604 void adds(const Register& rd, const Register& rn, const Operand& operand); 607 void cmn(const Register& rn, const Operand& operand); 610 void sub(const Register& rd, const Register& rn, const Operand& operand); 613 void subs(const Register& rd, const Register& rn, const Operand& operand); 616 void cmp(const Register& rn, const Operand& operand); 625 void adc(const Register& rd, const Register& rn, const Operand& operand); 628 void adcs(const Register& rd, const Register& rn, const Operand& operand); 631 void sbc(const Register& rd, const Register& rn, const Operand& operand); 634 void sbcs(const Register& rd, const Register& rn, const Operand& operand) [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
arm-dis.c | 2015 int rn = (given >> 16) & 0xf; local 2441 const char *rn = arm_regnames [(given >> 16) & 0xf]; local 2668 int rn = ((given >> 16) & 0xf); local 2698 int rn = ((given >> 16) & 0xf); local 2773 int rn = ((given >> 16) & 0xf); local [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
ARMDisassembler.cpp | [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |
/toolchain/binutils/binutils-2.25/gas/config/ |
tc-arm.c | [all...] |