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      1 /* tic30.h -- Header file for TI TMS320C30 opcode table
      2    Copyright (C) 1998-2014 Free Software Foundation, Inc.
      3    Contributed by Steven Haworth (steve (at) pm.cse.rmit.edu.au)
      4 
      5    This file is part of GDB, GAS, and the GNU binutils.
      6 
      7    GDB, GAS, and the GNU binutils are free software; you can redistribute
      8    them and/or modify them under the terms of the GNU General Public
      9    License as published by the Free Software Foundation; either version 3,
     10    or (at your option) any later version.
     11 
     12    GDB, GAS, and the GNU binutils are distributed in the hope that they
     13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
     14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
     15    the GNU General Public License for more details.
     16 
     17    You should have received a copy of the GNU General Public License
     18    along with this file; see the file COPYING3.  If not, write to the Free
     19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
     20    02110-1301, USA.  */
     21 
     22 /* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
     23    header file.  */
     24 
     25 #ifndef _TMS320_H_
     26 #define _TMS320_H_
     27 
     28 struct _register
     29 {
     30   char *name;
     31   unsigned char opcode;
     32   unsigned char regtype;
     33 };
     34 
     35 typedef struct _register reg;
     36 
     37 #define REG_Rn    0x01
     38 #define REG_ARn   0x02
     39 #define REG_DP    0x03
     40 #define REG_OTHER 0x04
     41 
     42 static const reg tic30_regtab[] = {
     43   { "r0", 0x00, REG_Rn },
     44   { "r1", 0x01, REG_Rn },
     45   { "r2", 0x02, REG_Rn },
     46   { "r3", 0x03, REG_Rn },
     47   { "r4", 0x04, REG_Rn },
     48   { "r5", 0x05, REG_Rn },
     49   { "r6", 0x06, REG_Rn },
     50   { "r7", 0x07, REG_Rn },
     51   { "ar0",0x08, REG_ARn },
     52   { "ar1",0x09, REG_ARn },
     53   { "ar2",0x0A, REG_ARn },
     54   { "ar3",0x0B, REG_ARn },
     55   { "ar4",0x0C, REG_ARn },
     56   { "ar5",0x0D, REG_ARn },
     57   { "ar6",0x0E, REG_ARn },
     58   { "ar7",0x0F, REG_ARn },
     59   { "dp", 0x10, REG_DP },
     60   { "ir0",0x11, REG_OTHER },
     61   { "ir1",0x12, REG_OTHER },
     62   { "bk", 0x13, REG_OTHER },
     63   { "sp", 0x14, REG_OTHER },
     64   { "st", 0x15, REG_OTHER },
     65   { "ie", 0x16, REG_OTHER },
     66   { "if", 0x17, REG_OTHER },
     67   { "iof",0x18, REG_OTHER },
     68   { "rs", 0x19, REG_OTHER },
     69   { "re", 0x1A, REG_OTHER },
     70   { "rc", 0x1B, REG_OTHER },
     71   { "R0", 0x00, REG_Rn },
     72   { "R1", 0x01, REG_Rn },
     73   { "R2", 0x02, REG_Rn },
     74   { "R3", 0x03, REG_Rn },
     75   { "R4", 0x04, REG_Rn },
     76   { "R5", 0x05, REG_Rn },
     77   { "R6", 0x06, REG_Rn },
     78   { "R7", 0x07, REG_Rn },
     79   { "AR0",0x08, REG_ARn },
     80   { "AR1",0x09, REG_ARn },
     81   { "AR2",0x0A, REG_ARn },
     82   { "AR3",0x0B, REG_ARn },
     83   { "AR4",0x0C, REG_ARn },
     84   { "AR5",0x0D, REG_ARn },
     85   { "AR6",0x0E, REG_ARn },
     86   { "AR7",0x0F, REG_ARn },
     87   { "DP", 0x10, REG_DP },
     88   { "IR0",0x11, REG_OTHER },
     89   { "IR1",0x12, REG_OTHER },
     90   { "BK", 0x13, REG_OTHER },
     91   { "SP", 0x14, REG_OTHER },
     92   { "ST", 0x15, REG_OTHER },
     93   { "IE", 0x16, REG_OTHER },
     94   { "IF", 0x17, REG_OTHER },
     95   { "IOF",0x18, REG_OTHER },
     96   { "RS", 0x19, REG_OTHER },
     97   { "RE", 0x1A, REG_OTHER },
     98   { "RC", 0x1B, REG_OTHER },
     99   { "",   0, 0 }
    100 };
    101 
    102 static const reg *const tic30_regtab_end
    103   = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]);
    104 
    105 /* Indirect Addressing Modes Modification Fields */
    106 /* Indirect Addressing with Displacement */
    107 #define PreDisp_Add        0x00
    108 #define PreDisp_Sub        0x01
    109 #define PreDisp_Add_Mod    0x02
    110 #define PreDisp_Sub_Mod    0x03
    111 #define PostDisp_Add_Mod   0x04
    112 #define PostDisp_Sub_Mod   0x05
    113 #define PostDisp_Add_Circ  0x06
    114 #define PostDisp_Sub_Circ  0x07
    115 /* Indirect Addressing with Index Register IR0 */
    116 #define PreIR0_Add         0x08
    117 #define PreIR0_Sub         0x09
    118 #define PreIR0_Add_Mod     0x0A
    119 #define PreIR0_Sub_Mod     0x0B
    120 #define PostIR0_Add_Mod    0x0C
    121 #define PostIR0_Sub_Mod    0x0D
    122 #define PostIR0_Add_Circ   0x0E
    123 #define PostIR0_Sub_Circ   0x0F
    124 /* Indirect Addressing with Index Register IR1 */
    125 #define PreIR1_Add         0x10
    126 #define PreIR1_Sub         0x11
    127 #define PreIR1_Add_Mod     0x12
    128 #define PreIR1_Sub_Mod     0x13
    129 #define PostIR1_Add_Mod    0x14
    130 #define PostIR1_Sub_Mod    0x15
    131 #define PostIR1_Add_Circ   0x16
    132 #define PostIR1_Sub_Circ   0x17
    133 /* Indirect Addressing (Special Cases) */
    134 #define IndirectOnly       0x18
    135 #define PostIR0_Add_BitRev 0x19
    136 
    137 typedef struct {
    138   char *syntax;
    139   unsigned char modfield;
    140   unsigned char displacement;
    141 } ind_addr_type;
    142 
    143 #define IMPLIED_DISP  0x01
    144 #define DISP_REQUIRED 0x02
    145 #define NO_DISP       0x03
    146 
    147 static const ind_addr_type tic30_indaddr_tab[] = {
    148   { "*+ar",       PreDisp_Add,        IMPLIED_DISP },
    149   { "*-ar",       PreDisp_Sub,        IMPLIED_DISP },
    150   { "*++ar",      PreDisp_Add_Mod,    IMPLIED_DISP },
    151   { "*--ar",      PreDisp_Sub_Mod,    IMPLIED_DISP },
    152   { "*ar++",      PostDisp_Add_Mod,   IMPLIED_DISP },
    153   { "*ar--",      PostDisp_Sub_Mod,   IMPLIED_DISP },
    154   { "*ar++%",     PostDisp_Add_Circ,  IMPLIED_DISP },
    155   { "*ar--%",     PostDisp_Sub_Circ,  IMPLIED_DISP },
    156   { "*+ar()",     PreDisp_Add,        DISP_REQUIRED },
    157   { "*-ar()",     PreDisp_Sub,        DISP_REQUIRED },
    158   { "*++ar()",    PreDisp_Add_Mod,    DISP_REQUIRED },
    159   { "*--ar()",    PreDisp_Sub_Mod,    DISP_REQUIRED },
    160   { "*ar++()",    PostDisp_Add_Mod,   DISP_REQUIRED },
    161   { "*ar--()",    PostDisp_Sub_Mod,   DISP_REQUIRED },
    162   { "*ar++()%",   PostDisp_Add_Circ,  DISP_REQUIRED },
    163   { "*ar--()%",   PostDisp_Sub_Circ,  DISP_REQUIRED },
    164   { "*+ar(ir0)",  PreIR0_Add,         NO_DISP },
    165   { "*-ar(ir0)",  PreIR0_Sub,         NO_DISP },
    166   { "*++ar(ir0)", PreIR0_Add_Mod,     NO_DISP },
    167   { "*--ar(ir0)", PreIR0_Sub_Mod,     NO_DISP },
    168   { "*ar++(ir0)", PostIR0_Add_Mod,    NO_DISP },
    169   { "*ar--(ir0)", PostIR0_Sub_Mod,    NO_DISP },
    170   { "*ar++(ir0)%",PostIR0_Add_Circ,   NO_DISP },
    171   { "*ar--(ir0)%",PostIR0_Sub_Circ,   NO_DISP },
    172   { "*+ar(ir1)",  PreIR1_Add,         NO_DISP },
    173   { "*-ar(ir1)",  PreIR1_Sub,         NO_DISP },
    174   { "*++ar(ir1)", PreIR1_Add_Mod,     NO_DISP },
    175   { "*--ar(ir1)", PreIR1_Sub_Mod,     NO_DISP },
    176   { "*ar++(ir1)", PostIR1_Add_Mod,    NO_DISP },
    177   { "*ar--(ir1)", PostIR1_Sub_Mod,    NO_DISP },
    178   { "*ar++(ir1)%",PostIR1_Add_Circ,   NO_DISP },
    179   { "*ar--(ir1)%",PostIR1_Sub_Circ,   NO_DISP },
    180   { "*ar",        IndirectOnly,       NO_DISP },
    181   { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP },
    182   { "",           0,0 }
    183 };
    184 
    185 static const ind_addr_type *const tic30_indaddrtab_end
    186   = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]);
    187 
    188 /* Possible operand types */
    189 /* Register types */
    190 #define Rn       0x0001
    191 #define ARn      0x0002
    192 #define DPReg    0x0004
    193 #define OtherReg 0x0008
    194 /* Addressing mode types */
    195 #define Direct   0x0010
    196 #define Indirect 0x0020
    197 #define Imm16    0x0040
    198 #define Disp     0x0080
    199 #define Imm24    0x0100
    200 #define Abs24    0x0200
    201 /* 3 operand addressing mode types */
    202 #define op3T1    0x0400
    203 #define op3T2    0x0800
    204 /* Interrupt vector */
    205 #define IVector  0x1000
    206 /* Not required */
    207 #define NotReq   0x2000
    208 
    209 #define GAddr1   Rn | Direct | Indirect | Imm16
    210 #define GAddr2   GAddr1 | AllReg
    211 #define TAddr1   op3T1 | Rn | Indirect
    212 #define TAddr2   op3T2 | Rn | Indirect
    213 #define Reg      Rn | ARn
    214 #define AllReg   Reg | DPReg | OtherReg
    215 
    216 typedef struct _template
    217 {
    218   char *name;
    219   unsigned int operands; /* how many operands */
    220   unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */
    221   /* the bits in opcode_modifier are used to generate the final opcode from
    222      the base_opcode.  These bits also are used to detect alternate forms of
    223      the same instruction */
    224   unsigned int opcode_modifier;
    225 
    226   /* opcode_modifier bits: */
    227 #define AddressMode 0x00600000
    228 #define PCRel       0x02000000
    229 #define StackOp     0x001F0000
    230 #define Rotate      StackOp
    231 
    232   /* operand_types[i] describes the type of operand i.  This is made
    233      by OR'ing together all of the possible type masks.  (e.g.
    234      'operand_types[i] = Reg|Imm' specifies that operand i can be
    235      either a register or an immediate operand */
    236   unsigned int operand_types[3];
    237   /* This defines the number type of an immediate argument to an instruction. */
    238   int imm_arg_type;
    239 #define Imm_None  0
    240 #define Imm_Float 1
    241 #define Imm_SInt  2
    242 #define Imm_UInt  3
    243 }
    244 insn_template;
    245 
    246 static const insn_template tic30_optab[] = {
    247   { "absf"   ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    248   { "absi"   ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    249   { "addc"   ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    250   { "addc3"  ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    251   { "addf"   ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    252   { "addf3"  ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
    253   { "addi"   ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    254   { "addi3"  ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    255   { "and"    ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    256   { "and3"   ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    257   { "andn"   ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    258   { "andn3"  ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    259   { "ash"    ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    260   { "ash3"   ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    261   { "b"      ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    262   { "bu"     ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    263   { "blo"    ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    264   { "bls"    ,1,0x68020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    265   { "bhi"    ,1,0x68030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    266   { "bhs"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    267   { "beq"    ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    268   { "bne"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    269   { "blt"    ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    270   { "ble"    ,1,0x68080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    271   { "bgt"    ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    272   { "bge"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    273   { "bz"     ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    274   { "bnz"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    275   { "bp"     ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    276   { "bn"     ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    277   { "bnn"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    278   { "bnv"    ,1,0x680C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    279   { "bv"     ,1,0x680D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    280   { "bnuf"   ,1,0x680E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    281   { "buf"    ,1,0x680F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    282   { "bnc"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    283   { "bc"     ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    284   { "bnlv"   ,1,0x68100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    285   { "blv"    ,1,0x68110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    286   { "bnluf"  ,1,0x68120000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    287   { "bluf"   ,1,0x68130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    288   { "bzuf"   ,1,0x68140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    289   { "bd"     ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    290   { "bud"    ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    291   { "blod"   ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    292   { "blsd"   ,1,0x68220000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    293   { "bhid"   ,1,0x68230000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    294   { "bhsd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    295   { "beqd"   ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    296   { "bned"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    297   { "bltd"   ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    298   { "bled"   ,1,0x68280000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    299   { "bgtd"   ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    300   { "bged"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    301   { "bzd"    ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    302   { "bnzd"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    303   { "bpd"    ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    304   { "bnd"    ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    305   { "bnnd"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    306   { "bnvd"   ,1,0x682C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    307   { "bvd"    ,1,0x682D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    308   { "bnufd"  ,1,0x682E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    309   { "bufd"   ,1,0x682F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    310   { "bncd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    311   { "bcd"    ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    312   { "bnlvd"  ,1,0x68300000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    313   { "blvd"   ,1,0x68310000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    314   { "bnlufd" ,1,0x68320000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    315   { "blufd"  ,1,0x68330000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    316   { "bzufd"  ,1,0x68340000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
    317   { "br"     ,1,0x60000000,0,           { Imm24, 0, 0 }, Imm_UInt },
    318   { "brd"    ,1,0x61000000,0,           { Imm24, 0, 0 }, Imm_UInt },
    319   { "call"   ,1,0x62000000,0,           { Imm24, 0, 0 }, Imm_UInt },
    320   { "callu"  ,1,0x70000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    321   { "calllo" ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    322   { "callls" ,1,0x70020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    323   { "callhi" ,1,0x70030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    324   { "callhs" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    325   { "calleq" ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    326   { "callne" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    327   { "calllt" ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    328   { "callle" ,1,0x70080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    329   { "callgt" ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    330   { "callge" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    331   { "callz"  ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    332   { "callnz" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    333   { "callp"  ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    334   { "calln"  ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    335   { "callnn" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    336   { "callnv" ,1,0x700C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    337   { "callv"  ,1,0x700D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    338   { "callnuf",1,0x700E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    339   { "calluf" ,1,0x700F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    340   { "callnc" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    341   { "callc"  ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    342   { "callnlv",1,0x70100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    343   { "calllv" ,1,0x70110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    344   { "callnluf",1,0x70120000,PCRel,      { AllReg|Disp, 0, 0 }, Imm_UInt },
    345   { "callluf",1,0x70130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    346   { "callzuf",1,0x70140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
    347   { "cmpf"   ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    348   { "cmpf3"  ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None },
    349   { "cmpi"   ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    350   { "cmpi3"  ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
    351   { "db"     ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    352   { "dbu"    ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    353   { "dblo"   ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    354   { "dbls"   ,2,0x6C020000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    355   { "dbhi"   ,2,0x6C030000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    356   { "dbhs"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    357   { "dbeq"   ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    358   { "dbne"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    359   { "dblt"   ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    360   { "dble"   ,2,0x6C080000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    361   { "dbgt"   ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    362   { "dbge"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    363   { "dbz"    ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    364   { "dbnz"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    365   { "dbp"    ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    366   { "dbn"    ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    367   { "dbnn"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    368   { "dbnv"   ,2,0x6C0C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    369   { "dbv"    ,2,0x6C0D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    370   { "dbnuf"  ,2,0x6C0E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    371   { "dbuf"   ,2,0x6C0F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    372   { "dbnc"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    373   { "dbc"    ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    374   { "dbnlv"  ,2,0x6C100000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    375   { "dblv"   ,2,0x6C110000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    376   { "dbnluf" ,2,0x6C120000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    377   { "dbluf"  ,2,0x6C130000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    378   { "dbzuf"  ,2,0x6C140000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    379   { "dbd"    ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    380   { "dbud"   ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    381   { "dblod"  ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    382   { "dblsd"  ,2,0x6C220000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    383   { "dbhid"  ,2,0x6C230000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    384   { "dbhsd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    385   { "dbeqd"  ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    386   { "dbned"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    387   { "dbltd"  ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    388   { "dbled"  ,2,0x6C280000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    389   { "dbgtd"  ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    390   { "dbged"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    391   { "dbzd"   ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    392   { "dbnzd"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    393   { "dbpd"   ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    394   { "dbnd"   ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    395   { "dbnnd"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    396   { "dbnvd"  ,2,0x6C2C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    397   { "dbvd"   ,2,0x6C2D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    398   { "dbnufd" ,2,0x6C2E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    399   { "dbufd"  ,2,0x6C2F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    400   { "dbncd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    401   { "dbcd"   ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    402   { "dbnlvd" ,2,0x6C300000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    403   { "dblvd"  ,2,0x6C310000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    404   { "dbnlufd",2,0x6C320000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    405   { "dblufd" ,2,0x6C330000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    406   { "dbzufd" ,2,0x6C340000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
    407   { "fix"    ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float },
    408   { "float"  ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt },
    409   { "iack"   ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None },
    410   { "idle"   ,0,0x06000000,0,           { 0, 0, 0 }, Imm_None },
    411   { "idle2"  ,0,0x06000001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
    412   { "lde"    ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    413   { "ldf"    ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    414   { "ldfu"   ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    415   { "ldflo"  ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    416   { "ldfls"  ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    417   { "ldfhi"  ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    418   { "ldfhs"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    419   { "ldfeq"  ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    420   { "ldfne"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    421   { "ldflt"  ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    422   { "ldfle"  ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    423   { "ldfgt"  ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    424   { "ldfge"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    425   { "ldfz"   ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    426   { "ldfnz"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    427   { "ldfp"   ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    428   { "ldfn"   ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    429   { "ldfnn"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    430   { "ldfnv"  ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    431   { "ldfv"   ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    432   { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    433   { "ldfuf"  ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    434   { "ldfnc"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    435   { "ldfc"   ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    436   { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    437   { "ldflv"  ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    438   { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    439   { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    440   { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    441   { "ldfi"   ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None },
    442   { "ldi"    ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    443   { "ldiu"   ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    444   { "ldilo"  ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    445   { "ldils"  ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    446   { "ldihi"  ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    447   { "ldihs"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    448   { "ldieq"  ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    449   { "ldine"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    450   { "ldilt"  ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    451   { "ldile"  ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    452   { "ldigt"  ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    453   { "ldige"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    454   { "ldiz"   ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    455   { "ldinz"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    456   { "ldip"   ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    457   { "ldin"   ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    458   { "ldinn"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    459   { "ldinv"  ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    460   { "ldiv"   ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    461   { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    462   { "ldiuf"  ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    463   { "ldinc"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    464   { "ldic"   ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    465   { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    466   { "ldilv"  ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    467   { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    468   { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    469   { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    470   { "ldii"   ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None },
    471   { "ldm"    ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    472   { "ldp"    ,2,0x08700000,0,           { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt },
    473   { "lopower",0,0x10800001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
    474   { "lsh"    ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    475   { "lsh3"   ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    476   { "maxspeed",0,0x10800000,0,          { 0, 0, 0 }, Imm_None }, /* LC31 Only */
    477   { "mpyf"   ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    478   { "mpyf3"  ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
    479   { "mpyi"   ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    480   { "mpyi3"  ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    481   { "negb"   ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    482   { "negf"   ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    483   { "negi"   ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    484   { "nop"    ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None },
    485   { "norm"   ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/
    486   { "not"    ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    487   { "or"     ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    488   { "or3"    ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    489   { "pop"    ,1,0x0E200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
    490   { "popf"   ,1,0x0EA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
    491   { "push"   ,1,0x0F200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
    492   { "pushf"  ,1,0x0FA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
    493   { "reti"   ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
    494   { "retiu"  ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
    495   { "retilo" ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
    496   { "retils" ,0,0x78020000,0,           { 0, 0, 0 }, Imm_None },
    497   { "retihi" ,0,0x78030000,0,           { 0, 0, 0 }, Imm_None },
    498   { "retihs" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
    499   { "retieq" ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
    500   { "retine" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
    501   { "retilt" ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
    502   { "retile" ,0,0x78080000,0,           { 0, 0, 0 }, Imm_None },
    503   { "retigt" ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
    504   { "retige" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
    505   { "retiz"  ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
    506   { "retinz" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
    507   { "retip"  ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
    508   { "retin"  ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
    509   { "retinn" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
    510   { "retinv" ,0,0x780C0000,0,           { 0, 0, 0 }, Imm_None },
    511   { "retiv"  ,0,0x780D0000,0,           { 0, 0, 0 }, Imm_None },
    512   { "retinuf",0,0x780E0000,0,           { 0, 0, 0 }, Imm_None },
    513   { "retiuf" ,0,0x780F0000,0,           { 0, 0, 0 }, Imm_None },
    514   { "retinc" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
    515   { "retic"  ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
    516   { "retinlv",0,0x78100000,0,           { 0, 0, 0 }, Imm_None },
    517   { "retilv" ,0,0x78110000,0,           { 0, 0, 0 }, Imm_None },
    518   { "retinluf",0,0x78120000,0,          { 0, 0, 0 }, Imm_None },
    519   { "retiluf",0,0x78130000,0,           { 0, 0, 0 }, Imm_None },
    520   { "retizuf",0,0x78140000,0,           { 0, 0, 0 }, Imm_None },
    521   { "rets"   ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
    522   { "retsu"  ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
    523   { "retslo" ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
    524   { "retsls" ,0,0x78820000,0,           { 0, 0, 0 }, Imm_None },
    525   { "retshi" ,0,0x78830000,0,           { 0, 0, 0 }, Imm_None },
    526   { "retshs" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
    527   { "retseq" ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
    528   { "retsne" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
    529   { "retslt" ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
    530   { "retsle" ,0,0x78880000,0,           { 0, 0, 0 }, Imm_None },
    531   { "retsgt" ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
    532   { "retsge" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
    533   { "retsz"  ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
    534   { "retsnz" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
    535   { "retsp"  ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
    536   { "retsn"  ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
    537   { "retsnn" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
    538   { "retsnv" ,0,0x788C0000,0,           { 0, 0, 0 }, Imm_None },
    539   { "retsv"  ,0,0x788D0000,0,           { 0, 0, 0 }, Imm_None },
    540   { "retsnuf",0,0x788E0000,0,           { 0, 0, 0 }, Imm_None },
    541   { "retsuf" ,0,0x788F0000,0,           { 0, 0, 0 }, Imm_None },
    542   { "retsnc" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
    543   { "retsc"  ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
    544   { "retsnlv",0,0x78900000,0,           { 0, 0, 0 }, Imm_None },
    545   { "retslv" ,0,0x78910000,0,           { 0, 0, 0 }, Imm_None },
    546   { "retsnluf",0,0x78920000,0,          { 0, 0, 0 }, Imm_None },
    547   { "retsluf",0,0x78930000,0,           { 0, 0, 0 }, Imm_None },
    548   { "retszuf",0,0x78940000,0,           { 0, 0, 0 }, Imm_None },
    549   { "rnd"    ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    550   { "rol"    ,1,0x11E00001,Rotate,      { AllReg, 0, 0 }, Imm_None },
    551   { "rolc"   ,1,0x12600001,Rotate,      { AllReg, 0, 0 }, Imm_None },
    552   { "ror"    ,1,0x12E0FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
    553   { "rorc"   ,1,0x1360FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
    554   { "rptb"   ,1,0x64000000,0,           { Imm24, 0, 0 }, Imm_UInt },
    555   { "rpts"   ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt },
    556   { "sigi"   ,0,0x16000000,0,           { 0, 0, 0 }, Imm_None },
    557   { "stf"    ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
    558   { "stfi"   ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
    559   { "sti"    ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
    560   { "stii"   ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
    561   { "subb"   ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    562   { "subb3"  ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    563   { "subc"   ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    564   { "subf"   ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    565   { "subf3"  ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
    566   { "subi"   ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    567   { "subi3"  ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    568   { "subrb"  ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    569   { "subrf"  ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
    570   { "subri"  ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
    571   { "swi"    ,0,0x66000000,0,           { 0, 0, 0 }, Imm_None },
    572   { "trap"   ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
    573   { "trapu"  ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
    574   { "traplo" ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
    575   { "trapls" ,1,0x74820020,0,           { IVector, 0, 0 }, Imm_None },
    576   { "traphi" ,1,0x74830020,0,           { IVector, 0, 0 }, Imm_None },
    577   { "traphs" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
    578   { "trapeq" ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
    579   { "trapne" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
    580   { "traplt" ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
    581   { "traple" ,1,0x74880020,0,           { IVector, 0, 0 }, Imm_None },
    582   { "trapgt" ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
    583   { "trapge" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
    584   { "trapz"  ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
    585   { "trapnz" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
    586   { "trapp"  ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
    587   { "trapn"  ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
    588   { "trapnn" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
    589   { "trapnv" ,1,0x748C0020,0,           { IVector, 0, 0 }, Imm_None },
    590   { "trapv"  ,1,0x748D0020,0,           { IVector, 0, 0 }, Imm_None },
    591   { "trapnuf",1,0x748E0020,0,           { IVector, 0, 0 }, Imm_None },
    592   { "trapuf" ,1,0x748F0020,0,           { IVector, 0, 0 }, Imm_None },
    593   { "trapnc" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
    594   { "trapc"  ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
    595   { "trapnlv",1,0x74900020,0,           { IVector, 0, 0 }, Imm_None },
    596   { "traplv" ,1,0x74910020,0,           { IVector, 0, 0 }, Imm_None },
    597   { "trapnluf",1,0x74920020,0,          { IVector, 0, 0 }, Imm_None },
    598   { "trapluf",1,0x74930020,0,           { IVector, 0, 0 }, Imm_None },
    599   { "trapzuf",1,0x74940020,0,           { IVector, 0, 0 }, Imm_None },
    600   { "tstb"   ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    601   { "tstb3"  ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
    602   { "xor"    ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
    603   { "xor3"   ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
    604   { ""       ,0,0x00000000,0,           { 0, 0, 0 }, 0 }
    605 };
    606 
    607 static const insn_template *const tic30_optab_end =
    608   tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
    609 
    610 typedef struct {
    611   char *name;
    612   unsigned int operands_1;
    613   unsigned int operands_2;
    614   unsigned int base_opcode;
    615   unsigned int operand_types[2][3];
    616   /* Which operand fits into which part of the final opcode word. */
    617   int oporder;
    618 } partemplate;
    619 
    620 /* oporder defines - not very descriptive. */
    621 #define OO_4op1   0
    622 #define OO_4op2   1
    623 #define OO_4op3   2
    624 #define OO_5op1   3
    625 #define OO_5op2   4
    626 #define OO_PField 5
    627 
    628 static const partemplate tic30_paroptab[] = {
    629   { "q_absf_stf",   2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    630 	OO_4op1 },
    631   { "q_absi_sti",   2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    632 	OO_4op1 },
    633   { "q_addf3_stf",  3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
    634 	OO_5op1 },
    635   { "q_addi3_sti",  3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
    636 	OO_5op1 },
    637   { "q_and3_sti",   3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
    638 	OO_5op1 },
    639   { "q_ash3_sti",   3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
    640 	OO_5op2 },
    641   { "q_fix_sti",    2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    642 	OO_4op1 },
    643   { "q_float_stf",  2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    644 	OO_4op1 },
    645   { "q_ldf_ldf",    2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
    646 	OO_4op2 },
    647   { "q_ldf_stf",    2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    648 	OO_4op1 },
    649   { "q_ldi_ldi",    2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
    650 	OO_4op2 },
    651   { "q_ldi_sti",    2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    652 	OO_4op1 },
    653   { "q_lsh3_sti",   3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
    654 	OO_5op2 },
    655   { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn },
    656  	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
    657   { "q_mpyf3_stf",  3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
    658 	OO_5op1 },
    659   { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn },
    660 	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
    661   { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn },
    662 	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
    663   { "q_mpyi3_sti",  3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
    664 	OO_5op1 },
    665   { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn },
    666 	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
    667   { "q_negf_stf",   2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    668 	OO_4op1 },
    669   { "q_negi_sti",   2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    670 	OO_4op1 },
    671   { "q_not_sti",    2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
    672 	OO_4op1 },
    673   { "q_or3_sti",    3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
    674 	OO_5op1 },
    675   { "q_stf_stf",    2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
    676 	OO_4op3 },
    677   { "q_sti_sti",    2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
    678 	OO_4op3 },
    679   { "q_subf3_stf",  3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
    680 	OO_5op2 },
    681   { "q_subi3_sti",  3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
    682 	OO_5op2 },
    683   { "q_xor3_sti",   3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
    684 	OO_5op1 },
    685   { "",             0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 }
    686 };
    687 
    688 static const partemplate *const tic30_paroptab_end =
    689   tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]);
    690 
    691 #endif
    692