| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 124 int Rd, int Rn,
129 int Rd, int Rm, int Rs, int Rn) = 0;
144 virtual void BX(int cc, int Rn) = 0;
155 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
157 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
159 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
161 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
164 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
166 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
168 int Rn, uint32_t offset = __immed8_pre(0)) = 0
[all...] |
| ARMAssemblerInterface.cpp | 70 int Rn, uint32_t offset)
72 LDR(cc, Rd, Rn, offset);
75 int Rn, uint32_t offset)
77 STR(cc, Rd, Rn, offset);
80 int Rd, int Rn, uint32_t Op2)
82 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
85 int Rd, int Rn, uint32_t Op2)
87 dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
|
| Arm64Assembler.cpp | 340 int s, int Rd, int Rn, uint32_t Op2)
397 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
398 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
399 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
400 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
401 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
408 int s, int Rd, int Rn, uint32_t Op2)
419 dataProcessingCommon(opcode, s, Wd, Rn, Op2);
423 dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2);
427 dataProcessingCommon(opSUB, s, Wd, Rn, Op2)
[all...] |
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
195 void ARMAssemblerProxy::BX(int cc, int Rn) {
196 mTarget->BX(cc, Rn);
212 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) {
213 mTarget->LDR(cc, Rd, Rn, offset);
215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
216 mTarget->LDRB(cc, Rd, Rn, offset)
[all...] |
| Arm64Assembler.h | 99 int Rd, int Rn,
102 int Rd, int Rm, int Rs, int Rn);
116 virtual void BX(int cc, int Rn);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t Op2);
128 int Rn, uint32_t Op2);
130 int Rn, uint32_t offset = 0);
133 int Rn, uint32_t offset = 0);
135 int Rn, uint32_t offset = 0);
137 int Rn, uint32_t offset = 0)
[all...] |
| ARMAssemblerProxy.h | 80 int Rd, int Rn,
83 int Rd, int Rm, int Rs, int Rn);
97 virtual void BX(int cc, int Rn);
105 int Rn, uint32_t offset = __immed12_pre(0));
107 int Rn, uint32_t offset = __immed12_pre(0));
109 int Rn, uint32_t offset = __immed12_pre(0));
111 int Rn, uint32_t offset = __immed12_pre(0));
113 int Rn, uint32_t offset = __immed8_pre(0));
115 int Rn, uint32_t offset = __immed8_pre(0));
117 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| ARMAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = __immed12_pre(0));
118 int Rn, uint32_t offset = __immed12_pre(0));
120 int Rn, uint32_t offset = __immed12_pre(0));
122 int Rn, uint32_t offset = __immed12_pre(0));
124 int Rn, uint32_t offset = __immed8_pre(0));
126 int Rn, uint32_t offset = __immed8_pre(0));
128 int Rn, uint32_t offset = __immed8_pre(0))
[all...] |
| MIPS64Assembler.cpp | 395 int s, int Rd, int Rn, uint32_t Op2)
411 mMips->AND(Rd, Rn, src);
413 mMips->ANDI(Rd, Rn, src);
420 mMips->ADDU(Rd, Rn, src);
422 mMips->ADDIU(Rd, Rn, src);
429 mMips->SUBU(Rd, Rn, src);
431 mMips->SUBIU(Rd, Rn, src);
438 mMips->DADDU(Rd, Rn, src);
440 mMips->DADDIU(Rd, Rn, src);
447 mMips->DSUBU(Rd, Rn, src)
[all...] |
| ARMAssembler.cpp | 203 int s, int Rd, int Rn, uint32_t Op2)
205 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
215 int Rd, int Rm, int Rs, int Rn) {
217 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
219 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
274 void ARMAssembler::BX(int cc, int Rn)
276 *mPC++ = (cc<<28) | 0x12FFF10 | Rn;
285 void ARMAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) {
286 *mPC++ = (cc<<28) | (1<<26) | (1<<20) | (Rn<<16) | (Rd<<12) | offset;
288 void ARMAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
[all...] |
| MIPS64Assembler.h | 96 int Rd, int Rn,
99 int Rd, int Rm, int Rs, int Rn);
113 virtual void BX(int cc, int Rn);
121 int Rn, uint32_t offset = 0);
123 int Rn, uint32_t offset = 0);
125 int Rn, uint32_t offset = 0);
127 int Rn, uint32_t offset = 0);
129 int Rn, uint32_t offset = 0);
131 int Rn, uint32_t offset = 0);
133 int Rn, uint32_t offset = 0)
[all...] |
| MIPSAssembler.cpp | 413 int s, int Rd, int Rn, uint32_t Op2)
430 mMips->AND(Rd, Rn, src);
432 mMips->ANDI(Rd, Rn, src);
439 mMips->ADDU(Rd, Rn, src);
441 mMips->ADDIU(Rd, Rn, src);
448 mMips->SUBU(Rd, Rn, src);
450 mMips->SUBIU(Rd, Rn, src);
456 mMips->XOR(Rd, Rn, src);
458 mMips->XORI(Rd, Rn, src);
464 mMips->OR(Rd, Rn, src)
[all...] |
| MIPSAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = 0);
118 int Rn, uint32_t offset = 0);
120 int Rn, uint32_t offset = 0);
122 int Rn, uint32_t offset = 0);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t offset = 0);
128 int Rn, uint32_t offset = 0)
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| tic30.h | 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arm3-bad.l | 2 .*arm3-bad.s:4: Error: Rn must not overlap other operands -- `swp r0,r1,\[r0\]'
3 .*arm3-bad.s:5: Error: Rn must not overlap other operands -- `swp r1,r0,\[r0\]'
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ArmDisassembler.c | 171 UINT32 Rn, Rd, Rm;
184 Rn = (OpCode >> 16) & 0xf;
198 // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
199 AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
201 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
202 AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
210 // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
211 // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
212 // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
[all...] |
| ThumbDisassembler.c | 149 { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
150 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
154 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
157 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
187 { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
188 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
190 { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
191 { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
192 { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]
193 { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| addsub.s | 27 .macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
35 \op \rd, \rn, W\()\rm_n, \extend
37 \op \rd, \rn, W\()\rm_n, \extend #\amount
46 \op \rd, \rn, \rm_r\()\rm_n, \extend
48 \op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
55 .macro do_addsub_ext type, op, Rn, reg, extend, amount
59 \op \reg\()16, \Rn, \reg\()1
62 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
64 adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
71 \op \reg\()ZR, \Rn, \reg\()
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/rc4/ |
| rc4_arm.s | 12 #define Rn R2
26 MOVW n+8(FP), Rn
56 CMP Rk, Rn
|
| /prebuilts/go/linux-x86/src/crypto/rc4/ |
| rc4_arm.s | 12 #define Rn R2
26 MOVW n+8(FP), Rn
56 CMP Rk, Rn
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| decode.go | 413 Rn := Reg((x >> 16) & (1<<4 - 1))
414 return Mem{Base: Rn, Mode: AddrOffset}
417 // Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!}
422 // Treat [<Rn>,+/-<Rm>]{!} like [<Rn>,+/-<Rm>{,<shift>}]{!}
427 // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!}
432 // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!
[all...] |
| tables.go | [all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| decode.go | 413 Rn := Reg((x >> 16) & (1<<4 - 1))
414 return Mem{Base: Rn, Mode: AddrOffset}
417 // Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!}
422 // Treat [<Rn>,+/-<Rm>]{!} like [<Rn>,+/-<Rm>{,<shift>}]{!}
427 // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!}
432 // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!
[all...] |
| tables.go | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
