1 /* 2 * Copyright 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <stdint.h> 27 #include "brw_reg.h" 28 #include "brw_defines.h" 29 #include "brw_context.h" 30 #include "compiler/nir/nir.h" 31 32 #ifdef __cplusplus 33 #include "brw_ir_allocator.h" 34 #endif 35 36 #define MAX_SAMPLER_MESSAGE_SIZE 11 37 #define MAX_VGRF_SIZE 16 38 39 #ifdef __cplusplus 40 struct backend_reg : private brw_reg 41 { 42 backend_reg() {} 43 backend_reg(const struct brw_reg ®) : brw_reg(reg) {} 44 45 const brw_reg &as_brw_reg() const 46 { 47 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); 48 assert(offset == 0); 49 return static_cast<const brw_reg &>(*this); 50 } 51 52 brw_reg &as_brw_reg() 53 { 54 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); 55 assert(offset == 0); 56 return static_cast<brw_reg &>(*this); 57 } 58 59 bool equals(const backend_reg &r) const; 60 61 bool is_zero() const; 62 bool is_one() const; 63 bool is_negative_one() const; 64 bool is_null() const; 65 bool is_accumulator() const; 66 67 /** Offset from the start of the (virtual) register in bytes. */ 68 uint16_t offset; 69 70 using brw_reg::type; 71 using brw_reg::file; 72 using brw_reg::negate; 73 using brw_reg::abs; 74 using brw_reg::address_mode; 75 using brw_reg::subnr; 76 using brw_reg::nr; 77 78 using brw_reg::swizzle; 79 using brw_reg::writemask; 80 using brw_reg::indirect_offset; 81 using brw_reg::vstride; 82 using brw_reg::width; 83 using brw_reg::hstride; 84 85 using brw_reg::df; 86 using brw_reg::f; 87 using brw_reg::d; 88 using brw_reg::ud; 89 }; 90 #endif 91 92 struct cfg_t; 93 struct bblock_t; 94 95 #ifdef __cplusplus 96 struct backend_instruction : public exec_node { 97 bool is_3src(const struct gen_device_info *devinfo) const; 98 bool is_tex() const; 99 bool is_math() const; 100 bool is_control_flow() const; 101 bool is_commutative() const; 102 bool can_do_source_mods() const; 103 bool can_do_saturate() const; 104 bool can_do_cmod() const; 105 bool reads_accumulator_implicitly() const; 106 bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const; 107 108 void remove(bblock_t *block); 109 void insert_after(bblock_t *block, backend_instruction *inst); 110 void insert_before(bblock_t *block, backend_instruction *inst); 111 void insert_before(bblock_t *block, exec_list *list); 112 113 /** 114 * True if the instruction has side effects other than writing to 115 * its destination registers. You are expected not to reorder or 116 * optimize these out unless you know what you are doing. 117 */ 118 bool has_side_effects() const; 119 120 /** 121 * True if the instruction might be affected by side effects of other 122 * instructions. 123 */ 124 bool is_volatile() const; 125 #else 126 struct backend_instruction { 127 struct exec_node link; 128 #endif 129 /** @{ 130 * Annotation for the generated IR. One of the two can be set. 131 */ 132 const void *ir; 133 const char *annotation; 134 /** @} */ 135 136 /** 137 * Execution size of the instruction. This is used by the generator to 138 * generate the correct binary for the given instruction. Current valid 139 * values are 1, 4, 8, 16, 32. 140 */ 141 uint8_t exec_size; 142 143 /** 144 * Channel group from the hardware execution and predication mask that 145 * should be applied to the instruction. The subset of channel enable 146 * signals (calculated from the EU control flow and predication state) 147 * given by [group, group + exec_size) will be used to mask GRF writes and 148 * any other side effects of the instruction. 149 */ 150 uint8_t group; 151 152 uint32_t offset; /**< spill/unspill offset or texture offset bitfield */ 153 uint8_t mlen; /**< SEND message length */ 154 int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ 155 uint8_t target; /**< MRT target. */ 156 unsigned size_written; /**< Data written to the destination register in bytes. */ 157 158 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ 159 enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */ 160 enum brw_predicate predicate; 161 bool predicate_inverse:1; 162 bool writes_accumulator:1; /**< instruction implicitly writes accumulator */ 163 bool force_writemask_all:1; 164 bool no_dd_clear:1; 165 bool no_dd_check:1; 166 bool saturate:1; 167 bool shadow_compare:1; 168 169 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional 170 * mod and predication. 171 */ 172 unsigned flag_subreg:1; 173 174 /** The number of hardware registers used for a message header. */ 175 uint8_t header_size; 176 }; 177 178 #ifdef __cplusplus 179 180 enum instruction_scheduler_mode { 181 SCHEDULE_PRE, 182 SCHEDULE_PRE_NON_LIFO, 183 SCHEDULE_PRE_LIFO, 184 SCHEDULE_POST, 185 }; 186 187 struct backend_shader { 188 protected: 189 190 backend_shader(const struct brw_compiler *compiler, 191 void *log_data, 192 void *mem_ctx, 193 const nir_shader *shader, 194 struct brw_stage_prog_data *stage_prog_data); 195 196 public: 197 198 const struct brw_compiler *compiler; 199 void *log_data; /* Passed to compiler->*_log functions */ 200 201 const struct gen_device_info * const devinfo; 202 const nir_shader *nir; 203 struct brw_stage_prog_data * const stage_prog_data; 204 205 /** ralloc context for temporary data used during compile */ 206 void *mem_ctx; 207 208 /** 209 * List of either fs_inst or vec4_instruction (inheriting from 210 * backend_instruction) 211 */ 212 exec_list instructions; 213 214 cfg_t *cfg; 215 216 gl_shader_stage stage; 217 bool debug_enabled; 218 const char *stage_name; 219 const char *stage_abbrev; 220 221 brw::simple_allocator alloc; 222 223 virtual void dump_instruction(backend_instruction *inst) = 0; 224 virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0; 225 virtual void dump_instructions(); 226 virtual void dump_instructions(const char *name); 227 228 void calculate_cfg(); 229 230 virtual void invalidate_live_intervals() = 0; 231 }; 232 233 bool brw_texture_offset(int *offsets, 234 unsigned num_components, 235 uint32_t *offset_bits); 236 237 void brw_setup_image_uniform_values(gl_shader_stage stage, 238 struct brw_stage_prog_data *stage_prog_data, 239 unsigned param_start_index, 240 const gl_uniform_storage *storage); 241 242 #else 243 struct backend_shader; 244 #endif /* __cplusplus */ 245 246 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type); 247 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op); 248 uint32_t brw_math_function(enum opcode op); 249 const char *brw_instruction_name(const struct gen_device_info *devinfo, 250 enum opcode op); 251 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg); 252 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg); 253 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg); 254 255 bool opt_predicated_break(struct backend_shader *s); 256 257 #ifdef __cplusplus 258 extern "C" { 259 #endif 260 261 /** 262 * Scratch data used when compiling a GLSL geometry shader. 263 */ 264 struct brw_gs_compile 265 { 266 struct brw_gs_prog_key key; 267 struct brw_vue_map input_vue_map; 268 269 unsigned control_data_bits_per_vertex; 270 unsigned control_data_header_size_bits; 271 }; 272 273 uint32_t 274 brw_assign_common_binding_table_offsets(const struct gen_device_info *devinfo, 275 const struct gl_program *prog, 276 struct brw_stage_prog_data *stage_prog_data, 277 uint32_t next_binding_table_offset); 278 279 bool brw_vs_precompile(struct gl_context *ctx, struct gl_program *prog); 280 bool brw_tcs_precompile(struct gl_context *ctx, 281 struct gl_shader_program *shader_prog, 282 struct gl_program *prog); 283 bool brw_tes_precompile(struct gl_context *ctx, 284 struct gl_shader_program *shader_prog, 285 struct gl_program *prog); 286 bool brw_gs_precompile(struct gl_context *ctx, struct gl_program *prog); 287 bool brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog); 288 bool brw_cs_precompile(struct gl_context *ctx, struct gl_program *prog); 289 290 GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog); 291 struct gl_linked_shader *brw_new_shader(gl_shader_stage stage); 292 293 unsigned get_atomic_counter_op(nir_intrinsic_op op); 294 295 #ifdef __cplusplus 296 } 297 #endif 298
