| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegisterScavenging.cpp | 356 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
359 if (!isAliasUsed(SReg)) {
360 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
361 return SReg;
368 ScavengedReg = SReg;
372 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
376 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
381 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
389 // ScavengedReg = SReg;
392 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
[all...] |
| VirtRegRewriter.cpp | 533 unsigned SReg = *SR;
534 if (RegKills[SReg] && KillOps[SReg]->getParent() != &MI)
535 ResurrectConfirmedKill(SReg, TRI, RegKills, KillOps);
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 373 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
376 if (!isRegUsed(SReg)) {
377 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
378 return SReg;
420 Scavenged[SI].Reg = SReg;
424 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
429 TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) +
433 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
441 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
452 // Scavenged[SI].Reg = SReg;
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 352 unsigned SReg = Src2->getReg();
353 if (TargetRegisterInfo::isVirtualRegister(SReg)) {
354 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);
357 if (SReg != AMDGPU::VCC)
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 596 unsigned SReg;
598 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
600 SReg = PPC::R0;
603 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
605 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
606 .addReg(SReg, RegState::Kill)
627 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
251 OutStreamer.AddComment(Twine(SReg));
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
