1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "PPCTargetMachine.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/IR/CallingConv.h" 31 #include "llvm/IR/Constants.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/Type.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/MathExtras.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/Target/TargetFrameLowering.h" 40 #include "llvm/Target/TargetInstrInfo.h" 41 #include "llvm/Target/TargetMachine.h" 42 #include "llvm/Target/TargetOptions.h" 43 #include <cstdlib> 44 45 using namespace llvm; 46 47 #define DEBUG_TYPE "reginfo" 48 49 #define GET_REGINFO_TARGET_DESC 50 #include "PPCGenRegisterInfo.inc" 51 52 static cl::opt<bool> 53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 54 cl::desc("Enable use of a base pointer for complex stack frames")); 55 56 static cl::opt<bool> 57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 58 cl::desc("Force the use of a base pointer in every function")); 59 60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) 61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, 62 TM.isPPC64() ? 0 : 1, 63 TM.isPPC64() ? 0 : 1), 64 TM(TM) { 65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 74 75 // 64-bit 76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 81 } 82 83 /// getPointerRegClass - Return the register class to use to hold pointers. 84 /// This is used for addressing modes. 85 const TargetRegisterClass * 86 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 87 const { 88 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 89 // when it checks for ZERO folding. 90 if (Kind == 1) { 91 if (TM.isPPC64()) 92 return &PPC::G8RC_NOX0RegClass; 93 return &PPC::GPRC_NOR0RegClass; 94 } 95 96 if (TM.isPPC64()) 97 return &PPC::G8RCRegClass; 98 return &PPC::GPRCRegClass; 99 } 100 101 const MCPhysReg* 102 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 104 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { 105 if (Subtarget.hasVSX()) 106 return CSR_64_AllRegs_VSX_SaveList; 107 if (Subtarget.hasAltivec()) 108 return CSR_64_AllRegs_Altivec_SaveList; 109 return CSR_64_AllRegs_SaveList; 110 } 111 112 if (Subtarget.isDarwinABI()) 113 return TM.isPPC64() 114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList 115 : CSR_Darwin64_SaveList) 116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList 117 : CSR_Darwin32_SaveList); 118 119 if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR()) 120 return CSR_SRV464_TLS_PE_SaveList; 121 122 // On PPC64, we might need to save r2 (but only if it is not reserved). 123 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); 124 125 return TM.isPPC64() 126 ? (Subtarget.hasAltivec() 127 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList 128 : CSR_SVR464_Altivec_SaveList) 129 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList)) 130 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList 131 : CSR_SVR432_SaveList); 132 } 133 134 const MCPhysReg * 135 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const { 136 assert(MF && "Invalid MachineFunction pointer."); 137 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 138 if (Subtarget.isDarwinABI()) 139 return nullptr; 140 if (!TM.isPPC64()) 141 return nullptr; 142 if (MF->getFunction()->getCallingConv() != CallingConv::CXX_FAST_TLS) 143 return nullptr; 144 if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR()) 145 return nullptr; 146 147 // On PPC64, we might need to save r2 (but only if it is not reserved). 148 bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2); 149 if (Subtarget.hasAltivec()) 150 return SaveR2 151 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList 152 : CSR_SVR464_Altivec_ViaCopy_SaveList; 153 else 154 return SaveR2 155 ? CSR_SVR464_R2_ViaCopy_SaveList 156 : CSR_SVR464_ViaCopy_SaveList; 157 } 158 159 const uint32_t * 160 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 161 CallingConv::ID CC) const { 162 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 163 if (CC == CallingConv::AnyReg) { 164 if (Subtarget.hasVSX()) 165 return CSR_64_AllRegs_VSX_RegMask; 166 if (Subtarget.hasAltivec()) 167 return CSR_64_AllRegs_Altivec_RegMask; 168 return CSR_64_AllRegs_RegMask; 169 } 170 171 if (Subtarget.isDarwinABI()) 172 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask 173 : CSR_Darwin64_RegMask) 174 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask 175 : CSR_Darwin32_RegMask); 176 177 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask 178 : CSR_SVR464_RegMask) 179 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask 180 : CSR_SVR432_RegMask); 181 } 182 183 const uint32_t* 184 PPCRegisterInfo::getNoPreservedMask() const { 185 return CSR_NoRegs_RegMask; 186 } 187 188 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 189 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) 190 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); 191 } 192 193 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 194 BitVector Reserved(getNumRegs()); 195 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 196 const PPCFrameLowering *TFI = getFrameLowering(MF); 197 198 // The ZERO register is not really a register, but the representation of r0 199 // when used in instructions that treat r0 as the constant 0. 200 Reserved.set(PPC::ZERO); 201 Reserved.set(PPC::ZERO8); 202 203 // The FP register is also not really a register, but is the representation 204 // of the frame pointer register used by ISD::FRAMEADDR. 205 Reserved.set(PPC::FP); 206 Reserved.set(PPC::FP8); 207 208 // The BP register is also not really a register, but is the representation 209 // of the base pointer register used by setjmp. 210 Reserved.set(PPC::BP); 211 Reserved.set(PPC::BP8); 212 213 // The counter registers must be reserved so that counter-based loops can 214 // be correctly formed (and the mtctr instructions are not DCE'd). 215 Reserved.set(PPC::CTR); 216 Reserved.set(PPC::CTR8); 217 218 Reserved.set(PPC::R1); 219 Reserved.set(PPC::LR); 220 Reserved.set(PPC::LR8); 221 Reserved.set(PPC::RM); 222 223 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 224 Reserved.set(PPC::VRSAVE); 225 226 // The SVR4 ABI reserves r2 and r13 227 if (Subtarget.isSVR4ABI()) { 228 Reserved.set(PPC::R2); // System-reserved register 229 Reserved.set(PPC::R13); // Small Data Area pointer register 230 } 231 232 // On PPC64, r13 is the thread pointer. Never allocate this register. 233 if (TM.isPPC64()) { 234 Reserved.set(PPC::R13); 235 236 Reserved.set(PPC::X1); 237 Reserved.set(PPC::X13); 238 239 if (TFI->needsFP(MF)) 240 Reserved.set(PPC::X31); 241 242 if (hasBasePointer(MF)) 243 Reserved.set(PPC::X30); 244 245 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 246 if (Subtarget.isSVR4ABI()) { 247 // We only reserve r2 if we need to use the TOC pointer. If we have no 248 // explicit uses of the TOC pointer (meaning we're a leaf function with 249 // no constant-pool loads, etc.) and we have no potential uses inside an 250 // inline asm block, then we can treat r2 has an ordinary callee-saved 251 // register. 252 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 253 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 254 Reserved.set(PPC::X2); 255 else 256 Reserved.reset(PPC::R2); 257 } 258 } 259 260 if (TFI->needsFP(MF)) 261 Reserved.set(PPC::R31); 262 263 bool IsPositionIndependent = TM.isPositionIndependent(); 264 if (hasBasePointer(MF)) { 265 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent) 266 Reserved.set(PPC::R29); 267 else 268 Reserved.set(PPC::R30); 269 } 270 271 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent) 272 Reserved.set(PPC::R30); 273 274 // Reserve Altivec registers when Altivec is unavailable. 275 if (!Subtarget.hasAltivec()) 276 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 277 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 278 Reserved.set(*I); 279 280 return Reserved; 281 } 282 283 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 284 MachineFunction &MF) const { 285 const PPCFrameLowering *TFI = getFrameLowering(MF); 286 const unsigned DefaultSafety = 1; 287 288 switch (RC->getID()) { 289 default: 290 return 0; 291 case PPC::G8RC_NOX0RegClassID: 292 case PPC::GPRC_NOR0RegClassID: 293 case PPC::G8RCRegClassID: 294 case PPC::GPRCRegClassID: { 295 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 296 return 32 - FP - DefaultSafety; 297 } 298 case PPC::F8RCRegClassID: 299 case PPC::F4RCRegClassID: 300 case PPC::QFRCRegClassID: 301 case PPC::QSRCRegClassID: 302 case PPC::QBRCRegClassID: 303 case PPC::VRRCRegClassID: 304 case PPC::VFRCRegClassID: 305 case PPC::VSLRCRegClassID: 306 case PPC::VSHRCRegClassID: 307 return 32 - DefaultSafety; 308 case PPC::VSRCRegClassID: 309 case PPC::VSFRCRegClassID: 310 case PPC::VSSRCRegClassID: 311 return 64 - DefaultSafety; 312 case PPC::CRRCRegClassID: 313 return 8 - DefaultSafety; 314 } 315 } 316 317 const TargetRegisterClass * 318 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 319 const MachineFunction &MF) const { 320 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 321 if (Subtarget.hasVSX()) { 322 // With VSX, we can inflate various sub-register classes to the full VSX 323 // register set. 324 325 if (RC == &PPC::F8RCRegClass) 326 return &PPC::VSFRCRegClass; 327 else if (RC == &PPC::VRRCRegClass) 328 return &PPC::VSRCRegClass; 329 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector()) 330 return &PPC::VSSRCRegClass; 331 } 332 333 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 334 } 335 336 //===----------------------------------------------------------------------===// 337 // Stack Frame Processing methods 338 //===----------------------------------------------------------------------===// 339 340 /// lowerDynamicAlloc - Generate the code for allocating an object in the 341 /// current frame. The sequence of code will be in the general form 342 /// 343 /// addi R0, SP, \#frameSize ; get the address of the previous frame 344 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 345 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 346 /// 347 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 348 // Get the instruction. 349 MachineInstr &MI = *II; 350 // Get the instruction's basic block. 351 MachineBasicBlock &MBB = *MI.getParent(); 352 // Get the basic block's function. 353 MachineFunction &MF = *MBB.getParent(); 354 // Get the frame info. 355 MachineFrameInfo *MFI = MF.getFrameInfo(); 356 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 357 // Get the instruction info. 358 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 359 // Determine whether 64-bit pointers are used. 360 bool LP64 = TM.isPPC64(); 361 DebugLoc dl = MI.getDebugLoc(); 362 363 // Get the maximum call stack size. 364 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 365 // Get the total frame size. 366 unsigned FrameSize = MFI->getStackSize(); 367 368 // Get stack alignments. 369 const PPCFrameLowering *TFI = getFrameLowering(MF); 370 unsigned TargetAlign = TFI->getStackAlignment(); 371 unsigned MaxAlign = MFI->getMaxAlignment(); 372 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 373 "Maximum call-frame size not sufficiently aligned"); 374 375 // Determine the previous frame's address. If FrameSize can't be 376 // represented as 16 bits or we need special alignment, then we load the 377 // previous frame's address from 0(SP). Why not do an addis of the hi? 378 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 379 // Constructing the constant and adding would take 3 instructions. 380 // Fortunately, a frame greater than 32K is rare. 381 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 382 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 383 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 384 385 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 386 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 387 .addReg(PPC::R31) 388 .addImm(FrameSize); 389 } else if (LP64) { 390 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 391 .addImm(0) 392 .addReg(PPC::X1); 393 } else { 394 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 395 .addImm(0) 396 .addReg(PPC::R1); 397 } 398 399 bool KillNegSizeReg = MI.getOperand(1).isKill(); 400 unsigned NegSizeReg = MI.getOperand(1).getReg(); 401 402 // Grow the stack and update the stack pointer link, then determine the 403 // address of new allocated space. 404 if (LP64) { 405 if (MaxAlign > TargetAlign) { 406 unsigned UnalNegSizeReg = NegSizeReg; 407 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 408 409 // Unfortunately, there is no andi, only andi., and we can't insert that 410 // here because we might clobber cr0 while it is live. 411 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 412 .addImm(~(MaxAlign-1)); 413 414 unsigned NegSizeReg1 = NegSizeReg; 415 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 416 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 417 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 418 .addReg(NegSizeReg1, RegState::Kill); 419 KillNegSizeReg = true; 420 } 421 422 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 423 .addReg(Reg, RegState::Kill) 424 .addReg(PPC::X1) 425 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 426 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 427 .addReg(PPC::X1) 428 .addImm(maxCallFrameSize); 429 } else { 430 if (MaxAlign > TargetAlign) { 431 unsigned UnalNegSizeReg = NegSizeReg; 432 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 433 434 // Unfortunately, there is no andi, only andi., and we can't insert that 435 // here because we might clobber cr0 while it is live. 436 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 437 .addImm(~(MaxAlign-1)); 438 439 unsigned NegSizeReg1 = NegSizeReg; 440 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 441 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 442 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 443 .addReg(NegSizeReg1, RegState::Kill); 444 KillNegSizeReg = true; 445 } 446 447 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 448 .addReg(Reg, RegState::Kill) 449 .addReg(PPC::R1) 450 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 451 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 452 .addReg(PPC::R1) 453 .addImm(maxCallFrameSize); 454 } 455 456 // Discard the DYNALLOC instruction. 457 MBB.erase(II); 458 } 459 460 void PPCRegisterInfo::lowerDynamicAreaOffset( 461 MachineBasicBlock::iterator II) const { 462 // Get the instruction. 463 MachineInstr &MI = *II; 464 // Get the instruction's basic block. 465 MachineBasicBlock &MBB = *MI.getParent(); 466 // Get the basic block's function. 467 MachineFunction &MF = *MBB.getParent(); 468 // Get the frame info. 469 MachineFrameInfo *MFI = MF.getFrameInfo(); 470 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 471 // Get the instruction info. 472 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 473 474 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 475 DebugLoc dl = MI.getDebugLoc(); 476 BuildMI(MBB, II, dl, TII.get(PPC::LI), MI.getOperand(0).getReg()) 477 .addImm(maxCallFrameSize); 478 MBB.erase(II); 479 } 480 481 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 482 /// reserving a whole register (R0), we scrounge for one here. This generates 483 /// code like this: 484 /// 485 /// mfcr rA ; Move the conditional register into GPR rA. 486 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 487 /// stw rA, FI ; Store rA to the frame. 488 /// 489 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 490 unsigned FrameIndex) const { 491 // Get the instruction. 492 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 493 // Get the instruction's basic block. 494 MachineBasicBlock &MBB = *MI.getParent(); 495 MachineFunction &MF = *MBB.getParent(); 496 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 497 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 498 DebugLoc dl = MI.getDebugLoc(); 499 500 bool LP64 = TM.isPPC64(); 501 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 502 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 503 504 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 505 unsigned SrcReg = MI.getOperand(0).getReg(); 506 507 // We need to store the CR in the low 4-bits of the saved value. First, issue 508 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 509 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 510 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 511 512 // If the saved register wasn't CR0, shift the bits left so that they are in 513 // CR0's slot. 514 if (SrcReg != PPC::CR0) { 515 unsigned Reg1 = Reg; 516 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 517 518 // rlwinm rA, rA, ShiftBits, 0, 31. 519 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 520 .addReg(Reg1, RegState::Kill) 521 .addImm(getEncodingValue(SrcReg) * 4) 522 .addImm(0) 523 .addImm(31); 524 } 525 526 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 527 .addReg(Reg, RegState::Kill), 528 FrameIndex); 529 530 // Discard the pseudo instruction. 531 MBB.erase(II); 532 } 533 534 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 535 unsigned FrameIndex) const { 536 // Get the instruction. 537 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 538 // Get the instruction's basic block. 539 MachineBasicBlock &MBB = *MI.getParent(); 540 MachineFunction &MF = *MBB.getParent(); 541 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 542 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 543 DebugLoc dl = MI.getDebugLoc(); 544 545 bool LP64 = TM.isPPC64(); 546 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 547 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 548 549 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 550 unsigned DestReg = MI.getOperand(0).getReg(); 551 assert(MI.definesRegister(DestReg) && 552 "RESTORE_CR does not define its destination"); 553 554 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 555 Reg), FrameIndex); 556 557 // If the reloaded register isn't CR0, shift the bits right so that they are 558 // in the right CR's slot. 559 if (DestReg != PPC::CR0) { 560 unsigned Reg1 = Reg; 561 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 562 563 unsigned ShiftBits = getEncodingValue(DestReg)*4; 564 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 565 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 566 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 567 .addImm(31); 568 } 569 570 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 571 .addReg(Reg, RegState::Kill); 572 573 // Discard the pseudo instruction. 574 MBB.erase(II); 575 } 576 577 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 578 unsigned FrameIndex) const { 579 // Get the instruction. 580 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 581 // Get the instruction's basic block. 582 MachineBasicBlock &MBB = *MI.getParent(); 583 MachineFunction &MF = *MBB.getParent(); 584 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 585 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 586 DebugLoc dl = MI.getDebugLoc(); 587 588 bool LP64 = TM.isPPC64(); 589 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 590 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 591 592 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 593 unsigned SrcReg = MI.getOperand(0).getReg(); 594 595 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 596 getCRFromCRBit(SrcReg)) 597 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 598 599 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 600 .addReg(getCRFromCRBit(SrcReg)); 601 602 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 603 // store is the first one. Mask all but that bit. 604 unsigned Reg1 = Reg; 605 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 606 607 // rlwinm rA, rA, ShiftBits, 0, 0. 608 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 609 .addReg(Reg1, RegState::Kill) 610 .addImm(getEncodingValue(SrcReg)) 611 .addImm(0).addImm(0); 612 613 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 614 .addReg(Reg, RegState::Kill), 615 FrameIndex); 616 617 // Discard the pseudo instruction. 618 MBB.erase(II); 619 } 620 621 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 622 unsigned FrameIndex) const { 623 // Get the instruction. 624 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 625 // Get the instruction's basic block. 626 MachineBasicBlock &MBB = *MI.getParent(); 627 MachineFunction &MF = *MBB.getParent(); 628 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 629 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 630 DebugLoc dl = MI.getDebugLoc(); 631 632 bool LP64 = TM.isPPC64(); 633 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 634 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 635 636 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 637 unsigned DestReg = MI.getOperand(0).getReg(); 638 assert(MI.definesRegister(DestReg) && 639 "RESTORE_CRBIT does not define its destination"); 640 641 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 642 Reg), FrameIndex); 643 644 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 645 646 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 647 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 648 .addReg(getCRFromCRBit(DestReg)); 649 650 unsigned ShiftBits = getEncodingValue(DestReg); 651 // rlwimi r11, r10, 32-ShiftBits, ..., ... 652 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 653 .addReg(RegO, RegState::Kill) 654 .addReg(Reg, RegState::Kill) 655 .addImm(ShiftBits ? 32 - ShiftBits : 0) 656 .addImm(ShiftBits) 657 .addImm(ShiftBits); 658 659 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 660 getCRFromCRBit(DestReg)) 661 .addReg(RegO, RegState::Kill) 662 // Make sure we have a use dependency all the way through this 663 // sequence of instructions. We can't have the other bits in the CR 664 // modified in between the mfocrf and the mtocrf. 665 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 666 667 // Discard the pseudo instruction. 668 MBB.erase(II); 669 } 670 671 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 672 unsigned FrameIndex) const { 673 // Get the instruction. 674 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 675 // Get the instruction's basic block. 676 MachineBasicBlock &MBB = *MI.getParent(); 677 MachineFunction &MF = *MBB.getParent(); 678 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 679 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 680 DebugLoc dl = MI.getDebugLoc(); 681 682 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 683 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 684 unsigned SrcReg = MI.getOperand(0).getReg(); 685 686 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 687 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 688 689 addFrameReference( 690 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill), 691 FrameIndex); 692 693 // Discard the pseudo instruction. 694 MBB.erase(II); 695 } 696 697 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 698 unsigned FrameIndex) const { 699 // Get the instruction. 700 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 701 // Get the instruction's basic block. 702 MachineBasicBlock &MBB = *MI.getParent(); 703 MachineFunction &MF = *MBB.getParent(); 704 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 705 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 706 DebugLoc dl = MI.getDebugLoc(); 707 708 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 709 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 710 unsigned DestReg = MI.getOperand(0).getReg(); 711 assert(MI.definesRegister(DestReg) && 712 "RESTORE_VRSAVE does not define its destination"); 713 714 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 715 Reg), FrameIndex); 716 717 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 718 .addReg(Reg, RegState::Kill); 719 720 // Discard the pseudo instruction. 721 MBB.erase(II); 722 } 723 724 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 725 unsigned Reg, int &FrameIdx) const { 726 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 727 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 728 // ABI, return true to prevent allocating an additional frame slot. 729 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 730 // is arbitrary and will be subsequently ignored. For 32-bit, we have 731 // previously created the stack slot if needed, so return its FrameIdx. 732 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 733 if (TM.isPPC64()) 734 FrameIdx = 0; 735 else { 736 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 737 FrameIdx = FI->getCRSpillFrameIndex(); 738 } 739 return true; 740 } 741 return false; 742 } 743 744 // Figure out if the offset in the instruction must be a multiple of 4. 745 // This is true for instructions like "STD". 746 static bool usesIXAddr(const MachineInstr &MI) { 747 unsigned OpC = MI.getOpcode(); 748 749 switch (OpC) { 750 default: 751 return false; 752 case PPC::LWA: 753 case PPC::LWA_32: 754 case PPC::LD: 755 case PPC::STD: 756 return true; 757 } 758 } 759 760 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 761 static unsigned getOffsetONFromFION(const MachineInstr &MI, 762 unsigned FIOperandNum) { 763 // Take into account whether it's an add or mem instruction 764 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 765 if (MI.isInlineAsm()) 766 OffsetOperandNo = FIOperandNum - 1; 767 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 768 MI.getOpcode() == TargetOpcode::PATCHPOINT) 769 OffsetOperandNo = FIOperandNum + 1; 770 771 return OffsetOperandNo; 772 } 773 774 void 775 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 776 int SPAdj, unsigned FIOperandNum, 777 RegScavenger *RS) const { 778 assert(SPAdj == 0 && "Unexpected"); 779 780 // Get the instruction. 781 MachineInstr &MI = *II; 782 // Get the instruction's basic block. 783 MachineBasicBlock &MBB = *MI.getParent(); 784 // Get the basic block's function. 785 MachineFunction &MF = *MBB.getParent(); 786 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 787 // Get the instruction info. 788 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 789 // Get the frame info. 790 MachineFrameInfo *MFI = MF.getFrameInfo(); 791 DebugLoc dl = MI.getDebugLoc(); 792 793 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 794 795 // Get the frame index. 796 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 797 798 // Get the frame pointer save index. Users of this index are primarily 799 // DYNALLOC instructions. 800 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 801 int FPSI = FI->getFramePointerSaveIndex(); 802 // Get the instruction opcode. 803 unsigned OpC = MI.getOpcode(); 804 805 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) { 806 lowerDynamicAreaOffset(II); 807 return; 808 } 809 810 // Special case for dynamic alloca. 811 if (FPSI && FrameIndex == FPSI && 812 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 813 lowerDynamicAlloc(II); 814 return; 815 } 816 817 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 818 if (OpC == PPC::SPILL_CR) { 819 lowerCRSpilling(II, FrameIndex); 820 return; 821 } else if (OpC == PPC::RESTORE_CR) { 822 lowerCRRestore(II, FrameIndex); 823 return; 824 } else if (OpC == PPC::SPILL_CRBIT) { 825 lowerCRBitSpilling(II, FrameIndex); 826 return; 827 } else if (OpC == PPC::RESTORE_CRBIT) { 828 lowerCRBitRestore(II, FrameIndex); 829 return; 830 } else if (OpC == PPC::SPILL_VRSAVE) { 831 lowerVRSAVESpilling(II, FrameIndex); 832 return; 833 } else if (OpC == PPC::RESTORE_VRSAVE) { 834 lowerVRSAVERestore(II, FrameIndex); 835 return; 836 } 837 838 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 839 MI.getOperand(FIOperandNum).ChangeToRegister( 840 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 841 842 // Figure out if the offset in the instruction is shifted right two bits. 843 bool isIXAddr = usesIXAddr(MI); 844 845 // If the instruction is not present in ImmToIdxMap, then it has no immediate 846 // form (and must be r+r). 847 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 848 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 849 850 // Now add the frame object offset to the offset from r1. 851 int Offset = MFI->getObjectOffset(FrameIndex); 852 Offset += MI.getOperand(OffsetOperandNo).getImm(); 853 854 // If we're not using a Frame Pointer that has been set to the value of the 855 // SP before having the stack size subtracted from it, then add the stack size 856 // to Offset to get the correct offset. 857 // Naked functions have stack size 0, although getStackSize may not reflect 858 // that because we didn't call all the pieces that compute it for naked 859 // functions. 860 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) { 861 if (!(hasBasePointer(MF) && FrameIndex < 0)) 862 Offset += MFI->getStackSize(); 863 } 864 865 // If we can, encode the offset directly into the instruction. If this is a 866 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 867 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 868 // clear can be encoded. This is extremely uncommon, because normally you 869 // only "std" to a stack slot that is at least 4-byte aligned, but it can 870 // happen in invalid code. 871 assert(OpC != PPC::DBG_VALUE && 872 "This should be handled in a target-independent way"); 873 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) || 874 OpC == TargetOpcode::STACKMAP || 875 OpC == TargetOpcode::PATCHPOINT)) { 876 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 877 return; 878 } 879 880 // The offset doesn't fit into a single register, scavenge one to build the 881 // offset in. 882 883 bool is64Bit = TM.isPPC64(); 884 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 885 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 886 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 887 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 888 SReg = MF.getRegInfo().createVirtualRegister(RC); 889 890 // Insert a set of rA with the full offset value before the ld, st, or add 891 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 892 .addImm(Offset >> 16); 893 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 894 .addReg(SRegHi, RegState::Kill) 895 .addImm(Offset); 896 897 // Convert into indexed form of the instruction: 898 // 899 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 900 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 901 unsigned OperandBase; 902 903 if (noImmForm) 904 OperandBase = 1; 905 else if (OpC != TargetOpcode::INLINEASM) { 906 assert(ImmToIdxMap.count(OpC) && 907 "No indexed form of load or store available!"); 908 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 909 MI.setDesc(TII.get(NewOpcode)); 910 OperandBase = 1; 911 } else { 912 OperandBase = OffsetOperandNo; 913 } 914 915 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 916 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 917 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 918 } 919 920 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 921 const PPCFrameLowering *TFI = getFrameLowering(MF); 922 923 if (!TM.isPPC64()) 924 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 925 else 926 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 927 } 928 929 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 930 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 931 if (!hasBasePointer(MF)) 932 return getFrameRegister(MF); 933 934 if (TM.isPPC64()) 935 return PPC::X30; 936 937 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent()) 938 return PPC::R29; 939 940 return PPC::R30; 941 } 942 943 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 944 if (!EnableBasePointer) 945 return false; 946 if (AlwaysBasePointer) 947 return true; 948 949 // If we need to realign the stack, then the stack pointer can no longer 950 // serve as an offset into the caller's stack space. As a result, we need a 951 // base pointer. 952 return needsStackRealignment(MF); 953 } 954 955 /// Returns true if the instruction's frame index 956 /// reference would be better served by a base register other than FP 957 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 958 /// references it should create new base registers for. 959 bool PPCRegisterInfo:: 960 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 961 assert(Offset < 0 && "Local offset must be negative"); 962 963 // It's the load/store FI references that cause issues, as it can be difficult 964 // to materialize the offset if it won't fit in the literal field. Estimate 965 // based on the size of the local frame and some conservative assumptions 966 // about the rest of the stack frame (note, this is pre-regalloc, so 967 // we don't know everything for certain yet) whether this offset is likely 968 // to be out of range of the immediate. Return true if so. 969 970 // We only generate virtual base registers for loads and stores that have 971 // an r+i form. Return false for everything else. 972 unsigned OpC = MI->getOpcode(); 973 if (!ImmToIdxMap.count(OpC)) 974 return false; 975 976 // Don't generate a new virtual base register just to add zero to it. 977 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 978 MI->getOperand(2).getImm() == 0) 979 return false; 980 981 MachineBasicBlock &MBB = *MI->getParent(); 982 MachineFunction &MF = *MBB.getParent(); 983 const PPCFrameLowering *TFI = getFrameLowering(MF); 984 unsigned StackEst = TFI->determineFrameLayout(MF, false, true); 985 986 // If we likely don't need a stack frame, then we probably don't need a 987 // virtual base register either. 988 if (!StackEst) 989 return false; 990 991 // Estimate an offset from the stack pointer. 992 // The incoming offset is relating to the SP at the start of the function, 993 // but when we access the local it'll be relative to the SP after local 994 // allocation, so adjust our SP-relative offset by that allocation size. 995 Offset += StackEst; 996 997 // The frame pointer will point to the end of the stack, so estimate the 998 // offset as the difference between the object offset and the FP location. 999 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset); 1000 } 1001 1002 /// Insert defining instruction(s) for BaseReg to 1003 /// be a pointer to FrameIdx at the beginning of the basic block. 1004 void PPCRegisterInfo:: 1005 materializeFrameBaseRegister(MachineBasicBlock *MBB, 1006 unsigned BaseReg, int FrameIdx, 1007 int64_t Offset) const { 1008 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 1009 1010 MachineBasicBlock::iterator Ins = MBB->begin(); 1011 DebugLoc DL; // Defaults to "unknown" 1012 if (Ins != MBB->end()) 1013 DL = Ins->getDebugLoc(); 1014 1015 const MachineFunction &MF = *MBB->getParent(); 1016 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1017 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1018 const MCInstrDesc &MCID = TII.get(ADDriOpc); 1019 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1020 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 1021 1022 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1023 .addFrameIndex(FrameIdx).addImm(Offset); 1024 } 1025 1026 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 1027 int64_t Offset) const { 1028 unsigned FIOperandNum = 0; 1029 while (!MI.getOperand(FIOperandNum).isFI()) { 1030 ++FIOperandNum; 1031 assert(FIOperandNum < MI.getNumOperands() && 1032 "Instr doesn't have FrameIndex operand!"); 1033 } 1034 1035 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1036 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1037 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1038 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1039 1040 MachineBasicBlock &MBB = *MI.getParent(); 1041 MachineFunction &MF = *MBB.getParent(); 1042 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1043 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1044 const MCInstrDesc &MCID = MI.getDesc(); 1045 MachineRegisterInfo &MRI = MF.getRegInfo(); 1046 MRI.constrainRegClass(BaseReg, 1047 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1048 } 1049 1050 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1051 unsigned BaseReg, 1052 int64_t Offset) const { 1053 unsigned FIOperandNum = 0; 1054 while (!MI->getOperand(FIOperandNum).isFI()) { 1055 ++FIOperandNum; 1056 assert(FIOperandNum < MI->getNumOperands() && 1057 "Instr doesn't have FrameIndex operand!"); 1058 } 1059 1060 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1061 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1062 1063 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1064 MI->getOpcode() == TargetOpcode::STACKMAP || 1065 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1066 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1067 } 1068