| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| LiveIntervalUnion.h | 92 void unify(LiveInterval &VirtReg);
95 void extract(LiveInterval &VirtReg);
112 LiveInterval *VirtReg;
113 LiveInterval::iterator VirtRegI; // current position in VirtReg
122 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
125 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
131 VirtReg = NULL;
142 if (UserTag == UTag && VirtReg == VReg &&
149 VirtReg = VReg;
154 LiveInterval &virtReg() const
[all...] |
| VirtRegMap.cpp | 118 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
119 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
129 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
130 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
131 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
134 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
137 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
138 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
139 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &
[all...] |
| RegAllocBasic.cpp | 125 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
268 LiveInterval &VirtReg = *I->second;
270 PhysReg2LiveUnion[RegNum].unify(VirtReg);
272 enqueue(&VirtReg);
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
277 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
279 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
280 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
282 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
[all...] |
| VirtRegRewriter.cpp | 368 // VirtReg - The virtual register itself.
369 unsigned VirtReg;
374 AssignedPhysReg(apr), VirtReg(vreg) {}
396 unsigned VirtReg) {
403 AssignedPhysReg, VirtReg));
437 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI,
445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
692 unsigned VirtReg = MO.getReg();
693 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
696 unsigned Phys = VRM.getPhys(VirtReg);
[all...] |
| PrologEpilogInserter.cpp | 822 unsigned VirtReg = 0;
842 if (Reg != VirtReg) {
848 VirtReg = Reg;
|
| LiveDebugVariables.cpp | 303 /// lookupVirtReg - Find the EC leader for VirtReg or null.
304 UserValue *lookupVirtReg(unsigned VirtReg);
335 void mapVirtReg(unsigned VirtReg, UserValue *EC);
429 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
430 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
431 UserValue *&Leader = virtRegToEqClass[VirtReg];
435 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
436 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
885 unsigned VirtReg = Loc.getReg();
886 if (VRM.isAssignedReg(VirtReg) &
[all...] |
| RegAllocFast.cpp | 111 // PhysRegState - One of the RegState enums, or a virtreg.
150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
155 void killVirtReg(unsigned VirtReg);
157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
165 unsigned VirtReg, unsigned Hint);
167 unsigned VirtReg, unsigned Hint);
176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
178 int SS = StackSlotForVirtReg[VirtReg];
187 StackSlotForVirtReg[VirtReg] = FrameIdx;
223 /// killVirtReg - Mark virtreg as no longer available
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 87 void unify(LiveInterval &VirtReg, const LiveRange &Range);
88 void unify(LiveInterval &VirtReg) {
89 unify(VirtReg, VirtReg);
93 void extract(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg) {
95 extract(VirtReg, VirtReg);
113 LiveInterval *VirtReg;
114 LiveInterval::iterator VirtRegI; // current position in VirtReg
[all...] |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /external/llvm/lib/CodeGen/ |
| VirtRegMap.cpp | 82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
83 unsigned Hint = MRI->getSimpleHint(VirtReg);
88 return getPhys(VirtReg) == Hint;
91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
92 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
100 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
101 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
102 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
104 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
105 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC)
[all...] |
| RegAllocFast.cpp | 71 unsigned VirtReg; // Virtual register number.
77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
80 return TargetRegisterInfo::virtReg2Index(VirtReg);
112 // PhysRegState - One of the RegState enums, or a virtreg.
171 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
176 void killVirtReg(unsigned VirtReg);
178 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
184 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
185 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
187 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const
[all...] |
| LiveDebugVariables.cpp | 310 /// lookupVirtReg - Find the EC leader for VirtReg or null.
311 UserValue *lookupVirtReg(unsigned VirtReg);
349 void mapVirtReg(unsigned VirtReg, UserValue *EC);
479 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
480 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
481 UserValue *&Leader = virtRegToEqClass[VirtReg];
485 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
486 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
923 unsigned VirtReg = Loc.getReg();
924 if (VRM.isAssignedReg(VirtReg) &
[all...] |
| MachineBasicBlock.cpp | 381 unsigned VirtReg = I->getOperand(0).getReg();
382 if (!MRI.constrainRegClass(VirtReg, RC))
384 return VirtReg;
388 unsigned VirtReg = MRI.createVirtualRegister(RC);
389 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
393 return VirtReg;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 36 unsigned VirtReg;
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
44 return TargetRegisterInfo::virtReg2Index(VirtReg);
|
