1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides basic encoding and assembly information for AArch64. 11 // 12 //===----------------------------------------------------------------------===// 13 #include "AArch64BaseInfo.h" 14 #include "llvm/ADT/ArrayRef.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/Support/Regex.h" 18 19 using namespace llvm; 20 21 namespace llvm { 22 namespace AArch64AT { 23 #define GET_AT_IMPL 24 #include "AArch64GenSystemOperands.inc" 25 } 26 } 27 28 29 namespace llvm { 30 namespace AArch64DB { 31 #define GET_DB_IMPL 32 #include "AArch64GenSystemOperands.inc" 33 } 34 } 35 36 namespace llvm { 37 namespace AArch64DC { 38 #define GET_DC_IMPL 39 #include "AArch64GenSystemOperands.inc" 40 } 41 } 42 43 namespace llvm { 44 namespace AArch64IC { 45 #define GET_IC_IMPL 46 #include "AArch64GenSystemOperands.inc" 47 } 48 } 49 50 namespace llvm { 51 namespace AArch64ISB { 52 #define GET_ISB_IMPL 53 #include "AArch64GenSystemOperands.inc" 54 } 55 } 56 namespace llvm { 57 namespace AArch64PRFM { 58 #define GET_PRFM_IMPL 59 #include "AArch64GenSystemOperands.inc" 60 } 61 } 62 63 namespace llvm { 64 namespace AArch64PState { 65 #define GET_PSTATE_IMPL 66 #include "AArch64GenSystemOperands.inc" 67 } 68 } 69 70 namespace llvm { 71 namespace AArch64PSBHint { 72 #define GET_PSB_IMPL 73 #include "AArch64GenSystemOperands.inc" 74 } 75 } 76 77 namespace llvm { 78 namespace AArch64SysReg { 79 #define GET_SYSREG_IMPL 80 #include "AArch64GenSystemOperands.inc" 81 } 82 } 83 84 uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) { 85 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name 86 Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$"); 87 88 std::string UpperName = Name.upper(); 89 SmallVector<StringRef, 5> Ops; 90 if (!GenericRegPattern.match(UpperName, &Ops)) 91 return -1; 92 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 94 uint32_t Bits; 95 Ops[1].getAsInteger(10, Op0); 96 Ops[2].getAsInteger(10, Op1); 97 Ops[3].getAsInteger(10, CRn); 98 Ops[4].getAsInteger(10, CRm); 99 Ops[5].getAsInteger(10, Op2); 100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 101 102 return Bits; 103 } 104 105 std::string AArch64SysReg::genericRegisterString(uint32_t Bits) { 106 assert(Bits < 0x10000); 107 uint32_t Op0 = (Bits >> 14) & 0x3; 108 uint32_t Op1 = (Bits >> 11) & 0x7; 109 uint32_t CRn = (Bits >> 7) & 0xf; 110 uint32_t CRm = (Bits >> 3) & 0xf; 111 uint32_t Op2 = Bits & 0x7; 112 113 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + 114 utostr(CRm) + "_" + utostr(Op2); 115 } 116 117 namespace llvm { 118 namespace AArch64TLBI { 119 #define GET_TLBI_IMPL 120 #include "AArch64GenSystemOperands.inc" 121 } 122 } 123