1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetRegisterInfo class. 11 // This file is responsible for the frame pointer elimination optimization 12 // on X86. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RegisterInfo.h" 17 #include "X86FrameLowering.h" 18 #include "X86InstrBuilder.h" 19 #include "X86MachineFunctionInfo.h" 20 #include "X86Subtarget.h" 21 #include "X86TargetMachine.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineFunctionPass.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/MC/MCAsmInfo.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Target/TargetFrameLowering.h" 37 #include "llvm/Target/TargetInstrInfo.h" 38 #include "llvm/Target/TargetMachine.h" 39 #include "llvm/Target/TargetOptions.h" 40 41 using namespace llvm; 42 43 #define GET_REGINFO_TARGET_DESC 44 #include "X86GenRegisterInfo.inc" 45 46 static cl::opt<bool> 47 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), 48 cl::desc("Enable use of a base pointer for complex stack frames")); 49 50 X86RegisterInfo::X86RegisterInfo(const Triple &TT) 51 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), 52 X86_MC::getDwarfRegFlavour(TT, false), 53 X86_MC::getDwarfRegFlavour(TT, true), 54 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { 55 X86_MC::initLLVMToSEHAndCVRegMapping(this); 56 57 // Cache some information. 58 Is64Bit = TT.isArch64Bit(); 59 IsWin64 = Is64Bit && TT.isOSWindows(); 60 61 // Use a callee-saved register as the base pointer. These registers must 62 // not conflict with any ABI requirements. For example, in 32-bit mode PIC 63 // requires GOT in the EBX register before function calls via PLT GOT pointer. 64 if (Is64Bit) { 65 SlotSize = 8; 66 // This matches the simplified 32-bit pointer code in the data layout 67 // computation. 68 // FIXME: Should use the data layout? 69 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32; 70 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; 71 FramePtr = Use64BitReg ? X86::RBP : X86::EBP; 72 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; 73 } else { 74 SlotSize = 4; 75 StackPtr = X86::ESP; 76 FramePtr = X86::EBP; 77 BasePtr = X86::ESI; 78 } 79 } 80 81 bool 82 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 83 // ExeDepsFixer and PostRAScheduler require liveness. 84 return true; 85 } 86 87 int 88 X86RegisterInfo::getSEHRegNum(unsigned i) const { 89 return getEncodingValue(i); 90 } 91 92 const TargetRegisterClass * 93 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, 94 unsigned Idx) const { 95 // The sub_8bit sub-register index is more constrained in 32-bit mode. 96 // It behaves just like the sub_8bit_hi index. 97 if (!Is64Bit && Idx == X86::sub_8bit) 98 Idx = X86::sub_8bit_hi; 99 100 // Forward to TableGen's default version. 101 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); 102 } 103 104 const TargetRegisterClass * 105 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 106 const TargetRegisterClass *B, 107 unsigned SubIdx) const { 108 // The sub_8bit sub-register index is more constrained in 32-bit mode. 109 if (!Is64Bit && SubIdx == X86::sub_8bit) { 110 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); 111 if (!A) 112 return nullptr; 113 } 114 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx); 115 } 116 117 const TargetRegisterClass * 118 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 119 const MachineFunction &MF) const { 120 // Don't allow super-classes of GR8_NOREX. This class is only used after 121 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied 122 // to the full GR8 register class in 64-bit mode, so we cannot allow the 123 // reigster class inflation. 124 // 125 // The GR8_NOREX class is always used in a way that won't be constrained to a 126 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the 127 // full GR8 class. 128 if (RC == &X86::GR8_NOREXRegClass) 129 return RC; 130 131 const TargetRegisterClass *Super = RC; 132 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 133 do { 134 switch (Super->getID()) { 135 case X86::GR8RegClassID: 136 case X86::GR16RegClassID: 137 case X86::GR32RegClassID: 138 case X86::GR64RegClassID: 139 case X86::FR32RegClassID: 140 case X86::FR64RegClassID: 141 case X86::RFP32RegClassID: 142 case X86::RFP64RegClassID: 143 case X86::RFP80RegClassID: 144 case X86::VR128RegClassID: 145 case X86::VR256RegClassID: 146 // Don't return a super-class that would shrink the spill size. 147 // That can happen with the vector and float classes. 148 if (Super->getSize() == RC->getSize()) 149 return Super; 150 } 151 Super = *I++; 152 } while (Super); 153 return RC; 154 } 155 156 const TargetRegisterClass * 157 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, 158 unsigned Kind) const { 159 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); 160 switch (Kind) { 161 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!"); 162 case 0: // Normal GPRs. 163 if (Subtarget.isTarget64BitLP64()) 164 return &X86::GR64RegClass; 165 // If the target is 64bit but we have been told to use 32bit addresses, 166 // we can still use 64-bit register as long as we know the high bits 167 // are zeros. 168 // Reflect that in the returned register class. 169 if (Is64Bit) { 170 // When the target also allows 64-bit frame pointer and we do have a 171 // frame, this is fine to use it for the address accesses as well. 172 const X86FrameLowering *TFI = getFrameLowering(MF); 173 return TFI->hasFP(MF) && TFI->Uses64BitFramePtr 174 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass 175 : &X86::LOW32_ADDR_ACCESSRegClass; 176 } 177 return &X86::GR32RegClass; 178 case 1: // Normal GPRs except the stack pointer (for encoding reasons). 179 if (Subtarget.isTarget64BitLP64()) 180 return &X86::GR64_NOSPRegClass; 181 // NOSP does not contain RIP, so no special case here. 182 return &X86::GR32_NOSPRegClass; 183 case 2: // NOREX GPRs. 184 if (Subtarget.isTarget64BitLP64()) 185 return &X86::GR64_NOREXRegClass; 186 return &X86::GR32_NOREXRegClass; 187 case 3: // NOREX GPRs except the stack pointer (for encoding reasons). 188 if (Subtarget.isTarget64BitLP64()) 189 return &X86::GR64_NOREX_NOSPRegClass; 190 // NOSP does not contain RIP, so no special case here. 191 return &X86::GR32_NOREX_NOSPRegClass; 192 case 4: // Available for tailcall (not callee-saved GPRs). 193 return getGPRsForTailCall(MF); 194 } 195 } 196 197 const TargetRegisterClass * 198 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const { 199 const Function *F = MF.getFunction(); 200 if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64)) 201 return &X86::GR64_TCW64RegClass; 202 else if (Is64Bit) 203 return &X86::GR64_TCRegClass; 204 205 bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false); 206 if (hasHipeCC) 207 return &X86::GR32RegClass; 208 return &X86::GR32_TCRegClass; 209 } 210 211 const TargetRegisterClass * 212 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 213 if (RC == &X86::CCRRegClass) { 214 if (Is64Bit) 215 return &X86::GR64RegClass; 216 else 217 return &X86::GR32RegClass; 218 } 219 return RC; 220 } 221 222 unsigned 223 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 224 MachineFunction &MF) const { 225 const X86FrameLowering *TFI = getFrameLowering(MF); 226 227 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; 228 switch (RC->getID()) { 229 default: 230 return 0; 231 case X86::GR32RegClassID: 232 return 4 - FPDiff; 233 case X86::GR64RegClassID: 234 return 12 - FPDiff; 235 case X86::VR128RegClassID: 236 return Is64Bit ? 10 : 4; 237 case X86::VR64RegClassID: 238 return 4; 239 } 240 } 241 242 const MCPhysReg * 243 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 244 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>(); 245 bool HasSSE = Subtarget.hasSSE1(); 246 bool HasAVX = Subtarget.hasAVX(); 247 bool HasAVX512 = Subtarget.hasAVX512(); 248 bool CallsEHReturn = MF->getMMI().callsEHReturn(); 249 250 assert(MF && "MachineFunction required"); 251 switch (MF->getFunction()->getCallingConv()) { 252 case CallingConv::GHC: 253 case CallingConv::HiPE: 254 return CSR_NoRegs_SaveList; 255 case CallingConv::AnyReg: 256 if (HasAVX) 257 return CSR_64_AllRegs_AVX_SaveList; 258 return CSR_64_AllRegs_SaveList; 259 case CallingConv::PreserveMost: 260 return CSR_64_RT_MostRegs_SaveList; 261 case CallingConv::PreserveAll: 262 if (HasAVX) 263 return CSR_64_RT_AllRegs_AVX_SaveList; 264 return CSR_64_RT_AllRegs_SaveList; 265 case CallingConv::CXX_FAST_TLS: 266 if (Is64Bit) 267 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ? 268 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList; 269 break; 270 case CallingConv::Intel_OCL_BI: { 271 if (HasAVX512 && IsWin64) 272 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList; 273 if (HasAVX512 && Is64Bit) 274 return CSR_64_Intel_OCL_BI_AVX512_SaveList; 275 if (HasAVX && IsWin64) 276 return CSR_Win64_Intel_OCL_BI_AVX_SaveList; 277 if (HasAVX && Is64Bit) 278 return CSR_64_Intel_OCL_BI_AVX_SaveList; 279 if (!HasAVX && !IsWin64 && Is64Bit) 280 return CSR_64_Intel_OCL_BI_SaveList; 281 break; 282 } 283 case CallingConv::HHVM: 284 return CSR_64_HHVM_SaveList; 285 case CallingConv::Cold: 286 if (Is64Bit) 287 return CSR_64_MostRegs_SaveList; 288 break; 289 case CallingConv::X86_64_Win64: 290 return CSR_Win64_SaveList; 291 case CallingConv::X86_64_SysV: 292 if (CallsEHReturn) 293 return CSR_64EHRet_SaveList; 294 return CSR_64_SaveList; 295 case CallingConv::X86_INTR: 296 if (Is64Bit) { 297 if (HasAVX512) 298 return CSR_64_AllRegs_AVX512_SaveList; 299 if (HasAVX) 300 return CSR_64_AllRegs_AVX_SaveList; 301 return CSR_64_AllRegs_SaveList; 302 } else { 303 if (HasAVX512) 304 return CSR_32_AllRegs_AVX512_SaveList; 305 if (HasAVX) 306 return CSR_32_AllRegs_AVX_SaveList; 307 if (HasSSE) 308 return CSR_32_AllRegs_SSE_SaveList; 309 return CSR_32_AllRegs_SaveList; 310 } 311 default: 312 break; 313 } 314 315 if (Is64Bit) { 316 if (IsWin64) 317 return CSR_Win64_SaveList; 318 if (CallsEHReturn) 319 return CSR_64EHRet_SaveList; 320 if (Subtarget.getTargetLowering()->supportSwiftError() && 321 MF->getFunction()->getAttributes().hasAttrSomewhere( 322 Attribute::SwiftError)) 323 return CSR_64_SwiftError_SaveList; 324 return CSR_64_SaveList; 325 } 326 if (CallsEHReturn) 327 return CSR_32EHRet_SaveList; 328 return CSR_32_SaveList; 329 } 330 331 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy( 332 const MachineFunction *MF) const { 333 assert(MF && "Invalid MachineFunction pointer."); 334 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 335 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR()) 336 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList; 337 return nullptr; 338 } 339 340 const uint32_t * 341 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF, 342 CallingConv::ID CC) const { 343 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); 344 bool HasSSE = Subtarget.hasSSE1(); 345 bool HasAVX = Subtarget.hasAVX(); 346 bool HasAVX512 = Subtarget.hasAVX512(); 347 348 switch (CC) { 349 case CallingConv::GHC: 350 case CallingConv::HiPE: 351 return CSR_NoRegs_RegMask; 352 case CallingConv::AnyReg: 353 if (HasAVX) 354 return CSR_64_AllRegs_AVX_RegMask; 355 return CSR_64_AllRegs_RegMask; 356 case CallingConv::PreserveMost: 357 return CSR_64_RT_MostRegs_RegMask; 358 case CallingConv::PreserveAll: 359 if (HasAVX) 360 return CSR_64_RT_AllRegs_AVX_RegMask; 361 return CSR_64_RT_AllRegs_RegMask; 362 case CallingConv::CXX_FAST_TLS: 363 if (Is64Bit) 364 return CSR_64_TLS_Darwin_RegMask; 365 break; 366 case CallingConv::Intel_OCL_BI: { 367 if (HasAVX512 && IsWin64) 368 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask; 369 if (HasAVX512 && Is64Bit) 370 return CSR_64_Intel_OCL_BI_AVX512_RegMask; 371 if (HasAVX && IsWin64) 372 return CSR_Win64_Intel_OCL_BI_AVX_RegMask; 373 if (HasAVX && Is64Bit) 374 return CSR_64_Intel_OCL_BI_AVX_RegMask; 375 if (!HasAVX && !IsWin64 && Is64Bit) 376 return CSR_64_Intel_OCL_BI_RegMask; 377 break; 378 } 379 case CallingConv::HHVM: 380 return CSR_64_HHVM_RegMask; 381 case CallingConv::Cold: 382 if (Is64Bit) 383 return CSR_64_MostRegs_RegMask; 384 break; 385 case CallingConv::X86_64_Win64: 386 return CSR_Win64_RegMask; 387 case CallingConv::X86_64_SysV: 388 return CSR_64_RegMask; 389 case CallingConv::X86_INTR: 390 if (Is64Bit) { 391 if (HasAVX512) 392 return CSR_64_AllRegs_AVX512_RegMask; 393 if (HasAVX) 394 return CSR_64_AllRegs_AVX_RegMask; 395 return CSR_64_AllRegs_RegMask; 396 } else { 397 if (HasAVX512) 398 return CSR_32_AllRegs_AVX512_RegMask; 399 if (HasAVX) 400 return CSR_32_AllRegs_AVX_RegMask; 401 if (HasSSE) 402 return CSR_32_AllRegs_SSE_RegMask; 403 return CSR_32_AllRegs_RegMask; 404 } 405 default: 406 break; 407 } 408 409 // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check 410 // callsEHReturn(). 411 if (Is64Bit) { 412 if (IsWin64) 413 return CSR_Win64_RegMask; 414 if (Subtarget.getTargetLowering()->supportSwiftError() && 415 MF.getFunction()->getAttributes().hasAttrSomewhere( 416 Attribute::SwiftError)) 417 return CSR_64_SwiftError_RegMask; 418 return CSR_64_RegMask; 419 } 420 return CSR_32_RegMask; 421 } 422 423 const uint32_t* 424 X86RegisterInfo::getNoPreservedMask() const { 425 return CSR_NoRegs_RegMask; 426 } 427 428 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const { 429 return CSR_64_TLS_Darwin_RegMask; 430 } 431 432 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 433 BitVector Reserved(getNumRegs()); 434 const X86FrameLowering *TFI = getFrameLowering(MF); 435 436 // Set the stack-pointer register and its aliases as reserved. 437 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid(); 438 ++I) 439 Reserved.set(*I); 440 441 // Set the instruction pointer register and its aliases as reserved. 442 for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid(); 443 ++I) 444 Reserved.set(*I); 445 446 // Set the frame-pointer register and its aliases as reserved if needed. 447 if (TFI->hasFP(MF)) { 448 for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid(); 449 ++I) 450 Reserved.set(*I); 451 } 452 453 // Set the base-pointer register and its aliases as reserved if needed. 454 if (hasBasePointer(MF)) { 455 CallingConv::ID CC = MF.getFunction()->getCallingConv(); 456 const uint32_t *RegMask = getCallPreservedMask(MF, CC); 457 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) 458 report_fatal_error( 459 "Stack realignment in presence of dynamic allocas is not supported with" 460 "this calling convention."); 461 462 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64); 463 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true); 464 I.isValid(); ++I) 465 Reserved.set(*I); 466 } 467 468 // Mark the segment registers as reserved. 469 Reserved.set(X86::CS); 470 Reserved.set(X86::SS); 471 Reserved.set(X86::DS); 472 Reserved.set(X86::ES); 473 Reserved.set(X86::FS); 474 Reserved.set(X86::GS); 475 476 // Mark the floating point stack registers as reserved. 477 for (unsigned n = 0; n != 8; ++n) 478 Reserved.set(X86::ST0 + n); 479 480 // Reserve the registers that only exist in 64-bit mode. 481 if (!Is64Bit) { 482 // These 8-bit registers are part of the x86-64 extension even though their 483 // super-registers are old 32-bits. 484 Reserved.set(X86::SIL); 485 Reserved.set(X86::DIL); 486 Reserved.set(X86::BPL); 487 Reserved.set(X86::SPL); 488 489 for (unsigned n = 0; n != 8; ++n) { 490 // R8, R9, ... 491 for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI) 492 Reserved.set(*AI); 493 494 // XMM8, XMM9, ... 495 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI) 496 Reserved.set(*AI); 497 } 498 } 499 if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) { 500 for (unsigned n = 16; n != 32; ++n) { 501 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI) 502 Reserved.set(*AI); 503 } 504 } 505 506 return Reserved; 507 } 508 509 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 510 // Check if the EFLAGS register is marked as live-out. This shouldn't happen, 511 // because the calling convention defines the EFLAGS register as NOT 512 // preserved. 513 // 514 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding 515 // an assert to track this and clear the register afterwards to avoid 516 // unnecessary crashes during release builds. 517 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) && 518 "EFLAGS are not live-out from a patchpoint."); 519 520 // Also clean other registers that don't need preserving (IP). 521 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) 522 Mask[Reg / 32] &= ~(1U << (Reg % 32)); 523 } 524 525 //===----------------------------------------------------------------------===// 526 // Stack Frame Processing methods 527 //===----------------------------------------------------------------------===// 528 529 static bool CantUseSP(const MachineFrameInfo *MFI) { 530 return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment(); 531 } 532 533 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const { 534 const MachineFrameInfo *MFI = MF.getFrameInfo(); 535 536 if (!EnableBasePointer) 537 return false; 538 539 // When we need stack realignment, we can't address the stack from the frame 540 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we 541 // can't address variables from the stack pointer. MS inline asm can 542 // reference locals while also adjusting the stack pointer. When we can't 543 // use both the SP and the FP, we need a separate base pointer register. 544 bool CantUseFP = needsStackRealignment(MF); 545 return CantUseFP && CantUseSP(MFI); 546 } 547 548 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const { 549 if (!TargetRegisterInfo::canRealignStack(MF)) 550 return false; 551 552 const MachineFrameInfo *MFI = MF.getFrameInfo(); 553 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 554 555 // Stack realignment requires a frame pointer. If we already started 556 // register allocation with frame pointer elimination, it is too late now. 557 if (!MRI->canReserveReg(FramePtr)) 558 return false; 559 560 // If a base pointer is necessary. Check that it isn't too late to reserve 561 // it. 562 if (CantUseSP(MFI)) 563 return MRI->canReserveReg(BasePtr); 564 return true; 565 } 566 567 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 568 unsigned Reg, int &FrameIdx) const { 569 // Since X86 defines assignCalleeSavedSpillSlots which always return true 570 // this function neither used nor tested. 571 llvm_unreachable("Unused function on X86. Otherwise need a test case."); 572 } 573 574 void 575 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 576 int SPAdj, unsigned FIOperandNum, 577 RegScavenger *RS) const { 578 MachineInstr &MI = *II; 579 MachineFunction &MF = *MI.getParent()->getParent(); 580 const X86FrameLowering *TFI = getFrameLowering(MF); 581 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 582 unsigned BasePtr; 583 584 unsigned Opc = MI.getOpcode(); 585 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm || 586 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64; 587 588 if (hasBasePointer(MF)) 589 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister()); 590 else if (needsStackRealignment(MF)) 591 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); 592 else if (AfterFPPop) 593 BasePtr = StackPtr; 594 else 595 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr); 596 597 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the 598 // simple FP case, and doesn't work with stack realignment. On 32-bit, the 599 // offset is from the traditional base pointer location. On 64-bit, the 600 // offset is from the SP at the end of the prologue, not the FP location. This 601 // matches the behavior of llvm.frameaddress. 602 unsigned IgnoredFrameReg; 603 if (Opc == TargetOpcode::LOCAL_ESCAPE) { 604 MachineOperand &FI = MI.getOperand(FIOperandNum); 605 int Offset; 606 Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg); 607 FI.ChangeToImmediate(Offset); 608 return; 609 } 610 611 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit 612 // register as source operand, semantic is the same and destination is 613 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided. 614 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr)) 615 BasePtr = getX86SubSuperRegister(BasePtr, 64); 616 617 // This must be part of a four operand memory reference. Replace the 618 // FrameIndex with base register with EBP. Add an offset to the offset. 619 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 620 621 // Now add the frame object offset to the offset from EBP. 622 int FIOffset; 623 if (AfterFPPop) { 624 // Tail call jmp happens after FP is popped. 625 const MachineFrameInfo *MFI = MF.getFrameInfo(); 626 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea(); 627 } else 628 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg); 629 630 if (BasePtr == StackPtr) 631 FIOffset += SPAdj; 632 633 // The frame index format for stackmaps and patchpoints is different from the 634 // X86 format. It only has a FI and an offset. 635 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) { 636 assert(BasePtr == FramePtr && "Expected the FP as base register"); 637 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset; 638 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 639 return; 640 } 641 642 if (MI.getOperand(FIOperandNum+3).isImm()) { 643 // Offset is a 32-bit integer. 644 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm()); 645 int Offset = FIOffset + Imm; 646 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) && 647 "Requesting 64-bit offset in 32-bit immediate!"); 648 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset); 649 } else { 650 // Offset is symbolic. This is extremely rare. 651 uint64_t Offset = FIOffset + 652 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset(); 653 MI.getOperand(FIOperandNum + 3).setOffset(Offset); 654 } 655 } 656 657 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 658 const X86FrameLowering *TFI = getFrameLowering(MF); 659 return TFI->hasFP(MF) ? FramePtr : StackPtr; 660 } 661 662 unsigned 663 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const { 664 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); 665 unsigned FrameReg = getFrameRegister(MF); 666 if (Subtarget.isTarget64BitILP32()) 667 FrameReg = getX86SubSuperRegister(FrameReg, 32); 668 return FrameReg; 669 } 670 671 unsigned llvm::get512BitSuperRegister(unsigned Reg) { 672 if (Reg >= X86::XMM0 && Reg <= X86::XMM31) 673 return X86::ZMM0 + (Reg - X86::XMM0); 674 if (Reg >= X86::YMM0 && Reg <= X86::YMM31) 675 return X86::ZMM0 + (Reg - X86::YMM0); 676 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31) 677 return Reg; 678 llvm_unreachable("Unexpected SIMD register"); 679 } 680
