1 /************************************************************************** 2 * 3 * Copyright 2007 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 /** 30 * @file 31 * 32 * Abstract graphics pipe state objects. 33 * 34 * Basic notes: 35 * 1. Want compact representations, so we use bitfields. 36 * 2. Put bitfields before other (GLfloat) fields. 37 */ 38 39 40 #ifndef PIPE_STATE_H 41 #define PIPE_STATE_H 42 43 #include "p_compiler.h" 44 #include "p_defines.h" 45 #include "p_format.h" 46 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 53 /** 54 * Implementation limits 55 */ 56 #define PIPE_MAX_ATTRIBS 32 57 #define PIPE_MAX_CLIP_PLANES 8 58 #define PIPE_MAX_COLOR_BUFS 8 59 #define PIPE_MAX_CONSTANT_BUFFERS 32 60 #define PIPE_MAX_SAMPLERS 32 61 #define PIPE_MAX_SHADER_INPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */ 62 #define PIPE_MAX_SHADER_OUTPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */ 63 #define PIPE_MAX_SHADER_SAMPLER_VIEWS 32 64 #define PIPE_MAX_SHADER_BUFFERS 32 65 #define PIPE_MAX_SHADER_IMAGES 32 66 #define PIPE_MAX_TEXTURE_LEVELS 16 67 #define PIPE_MAX_SO_BUFFERS 4 68 #define PIPE_MAX_SO_OUTPUTS 64 69 #define PIPE_MAX_VIEWPORTS 16 70 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT 8 71 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT 2 72 #define PIPE_MAX_WINDOW_RECTANGLES 8 73 74 75 struct pipe_reference 76 { 77 int32_t count; /* atomic */ 78 }; 79 80 81 82 /** 83 * Primitive (point/line/tri) rasterization info 84 */ 85 struct pipe_rasterizer_state 86 { 87 unsigned flatshade:1; 88 unsigned light_twoside:1; 89 unsigned clamp_vertex_color:1; 90 unsigned clamp_fragment_color:1; 91 unsigned front_ccw:1; 92 unsigned cull_face:2; /**< PIPE_FACE_x */ 93 unsigned fill_front:2; /**< PIPE_POLYGON_MODE_x */ 94 unsigned fill_back:2; /**< PIPE_POLYGON_MODE_x */ 95 unsigned offset_point:1; 96 unsigned offset_line:1; 97 unsigned offset_tri:1; 98 unsigned scissor:1; 99 unsigned poly_smooth:1; 100 unsigned poly_stipple_enable:1; 101 unsigned point_smooth:1; 102 unsigned sprite_coord_mode:1; /**< PIPE_SPRITE_COORD_ */ 103 unsigned point_quad_rasterization:1; /** points rasterized as quads or points */ 104 unsigned point_tri_clip:1; /** large points clipped as tris or points */ 105 unsigned point_size_per_vertex:1; /**< size computed in vertex shader */ 106 unsigned multisample:1; /* XXX maybe more ms state in future */ 107 unsigned force_persample_interp:1; 108 unsigned line_smooth:1; 109 unsigned line_stipple_enable:1; 110 unsigned line_last_pixel:1; 111 112 /** 113 * Use the first vertex of a primitive as the provoking vertex for 114 * flat shading. 115 */ 116 unsigned flatshade_first:1; 117 118 unsigned half_pixel_center:1; 119 unsigned bottom_edge_rule:1; 120 121 /** 122 * When true, rasterization is disabled and no pixels are written. 123 * This only makes sense with the Stream Out functionality. 124 */ 125 unsigned rasterizer_discard:1; 126 127 /** 128 * When false, depth clipping is disabled and the depth value will be 129 * clamped later at the per-pixel level before depth testing. 130 * This depends on PIPE_CAP_DEPTH_CLIP_DISABLE. 131 */ 132 unsigned depth_clip:1; 133 134 /** 135 * When true clip space in the z axis goes from [0..1] (D3D). When false 136 * [-1, 1] (GL). 137 * 138 * NOTE: D3D will always use depth clamping. 139 */ 140 unsigned clip_halfz:1; 141 142 /** 143 * When true do not scale offset_units and use same rules for unorm and 144 * float depth buffers (D3D9). When false use GL/D3D1X behaviour. 145 * This depends on PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. 146 */ 147 unsigned offset_units_unscaled:1; 148 149 /** 150 * Enable bits for clipping half-spaces. 151 * This applies to both user clip planes and shader clip distances. 152 * Note that if the bound shader exports any clip distances, these 153 * replace all user clip planes, and clip half-spaces enabled here 154 * but not written by the shader count as disabled. 155 */ 156 unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES; 157 158 unsigned line_stipple_factor:8; /**< [1..256] actually */ 159 unsigned line_stipple_pattern:16; 160 161 uint32_t sprite_coord_enable; /* referring to 32 TEXCOORD/GENERIC inputs */ 162 163 float line_width; 164 float point_size; /**< used when no per-vertex size */ 165 float offset_units; 166 float offset_scale; 167 float offset_clamp; 168 }; 169 170 171 struct pipe_poly_stipple 172 { 173 unsigned stipple[32]; 174 }; 175 176 177 struct pipe_viewport_state 178 { 179 float scale[3]; 180 float translate[3]; 181 }; 182 183 184 struct pipe_scissor_state 185 { 186 unsigned minx:16; 187 unsigned miny:16; 188 unsigned maxx:16; 189 unsigned maxy:16; 190 }; 191 192 193 struct pipe_clip_state 194 { 195 float ucp[PIPE_MAX_CLIP_PLANES][4]; 196 }; 197 198 /** 199 * A single output for vertex transform feedback. 200 */ 201 struct pipe_stream_output 202 { 203 unsigned register_index:8; /**< 0 to PIPE_MAX_SHADER_OUTPUTS */ 204 unsigned start_component:2; /** 0 to 3 */ 205 unsigned num_components:3; /** 1 to 4 */ 206 unsigned output_buffer:3; /**< 0 to PIPE_MAX_SO_BUFFERS */ 207 unsigned dst_offset:16; /**< offset into the buffer in dwords */ 208 unsigned stream:2; /**< 0 to 3 */ 209 }; 210 211 /** 212 * Stream output for vertex transform feedback. 213 */ 214 struct pipe_stream_output_info 215 { 216 unsigned num_outputs; 217 /** stride for an entire vertex for each buffer in dwords */ 218 unsigned stride[PIPE_MAX_SO_BUFFERS]; 219 220 /** 221 * Array of stream outputs, in the order they are to be written in. 222 * Selected components are tightly packed into the output buffer. 223 */ 224 struct pipe_stream_output output[PIPE_MAX_SO_OUTPUTS]; 225 }; 226 227 /** 228 * The 'type' parameter identifies whether the shader state contains TGSI 229 * tokens, etc. If the driver returns 'PIPE_SHADER_IR_TGSI' for the 230 * 'PIPE_SHADER_CAP_PREFERRED_IR' shader param, the ir will *always* be 231 * 'PIPE_SHADER_IR_TGSI' and the tokens ptr will be valid. If the driver 232 * requests a different 'pipe_shader_ir' type, then it must check the 'type' 233 * enum to see if it is getting TGSI tokens or its preferred IR. 234 * 235 * TODO pipe_compute_state should probably get similar treatment to handle 236 * multiple IR's in a cleaner way.. 237 * 238 * NOTE: since it is expected that the consumer will want to perform 239 * additional passes on the nir_shader, the driver takes ownership of 240 * the nir_shader. If state trackers need to hang on to the IR (for 241 * example, variant management), it should use nir_shader_clone(). 242 */ 243 struct pipe_shader_state 244 { 245 enum pipe_shader_ir type; 246 /* TODO move tokens into union. */ 247 const struct tgsi_token *tokens; 248 union { 249 void *llvm; 250 void *native; 251 void *nir; 252 } ir; 253 struct pipe_stream_output_info stream_output; 254 }; 255 256 static inline void 257 pipe_shader_state_from_tgsi(struct pipe_shader_state *state, 258 const struct tgsi_token *tokens) 259 { 260 state->type = PIPE_SHADER_IR_TGSI; 261 state->tokens = tokens; 262 memset(&state->stream_output, 0, sizeof(state->stream_output)); 263 } 264 265 struct pipe_depth_state 266 { 267 unsigned enabled:1; /**< depth test enabled? */ 268 unsigned writemask:1; /**< allow depth buffer writes? */ 269 unsigned func:3; /**< depth test func (PIPE_FUNC_x) */ 270 unsigned bounds_test:1; /**< depth bounds test enabled? */ 271 float bounds_min; /**< minimum depth bound */ 272 float bounds_max; /**< maximum depth bound */ 273 }; 274 275 276 struct pipe_stencil_state 277 { 278 unsigned enabled:1; /**< stencil[0]: stencil enabled, stencil[1]: two-side enabled */ 279 unsigned func:3; /**< PIPE_FUNC_x */ 280 unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */ 281 unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */ 282 unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */ 283 unsigned valuemask:8; 284 unsigned writemask:8; 285 }; 286 287 288 struct pipe_alpha_state 289 { 290 unsigned enabled:1; 291 unsigned func:3; /**< PIPE_FUNC_x */ 292 float ref_value; /**< reference value */ 293 }; 294 295 296 struct pipe_depth_stencil_alpha_state 297 { 298 struct pipe_depth_state depth; 299 struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */ 300 struct pipe_alpha_state alpha; 301 }; 302 303 304 struct pipe_rt_blend_state 305 { 306 unsigned blend_enable:1; 307 308 unsigned rgb_func:3; /**< PIPE_BLEND_x */ 309 unsigned rgb_src_factor:5; /**< PIPE_BLENDFACTOR_x */ 310 unsigned rgb_dst_factor:5; /**< PIPE_BLENDFACTOR_x */ 311 312 unsigned alpha_func:3; /**< PIPE_BLEND_x */ 313 unsigned alpha_src_factor:5; /**< PIPE_BLENDFACTOR_x */ 314 unsigned alpha_dst_factor:5; /**< PIPE_BLENDFACTOR_x */ 315 316 unsigned colormask:4; /**< bitmask of PIPE_MASK_R/G/B/A */ 317 }; 318 319 320 struct pipe_blend_state 321 { 322 unsigned independent_blend_enable:1; 323 unsigned logicop_enable:1; 324 unsigned logicop_func:4; /**< PIPE_LOGICOP_x */ 325 unsigned dither:1; 326 unsigned alpha_to_coverage:1; 327 unsigned alpha_to_one:1; 328 struct pipe_rt_blend_state rt[PIPE_MAX_COLOR_BUFS]; 329 }; 330 331 332 struct pipe_blend_color 333 { 334 float color[4]; 335 }; 336 337 338 struct pipe_stencil_ref 339 { 340 ubyte ref_value[2]; 341 }; 342 343 344 /** 345 * Note that pipe_surfaces are "texture views for rendering" 346 * and so in the case of ARB_framebuffer_no_attachment there 347 * is no pipe_surface state available such that we may 348 * extract the number of samples and layers. 349 */ 350 struct pipe_framebuffer_state 351 { 352 unsigned width, height; 353 unsigned samples; /**< Number of samples in a no-attachment framebuffer */ 354 unsigned layers; /**< Number of layers in a no-attachment framebuffer */ 355 356 /** multiple color buffers for multiple render targets */ 357 unsigned nr_cbufs; 358 struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS]; 359 360 struct pipe_surface *zsbuf; /**< Z/stencil buffer */ 361 }; 362 363 364 /** 365 * Texture sampler state. 366 */ 367 struct pipe_sampler_state 368 { 369 unsigned wrap_s:3; /**< PIPE_TEX_WRAP_x */ 370 unsigned wrap_t:3; /**< PIPE_TEX_WRAP_x */ 371 unsigned wrap_r:3; /**< PIPE_TEX_WRAP_x */ 372 unsigned min_img_filter:1; /**< PIPE_TEX_FILTER_x */ 373 unsigned min_mip_filter:2; /**< PIPE_TEX_MIPFILTER_x */ 374 unsigned mag_img_filter:1; /**< PIPE_TEX_FILTER_x */ 375 unsigned compare_mode:1; /**< PIPE_TEX_COMPARE_x */ 376 unsigned compare_func:3; /**< PIPE_FUNC_x */ 377 unsigned normalized_coords:1; /**< Are coords normalized to [0,1]? */ 378 unsigned max_anisotropy:5; 379 unsigned seamless_cube_map:1; 380 float lod_bias; /**< LOD/lambda bias */ 381 float min_lod, max_lod; /**< LOD clamp range, after bias */ 382 union pipe_color_union border_color; 383 }; 384 385 union pipe_surface_desc { 386 struct { 387 unsigned level; 388 unsigned first_layer:16; 389 unsigned last_layer:16; 390 } tex; 391 struct { 392 unsigned first_element; 393 unsigned last_element; 394 } buf; 395 }; 396 397 /** 398 * A view into a texture that can be bound to a color render target / 399 * depth stencil attachment point. 400 */ 401 struct pipe_surface 402 { 403 struct pipe_reference reference; 404 struct pipe_resource *texture; /**< resource into which this is a view */ 405 struct pipe_context *context; /**< context this surface belongs to */ 406 enum pipe_format format; 407 408 /* XXX width/height should be removed */ 409 unsigned width; /**< logical width in pixels */ 410 unsigned height; /**< logical height in pixels */ 411 412 unsigned writable:1; /**< writable shader resource */ 413 414 union pipe_surface_desc u; 415 }; 416 417 418 /** 419 * A view into a texture that can be bound to a shader stage. 420 */ 421 struct pipe_sampler_view 422 { 423 struct pipe_reference reference; 424 enum pipe_texture_target target; /**< PIPE_TEXTURE_x */ 425 enum pipe_format format; /**< typed PIPE_FORMAT_x */ 426 struct pipe_resource *texture; /**< texture into which this is a view */ 427 struct pipe_context *context; /**< context this view belongs to */ 428 union { 429 struct { 430 unsigned first_layer:16; /**< first layer to use for array textures */ 431 unsigned last_layer:16; /**< last layer to use for array textures */ 432 unsigned first_level:8; /**< first mipmap level to use */ 433 unsigned last_level:8; /**< last mipmap level to use */ 434 } tex; 435 struct { 436 unsigned offset; /**< offset in bytes */ 437 unsigned size; /**< size of the readable sub-range in bytes */ 438 } buf; 439 } u; 440 unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */ 441 unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */ 442 unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */ 443 unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */ 444 }; 445 446 447 /** 448 * A description of a buffer or texture image that can be bound to a shader 449 * stage. 450 */ 451 struct pipe_image_view 452 { 453 struct pipe_resource *resource; /**< resource into which this is a view */ 454 enum pipe_format format; /**< typed PIPE_FORMAT_x */ 455 unsigned access; /**< PIPE_IMAGE_ACCESS_x */ 456 457 union { 458 struct { 459 unsigned first_layer:16; /**< first layer to use for array textures */ 460 unsigned last_layer:16; /**< last layer to use for array textures */ 461 unsigned level:8; /**< mipmap level to use */ 462 } tex; 463 struct { 464 unsigned offset; /**< offset in bytes */ 465 unsigned size; /**< size of the accessible sub-range in bytes */ 466 } buf; 467 } u; 468 }; 469 470 471 /** 472 * Subregion of 1D/2D/3D image resource. 473 */ 474 struct pipe_box 475 { 476 int x; 477 int y; 478 int z; 479 int width; 480 int height; 481 int depth; 482 }; 483 484 485 /** 486 * A memory object/resource such as a vertex buffer or texture. 487 */ 488 struct pipe_resource 489 { 490 struct pipe_reference reference; 491 struct pipe_screen *screen; /**< screen that this texture belongs to */ 492 enum pipe_texture_target target; /**< PIPE_TEXTURE_x */ 493 enum pipe_format format; /**< PIPE_FORMAT_x */ 494 495 unsigned width0; 496 unsigned height0; 497 unsigned depth0; 498 unsigned array_size; 499 500 unsigned last_level:8; /**< Index of last mipmap level present/defined */ 501 unsigned nr_samples:8; /**< for multisampled surfaces, nr of samples */ 502 unsigned usage:8; /**< PIPE_USAGE_x (not a bitmask) */ 503 504 unsigned bind; /**< bitmask of PIPE_BIND_x */ 505 unsigned flags; /**< bitmask of PIPE_RESOURCE_FLAG_x */ 506 507 /** 508 * For planar images, ie. YUV EGLImage external, etc, pointer to the 509 * next plane. 510 */ 511 struct pipe_resource *next; 512 }; 513 514 515 /** 516 * Transfer object. For data transfer to/from a resource. 517 */ 518 struct pipe_transfer 519 { 520 struct pipe_resource *resource; /**< resource to transfer to/from */ 521 unsigned level; /**< texture mipmap level */ 522 enum pipe_transfer_usage usage; 523 struct pipe_box box; /**< region of the resource to access */ 524 unsigned stride; /**< row stride in bytes */ 525 unsigned layer_stride; /**< image/layer stride in bytes */ 526 }; 527 528 529 530 /** 531 * A vertex buffer. Typically, all the vertex data/attributes for 532 * drawing something will be in one buffer. But it's also possible, for 533 * example, to put colors in one buffer and texcoords in another. 534 */ 535 struct pipe_vertex_buffer 536 { 537 unsigned stride; /**< stride to same attrib in next vertex, in bytes */ 538 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 539 struct pipe_resource *buffer; /**< the actual buffer */ 540 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */ 541 }; 542 543 544 /** 545 * A constant buffer. A subrange of an existing buffer can be set 546 * as a constant buffer. 547 */ 548 struct pipe_constant_buffer 549 { 550 struct pipe_resource *buffer; /**< the actual buffer */ 551 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 552 unsigned buffer_size; /**< how much data can be read in shader */ 553 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */ 554 }; 555 556 557 /** 558 * An untyped shader buffer supporting loads, stores, and atomics. 559 */ 560 struct pipe_shader_buffer { 561 struct pipe_resource *buffer; /**< the actual buffer */ 562 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 563 unsigned buffer_size; /**< how much data can be read in shader */ 564 }; 565 566 567 /** 568 * A stream output target. The structure specifies the range vertices can 569 * be written to. 570 * 571 * In addition to that, the structure should internally maintain the offset 572 * into the buffer, which should be incremented everytime something is written 573 * (appended) to it. The internal offset is buffer_offset + how many bytes 574 * have been written. The internal offset can be stored on the device 575 * and the CPU actually doesn't have to query it. 576 * 577 * Note that the buffer_size variable is actually specifying the available 578 * space in the buffer, not the size of the attached buffer. 579 * In other words in majority of cases buffer_size would simply be 580 * 'buffer->width0 - buffer_offset', so buffer_size refers to the size 581 * of the buffer left, after accounting for buffer offset, for stream output 582 * to write to. 583 * 584 * Use PIPE_QUERY_SO_STATISTICS to know how many primitives have 585 * actually been written. 586 */ 587 struct pipe_stream_output_target 588 { 589 struct pipe_reference reference; 590 struct pipe_resource *buffer; /**< the output buffer */ 591 struct pipe_context *context; /**< context this SO target belongs to */ 592 593 unsigned buffer_offset; /**< offset where data should be written, in bytes */ 594 unsigned buffer_size; /**< how much data is allowed to be written */ 595 }; 596 597 598 /** 599 * Information to describe a vertex attribute (position, color, etc) 600 */ 601 struct pipe_vertex_element 602 { 603 /** Offset of this attribute, in bytes, from the start of the vertex */ 604 unsigned src_offset; 605 606 /** Instance data rate divisor. 0 means this is per-vertex data, 607 * n means per-instance data used for n consecutive instances (n > 0). 608 */ 609 unsigned instance_divisor; 610 611 /** Which vertex_buffer (as given to pipe->set_vertex_buffer()) does 612 * this attribute live in? 613 */ 614 unsigned vertex_buffer_index; 615 616 enum pipe_format src_format; 617 }; 618 619 620 /** 621 * An index buffer. When an index buffer is bound, all indices to vertices 622 * will be looked up in the buffer. 623 */ 624 struct pipe_index_buffer 625 { 626 unsigned index_size; /**< size of an index, in bytes */ 627 unsigned offset; /**< offset to start of data in buffer, in bytes */ 628 struct pipe_resource *buffer; /**< the actual buffer */ 629 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */ 630 }; 631 632 633 /** 634 * Information to describe a draw_vbo call. 635 */ 636 struct pipe_draw_info 637 { 638 boolean indexed; /**< use index buffer */ 639 640 enum pipe_prim_type mode; /**< the mode of the primitive */ 641 unsigned start; /**< the index of the first vertex */ 642 unsigned count; /**< number of vertices */ 643 644 unsigned start_instance; /**< first instance id */ 645 unsigned instance_count; /**< number of instances */ 646 647 unsigned drawid; /**< id of this draw in a multidraw */ 648 649 unsigned vertices_per_patch; /**< the number of vertices per patch */ 650 651 /** 652 * For indexed drawing, these fields apply after index lookup. 653 */ 654 int index_bias; /**< a bias to be added to each index */ 655 unsigned min_index; /**< the min index */ 656 unsigned max_index; /**< the max index */ 657 658 /** 659 * Primitive restart enable/index (only applies to indexed drawing) 660 */ 661 boolean primitive_restart; 662 unsigned restart_index; 663 664 /** 665 * Stream output target. If not NULL, it's used to provide the 'count' 666 * parameter based on the number vertices captured by the stream output 667 * stage. (or generally, based on the number of bytes captured) 668 * 669 * Only 'mode', 'start_instance', and 'instance_count' are taken into 670 * account, all the other variables from pipe_draw_info are ignored. 671 * 672 * 'start' is implicitly 0 and 'count' is set as discussed above. 673 * The draw command is non-indexed. 674 * 675 * Note that this only provides the count. The vertex buffers must 676 * be set via set_vertex_buffers manually. 677 */ 678 struct pipe_stream_output_target *count_from_stream_output; 679 680 /* Indirect draw parameters resource: If not NULL, most values are taken 681 * from this buffer instead, which is laid out as follows: 682 * 683 * if indexed is TRUE: 684 * struct { 685 * uint32_t count; 686 * uint32_t instance_count; 687 * uint32_t start; 688 * int32_t index_bias; 689 * uint32_t start_instance; 690 * }; 691 * otherwise: 692 * struct { 693 * uint32_t count; 694 * uint32_t instance_count; 695 * uint32_t start; 696 * uint32_t start_instance; 697 * }; 698 */ 699 struct pipe_resource *indirect; 700 unsigned indirect_offset; /**< must be 4 byte aligned */ 701 unsigned indirect_stride; /**< must be 4 byte aligned */ 702 unsigned indirect_count; /**< number of indirect draws */ 703 704 /* Indirect draw count resource: If not NULL, contains a 32-bit value which 705 * is to be used as the real indirect_count. In that case indirect_count 706 * becomes the maximum possible value. 707 */ 708 struct pipe_resource *indirect_params; 709 unsigned indirect_params_offset; /**< must be 4 byte aligned */ 710 }; 711 712 713 /** 714 * Information to describe a blit call. 715 */ 716 struct pipe_blit_info 717 { 718 struct { 719 struct pipe_resource *resource; 720 unsigned level; 721 struct pipe_box box; /**< negative width, height only legal for src */ 722 /* For pipe_surface-like format casting: */ 723 enum pipe_format format; /**< must be supported for sampling (src) 724 or rendering (dst), ZS is always supported */ 725 } dst, src; 726 727 unsigned mask; /**< bitmask of PIPE_MASK_R/G/B/A/Z/S */ 728 unsigned filter; /**< PIPE_TEX_FILTER_* */ 729 730 boolean scissor_enable; 731 struct pipe_scissor_state scissor; 732 733 /* Window rectangles can either be inclusive or exclusive. */ 734 boolean window_rectangle_include; 735 unsigned num_window_rectangles; 736 struct pipe_scissor_state window_rectangles[PIPE_MAX_WINDOW_RECTANGLES]; 737 738 boolean render_condition_enable; /**< whether the blit should honor the 739 current render condition */ 740 boolean alpha_blend; /* dst.rgb = src.rgb * src.a + dst.rgb * (1 - src.a) */ 741 }; 742 743 /** 744 * Information to describe a launch_grid call. 745 */ 746 struct pipe_grid_info 747 { 748 /** 749 * For drivers that use PIPE_SHADER_IR_LLVM as their prefered IR, this value 750 * will be the index of the kernel in the opencl.kernels metadata list. 751 */ 752 uint32_t pc; 753 754 /** 755 * Will be used to initialize the INPUT resource, and it should point to a 756 * buffer of at least pipe_compute_state::req_input_mem bytes. 757 */ 758 void *input; 759 760 /** 761 * Grid number of dimensions, 1-3, e.g. the work_dim parameter passed to 762 * clEnqueueNDRangeKernel. Note block[] and grid[] must be padded with 763 * 1 for non-used dimensions. 764 */ 765 uint work_dim; 766 767 /** 768 * Determine the layout of the working block (in thread units) to be used. 769 */ 770 uint block[3]; 771 772 /** 773 * Determine the layout of the grid (in block units) to be used. 774 */ 775 uint grid[3]; 776 777 /* Indirect compute parameters resource: If not NULL, block sizes are taken 778 * from this buffer instead, which is laid out as follows: 779 * 780 * struct { 781 * uint32_t num_blocks_x; 782 * uint32_t num_blocks_y; 783 * uint32_t num_blocks_z; 784 * }; 785 */ 786 struct pipe_resource *indirect; 787 unsigned indirect_offset; /**< must be 4 byte aligned */ 788 }; 789 790 /** 791 * Structure used as a header for serialized LLVM programs. 792 */ 793 struct pipe_llvm_program_header 794 { 795 uint32_t num_bytes; /**< Number of bytes in the LLVM bytecode program. */ 796 }; 797 798 struct pipe_compute_state 799 { 800 enum pipe_shader_ir ir_type; /**< IR type contained in prog. */ 801 const void *prog; /**< Compute program to be executed. */ 802 unsigned req_local_mem; /**< Required size of the LOCAL resource. */ 803 unsigned req_private_mem; /**< Required size of the PRIVATE resource. */ 804 unsigned req_input_mem; /**< Required size of the INPUT resource. */ 805 }; 806 807 /** 808 * Structure that contains a callback for debug messages from the driver back 809 * to the state tracker. 810 */ 811 struct pipe_debug_callback 812 { 813 /** 814 * When set to \c true, the callback may be called asynchronously from a 815 * driver-created thread. 816 */ 817 bool async; 818 819 /** 820 * Callback for the driver to report debug/performance/etc information back 821 * to the state tracker. 822 * 823 * \param data user-supplied data pointer 824 * \param id message type identifier, if pointed value is 0, then a 825 * new id is assigned 826 * \param type PIPE_DEBUG_TYPE_* 827 * \param format printf-style format string 828 * \param args args for format string 829 */ 830 void (*debug_message)(void *data, 831 unsigned *id, 832 enum pipe_debug_type type, 833 const char *fmt, 834 va_list args); 835 void *data; 836 }; 837 838 /** 839 * Structure that contains a callback for device reset messages from the driver 840 * back to the state tracker. 841 * 842 * The callback must not be called from driver-created threads. 843 */ 844 struct pipe_device_reset_callback 845 { 846 /** 847 * Callback for the driver to report when a device reset is detected. 848 * 849 * \param data user-supplied data pointer 850 * \param status PIPE_*_RESET 851 */ 852 void (*reset)(void *data, enum pipe_reset_status status); 853 854 void *data; 855 }; 856 857 /** 858 * Information about memory usage. All sizes are in kilobytes. 859 */ 860 struct pipe_memory_info 861 { 862 unsigned total_device_memory; /**< size of device memory, e.g. VRAM */ 863 unsigned avail_device_memory; /**< free device memory at the moment */ 864 unsigned total_staging_memory; /**< size of staging memory, e.g. GART */ 865 unsigned avail_staging_memory; /**< free staging memory at the moment */ 866 unsigned device_memory_evicted; /**< size of memory evicted (monotonic counter) */ 867 unsigned nr_device_memory_evictions; /**< # of evictions (monotonic counter) */ 868 }; 869 870 #ifdef __cplusplus 871 } 872 #endif 873 874 #endif 875