1 /* tc-mips.c -- assemble code for a MIPS chip. 2 Copyright (C) 1993-2014 Free Software Foundation, Inc. 3 Contributed by the OSF and Ralph Campbell. 4 Written by Keith Knowles and Ralph Campbell, working independently. 5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus 6 Support. 7 8 This file is part of GAS. 9 10 GAS is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 GAS is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GAS; see the file COPYING. If not, write to the Free 22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 23 02110-1301, USA. */ 24 25 #include "as.h" 26 #include "config.h" 27 #include "subsegs.h" 28 #include "safe-ctype.h" 29 30 #include "opcode/mips.h" 31 #include "itbl-ops.h" 32 #include "dwarf2dbg.h" 33 #include "dw2gencfi.h" 34 35 /* Check assumptions made in this file. */ 36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; 37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; 38 39 #ifdef DEBUG 40 #define DBG(x) printf x 41 #else 42 #define DBG(x) 43 #endif 44 45 #define streq(a, b) (strcmp (a, b) == 0) 46 47 #define SKIP_SPACE_TABS(S) \ 48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) 49 50 /* Clean up namespace so we can include obj-elf.h too. */ 51 static int mips_output_flavor (void); 52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } 53 #undef OBJ_PROCESS_STAB 54 #undef OUTPUT_FLAVOR 55 #undef S_GET_ALIGN 56 #undef S_GET_SIZE 57 #undef S_SET_ALIGN 58 #undef S_SET_SIZE 59 #undef obj_frob_file 60 #undef obj_frob_file_after_relocs 61 #undef obj_frob_symbol 62 #undef obj_pop_insert 63 #undef obj_sec_sym_ok_for_reloc 64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES 65 66 #include "obj-elf.h" 67 /* Fix any of them that we actually care about. */ 68 #undef OUTPUT_FLAVOR 69 #define OUTPUT_FLAVOR mips_output_flavor() 70 71 #include "elf/mips.h" 72 73 #ifndef ECOFF_DEBUGGING 74 #define NO_ECOFF_DEBUGGING 75 #define ECOFF_DEBUGGING 0 76 #endif 77 78 int mips_flag_mdebug = -1; 79 80 /* Control generation of .pdr sections. Off by default on IRIX: the native 81 linker doesn't know about and discards them, but relocations against them 82 remain, leading to rld crashes. */ 83 #ifdef TE_IRIX 84 int mips_flag_pdr = FALSE; 85 #else 86 int mips_flag_pdr = TRUE; 87 #endif 88 89 #include "ecoff.h" 90 91 static char *mips_regmask_frag; 92 static char *mips_flags_frag; 93 94 #define ZERO 0 95 #define ATREG 1 96 #define S0 16 97 #define S7 23 98 #define TREG 24 99 #define PIC_CALL_REG 25 100 #define KT0 26 101 #define KT1 27 102 #define GP 28 103 #define SP 29 104 #define FP 30 105 #define RA 31 106 107 #define ILLEGAL_REG (32) 108 109 #define AT mips_opts.at 110 111 extern int target_big_endian; 112 113 /* The name of the readonly data section. */ 114 #define RDATA_SECTION_NAME ".rodata" 115 116 /* Ways in which an instruction can be "appended" to the output. */ 117 enum append_method { 118 /* Just add it normally. */ 119 APPEND_ADD, 120 121 /* Add it normally and then add a nop. */ 122 APPEND_ADD_WITH_NOP, 123 124 /* Turn an instruction with a delay slot into a "compact" version. */ 125 APPEND_ADD_COMPACT, 126 127 /* Insert the instruction before the last one. */ 128 APPEND_SWAP 129 }; 130 131 /* Information about an instruction, including its format, operands 132 and fixups. */ 133 struct mips_cl_insn 134 { 135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */ 136 const struct mips_opcode *insn_mo; 137 138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is 139 a copy of INSN_MO->match with the operands filled in. If we have 140 decided to use an extended MIPS16 instruction, this includes the 141 extension. */ 142 unsigned long insn_opcode; 143 144 /* The frag that contains the instruction. */ 145 struct frag *frag; 146 147 /* The offset into FRAG of the first instruction byte. */ 148 long where; 149 150 /* The relocs associated with the instruction, if any. */ 151 fixS *fixp[3]; 152 153 /* True if this entry cannot be moved from its current position. */ 154 unsigned int fixed_p : 1; 155 156 /* True if this instruction occurred in a .set noreorder block. */ 157 unsigned int noreorder_p : 1; 158 159 /* True for mips16 instructions that jump to an absolute address. */ 160 unsigned int mips16_absolute_jump_p : 1; 161 162 /* True if this instruction is complete. */ 163 unsigned int complete_p : 1; 164 165 /* True if this instruction is cleared from history by unconditional 166 branch. */ 167 unsigned int cleared_p : 1; 168 }; 169 170 /* The ABI to use. */ 171 enum mips_abi_level 172 { 173 NO_ABI = 0, 174 O32_ABI, 175 O64_ABI, 176 N32_ABI, 177 N64_ABI, 178 EABI_ABI 179 }; 180 181 /* MIPS ABI we are using for this output file. */ 182 static enum mips_abi_level mips_abi = NO_ABI; 183 184 /* Whether or not we have code that can call pic code. */ 185 int mips_abicalls = FALSE; 186 187 /* Whether or not we have code which can be put into a shared 188 library. */ 189 static bfd_boolean mips_in_shared = TRUE; 190 191 /* This is the set of options which may be modified by the .set 192 pseudo-op. We use a struct so that .set push and .set pop are more 193 reliable. */ 194 195 struct mips_set_options 196 { 197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 198 if it has not been initialized. Changed by `.set mipsN', and the 199 -mipsN command line option, and the default CPU. */ 200 int isa; 201 /* Enabled Application Specific Extensions (ASEs). Changed by `.set 202 <asename>', by command line options, and based on the default 203 architecture. */ 204 int ase; 205 /* Whether we are assembling for the mips16 processor. 0 if we are 206 not, 1 if we are, and -1 if the value has not been initialized. 207 Changed by `.set mips16' and `.set nomips16', and the -mips16 and 208 -nomips16 command line options, and the default CPU. */ 209 int mips16; 210 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, 211 1 if we are, and -1 if the value has not been initialized. Changed 212 by `.set micromips' and `.set nomicromips', and the -mmicromips 213 and -mno-micromips command line options, and the default CPU. */ 214 int micromips; 215 /* Non-zero if we should not reorder instructions. Changed by `.set 216 reorder' and `.set noreorder'. */ 217 int noreorder; 218 /* Non-zero if we should not permit the register designated "assembler 219 temporary" to be used in instructions. The value is the register 220 number, normally $at ($1). Changed by `.set at=REG', `.set noat' 221 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ 222 unsigned int at; 223 /* Non-zero if we should warn when a macro instruction expands into 224 more than one machine instruction. Changed by `.set nomacro' and 225 `.set macro'. */ 226 int warn_about_macros; 227 /* Non-zero if we should not move instructions. Changed by `.set 228 move', `.set volatile', `.set nomove', and `.set novolatile'. */ 229 int nomove; 230 /* Non-zero if we should not optimize branches by moving the target 231 of the branch into the delay slot. Actually, we don't perform 232 this optimization anyhow. Changed by `.set bopt' and `.set 233 nobopt'. */ 234 int nobopt; 235 /* Non-zero if we should not autoextend mips16 instructions. 236 Changed by `.set autoextend' and `.set noautoextend'. */ 237 int noautoextend; 238 /* True if we should only emit 32-bit microMIPS instructions. 239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32 240 and -mno-insn32 command line options. */ 241 bfd_boolean insn32; 242 /* Restrict general purpose registers and floating point registers 243 to 32 bit. This is initially determined when -mgp32 or -mfp32 244 is passed but can changed if the assembler code uses .set mipsN. */ 245 int gp; 246 int fp; 247 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march 248 command line option, and the default CPU. */ 249 int arch; 250 /* True if ".set sym32" is in effect. */ 251 bfd_boolean sym32; 252 /* True if floating-point operations are not allowed. Changed by .set 253 softfloat or .set hardfloat, by command line options -msoft-float or 254 -mhard-float. The default is false. */ 255 bfd_boolean soft_float; 256 257 /* True if only single-precision floating-point operations are allowed. 258 Changed by .set singlefloat or .set doublefloat, command-line options 259 -msingle-float or -mdouble-float. The default is false. */ 260 bfd_boolean single_float; 261 262 /* 1 if single-precision operations on odd-numbered registers are 263 allowed. */ 264 int oddspreg; 265 }; 266 267 /* Specifies whether module level options have been checked yet. */ 268 static bfd_boolean file_mips_opts_checked = FALSE; 269 270 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the 271 value has not been initialized. Changed by `.nan legacy' and 272 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line 273 options, and the default CPU. */ 274 static int mips_nan2008 = -1; 275 276 /* This is the struct we use to hold the module level set of options. 277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and 278 fp fields to -1 to indicate that they have not been initialized. */ 279 280 static struct mips_set_options file_mips_opts = 281 { 282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 283 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 285 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 286 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 287 }; 288 289 /* This is similar to file_mips_opts, but for the current set of options. */ 290 291 static struct mips_set_options mips_opts = 292 { 293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 294 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 296 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 297 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 298 }; 299 300 /* Which bits of file_ase were explicitly set or cleared by ASE options. */ 301 static unsigned int file_ase_explicit; 302 303 /* These variables are filled in with the masks of registers used. 304 The object format code reads them and puts them in the appropriate 305 place. */ 306 unsigned long mips_gprmask; 307 unsigned long mips_cprmask[4]; 308 309 /* True if any MIPS16 code was produced. */ 310 static int file_ase_mips16; 311 312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ 313 || mips_opts.isa == ISA_MIPS32R2 \ 314 || mips_opts.isa == ISA_MIPS32R3 \ 315 || mips_opts.isa == ISA_MIPS32R5 \ 316 || mips_opts.isa == ISA_MIPS64 \ 317 || mips_opts.isa == ISA_MIPS64R2 \ 318 || mips_opts.isa == ISA_MIPS64R3 \ 319 || mips_opts.isa == ISA_MIPS64R5) 320 321 /* True if any microMIPS code was produced. */ 322 static int file_ase_micromips; 323 324 /* True if we want to create R_MIPS_JALR for jalr $25. */ 325 #ifdef TE_IRIX 326 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI 327 #else 328 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, 329 because there's no place for any addend, the only acceptable 330 expression is a bare symbol. */ 331 #define MIPS_JALR_HINT_P(EXPR) \ 332 (!HAVE_IN_PLACE_ADDENDS \ 333 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) 334 #endif 335 336 /* The argument of the -march= flag. The architecture we are assembling. */ 337 static const char *mips_arch_string; 338 339 /* The argument of the -mtune= flag. The architecture for which we 340 are optimizing. */ 341 static int mips_tune = CPU_UNKNOWN; 342 static const char *mips_tune_string; 343 344 /* True when generating 32-bit code for a 64-bit processor. */ 345 static int mips_32bitmode = 0; 346 347 /* True if the given ABI requires 32-bit registers. */ 348 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) 349 350 /* Likewise 64-bit registers. */ 351 #define ABI_NEEDS_64BIT_REGS(ABI) \ 352 ((ABI) == N32_ABI \ 353 || (ABI) == N64_ABI \ 354 || (ABI) == O64_ABI) 355 356 #define ISA_IS_R6(ISA) \ 357 ((ISA) == ISA_MIPS32R6 \ 358 || (ISA) == ISA_MIPS64R6) 359 360 /* Return true if ISA supports 64 bit wide gp registers. */ 361 #define ISA_HAS_64BIT_REGS(ISA) \ 362 ((ISA) == ISA_MIPS3 \ 363 || (ISA) == ISA_MIPS4 \ 364 || (ISA) == ISA_MIPS5 \ 365 || (ISA) == ISA_MIPS64 \ 366 || (ISA) == ISA_MIPS64R2 \ 367 || (ISA) == ISA_MIPS64R3 \ 368 || (ISA) == ISA_MIPS64R5 \ 369 || (ISA) == ISA_MIPS64R6) 370 371 /* Return true if ISA supports 64 bit wide float registers. */ 372 #define ISA_HAS_64BIT_FPRS(ISA) \ 373 ((ISA) == ISA_MIPS3 \ 374 || (ISA) == ISA_MIPS4 \ 375 || (ISA) == ISA_MIPS5 \ 376 || (ISA) == ISA_MIPS32R2 \ 377 || (ISA) == ISA_MIPS32R3 \ 378 || (ISA) == ISA_MIPS32R5 \ 379 || (ISA) == ISA_MIPS32R6 \ 380 || (ISA) == ISA_MIPS64 \ 381 || (ISA) == ISA_MIPS64R2 \ 382 || (ISA) == ISA_MIPS64R3 \ 383 || (ISA) == ISA_MIPS64R5 \ 384 || (ISA) == ISA_MIPS64R6) 385 386 /* Return true if ISA supports 64-bit right rotate (dror et al.) 387 instructions. */ 388 #define ISA_HAS_DROR(ISA) \ 389 ((ISA) == ISA_MIPS64R2 \ 390 || (ISA) == ISA_MIPS64R3 \ 391 || (ISA) == ISA_MIPS64R5 \ 392 || (ISA) == ISA_MIPS64R6 \ 393 || (mips_opts.micromips \ 394 && ISA_HAS_64BIT_REGS (ISA)) \ 395 ) 396 397 /* Return true if ISA supports 32-bit right rotate (ror et al.) 398 instructions. */ 399 #define ISA_HAS_ROR(ISA) \ 400 ((ISA) == ISA_MIPS32R2 \ 401 || (ISA) == ISA_MIPS32R3 \ 402 || (ISA) == ISA_MIPS32R5 \ 403 || (ISA) == ISA_MIPS32R6 \ 404 || (ISA) == ISA_MIPS64R2 \ 405 || (ISA) == ISA_MIPS64R3 \ 406 || (ISA) == ISA_MIPS64R5 \ 407 || (ISA) == ISA_MIPS64R6 \ 408 || (mips_opts.ase & ASE_SMARTMIPS) \ 409 || mips_opts.micromips \ 410 ) 411 412 /* Return true if ISA supports single-precision floats in odd registers. */ 413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ 414 (((ISA) == ISA_MIPS32 \ 415 || (ISA) == ISA_MIPS32R2 \ 416 || (ISA) == ISA_MIPS32R3 \ 417 || (ISA) == ISA_MIPS32R5 \ 418 || (ISA) == ISA_MIPS32R6 \ 419 || (ISA) == ISA_MIPS64 \ 420 || (ISA) == ISA_MIPS64R2 \ 421 || (ISA) == ISA_MIPS64R3 \ 422 || (ISA) == ISA_MIPS64R5 \ 423 || (ISA) == ISA_MIPS64R6 \ 424 || (CPU) == CPU_R5900) \ 425 && (CPU) != CPU_LOONGSON_3A) 426 427 /* Return true if ISA supports move to/from high part of a 64-bit 428 floating-point register. */ 429 #define ISA_HAS_MXHC1(ISA) \ 430 ((ISA) == ISA_MIPS32R2 \ 431 || (ISA) == ISA_MIPS32R3 \ 432 || (ISA) == ISA_MIPS32R5 \ 433 || (ISA) == ISA_MIPS32R6 \ 434 || (ISA) == ISA_MIPS64R2 \ 435 || (ISA) == ISA_MIPS64R3 \ 436 || (ISA) == ISA_MIPS64R5 \ 437 || (ISA) == ISA_MIPS64R6) 438 439 /* Return true if ISA supports legacy NAN. */ 440 #define ISA_HAS_LEGACY_NAN(ISA) \ 441 ((ISA) == ISA_MIPS1 \ 442 || (ISA) == ISA_MIPS2 \ 443 || (ISA) == ISA_MIPS3 \ 444 || (ISA) == ISA_MIPS4 \ 445 || (ISA) == ISA_MIPS5 \ 446 || (ISA) == ISA_MIPS32 \ 447 || (ISA) == ISA_MIPS32R2 \ 448 || (ISA) == ISA_MIPS32R3 \ 449 || (ISA) == ISA_MIPS32R5 \ 450 || (ISA) == ISA_MIPS64 \ 451 || (ISA) == ISA_MIPS64R2 \ 452 || (ISA) == ISA_MIPS64R3 \ 453 || (ISA) == ISA_MIPS64R5) 454 455 #define GPR_SIZE \ 456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ 457 ? 32 \ 458 : mips_opts.gp) 459 460 #define FPR_SIZE \ 461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ 462 ? 32 \ 463 : mips_opts.fp) 464 465 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) 466 467 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) 468 469 /* True if relocations are stored in-place. */ 470 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) 471 472 /* The ABI-derived address size. */ 473 #define HAVE_64BIT_ADDRESSES \ 474 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) 475 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) 476 477 /* The size of symbolic constants (i.e., expressions of the form 478 "SYMBOL" or "SYMBOL + OFFSET"). */ 479 #define HAVE_32BIT_SYMBOLS \ 480 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) 481 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) 482 483 /* Addresses are loaded in different ways, depending on the address size 484 in use. The n32 ABI Documentation also mandates the use of additions 485 with overflow checking, but existing implementations don't follow it. */ 486 #define ADDRESS_ADD_INSN \ 487 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") 488 489 #define ADDRESS_ADDI_INSN \ 490 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") 491 492 #define ADDRESS_LOAD_INSN \ 493 (HAVE_32BIT_ADDRESSES ? "lw" : "ld") 494 495 #define ADDRESS_STORE_INSN \ 496 (HAVE_32BIT_ADDRESSES ? "sw" : "sd") 497 498 /* Return true if the given CPU supports the MIPS16 ASE. */ 499 #define CPU_HAS_MIPS16(cpu) \ 500 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ 501 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) 502 503 /* Return true if the given CPU supports the microMIPS ASE. */ 504 #define CPU_HAS_MICROMIPS(cpu) 0 505 506 /* True if CPU has a dror instruction. */ 507 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) 508 509 /* True if CPU has a ror instruction. */ 510 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) 511 512 /* True if CPU is in the Octeon family */ 513 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ 514 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) 515 516 /* True if CPU has seq/sne and seqi/snei instructions. */ 517 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) 518 519 /* True, if CPU has support for ldc1 and sdc1. */ 520 #define CPU_HAS_LDC1_SDC1(CPU) \ 521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) 522 523 /* True if mflo and mfhi can be immediately followed by instructions 524 which write to the HI and LO registers. 525 526 According to MIPS specifications, MIPS ISAs I, II, and III need 527 (at least) two instructions between the reads of HI/LO and 528 instructions which write them, and later ISAs do not. Contradicting 529 the MIPS specifications, some MIPS IV processor user manuals (e.g. 530 the UM for the NEC Vr5000) document needing the instructions between 531 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 532 MIPS64 and later ISAs to have the interlocks, plus any specific 533 earlier-ISA CPUs for which CPU documentation declares that the 534 instructions are really interlocked. */ 535 #define hilo_interlocks \ 536 (mips_opts.isa == ISA_MIPS32 \ 537 || mips_opts.isa == ISA_MIPS32R2 \ 538 || mips_opts.isa == ISA_MIPS32R3 \ 539 || mips_opts.isa == ISA_MIPS32R5 \ 540 || mips_opts.isa == ISA_MIPS32R6 \ 541 || mips_opts.isa == ISA_MIPS64 \ 542 || mips_opts.isa == ISA_MIPS64R2 \ 543 || mips_opts.isa == ISA_MIPS64R3 \ 544 || mips_opts.isa == ISA_MIPS64R5 \ 545 || mips_opts.isa == ISA_MIPS64R6 \ 546 || mips_opts.arch == CPU_R4010 \ 547 || mips_opts.arch == CPU_R5900 \ 548 || mips_opts.arch == CPU_R10000 \ 549 || mips_opts.arch == CPU_R12000 \ 550 || mips_opts.arch == CPU_R14000 \ 551 || mips_opts.arch == CPU_R16000 \ 552 || mips_opts.arch == CPU_RM7000 \ 553 || mips_opts.arch == CPU_VR5500 \ 554 || mips_opts.micromips \ 555 ) 556 557 /* Whether the processor uses hardware interlocks to protect reads 558 from the GPRs after they are loaded from memory, and thus does not 559 require nops to be inserted. This applies to instructions marked 560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA 561 level I and microMIPS mode instructions are always interlocked. */ 562 #define gpr_interlocks \ 563 (mips_opts.isa != ISA_MIPS1 \ 564 || mips_opts.arch == CPU_R3900 \ 565 || mips_opts.arch == CPU_R5900 \ 566 || mips_opts.micromips \ 567 ) 568 569 /* Whether the processor uses hardware interlocks to avoid delays 570 required by coprocessor instructions, and thus does not require 571 nops to be inserted. This applies to instructions marked 572 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between 573 instructions marked INSN_WRITE_COND_CODE and ones marked 574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA 575 levels I, II, and III and microMIPS mode instructions are always 576 interlocked. */ 577 /* Itbl support may require additional care here. */ 578 #define cop_interlocks \ 579 ((mips_opts.isa != ISA_MIPS1 \ 580 && mips_opts.isa != ISA_MIPS2 \ 581 && mips_opts.isa != ISA_MIPS3) \ 582 || mips_opts.arch == CPU_R4300 \ 583 || mips_opts.micromips \ 584 ) 585 586 /* Whether the processor uses hardware interlocks to protect reads 587 from coprocessor registers after they are loaded from memory, and 588 thus does not require nops to be inserted. This applies to 589 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only 590 requires at MIPS ISA level I and microMIPS mode instructions are 591 always interlocked. */ 592 #define cop_mem_interlocks \ 593 (mips_opts.isa != ISA_MIPS1 \ 594 || mips_opts.micromips \ 595 ) 596 597 /* Is this a mfhi or mflo instruction? */ 598 #define MF_HILO_INSN(PINFO) \ 599 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) 600 601 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) 602 has been selected. This implies, in particular, that addresses of text 603 labels have their LSB set. */ 604 #define HAVE_CODE_COMPRESSION \ 605 ((mips_opts.mips16 | mips_opts.micromips) != 0) 606 607 /* The minimum and maximum signed values that can be stored in a GPR. */ 608 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) 609 #define GPR_SMIN (-GPR_SMAX - 1) 610 611 /* MIPS PIC level. */ 612 613 enum mips_pic_level mips_pic; 614 615 /* 1 if we should generate 32 bit offsets from the $gp register in 616 SVR4_PIC mode. Currently has no meaning in other modes. */ 617 static int mips_big_got = 0; 618 619 /* 1 if trap instructions should used for overflow rather than break 620 instructions. */ 621 static int mips_trap = 0; 622 623 /* 1 if double width floating point constants should not be constructed 624 by assembling two single width halves into two single width floating 625 point registers which just happen to alias the double width destination 626 register. On some architectures this aliasing can be disabled by a bit 627 in the status register, and the setting of this bit cannot be determined 628 automatically at assemble time. */ 629 static int mips_disable_float_construction; 630 631 /* Non-zero if any .set noreorder directives were used. */ 632 633 static int mips_any_noreorder; 634 635 /* Non-zero if nops should be inserted when the register referenced in 636 an mfhi/mflo instruction is read in the next two instructions. */ 637 static int mips_7000_hilo_fix; 638 639 /* The size of objects in the small data section. */ 640 static unsigned int g_switch_value = 8; 641 /* Whether the -G option was used. */ 642 static int g_switch_seen = 0; 643 644 #define N_RMASK 0xc4 645 #define N_VFP 0xd4 646 647 /* If we can determine in advance that GP optimization won't be 648 possible, we can skip the relaxation stuff that tries to produce 649 GP-relative references. This makes delay slot optimization work 650 better. 651 652 This function can only provide a guess, but it seems to work for 653 gcc output. It needs to guess right for gcc, otherwise gcc 654 will put what it thinks is a GP-relative instruction in a branch 655 delay slot. 656 657 I don't know if a fix is needed for the SVR4_PIC mode. I've only 658 fixed it for the non-PIC mode. KR 95/04/07 */ 659 static int nopic_need_relax (symbolS *, int); 660 661 /* handle of the OPCODE hash table */ 662 static struct hash_control *op_hash = NULL; 663 664 /* The opcode hash table we use for the mips16. */ 665 static struct hash_control *mips16_op_hash = NULL; 666 667 /* The opcode hash table we use for the microMIPS ASE. */ 668 static struct hash_control *micromips_op_hash = NULL; 669 670 /* This array holds the chars that always start a comment. If the 671 pre-processor is disabled, these aren't very useful */ 672 const char comment_chars[] = "#"; 673 674 /* This array holds the chars that only start a comment at the beginning of 675 a line. If the line seems to have the form '# 123 filename' 676 .line and .file directives will appear in the pre-processed output */ 677 /* Note that input_file.c hand checks for '#' at the beginning of the 678 first line of the input file. This is because the compiler outputs 679 #NO_APP at the beginning of its output. */ 680 /* Also note that C style comments are always supported. */ 681 const char line_comment_chars[] = "#"; 682 683 /* This array holds machine specific line separator characters. */ 684 const char line_separator_chars[] = ";"; 685 686 /* Chars that can be used to separate mant from exp in floating point nums */ 687 const char EXP_CHARS[] = "eE"; 688 689 /* Chars that mean this number is a floating point constant */ 690 /* As in 0f12.456 */ 691 /* or 0d1.2345e12 */ 692 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 693 694 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 695 changed in read.c . Ideally it shouldn't have to know about it at all, 696 but nothing is ideal around here. 697 */ 698 699 /* Types of printf format used for instruction-related error messages. 700 "I" means int ("%d") and "S" means string ("%s"). */ 701 enum mips_insn_error_format { 702 ERR_FMT_PLAIN, 703 ERR_FMT_I, 704 ERR_FMT_SS, 705 }; 706 707 /* Information about an error that was found while assembling the current 708 instruction. */ 709 struct mips_insn_error { 710 /* We sometimes need to match an instruction against more than one 711 opcode table entry. Errors found during this matching are reported 712 against a particular syntactic argument rather than against the 713 instruction as a whole. We grade these messages so that errors 714 against argument N have a greater priority than an error against 715 any argument < N, since the former implies that arguments up to N 716 were acceptable and that the opcode entry was therefore a closer match. 717 If several matches report an error against the same argument, 718 we only use that error if it is the same in all cases. 719 720 min_argnum is the minimum argument number for which an error message 721 should be accepted. It is 0 if MSG is against the instruction as 722 a whole. */ 723 int min_argnum; 724 725 /* The printf()-style message, including its format and arguments. */ 726 enum mips_insn_error_format format; 727 const char *msg; 728 union { 729 int i; 730 const char *ss[2]; 731 } u; 732 }; 733 734 /* The error that should be reported for the current instruction. */ 735 static struct mips_insn_error insn_error; 736 737 static int auto_align = 1; 738 739 /* When outputting SVR4 PIC code, the assembler needs to know the 740 offset in the stack frame from which to restore the $gp register. 741 This is set by the .cprestore pseudo-op, and saved in this 742 variable. */ 743 static offsetT mips_cprestore_offset = -1; 744 745 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some 746 more optimizations, it can use a register value instead of a memory-saved 747 offset and even an other register than $gp as global pointer. */ 748 static offsetT mips_cpreturn_offset = -1; 749 static int mips_cpreturn_register = -1; 750 static int mips_gp_register = GP; 751 static int mips_gprel_offset = 0; 752 753 /* Whether mips_cprestore_offset has been set in the current function 754 (or whether it has already been warned about, if not). */ 755 static int mips_cprestore_valid = 0; 756 757 /* This is the register which holds the stack frame, as set by the 758 .frame pseudo-op. This is needed to implement .cprestore. */ 759 static int mips_frame_reg = SP; 760 761 /* Whether mips_frame_reg has been set in the current function 762 (or whether it has already been warned about, if not). */ 763 static int mips_frame_reg_valid = 0; 764 765 /* To output NOP instructions correctly, we need to keep information 766 about the previous two instructions. */ 767 768 /* Whether we are optimizing. The default value of 2 means to remove 769 unneeded NOPs and swap branch instructions when possible. A value 770 of 1 means to not swap branches. A value of 0 means to always 771 insert NOPs. */ 772 static int mips_optimize = 2; 773 774 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is 775 equivalent to seeing no -g option at all. */ 776 static int mips_debug = 0; 777 778 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ 779 #define MAX_VR4130_NOPS 4 780 781 /* The maximum number of NOPs needed to fill delay slots. */ 782 #define MAX_DELAY_NOPS 2 783 784 /* The maximum number of NOPs needed for any purpose. */ 785 #define MAX_NOPS 4 786 787 /* A list of previous instructions, with index 0 being the most recent. 788 We need to look back MAX_NOPS instructions when filling delay slots 789 or working around processor errata. We need to look back one 790 instruction further if we're thinking about using history[0] to 791 fill a branch delay slot. */ 792 static struct mips_cl_insn history[1 + MAX_NOPS]; 793 794 /* Arrays of operands for each instruction. */ 795 #define MAX_OPERANDS 6 796 struct mips_operand_array { 797 const struct mips_operand *operand[MAX_OPERANDS]; 798 }; 799 static struct mips_operand_array *mips_operands; 800 static struct mips_operand_array *mips16_operands; 801 static struct mips_operand_array *micromips_operands; 802 803 /* Nop instructions used by emit_nop. */ 804 static struct mips_cl_insn nop_insn; 805 static struct mips_cl_insn mips16_nop_insn; 806 static struct mips_cl_insn micromips_nop16_insn; 807 static struct mips_cl_insn micromips_nop32_insn; 808 809 /* The appropriate nop for the current mode. */ 810 #define NOP_INSN (mips_opts.mips16 \ 811 ? &mips16_nop_insn \ 812 : (mips_opts.micromips \ 813 ? (mips_opts.insn32 \ 814 ? µmips_nop32_insn \ 815 : µmips_nop16_insn) \ 816 : &nop_insn)) 817 818 /* The size of NOP_INSN in bytes. */ 819 #define NOP_INSN_SIZE ((mips_opts.mips16 \ 820 || (mips_opts.micromips && !mips_opts.insn32)) \ 821 ? 2 : 4) 822 823 /* If this is set, it points to a frag holding nop instructions which 824 were inserted before the start of a noreorder section. If those 825 nops turn out to be unnecessary, the size of the frag can be 826 decreased. */ 827 static fragS *prev_nop_frag; 828 829 /* The number of nop instructions we created in prev_nop_frag. */ 830 static int prev_nop_frag_holds; 831 832 /* The number of nop instructions that we know we need in 833 prev_nop_frag. */ 834 static int prev_nop_frag_required; 835 836 /* The number of instructions we've seen since prev_nop_frag. */ 837 static int prev_nop_frag_since; 838 839 /* Relocations against symbols are sometimes done in two parts, with a HI 840 relocation and a LO relocation. Each relocation has only 16 bits of 841 space to store an addend. This means that in order for the linker to 842 handle carries correctly, it must be able to locate both the HI and 843 the LO relocation. This means that the relocations must appear in 844 order in the relocation table. 845 846 In order to implement this, we keep track of each unmatched HI 847 relocation. We then sort them so that they immediately precede the 848 corresponding LO relocation. */ 849 850 struct mips_hi_fixup 851 { 852 /* Next HI fixup. */ 853 struct mips_hi_fixup *next; 854 /* This fixup. */ 855 fixS *fixp; 856 /* The section this fixup is in. */ 857 segT seg; 858 }; 859 860 /* The list of unmatched HI relocs. */ 861 862 static struct mips_hi_fixup *mips_hi_fixup_list; 863 864 /* The frag containing the last explicit relocation operator. 865 Null if explicit relocations have not been used. */ 866 867 static fragS *prev_reloc_op_frag; 868 869 /* Map mips16 register numbers to normal MIPS register numbers. */ 870 871 static const unsigned int mips16_to_32_reg_map[] = 872 { 873 16, 17, 2, 3, 4, 5, 6, 7 874 }; 875 876 /* Map microMIPS register numbers to normal MIPS register numbers. */ 877 878 #define micromips_to_32_reg_d_map mips16_to_32_reg_map 879 880 /* The microMIPS registers with type h. */ 881 static const unsigned int micromips_to_32_reg_h_map1[] = 882 { 883 5, 5, 6, 4, 4, 4, 4, 4 884 }; 885 static const unsigned int micromips_to_32_reg_h_map2[] = 886 { 887 6, 7, 7, 21, 22, 5, 6, 7 888 }; 889 890 /* The microMIPS registers with type m. */ 891 static const unsigned int micromips_to_32_reg_m_map[] = 892 { 893 0, 17, 2, 3, 16, 18, 19, 20 894 }; 895 896 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map 897 898 /* Classifies the kind of instructions we're interested in when 899 implementing -mfix-vr4120. */ 900 enum fix_vr4120_class 901 { 902 FIX_VR4120_MACC, 903 FIX_VR4120_DMACC, 904 FIX_VR4120_MULT, 905 FIX_VR4120_DMULT, 906 FIX_VR4120_DIV, 907 FIX_VR4120_MTHILO, 908 NUM_FIX_VR4120_CLASSES 909 }; 910 911 /* ...likewise -mfix-loongson2f-jump. */ 912 static bfd_boolean mips_fix_loongson2f_jump; 913 914 /* ...likewise -mfix-loongson2f-nop. */ 915 static bfd_boolean mips_fix_loongson2f_nop; 916 917 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ 918 static bfd_boolean mips_fix_loongson2f; 919 920 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if 921 there must be at least one other instruction between an instruction 922 of type X and an instruction of type Y. */ 923 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; 924 925 /* True if -mfix-vr4120 is in force. */ 926 static int mips_fix_vr4120; 927 928 /* ...likewise -mfix-vr4130. */ 929 static int mips_fix_vr4130; 930 931 /* ...likewise -mfix-24k. */ 932 static int mips_fix_24k; 933 934 /* ...likewise -mfix-rm7000 */ 935 static int mips_fix_rm7000; 936 937 /* ...likewise -mfix-cn63xxp1 */ 938 static bfd_boolean mips_fix_cn63xxp1; 939 940 /* We don't relax branches by default, since this causes us to expand 941 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we 942 fail to compute the offset before expanding the macro to the most 943 efficient expansion. */ 944 945 static int mips_relax_branch; 946 947 /* The expansion of many macros depends on the type of symbol that 949 they refer to. For example, when generating position-dependent code, 950 a macro that refers to a symbol may have two different expansions, 951 one which uses GP-relative addresses and one which uses absolute 952 addresses. When generating SVR4-style PIC, a macro may have 953 different expansions for local and global symbols. 954 955 We handle these situations by generating both sequences and putting 956 them in variant frags. In position-dependent code, the first sequence 957 will be the GP-relative one and the second sequence will be the 958 absolute one. In SVR4 PIC, the first sequence will be for global 959 symbols and the second will be for local symbols. 960 961 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and 962 SECOND are the lengths of the two sequences in bytes. These fields 963 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, 964 the subtype has the following flags: 965 966 RELAX_USE_SECOND 967 Set if it has been decided that we should use the second 968 sequence instead of the first. 969 970 RELAX_SECOND_LONGER 971 Set in the first variant frag if the macro's second implementation 972 is longer than its first. This refers to the macro as a whole, 973 not an individual relaxation. 974 975 RELAX_NOMACRO 976 Set in the first variant frag if the macro appeared in a .set nomacro 977 block and if one alternative requires a warning but the other does not. 978 979 RELAX_DELAY_SLOT 980 Like RELAX_NOMACRO, but indicates that the macro appears in a branch 981 delay slot. 982 983 RELAX_DELAY_SLOT_16BIT 984 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a 985 16-bit instruction. 986 987 RELAX_DELAY_SLOT_SIZE_FIRST 988 Like RELAX_DELAY_SLOT, but indicates that the first implementation of 989 the macro is of the wrong size for the branch delay slot. 990 991 RELAX_DELAY_SLOT_SIZE_SECOND 992 Like RELAX_DELAY_SLOT, but indicates that the second implementation of 993 the macro is of the wrong size for the branch delay slot. 994 995 The frag's "opcode" points to the first fixup for relaxable code. 996 997 Relaxable macros are generated using a sequence such as: 998 999 relax_start (SYMBOL); 1000 ... generate first expansion ... 1001 relax_switch (); 1002 ... generate second expansion ... 1003 relax_end (); 1004 1005 The code and fixups for the unwanted alternative are discarded 1006 by md_convert_frag. */ 1007 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) 1008 1009 #define RELAX_FIRST(X) (((X) >> 8) & 0xff) 1010 #define RELAX_SECOND(X) ((X) & 0xff) 1011 #define RELAX_USE_SECOND 0x10000 1012 #define RELAX_SECOND_LONGER 0x20000 1013 #define RELAX_NOMACRO 0x40000 1014 #define RELAX_DELAY_SLOT 0x80000 1015 #define RELAX_DELAY_SLOT_16BIT 0x100000 1016 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 1017 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 1018 1019 /* Branch without likely bit. If label is out of range, we turn: 1020 1021 beq reg1, reg2, label 1022 delay slot 1023 1024 into 1025 1026 bne reg1, reg2, 0f 1027 nop 1028 j label 1029 0: delay slot 1030 1031 with the following opcode replacements: 1032 1033 beq <-> bne 1034 blez <-> bgtz 1035 bltz <-> bgez 1036 bc1f <-> bc1t 1037 1038 bltzal <-> bgezal (with jal label instead of j label) 1039 1040 Even though keeping the delay slot instruction in the delay slot of 1041 the branch would be more efficient, it would be very tricky to do 1042 correctly, because we'd have to introduce a variable frag *after* 1043 the delay slot instruction, and expand that instead. Let's do it 1044 the easy way for now, even if the branch-not-taken case now costs 1045 one additional instruction. Out-of-range branches are not supposed 1046 to be common, anyway. 1047 1048 Branch likely. If label is out of range, we turn: 1049 1050 beql reg1, reg2, label 1051 delay slot (annulled if branch not taken) 1052 1053 into 1054 1055 beql reg1, reg2, 1f 1056 nop 1057 beql $0, $0, 2f 1058 nop 1059 1: j[al] label 1060 delay slot (executed only if branch taken) 1061 2: 1062 1063 It would be possible to generate a shorter sequence by losing the 1064 likely bit, generating something like: 1065 1066 bne reg1, reg2, 0f 1067 nop 1068 j[al] label 1069 delay slot (executed only if branch taken) 1070 0: 1071 1072 beql -> bne 1073 bnel -> beq 1074 blezl -> bgtz 1075 bgtzl -> blez 1076 bltzl -> bgez 1077 bgezl -> bltz 1078 bc1fl -> bc1t 1079 bc1tl -> bc1f 1080 1081 bltzall -> bgezal (with jal label instead of j label) 1082 bgezall -> bltzal (ditto) 1083 1084 1085 but it's not clear that it would actually improve performance. */ 1086 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ 1087 ((relax_substateT) \ 1088 (0xc0000000 \ 1089 | ((at) & 0x1f) \ 1090 | ((toofar) ? 0x20 : 0) \ 1091 | ((link) ? 0x40 : 0) \ 1092 | ((likely) ? 0x80 : 0) \ 1093 | ((uncond) ? 0x100 : 0))) 1094 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 1095 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) 1096 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) 1097 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) 1098 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) 1099 #define RELAX_BRANCH_AT(i) ((i) & 0x1f) 1100 1101 /* For mips16 code, we use an entirely different form of relaxation. 1102 mips16 supports two versions of most instructions which take 1103 immediate values: a small one which takes some small value, and a 1104 larger one which takes a 16 bit value. Since branches also follow 1105 this pattern, relaxing these values is required. 1106 1107 We can assemble both mips16 and normal MIPS code in a single 1108 object. Therefore, we need to support this type of relaxation at 1109 the same time that we support the relaxation described above. We 1110 use the high bit of the subtype field to distinguish these cases. 1111 1112 The information we store for this type of relaxation is the 1113 argument code found in the opcode file for this relocation, whether 1114 the user explicitly requested a small or extended form, and whether 1115 the relocation is in a jump or jal delay slot. That tells us the 1116 size of the value, and how it should be stored. We also store 1117 whether the fragment is considered to be extended or not. We also 1118 store whether this is known to be a branch to a different section, 1119 whether we have tried to relax this frag yet, and whether we have 1120 ever extended a PC relative fragment because of a shift count. */ 1121 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ 1122 (0x80000000 \ 1123 | ((type) & 0xff) \ 1124 | ((small) ? 0x100 : 0) \ 1125 | ((ext) ? 0x200 : 0) \ 1126 | ((dslot) ? 0x400 : 0) \ 1127 | ((jal_dslot) ? 0x800 : 0)) 1128 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) 1129 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) 1130 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) 1131 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) 1132 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) 1133 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) 1134 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) 1135 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) 1136 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) 1137 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) 1138 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) 1139 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) 1140 1141 /* For microMIPS code, we use relaxation similar to one we use for 1142 MIPS16 code. Some instructions that take immediate values support 1143 two encodings: a small one which takes some small value, and a 1144 larger one which takes a 16 bit value. As some branches also follow 1145 this pattern, relaxing these values is required. 1146 1147 We can assemble both microMIPS and normal MIPS code in a single 1148 object. Therefore, we need to support this type of relaxation at 1149 the same time that we support the relaxation described above. We 1150 use one of the high bits of the subtype field to distinguish these 1151 cases. 1152 1153 The information we store for this type of relaxation is the argument 1154 code found in the opcode file for this relocation, the register 1155 selected as the assembler temporary, whether the branch is 1156 unconditional, whether it is compact, whether it stores the link 1157 address implicitly in $ra, whether relaxation of out-of-range 32-bit 1158 branches to a sequence of instructions is enabled, and whether the 1159 displacement of a branch is too large to fit as an immediate argument 1160 of a 16-bit and a 32-bit branch, respectively. */ 1161 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ 1162 relax32, toofar16, toofar32) \ 1163 (0x40000000 \ 1164 | ((type) & 0xff) \ 1165 | (((at) & 0x1f) << 8) \ 1166 | ((uncond) ? 0x2000 : 0) \ 1167 | ((compact) ? 0x4000 : 0) \ 1168 | ((link) ? 0x8000 : 0) \ 1169 | ((relax32) ? 0x10000 : 0) \ 1170 | ((toofar16) ? 0x20000 : 0) \ 1171 | ((toofar32) ? 0x40000 : 0)) 1172 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) 1173 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) 1174 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) 1175 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) 1176 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) 1177 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) 1178 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) 1179 1180 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) 1181 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) 1182 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) 1183 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) 1184 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) 1185 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) 1186 1187 /* Sign-extend 16-bit value X. */ 1188 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) 1189 1190 /* Is the given value a sign-extended 32-bit value? */ 1191 #define IS_SEXT_32BIT_NUM(x) \ 1192 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 1193 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 1194 1195 /* Is the given value a sign-extended 16-bit value? */ 1196 #define IS_SEXT_16BIT_NUM(x) \ 1197 (((x) &~ (offsetT) 0x7fff) == 0 \ 1198 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) 1199 1200 /* Is the given value a sign-extended 12-bit value? */ 1201 #define IS_SEXT_12BIT_NUM(x) \ 1202 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) 1203 1204 /* Is the given value a sign-extended 9-bit value? */ 1205 #define IS_SEXT_9BIT_NUM(x) \ 1206 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) 1207 1208 /* Is the given value a zero-extended 32-bit value? Or a negated one? */ 1209 #define IS_ZEXT_32BIT_NUM(x) \ 1210 (((x) &~ (offsetT) 0xffffffff) == 0 \ 1211 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 1212 1213 /* Extract bits MASK << SHIFT from STRUCT and shift them right 1214 SHIFT places. */ 1215 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ 1216 (((STRUCT) >> (SHIFT)) & (MASK)) 1217 1218 /* Extract the operand given by FIELD from mips_cl_insn INSN. */ 1219 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ 1220 (!(MICROMIPS) \ 1221 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ 1222 : EXTRACT_BITS ((INSN).insn_opcode, \ 1223 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) 1224 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ 1225 EXTRACT_BITS ((INSN).insn_opcode, \ 1226 MIPS16OP_MASK_##FIELD, \ 1227 MIPS16OP_SH_##FIELD) 1228 1229 /* The MIPS16 EXTEND opcode, shifted left 16 places. */ 1230 #define MIPS16_EXTEND (0xf000U << 16) 1231 1232 /* Whether or not we are emitting a branch-likely macro. */ 1234 static bfd_boolean emit_branch_likely_macro = FALSE; 1235 1236 /* Global variables used when generating relaxable macros. See the 1237 comment above RELAX_ENCODE for more details about how relaxation 1238 is used. */ 1239 static struct { 1240 /* 0 if we're not emitting a relaxable macro. 1241 1 if we're emitting the first of the two relaxation alternatives. 1242 2 if we're emitting the second alternative. */ 1243 int sequence; 1244 1245 /* The first relaxable fixup in the current frag. (In other words, 1246 the first fixup that refers to relaxable code.) */ 1247 fixS *first_fixup; 1248 1249 /* sizes[0] says how many bytes of the first alternative are stored in 1250 the current frag. Likewise sizes[1] for the second alternative. */ 1251 unsigned int sizes[2]; 1252 1253 /* The symbol on which the choice of sequence depends. */ 1254 symbolS *symbol; 1255 } mips_relax; 1256 1257 /* Global variables used to decide whether a macro needs a warning. */ 1259 static struct { 1260 /* True if the macro is in a branch delay slot. */ 1261 bfd_boolean delay_slot_p; 1262 1263 /* Set to the length in bytes required if the macro is in a delay slot 1264 that requires a specific length of instruction, otherwise zero. */ 1265 unsigned int delay_slot_length; 1266 1267 /* For relaxable macros, sizes[0] is the length of the first alternative 1268 in bytes and sizes[1] is the length of the second alternative. 1269 For non-relaxable macros, both elements give the length of the 1270 macro in bytes. */ 1271 unsigned int sizes[2]; 1272 1273 /* For relaxable macros, first_insn_sizes[0] is the length of the first 1274 instruction of the first alternative in bytes and first_insn_sizes[1] 1275 is the length of the first instruction of the second alternative. 1276 For non-relaxable macros, both elements give the length of the first 1277 instruction in bytes. 1278 1279 Set to zero if we haven't yet seen the first instruction. */ 1280 unsigned int first_insn_sizes[2]; 1281 1282 /* For relaxable macros, insns[0] is the number of instructions for the 1283 first alternative and insns[1] is the number of instructions for the 1284 second alternative. 1285 1286 For non-relaxable macros, both elements give the number of 1287 instructions for the macro. */ 1288 unsigned int insns[2]; 1289 1290 /* The first variant frag for this macro. */ 1291 fragS *first_frag; 1292 } mips_macro_warning; 1293 1294 /* Prototypes for static functions. */ 1296 1297 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; 1298 1299 static void append_insn 1300 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, 1301 bfd_boolean expansionp); 1302 static void mips_no_prev_insn (void); 1303 static void macro_build (expressionS *, const char *, const char *, ...); 1304 static void mips16_macro_build 1305 (expressionS *, const char *, const char *, va_list *); 1306 static void load_register (int, expressionS *, int); 1307 static void macro_start (void); 1308 static void macro_end (void); 1309 static void macro (struct mips_cl_insn *ip, char *str); 1310 static void mips16_macro (struct mips_cl_insn * ip); 1311 static void mips_ip (char *str, struct mips_cl_insn * ip); 1312 static void mips16_ip (char *str, struct mips_cl_insn * ip); 1313 static void mips16_immed 1314 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, 1315 unsigned int, unsigned long *); 1316 static size_t my_getSmallExpression 1317 (expressionS *, bfd_reloc_code_real_type *, char *); 1318 static void my_getExpression (expressionS *, char *); 1319 static void s_align (int); 1320 static void s_change_sec (int); 1321 static void s_change_section (int); 1322 static void s_cons (int); 1323 static void s_float_cons (int); 1324 static void s_mips_globl (int); 1325 static void s_option (int); 1326 static void s_mipsset (int); 1327 static void s_abicalls (int); 1328 static void s_cpload (int); 1329 static void s_cpsetup (int); 1330 static void s_cplocal (int); 1331 static void s_cprestore (int); 1332 static void s_cpreturn (int); 1333 static void s_dtprelword (int); 1334 static void s_dtpreldword (int); 1335 static void s_tprelword (int); 1336 static void s_tpreldword (int); 1337 static void s_gpvalue (int); 1338 static void s_gpword (int); 1339 static void s_gpdword (int); 1340 static void s_ehword (int); 1341 static void s_cpadd (int); 1342 static void s_insn (int); 1343 static void s_nan (int); 1344 static void s_module (int); 1345 static void s_mips_ent (int); 1346 static void s_mips_end (int); 1347 static void s_mips_frame (int); 1348 static void s_mips_mask (int reg_type); 1349 static void s_mips_stab (int); 1350 static void s_mips_weakext (int); 1351 static void s_mips_file (int); 1352 static void s_mips_loc (int); 1353 static bfd_boolean pic_need_relax (symbolS *, asection *); 1354 static int relaxed_branch_length (fragS *, asection *, int); 1355 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); 1356 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); 1357 static void file_mips_check_options (void); 1358 1359 /* Table and functions used to map between CPU/ISA names, and 1360 ISA levels, and CPU numbers. */ 1361 1362 struct mips_cpu_info 1363 { 1364 const char *name; /* CPU or ISA name. */ 1365 int flags; /* MIPS_CPU_* flags. */ 1366 int ase; /* Set of ASEs implemented by the CPU. */ 1367 int isa; /* ISA level. */ 1368 int cpu; /* CPU number (default CPU if ISA). */ 1369 }; 1370 1371 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ 1372 1373 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); 1374 static const struct mips_cpu_info *mips_cpu_info_from_isa (int); 1375 static const struct mips_cpu_info *mips_cpu_info_from_arch (int); 1376 1377 /* Command-line options. */ 1379 const char *md_shortopts = "O::g::G:"; 1380 1381 enum options 1382 { 1383 OPTION_MARCH = OPTION_MD_BASE, 1384 OPTION_MTUNE, 1385 OPTION_MIPS1, 1386 OPTION_MIPS2, 1387 OPTION_MIPS3, 1388 OPTION_MIPS4, 1389 OPTION_MIPS5, 1390 OPTION_MIPS32, 1391 OPTION_MIPS64, 1392 OPTION_MIPS32R2, 1393 OPTION_MIPS32R3, 1394 OPTION_MIPS32R5, 1395 OPTION_MIPS32R6, 1396 OPTION_MIPS64R2, 1397 OPTION_MIPS64R3, 1398 OPTION_MIPS64R5, 1399 OPTION_MIPS64R6, 1400 OPTION_MIPS16, 1401 OPTION_NO_MIPS16, 1402 OPTION_MIPS3D, 1403 OPTION_NO_MIPS3D, 1404 OPTION_MDMX, 1405 OPTION_NO_MDMX, 1406 OPTION_DSP, 1407 OPTION_NO_DSP, 1408 OPTION_MT, 1409 OPTION_NO_MT, 1410 OPTION_VIRT, 1411 OPTION_NO_VIRT, 1412 OPTION_MSA, 1413 OPTION_NO_MSA, 1414 OPTION_SMARTMIPS, 1415 OPTION_NO_SMARTMIPS, 1416 OPTION_DSPR2, 1417 OPTION_NO_DSPR2, 1418 OPTION_DSPR6, 1419 OPTION_NO_DSPR6, 1420 OPTION_EVA, 1421 OPTION_NO_EVA, 1422 OPTION_XPA, 1423 OPTION_NO_XPA, 1424 OPTION_MXU, 1425 OPTION_NO_MXU, 1426 OPTION_MICROMIPS, 1427 OPTION_NO_MICROMIPS, 1428 OPTION_MCU, 1429 OPTION_NO_MCU, 1430 OPTION_COMPAT_ARCH_BASE, 1431 OPTION_M4650, 1432 OPTION_NO_M4650, 1433 OPTION_M4010, 1434 OPTION_NO_M4010, 1435 OPTION_M4100, 1436 OPTION_NO_M4100, 1437 OPTION_M3900, 1438 OPTION_NO_M3900, 1439 OPTION_M7000_HILO_FIX, 1440 OPTION_MNO_7000_HILO_FIX, 1441 OPTION_FIX_24K, 1442 OPTION_NO_FIX_24K, 1443 OPTION_FIX_RM7000, 1444 OPTION_NO_FIX_RM7000, 1445 OPTION_FIX_LOONGSON2F_JUMP, 1446 OPTION_NO_FIX_LOONGSON2F_JUMP, 1447 OPTION_FIX_LOONGSON2F_NOP, 1448 OPTION_NO_FIX_LOONGSON2F_NOP, 1449 OPTION_FIX_VR4120, 1450 OPTION_NO_FIX_VR4120, 1451 OPTION_FIX_VR4130, 1452 OPTION_NO_FIX_VR4130, 1453 OPTION_FIX_CN63XXP1, 1454 OPTION_NO_FIX_CN63XXP1, 1455 OPTION_TRAP, 1456 OPTION_BREAK, 1457 OPTION_EB, 1458 OPTION_EL, 1459 OPTION_FP32, 1460 OPTION_GP32, 1461 OPTION_CONSTRUCT_FLOATS, 1462 OPTION_NO_CONSTRUCT_FLOATS, 1463 OPTION_FP64, 1464 OPTION_FPXX, 1465 OPTION_GP64, 1466 OPTION_RELAX_BRANCH, 1467 OPTION_NO_RELAX_BRANCH, 1468 OPTION_INSN32, 1469 OPTION_NO_INSN32, 1470 OPTION_MSHARED, 1471 OPTION_MNO_SHARED, 1472 OPTION_MSYM32, 1473 OPTION_MNO_SYM32, 1474 OPTION_SOFT_FLOAT, 1475 OPTION_HARD_FLOAT, 1476 OPTION_SINGLE_FLOAT, 1477 OPTION_DOUBLE_FLOAT, 1478 OPTION_32, 1479 OPTION_CALL_SHARED, 1480 OPTION_CALL_NONPIC, 1481 OPTION_NON_SHARED, 1482 OPTION_XGOT, 1483 OPTION_MABI, 1484 OPTION_N32, 1485 OPTION_64, 1486 OPTION_MDEBUG, 1487 OPTION_NO_MDEBUG, 1488 OPTION_PDR, 1489 OPTION_NO_PDR, 1490 OPTION_MVXWORKS_PIC, 1491 OPTION_NAN, 1492 OPTION_ODD_SPREG, 1493 OPTION_NO_ODD_SPREG, 1494 OPTION_END_OF_ENUM 1495 }; 1496 1497 struct option md_longopts[] = 1498 { 1499 /* Options which specify architecture. */ 1500 {"march", required_argument, NULL, OPTION_MARCH}, 1501 {"mtune", required_argument, NULL, OPTION_MTUNE}, 1502 {"mips0", no_argument, NULL, OPTION_MIPS1}, 1503 {"mips1", no_argument, NULL, OPTION_MIPS1}, 1504 {"mips2", no_argument, NULL, OPTION_MIPS2}, 1505 {"mips3", no_argument, NULL, OPTION_MIPS3}, 1506 {"mips4", no_argument, NULL, OPTION_MIPS4}, 1507 {"mips5", no_argument, NULL, OPTION_MIPS5}, 1508 {"mips32", no_argument, NULL, OPTION_MIPS32}, 1509 {"mips64", no_argument, NULL, OPTION_MIPS64}, 1510 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, 1511 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, 1512 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, 1513 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, 1514 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, 1515 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, 1516 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, 1517 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, 1518 1519 /* Options which specify Application Specific Extensions (ASEs). */ 1520 {"mips16", no_argument, NULL, OPTION_MIPS16}, 1521 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, 1522 {"mips3d", no_argument, NULL, OPTION_MIPS3D}, 1523 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, 1524 {"mdmx", no_argument, NULL, OPTION_MDMX}, 1525 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, 1526 {"mdsp", no_argument, NULL, OPTION_DSP}, 1527 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, 1528 {"mmt", no_argument, NULL, OPTION_MT}, 1529 {"mno-mt", no_argument, NULL, OPTION_NO_MT}, 1530 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, 1531 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, 1532 {"mdspr2", no_argument, NULL, OPTION_DSPR2}, 1533 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, 1534 {"mdspr6", no_argument, NULL, OPTION_DSPR6}, 1535 {"mno-dspr6", no_argument, NULL, OPTION_NO_DSPR6}, 1536 {"meva", no_argument, NULL, OPTION_EVA}, 1537 {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, 1538 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, 1539 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, 1540 {"mmcu", no_argument, NULL, OPTION_MCU}, 1541 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, 1542 {"mvirt", no_argument, NULL, OPTION_VIRT}, 1543 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, 1544 {"mmsa", no_argument, NULL, OPTION_MSA}, 1545 {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, 1546 {"mxpa", no_argument, NULL, OPTION_XPA}, 1547 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, 1548 {"mmxu", no_argument, NULL, OPTION_MXU}, 1549 {"mno-mxu", no_argument, NULL, OPTION_NO_MXU}, 1550 1551 /* Old-style architecture options. Don't add more of these. */ 1552 {"m4650", no_argument, NULL, OPTION_M4650}, 1553 {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, 1554 {"m4010", no_argument, NULL, OPTION_M4010}, 1555 {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, 1556 {"m4100", no_argument, NULL, OPTION_M4100}, 1557 {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, 1558 {"m3900", no_argument, NULL, OPTION_M3900}, 1559 {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, 1560 1561 /* Options which enable bug fixes. */ 1562 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, 1563 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1564 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1565 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, 1566 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, 1567 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, 1568 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, 1569 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 1570 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 1571 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, 1572 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, 1573 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, 1574 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, 1575 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, 1576 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, 1577 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, 1578 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, 1579 1580 /* Miscellaneous options. */ 1581 {"trap", no_argument, NULL, OPTION_TRAP}, 1582 {"no-break", no_argument, NULL, OPTION_TRAP}, 1583 {"break", no_argument, NULL, OPTION_BREAK}, 1584 {"no-trap", no_argument, NULL, OPTION_BREAK}, 1585 {"EB", no_argument, NULL, OPTION_EB}, 1586 {"EL", no_argument, NULL, OPTION_EL}, 1587 {"mfp32", no_argument, NULL, OPTION_FP32}, 1588 {"mgp32", no_argument, NULL, OPTION_GP32}, 1589 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, 1590 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, 1591 {"mfp64", no_argument, NULL, OPTION_FP64}, 1592 {"mfpxx", no_argument, NULL, OPTION_FPXX}, 1593 {"mgp64", no_argument, NULL, OPTION_GP64}, 1594 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, 1595 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, 1596 {"minsn32", no_argument, NULL, OPTION_INSN32}, 1597 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, 1598 {"mshared", no_argument, NULL, OPTION_MSHARED}, 1599 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, 1600 {"msym32", no_argument, NULL, OPTION_MSYM32}, 1601 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, 1602 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, 1603 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, 1604 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, 1605 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, 1606 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, 1607 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, 1608 1609 /* Strictly speaking this next option is ELF specific, 1610 but we allow it for other ports as well in order to 1611 make testing easier. */ 1612 {"32", no_argument, NULL, OPTION_32}, 1613 1614 /* ELF-specific options. */ 1615 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 1616 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, 1617 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, 1618 {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, 1619 {"xgot", no_argument, NULL, OPTION_XGOT}, 1620 {"mabi", required_argument, NULL, OPTION_MABI}, 1621 {"n32", no_argument, NULL, OPTION_N32}, 1622 {"64", no_argument, NULL, OPTION_64}, 1623 {"mdebug", no_argument, NULL, OPTION_MDEBUG}, 1624 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, 1625 {"mpdr", no_argument, NULL, OPTION_PDR}, 1626 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, 1627 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, 1628 {"mnan", required_argument, NULL, OPTION_NAN}, 1629 1630 {NULL, no_argument, NULL, 0} 1631 }; 1632 size_t md_longopts_size = sizeof (md_longopts); 1633 1634 /* Information about either an Application Specific Extension or an 1636 optional architecture feature that, for simplicity, we treat in the 1637 same way as an ASE. */ 1638 struct mips_ase 1639 { 1640 /* The name of the ASE, used in both the command-line and .set options. */ 1641 const char *name; 1642 1643 /* The associated ASE_* flags. If the ASE is available on both 32-bit 1644 and 64-bit architectures, the flags here refer to the subset that 1645 is available on both. */ 1646 unsigned int flags; 1647 1648 /* The ASE_* flag used for instructions that are available on 64-bit 1649 architectures but that are not included in FLAGS. */ 1650 unsigned int flags64; 1651 1652 /* The command-line options that turn the ASE on and off. */ 1653 int option_on; 1654 int option_off; 1655 1656 /* The minimum required architecture revisions for MIPS32, MIPS64, 1657 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ 1658 int mips32_rev; 1659 int mips64_rev; 1660 int micromips32_rev; 1661 int micromips64_rev; 1662 1663 /* The architecture where the ASE was removed or -1 if the extension has not 1664 been removed. */ 1665 int rem_rev; 1666 }; 1667 1668 /* A table of all supported ASEs. */ 1669 static const struct mips_ase mips_ases[] = { 1670 { "dsp", ASE_DSP, ASE_DSP64, 1671 OPTION_DSP, OPTION_NO_DSP, 1672 2, 2, 2, 2, 1673 -1 }, 1674 1675 { "dspr2", ASE_DSP | ASE_DSPR2, 0, 1676 OPTION_DSPR2, OPTION_NO_DSPR2, 1677 2, 2, 2, 2, 1678 -1 }, 1679 1680 { "dspr6", ASE_DSP | ASE_DSPR2 | ASE_DSPR6, 0, 1681 OPTION_DSPR6, OPTION_NO_DSPR6, 1682 6, 6, 6, 6, 1683 -1 }, 1684 1685 { "eva", ASE_EVA, 0, 1686 OPTION_EVA, OPTION_NO_EVA, 1687 2, 2, 2, 2, 1688 -1 }, 1689 1690 { "mcu", ASE_MCU, 0, 1691 OPTION_MCU, OPTION_NO_MCU, 1692 2, 2, 2, 2, 1693 -1 }, 1694 1695 /* Deprecated in MIPS64r5, but we don't implement that yet. */ 1696 { "mdmx", ASE_MDMX, 0, 1697 OPTION_MDMX, OPTION_NO_MDMX, 1698 -1, 1, -1, -1, 1699 6 }, 1700 1701 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ 1702 { "mips3d", ASE_MIPS3D, 0, 1703 OPTION_MIPS3D, OPTION_NO_MIPS3D, 1704 2, 1, -1, -1, 1705 6 }, 1706 1707 { "mt", ASE_MT, 0, 1708 OPTION_MT, OPTION_NO_MT, 1709 2, 2, -1, -1, 1710 -1 }, 1711 1712 { "smartmips", ASE_SMARTMIPS, 0, 1713 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, 1714 1, -1, -1, -1, 1715 6 }, 1716 1717 { "virt", ASE_VIRT, ASE_VIRT64, 1718 OPTION_VIRT, OPTION_NO_VIRT, 1719 2, 2, 2, 2, 1720 -1 }, 1721 1722 { "msa", ASE_MSA, ASE_MSA64, 1723 OPTION_MSA, OPTION_NO_MSA, 1724 2, 2, 2, 2, 1725 -1 }, 1726 1727 { "xpa", ASE_XPA, 0, 1728 OPTION_XPA, OPTION_NO_XPA, 1729 2, 2, -1, -1, 1730 -1 }, 1731 1732 { "mxu", ASE_MXU, 0, 1733 OPTION_MXU, OPTION_NO_MXU, 1734 1, 1, -1, -1, 1735 -1 }, 1736 }; 1737 1738 /* The set of ASEs that require -mfp64. */ 1739 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) 1740 1741 /* Groups of ASE_* flags that represent different revisions of an ASE. */ 1742 static const unsigned int mips_ase_groups[] = { 1743 ASE_DSP | ASE_DSPR2 | ASE_DSPR6 1744 }; 1745 1746 /* Pseudo-op table. 1748 1749 The following pseudo-ops from the Kane and Heinrich MIPS book 1750 should be defined here, but are currently unsupported: .alias, 1751 .galive, .gjaldef, .gjrlive, .livereg, .noalias. 1752 1753 The following pseudo-ops from the Kane and Heinrich MIPS book are 1754 specific to the type of debugging information being generated, and 1755 should be defined by the object format: .aent, .begin, .bend, 1756 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, 1757 .vreg. 1758 1759 The following pseudo-ops from the Kane and Heinrich MIPS book are 1760 not MIPS CPU specific, but are also not specific to the object file 1761 format. This file is probably the best place to define them, but 1762 they are not currently supported: .asm0, .endr, .lab, .struct. */ 1763 1764 static const pseudo_typeS mips_pseudo_table[] = 1765 { 1766 /* MIPS specific pseudo-ops. */ 1767 {"option", s_option, 0}, 1768 {"set", s_mipsset, 0}, 1769 {"rdata", s_change_sec, 'r'}, 1770 {"sdata", s_change_sec, 's'}, 1771 {"livereg", s_ignore, 0}, 1772 {"abicalls", s_abicalls, 0}, 1773 {"cpload", s_cpload, 0}, 1774 {"cpsetup", s_cpsetup, 0}, 1775 {"cplocal", s_cplocal, 0}, 1776 {"cprestore", s_cprestore, 0}, 1777 {"cpreturn", s_cpreturn, 0}, 1778 {"dtprelword", s_dtprelword, 0}, 1779 {"dtpreldword", s_dtpreldword, 0}, 1780 {"tprelword", s_tprelword, 0}, 1781 {"tpreldword", s_tpreldword, 0}, 1782 {"gpvalue", s_gpvalue, 0}, 1783 {"gpword", s_gpword, 0}, 1784 {"gpdword", s_gpdword, 0}, 1785 {"ehword", s_ehword, 0}, 1786 {"cpadd", s_cpadd, 0}, 1787 {"insn", s_insn, 0}, 1788 {"nan", s_nan, 0}, 1789 {"module", s_module, 0}, 1790 1791 /* Relatively generic pseudo-ops that happen to be used on MIPS 1792 chips. */ 1793 {"asciiz", stringer, 8 + 1}, 1794 {"bss", s_change_sec, 'b'}, 1795 {"err", s_err, 0}, 1796 {"half", s_cons, 1}, 1797 {"dword", s_cons, 3}, 1798 {"weakext", s_mips_weakext, 0}, 1799 {"origin", s_org, 0}, 1800 {"repeat", s_rept, 0}, 1801 1802 /* For MIPS this is non-standard, but we define it for consistency. */ 1803 {"sbss", s_change_sec, 'B'}, 1804 1805 /* These pseudo-ops are defined in read.c, but must be overridden 1806 here for one reason or another. */ 1807 {"align", s_align, 0}, 1808 {"byte", s_cons, 0}, 1809 {"data", s_change_sec, 'd'}, 1810 {"double", s_float_cons, 'd'}, 1811 {"float", s_float_cons, 'f'}, 1812 {"globl", s_mips_globl, 0}, 1813 {"global", s_mips_globl, 0}, 1814 {"hword", s_cons, 1}, 1815 {"int", s_cons, 2}, 1816 {"long", s_cons, 2}, 1817 {"octa", s_cons, 4}, 1818 {"quad", s_cons, 3}, 1819 {"section", s_change_section, 0}, 1820 {"short", s_cons, 1}, 1821 {"single", s_float_cons, 'f'}, 1822 {"stabd", s_mips_stab, 'd'}, 1823 {"stabn", s_mips_stab, 'n'}, 1824 {"stabs", s_mips_stab, 's'}, 1825 {"text", s_change_sec, 't'}, 1826 {"word", s_cons, 2}, 1827 1828 { "extern", ecoff_directive_extern, 0}, 1829 1830 { NULL, NULL, 0 }, 1831 }; 1832 1833 static const pseudo_typeS mips_nonecoff_pseudo_table[] = 1834 { 1835 /* These pseudo-ops should be defined by the object file format. 1836 However, a.out doesn't support them, so we have versions here. */ 1837 {"aent", s_mips_ent, 1}, 1838 {"bgnb", s_ignore, 0}, 1839 {"end", s_mips_end, 0}, 1840 {"endb", s_ignore, 0}, 1841 {"ent", s_mips_ent, 0}, 1842 {"file", s_mips_file, 0}, 1843 {"fmask", s_mips_mask, 'F'}, 1844 {"frame", s_mips_frame, 0}, 1845 {"loc", s_mips_loc, 0}, 1846 {"mask", s_mips_mask, 'R'}, 1847 {"verstamp", s_ignore, 0}, 1848 { NULL, NULL, 0 }, 1849 }; 1850 1851 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the 1852 purpose of the `.dc.a' internal pseudo-op. */ 1853 1854 int 1855 mips_address_bytes (void) 1856 { 1857 file_mips_check_options (); 1858 return HAVE_64BIT_ADDRESSES ? 8 : 4; 1859 } 1860 1861 extern void pop_insert (const pseudo_typeS *); 1862 1863 void 1864 mips_pop_insert (void) 1865 { 1866 pop_insert (mips_pseudo_table); 1867 if (! ECOFF_DEBUGGING) 1868 pop_insert (mips_nonecoff_pseudo_table); 1869 } 1870 1871 /* Symbols labelling the current insn. */ 1873 1874 struct insn_label_list 1875 { 1876 struct insn_label_list *next; 1877 symbolS *label; 1878 }; 1879 1880 static struct insn_label_list *free_insn_labels; 1881 #define label_list tc_segment_info_data.labels 1882 1883 static void mips_clear_insn_labels (void); 1884 static void mips_mark_labels (void); 1885 static void mips_compressed_mark_labels (void); 1886 1887 static inline void 1888 mips_clear_insn_labels (void) 1889 { 1890 struct insn_label_list **pl; 1891 segment_info_type *si; 1892 1893 if (now_seg) 1894 { 1895 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 1896 ; 1897 1898 si = seg_info (now_seg); 1899 *pl = si->label_list; 1900 si->label_list = NULL; 1901 } 1902 } 1903 1904 /* Mark instruction labels in MIPS16/microMIPS mode. */ 1905 1906 static inline void 1907 mips_mark_labels (void) 1908 { 1909 if (HAVE_CODE_COMPRESSION) 1910 mips_compressed_mark_labels (); 1911 } 1912 1913 static char *expr_end; 1915 1916 /* An expression in a macro instruction. This is set by mips_ip and 1917 mips16_ip and when populated is always an O_constant. */ 1918 1919 static expressionS imm_expr; 1920 1921 /* The relocatable field in an instruction and the relocs associated 1922 with it. These variables are used for instructions like LUI and 1923 JAL as well as true offsets. They are also used for address 1924 operands in macros. */ 1925 1926 static expressionS offset_expr; 1927 static bfd_reloc_code_real_type offset_reloc[3] 1928 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1929 1930 /* This is set to the resulting size of the instruction to be produced 1931 by mips16_ip if an explicit extension is used or by mips_ip if an 1932 explicit size is supplied. */ 1933 1934 static unsigned int forced_insn_length; 1935 1936 /* True if we are assembling an instruction. All dot symbols defined during 1937 this time should be treated as code labels. */ 1938 1939 static bfd_boolean mips_assembling_insn; 1940 1941 /* The pdr segment for per procedure frame/regmask info. Not used for 1942 ECOFF debugging. */ 1943 1944 static segT pdr_seg; 1945 1946 /* The default target format to use. */ 1947 1948 #if defined (TE_FreeBSD) 1949 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" 1950 #elif defined (TE_TMIPS) 1951 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" 1952 #else 1953 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" 1954 #endif 1955 1956 const char * 1957 mips_target_format (void) 1958 { 1959 switch (OUTPUT_FLAVOR) 1960 { 1961 case bfd_target_elf_flavour: 1962 #ifdef TE_VXWORKS 1963 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) 1964 return (target_big_endian 1965 ? "elf32-bigmips-vxworks" 1966 : "elf32-littlemips-vxworks"); 1967 #endif 1968 return (target_big_endian 1969 ? (HAVE_64BIT_OBJECTS 1970 ? ELF_TARGET ("elf64-", "big") 1971 : (HAVE_NEWABI 1972 ? ELF_TARGET ("elf32-n", "big") 1973 : ELF_TARGET ("elf32-", "big"))) 1974 : (HAVE_64BIT_OBJECTS 1975 ? ELF_TARGET ("elf64-", "little") 1976 : (HAVE_NEWABI 1977 ? ELF_TARGET ("elf32-n", "little") 1978 : ELF_TARGET ("elf32-", "little")))); 1979 default: 1980 abort (); 1981 return NULL; 1982 } 1983 } 1984 1985 /* Return the ISA revision that is currently in use, or 0 if we are 1986 generating code for MIPS V or below. */ 1987 1988 static int 1989 mips_isa_rev (void) 1990 { 1991 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) 1992 return 2; 1993 1994 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) 1995 return 3; 1996 1997 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) 1998 return 5; 1999 2000 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) 2001 return 6; 2002 2003 /* microMIPS implies revision 2 or above. */ 2004 if (mips_opts.micromips) 2005 return 2; 2006 2007 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) 2008 return 1; 2009 2010 return 0; 2011 } 2012 2013 /* Return the mask of all ASEs that are revisions of those in FLAGS. */ 2014 2015 static unsigned int 2016 mips_ase_mask (unsigned int flags) 2017 { 2018 unsigned int i; 2019 2020 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) 2021 if (flags & mips_ase_groups[i]) 2022 flags |= mips_ase_groups[i]; 2023 return flags; 2024 } 2025 2026 /* Check whether the current ISA supports ASE. Issue a warning if 2027 appropriate. */ 2028 2029 static void 2030 mips_check_isa_supports_ase (const struct mips_ase *ase) 2031 { 2032 const char *base; 2033 int min_rev, size; 2034 static unsigned int warned_isa; 2035 static unsigned int warned_fp32; 2036 2037 if (ISA_HAS_64BIT_REGS (mips_opts.isa)) 2038 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; 2039 else 2040 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; 2041 if ((min_rev < 0 || mips_isa_rev () < min_rev) 2042 && (warned_isa & ase->flags) != ase->flags) 2043 { 2044 warned_isa |= ase->flags; 2045 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2046 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2047 if (min_rev < 0) 2048 as_warn (_("the %d-bit %s architecture does not support the" 2049 " `%s' extension"), size, base, ase->name); 2050 else 2051 as_warn (_("the `%s' extension requires %s%d revision %d or greater"), 2052 ase->name, base, size, min_rev); 2053 } 2054 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) 2055 && (warned_isa & ase->flags) != ase->flags) 2056 { 2057 warned_isa |= ase->flags; 2058 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2059 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2060 as_warn (_("the `%s' extension was removed in %s%d revision %d"), 2061 ase->name, base, size, ase->rem_rev); 2062 } 2063 2064 if ((ase->flags & FP64_ASES) 2065 && mips_opts.fp != 64 2066 && (warned_fp32 & ase->flags) != ase->flags) 2067 { 2068 warned_fp32 |= ase->flags; 2069 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); 2070 } 2071 } 2072 2073 /* Check all enabled ASEs to see whether they are supported by the 2074 chosen architecture. */ 2075 2076 static void 2077 mips_check_isa_supports_ases (void) 2078 { 2079 unsigned int i, mask; 2080 2081 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2082 { 2083 mask = mips_ase_mask (mips_ases[i].flags); 2084 if ((mips_opts.ase & mask) == mips_ases[i].flags) 2085 mips_check_isa_supports_ase (&mips_ases[i]); 2086 } 2087 } 2088 2089 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags 2090 that were affected. */ 2091 2092 static unsigned int 2093 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, 2094 bfd_boolean enabled_p) 2095 { 2096 unsigned int mask; 2097 2098 mask = mips_ase_mask (ase->flags); 2099 opts->ase &= ~mask; 2100 if (enabled_p) 2101 opts->ase |= ase->flags; 2102 return mask; 2103 } 2104 2105 /* Return the ASE called NAME, or null if none. */ 2106 2107 static const struct mips_ase * 2108 mips_lookup_ase (const char *name) 2109 { 2110 unsigned int i; 2111 2112 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2113 if (strcmp (name, mips_ases[i].name) == 0) 2114 return &mips_ases[i]; 2115 return NULL; 2116 } 2117 2118 /* Return the length of a microMIPS instruction in bytes. If bits of 2119 the mask beyond the low 16 are 0, then it is a 16-bit instruction. 2120 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f 2121 major opcode) will require further modifications to the opcode 2122 table. */ 2123 2124 static inline unsigned int 2125 micromips_insn_length (const struct mips_opcode *mo) 2126 { 2127 return (mo->mask >> 16) == 0 ? 2 : 4; 2128 } 2129 2130 /* Return the length of MIPS16 instruction OPCODE. */ 2131 2132 static inline unsigned int 2133 mips16_opcode_length (unsigned long opcode) 2134 { 2135 return (opcode >> 16) == 0 ? 2 : 4; 2136 } 2137 2138 /* Return the length of instruction INSN. */ 2139 2140 static inline unsigned int 2141 insn_length (const struct mips_cl_insn *insn) 2142 { 2143 if (mips_opts.micromips) 2144 return micromips_insn_length (insn->insn_mo); 2145 else if (mips_opts.mips16) 2146 return mips16_opcode_length (insn->insn_opcode); 2147 else 2148 return 4; 2149 } 2150 2151 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 2152 2153 static void 2154 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) 2155 { 2156 size_t i; 2157 2158 insn->insn_mo = mo; 2159 insn->insn_opcode = mo->match; 2160 insn->frag = NULL; 2161 insn->where = 0; 2162 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2163 insn->fixp[i] = NULL; 2164 insn->fixed_p = (mips_opts.noreorder > 0); 2165 insn->noreorder_p = (mips_opts.noreorder > 0); 2166 insn->mips16_absolute_jump_p = 0; 2167 insn->complete_p = 0; 2168 insn->cleared_p = 0; 2169 } 2170 2171 /* Get a list of all the operands in INSN. */ 2172 2173 static const struct mips_operand_array * 2174 insn_operands (const struct mips_cl_insn *insn) 2175 { 2176 if (insn->insn_mo >= &mips_opcodes[0] 2177 && insn->insn_mo < &mips_opcodes[NUMOPCODES]) 2178 return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; 2179 2180 if (insn->insn_mo >= &mips16_opcodes[0] 2181 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) 2182 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; 2183 2184 if (insn->insn_mo >= µmips_opcodes[0] 2185 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) 2186 return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; 2187 2188 abort (); 2189 } 2190 2191 /* Get a description of operand OPNO of INSN. */ 2192 2193 static const struct mips_operand * 2194 insn_opno (const struct mips_cl_insn *insn, unsigned opno) 2195 { 2196 const struct mips_operand_array *operands; 2197 2198 operands = insn_operands (insn); 2199 if (opno >= MAX_OPERANDS || !operands->operand[opno]) 2200 abort (); 2201 return operands->operand[opno]; 2202 } 2203 2204 /* Install UVAL as the value of OPERAND in INSN. */ 2205 2206 static inline void 2207 insn_insert_operand (struct mips_cl_insn *insn, 2208 const struct mips_operand *operand, unsigned int uval) 2209 { 2210 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); 2211 } 2212 2213 /* Extract the value of OPERAND from INSN. */ 2214 2215 static inline unsigned 2216 insn_extract_operand (const struct mips_cl_insn *insn, 2217 const struct mips_operand *operand) 2218 { 2219 return mips_extract_operand (operand, insn->insn_opcode); 2220 } 2221 2222 /* Record the current MIPS16/microMIPS mode in now_seg. */ 2223 2224 static void 2225 mips_record_compressed_mode (void) 2226 { 2227 segment_info_type *si; 2228 2229 si = seg_info (now_seg); 2230 if (si->tc_segment_info_data.mips16 != mips_opts.mips16) 2231 si->tc_segment_info_data.mips16 = mips_opts.mips16; 2232 if (si->tc_segment_info_data.micromips != mips_opts.micromips) 2233 si->tc_segment_info_data.micromips = mips_opts.micromips; 2234 } 2235 2236 /* Read a standard MIPS instruction from BUF. */ 2237 2238 static unsigned long 2239 read_insn (char *buf) 2240 { 2241 if (target_big_endian) 2242 return bfd_getb32 ((bfd_byte *) buf); 2243 else 2244 return bfd_getl32 ((bfd_byte *) buf); 2245 } 2246 2247 /* Write standard MIPS instruction INSN to BUF. Return a pointer to 2248 the next byte. */ 2249 2250 static char * 2251 write_insn (char *buf, unsigned int insn) 2252 { 2253 md_number_to_chars (buf, insn, 4); 2254 return buf + 4; 2255 } 2256 2257 /* Read a microMIPS or MIPS16 opcode from BUF, given that it 2258 has length LENGTH. */ 2259 2260 static unsigned long 2261 read_compressed_insn (char *buf, unsigned int length) 2262 { 2263 unsigned long insn; 2264 unsigned int i; 2265 2266 insn = 0; 2267 for (i = 0; i < length; i += 2) 2268 { 2269 insn <<= 16; 2270 if (target_big_endian) 2271 insn |= bfd_getb16 ((char *) buf); 2272 else 2273 insn |= bfd_getl16 ((char *) buf); 2274 buf += 2; 2275 } 2276 return insn; 2277 } 2278 2279 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the 2280 instruction is LENGTH bytes long. Return a pointer to the next byte. */ 2281 2282 static char * 2283 write_compressed_insn (char *buf, unsigned int insn, unsigned int length) 2284 { 2285 unsigned int i; 2286 2287 for (i = 0; i < length; i += 2) 2288 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); 2289 return buf + length; 2290 } 2291 2292 /* Install INSN at the location specified by its "frag" and "where" fields. */ 2293 2294 static void 2295 install_insn (const struct mips_cl_insn *insn) 2296 { 2297 char *f = insn->frag->fr_literal + insn->where; 2298 if (HAVE_CODE_COMPRESSION) 2299 write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); 2300 else 2301 write_insn (f, insn->insn_opcode); 2302 mips_record_compressed_mode (); 2303 } 2304 2305 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 2306 and install the opcode in the new location. */ 2307 2308 static void 2309 move_insn (struct mips_cl_insn *insn, fragS *frag, long where) 2310 { 2311 size_t i; 2312 2313 insn->frag = frag; 2314 insn->where = where; 2315 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2316 if (insn->fixp[i] != NULL) 2317 { 2318 insn->fixp[i]->fx_frag = frag; 2319 insn->fixp[i]->fx_where = where; 2320 } 2321 install_insn (insn); 2322 } 2323 2324 /* Add INSN to the end of the output. */ 2325 2326 static void 2327 add_fixed_insn (struct mips_cl_insn *insn) 2328 { 2329 char *f = frag_more (insn_length (insn)); 2330 move_insn (insn, frag_now, f - frag_now->fr_literal); 2331 } 2332 2333 /* Start a variant frag and move INSN to the start of the variant part, 2334 marking it as fixed. The other arguments are as for frag_var. */ 2335 2336 static void 2337 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, 2338 relax_substateT subtype, symbolS *symbol, offsetT offset) 2339 { 2340 frag_grow (max_chars); 2341 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 2342 insn->fixed_p = 1; 2343 frag_var (rs_machine_dependent, max_chars, var, 2344 subtype, symbol, offset, NULL); 2345 } 2346 2347 /* Insert N copies of INSN into the history buffer, starting at 2348 position FIRST. Neither FIRST nor N need to be clipped. */ 2349 2350 static void 2351 insert_into_history (unsigned int first, unsigned int n, 2352 const struct mips_cl_insn *insn) 2353 { 2354 if (mips_relax.sequence != 2) 2355 { 2356 unsigned int i; 2357 2358 for (i = ARRAY_SIZE (history); i-- > first;) 2359 if (i >= first + n) 2360 history[i] = history[i - n]; 2361 else 2362 history[i] = *insn; 2363 } 2364 } 2365 2366 /* Clear the error in insn_error. */ 2367 2368 static void 2369 clear_insn_error (void) 2370 { 2371 memset (&insn_error, 0, sizeof (insn_error)); 2372 } 2373 2374 /* Possibly record error message MSG for the current instruction. 2375 If the error is about a particular argument, ARGNUM is the 1-based 2376 number of that argument, otherwise it is 0. FORMAT is the format 2377 of MSG. Return true if MSG was used, false if the current message 2378 was kept. */ 2379 2380 static bfd_boolean 2381 set_insn_error_format (int argnum, enum mips_insn_error_format format, 2382 const char *msg) 2383 { 2384 if (argnum == 0) 2385 { 2386 /* Give priority to errors against specific arguments, and to 2387 the first whole-instruction message. */ 2388 if (insn_error.msg) 2389 return FALSE; 2390 } 2391 else 2392 { 2393 /* Keep insn_error if it is against a later argument. */ 2394 if (argnum < insn_error.min_argnum) 2395 return FALSE; 2396 2397 /* If both errors are against the same argument but are different, 2398 give up on reporting a specific error for this argument. 2399 See the comment about mips_insn_error for details. */ 2400 if (argnum == insn_error.min_argnum 2401 && insn_error.msg 2402 && strcmp (insn_error.msg, msg) != 0) 2403 { 2404 insn_error.msg = 0; 2405 insn_error.min_argnum += 1; 2406 return FALSE; 2407 } 2408 } 2409 insn_error.min_argnum = argnum; 2410 insn_error.format = format; 2411 insn_error.msg = msg; 2412 return TRUE; 2413 } 2414 2415 /* Record an instruction error with no % format fields. ARGNUM and MSG are 2416 as for set_insn_error_format. */ 2417 2418 static void 2419 set_insn_error (int argnum, const char *msg) 2420 { 2421 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); 2422 } 2423 2424 /* Record an instruction error with one %d field I. ARGNUM and MSG are 2425 as for set_insn_error_format. */ 2426 2427 static void 2428 set_insn_error_i (int argnum, const char *msg, int i) 2429 { 2430 if (set_insn_error_format (argnum, ERR_FMT_I, msg)) 2431 insn_error.u.i = i; 2432 } 2433 2434 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG 2435 are as for set_insn_error_format. */ 2436 2437 static void 2438 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) 2439 { 2440 if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) 2441 { 2442 insn_error.u.ss[0] = s1; 2443 insn_error.u.ss[1] = s2; 2444 } 2445 } 2446 2447 /* Report the error in insn_error, which is against assembly code STR. */ 2448 2449 static void 2450 report_insn_error (const char *str) 2451 { 2452 const char *msg; 2453 2454 msg = ACONCAT ((insn_error.msg, " `%s'", NULL)); 2455 switch (insn_error.format) 2456 { 2457 case ERR_FMT_PLAIN: 2458 as_bad (msg, str); 2459 break; 2460 2461 case ERR_FMT_I: 2462 as_bad (msg, insn_error.u.i, str); 2463 break; 2464 2465 case ERR_FMT_SS: 2466 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); 2467 break; 2468 } 2469 } 2470 2471 /* Initialize vr4120_conflicts. There is a bit of duplication here: 2472 the idea is to make it obvious at a glance that each errata is 2473 included. */ 2474 2475 static void 2476 init_vr4120_conflicts (void) 2477 { 2478 #define CONFLICT(FIRST, SECOND) \ 2479 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND 2480 2481 /* Errata 21 - [D]DIV[U] after [D]MACC */ 2482 CONFLICT (MACC, DIV); 2483 CONFLICT (DMACC, DIV); 2484 2485 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ 2486 CONFLICT (DMULT, DMULT); 2487 CONFLICT (DMULT, DMACC); 2488 CONFLICT (DMACC, DMULT); 2489 CONFLICT (DMACC, DMACC); 2490 2491 /* Errata 24 - MT{LO,HI} after [D]MACC */ 2492 CONFLICT (MACC, MTHILO); 2493 CONFLICT (DMACC, MTHILO); 2494 2495 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU 2496 instruction is executed immediately after a MACC or DMACC 2497 instruction, the result of [either instruction] is incorrect." */ 2498 CONFLICT (MACC, MULT); 2499 CONFLICT (MACC, DMULT); 2500 CONFLICT (DMACC, MULT); 2501 CONFLICT (DMACC, DMULT); 2502 2503 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is 2504 executed immediately after a DMULT, DMULTU, DIV, DIVU, 2505 DDIV or DDIVU instruction, the result of the MACC or 2506 DMACC instruction is incorrect.". */ 2507 CONFLICT (DMULT, MACC); 2508 CONFLICT (DMULT, DMACC); 2509 CONFLICT (DIV, MACC); 2510 CONFLICT (DIV, DMACC); 2511 2512 #undef CONFLICT 2513 } 2514 2515 struct regname { 2516 const char *name; 2517 unsigned int num; 2518 }; 2519 2520 #define RNUM_MASK 0x00000ff 2521 #define RTYPE_MASK 0x1ffff00 2522 #define RTYPE_NUM 0x0000100 2523 #define RTYPE_FPU 0x0000200 2524 #define RTYPE_FCC 0x0000400 2525 #define RTYPE_VEC 0x0000800 2526 #define RTYPE_GP 0x0001000 2527 #define RTYPE_CP0 0x0002000 2528 #define RTYPE_PC 0x0004000 2529 #define RTYPE_ACC 0x0008000 2530 #define RTYPE_CCC 0x0010000 2531 #define RTYPE_VI 0x0020000 2532 #define RTYPE_VF 0x0040000 2533 #define RTYPE_R5900_I 0x0080000 2534 #define RTYPE_R5900_Q 0x0100000 2535 #define RTYPE_R5900_R 0x0200000 2536 #define RTYPE_R5900_ACC 0x0400000 2537 #define RTYPE_MSA 0x0800000 2538 #define RTYPE_MXU 0x1000000 2539 #define RWARN 0x8000000 2540 2541 #define GENERIC_REGISTER_NUMBERS \ 2542 {"$0", RTYPE_NUM | 0}, \ 2543 {"$1", RTYPE_NUM | 1}, \ 2544 {"$2", RTYPE_NUM | 2}, \ 2545 {"$3", RTYPE_NUM | 3}, \ 2546 {"$4", RTYPE_NUM | 4}, \ 2547 {"$5", RTYPE_NUM | 5}, \ 2548 {"$6", RTYPE_NUM | 6}, \ 2549 {"$7", RTYPE_NUM | 7}, \ 2550 {"$8", RTYPE_NUM | 8}, \ 2551 {"$9", RTYPE_NUM | 9}, \ 2552 {"$10", RTYPE_NUM | 10}, \ 2553 {"$11", RTYPE_NUM | 11}, \ 2554 {"$12", RTYPE_NUM | 12}, \ 2555 {"$13", RTYPE_NUM | 13}, \ 2556 {"$14", RTYPE_NUM | 14}, \ 2557 {"$15", RTYPE_NUM | 15}, \ 2558 {"$16", RTYPE_NUM | 16}, \ 2559 {"$17", RTYPE_NUM | 17}, \ 2560 {"$18", RTYPE_NUM | 18}, \ 2561 {"$19", RTYPE_NUM | 19}, \ 2562 {"$20", RTYPE_NUM | 20}, \ 2563 {"$21", RTYPE_NUM | 21}, \ 2564 {"$22", RTYPE_NUM | 22}, \ 2565 {"$23", RTYPE_NUM | 23}, \ 2566 {"$24", RTYPE_NUM | 24}, \ 2567 {"$25", RTYPE_NUM | 25}, \ 2568 {"$26", RTYPE_NUM | 26}, \ 2569 {"$27", RTYPE_NUM | 27}, \ 2570 {"$28", RTYPE_NUM | 28}, \ 2571 {"$29", RTYPE_NUM | 29}, \ 2572 {"$30", RTYPE_NUM | 30}, \ 2573 {"$31", RTYPE_NUM | 31} 2574 2575 #define FPU_REGISTER_NAMES \ 2576 {"$f0", RTYPE_FPU | 0}, \ 2577 {"$f1", RTYPE_FPU | 1}, \ 2578 {"$f2", RTYPE_FPU | 2}, \ 2579 {"$f3", RTYPE_FPU | 3}, \ 2580 {"$f4", RTYPE_FPU | 4}, \ 2581 {"$f5", RTYPE_FPU | 5}, \ 2582 {"$f6", RTYPE_FPU | 6}, \ 2583 {"$f7", RTYPE_FPU | 7}, \ 2584 {"$f8", RTYPE_FPU | 8}, \ 2585 {"$f9", RTYPE_FPU | 9}, \ 2586 {"$f10", RTYPE_FPU | 10}, \ 2587 {"$f11", RTYPE_FPU | 11}, \ 2588 {"$f12", RTYPE_FPU | 12}, \ 2589 {"$f13", RTYPE_FPU | 13}, \ 2590 {"$f14", RTYPE_FPU | 14}, \ 2591 {"$f15", RTYPE_FPU | 15}, \ 2592 {"$f16", RTYPE_FPU | 16}, \ 2593 {"$f17", RTYPE_FPU | 17}, \ 2594 {"$f18", RTYPE_FPU | 18}, \ 2595 {"$f19", RTYPE_FPU | 19}, \ 2596 {"$f20", RTYPE_FPU | 20}, \ 2597 {"$f21", RTYPE_FPU | 21}, \ 2598 {"$f22", RTYPE_FPU | 22}, \ 2599 {"$f23", RTYPE_FPU | 23}, \ 2600 {"$f24", RTYPE_FPU | 24}, \ 2601 {"$f25", RTYPE_FPU | 25}, \ 2602 {"$f26", RTYPE_FPU | 26}, \ 2603 {"$f27", RTYPE_FPU | 27}, \ 2604 {"$f28", RTYPE_FPU | 28}, \ 2605 {"$f29", RTYPE_FPU | 29}, \ 2606 {"$f30", RTYPE_FPU | 30}, \ 2607 {"$f31", RTYPE_FPU | 31} 2608 2609 #define FPU_CONDITION_CODE_NAMES \ 2610 {"$fcc0", RTYPE_FCC | 0}, \ 2611 {"$fcc1", RTYPE_FCC | 1}, \ 2612 {"$fcc2", RTYPE_FCC | 2}, \ 2613 {"$fcc3", RTYPE_FCC | 3}, \ 2614 {"$fcc4", RTYPE_FCC | 4}, \ 2615 {"$fcc5", RTYPE_FCC | 5}, \ 2616 {"$fcc6", RTYPE_FCC | 6}, \ 2617 {"$fcc7", RTYPE_FCC | 7} 2618 2619 #define COPROC_CONDITION_CODE_NAMES \ 2620 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ 2621 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ 2622 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ 2623 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ 2624 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ 2625 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ 2626 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ 2627 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} 2628 2629 #define N32N64_SYMBOLIC_REGISTER_NAMES \ 2630 {"$a4", RTYPE_GP | 8}, \ 2631 {"$a5", RTYPE_GP | 9}, \ 2632 {"$a6", RTYPE_GP | 10}, \ 2633 {"$a7", RTYPE_GP | 11}, \ 2634 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ 2635 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ 2636 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ 2637 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ 2638 {"$t0", RTYPE_GP | 12}, \ 2639 {"$t1", RTYPE_GP | 13}, \ 2640 {"$t2", RTYPE_GP | 14}, \ 2641 {"$t3", RTYPE_GP | 15} 2642 2643 #define O32_SYMBOLIC_REGISTER_NAMES \ 2644 {"$t0", RTYPE_GP | 8}, \ 2645 {"$t1", RTYPE_GP | 9}, \ 2646 {"$t2", RTYPE_GP | 10}, \ 2647 {"$t3", RTYPE_GP | 11}, \ 2648 {"$t4", RTYPE_GP | 12}, \ 2649 {"$t5", RTYPE_GP | 13}, \ 2650 {"$t6", RTYPE_GP | 14}, \ 2651 {"$t7", RTYPE_GP | 15}, \ 2652 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ 2653 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ 2654 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ 2655 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ 2656 2657 /* Remaining symbolic register names */ 2658 #define SYMBOLIC_REGISTER_NAMES \ 2659 {"$zero", RTYPE_GP | 0}, \ 2660 {"$at", RTYPE_GP | 1}, \ 2661 {"$AT", RTYPE_GP | 1}, \ 2662 {"$v0", RTYPE_GP | 2}, \ 2663 {"$v1", RTYPE_GP | 3}, \ 2664 {"$a0", RTYPE_GP | 4}, \ 2665 {"$a1", RTYPE_GP | 5}, \ 2666 {"$a2", RTYPE_GP | 6}, \ 2667 {"$a3", RTYPE_GP | 7}, \ 2668 {"$s0", RTYPE_GP | 16}, \ 2669 {"$s1", RTYPE_GP | 17}, \ 2670 {"$s2", RTYPE_GP | 18}, \ 2671 {"$s3", RTYPE_GP | 19}, \ 2672 {"$s4", RTYPE_GP | 20}, \ 2673 {"$s5", RTYPE_GP | 21}, \ 2674 {"$s6", RTYPE_GP | 22}, \ 2675 {"$s7", RTYPE_GP | 23}, \ 2676 {"$t8", RTYPE_GP | 24}, \ 2677 {"$t9", RTYPE_GP | 25}, \ 2678 {"$k0", RTYPE_GP | 26}, \ 2679 {"$kt0", RTYPE_GP | 26}, \ 2680 {"$k1", RTYPE_GP | 27}, \ 2681 {"$kt1", RTYPE_GP | 27}, \ 2682 {"$gp", RTYPE_GP | 28}, \ 2683 {"$sp", RTYPE_GP | 29}, \ 2684 {"$s8", RTYPE_GP | 30}, \ 2685 {"$fp", RTYPE_GP | 30}, \ 2686 {"$ra", RTYPE_GP | 31} 2687 2688 #define MIPS16_SPECIAL_REGISTER_NAMES \ 2689 {"$pc", RTYPE_PC | 0} 2690 2691 #define MDMX_VECTOR_REGISTER_NAMES \ 2692 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ 2693 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ 2694 {"$v2", RTYPE_VEC | 2}, \ 2695 {"$v3", RTYPE_VEC | 3}, \ 2696 {"$v4", RTYPE_VEC | 4}, \ 2697 {"$v5", RTYPE_VEC | 5}, \ 2698 {"$v6", RTYPE_VEC | 6}, \ 2699 {"$v7", RTYPE_VEC | 7}, \ 2700 {"$v8", RTYPE_VEC | 8}, \ 2701 {"$v9", RTYPE_VEC | 9}, \ 2702 {"$v10", RTYPE_VEC | 10}, \ 2703 {"$v11", RTYPE_VEC | 11}, \ 2704 {"$v12", RTYPE_VEC | 12}, \ 2705 {"$v13", RTYPE_VEC | 13}, \ 2706 {"$v14", RTYPE_VEC | 14}, \ 2707 {"$v15", RTYPE_VEC | 15}, \ 2708 {"$v16", RTYPE_VEC | 16}, \ 2709 {"$v17", RTYPE_VEC | 17}, \ 2710 {"$v18", RTYPE_VEC | 18}, \ 2711 {"$v19", RTYPE_VEC | 19}, \ 2712 {"$v20", RTYPE_VEC | 20}, \ 2713 {"$v21", RTYPE_VEC | 21}, \ 2714 {"$v22", RTYPE_VEC | 22}, \ 2715 {"$v23", RTYPE_VEC | 23}, \ 2716 {"$v24", RTYPE_VEC | 24}, \ 2717 {"$v25", RTYPE_VEC | 25}, \ 2718 {"$v26", RTYPE_VEC | 26}, \ 2719 {"$v27", RTYPE_VEC | 27}, \ 2720 {"$v28", RTYPE_VEC | 28}, \ 2721 {"$v29", RTYPE_VEC | 29}, \ 2722 {"$v30", RTYPE_VEC | 30}, \ 2723 {"$v31", RTYPE_VEC | 31} 2724 2725 #define R5900_I_NAMES \ 2726 {"$I", RTYPE_R5900_I | 0} 2727 2728 #define R5900_Q_NAMES \ 2729 {"$Q", RTYPE_R5900_Q | 0} 2730 2731 #define R5900_R_NAMES \ 2732 {"$R", RTYPE_R5900_R | 0} 2733 2734 #define R5900_ACC_NAMES \ 2735 {"$ACC", RTYPE_R5900_ACC | 0 } 2736 2737 #define MIPS_DSP_ACCUMULATOR_NAMES \ 2738 {"$ac0", RTYPE_ACC | 0}, \ 2739 {"$ac1", RTYPE_ACC | 1}, \ 2740 {"$ac2", RTYPE_ACC | 2}, \ 2741 {"$ac3", RTYPE_ACC | 3} 2742 2743 #define MXU_REGISTER_NAMES \ 2744 {"xr0", RTYPE_MXU | 0}, \ 2745 {"xr1", RTYPE_MXU | 1}, \ 2746 {"xr2", RTYPE_MXU | 2}, \ 2747 {"xr3", RTYPE_MXU | 3}, \ 2748 {"xr4", RTYPE_MXU | 4}, \ 2749 {"xr5", RTYPE_MXU | 5}, \ 2750 {"xr6", RTYPE_MXU | 6}, \ 2751 {"xr7", RTYPE_MXU | 7}, \ 2752 {"xr8", RTYPE_MXU | 8}, \ 2753 {"xr9", RTYPE_MXU | 9}, \ 2754 {"xr10", RTYPE_MXU | 10}, \ 2755 {"xr11", RTYPE_MXU | 11}, \ 2756 {"xr12", RTYPE_MXU | 12}, \ 2757 {"xr13", RTYPE_MXU | 13}, \ 2758 {"xr14", RTYPE_MXU | 14}, \ 2759 {"xr15", RTYPE_MXU | 15}, \ 2760 {"xr16", RTYPE_MXU | 16}, \ 2761 {"mxu_cr", RTYPE_MXU | 16} 2762 2763 static const struct regname reg_names[] = { 2764 GENERIC_REGISTER_NUMBERS, 2765 FPU_REGISTER_NAMES, 2766 FPU_CONDITION_CODE_NAMES, 2767 COPROC_CONDITION_CODE_NAMES, 2768 2769 /* The $txx registers depends on the abi, 2770 these will be added later into the symbol table from 2771 one of the tables below once mips_abi is set after 2772 parsing of arguments from the command line. */ 2773 SYMBOLIC_REGISTER_NAMES, 2774 2775 MIPS16_SPECIAL_REGISTER_NAMES, 2776 MDMX_VECTOR_REGISTER_NAMES, 2777 R5900_I_NAMES, 2778 R5900_Q_NAMES, 2779 R5900_R_NAMES, 2780 R5900_ACC_NAMES, 2781 MIPS_DSP_ACCUMULATOR_NAMES, 2782 MXU_REGISTER_NAMES, 2783 {0, 0} 2784 }; 2785 2786 static const struct regname reg_names_o32[] = { 2787 O32_SYMBOLIC_REGISTER_NAMES, 2788 {0, 0} 2789 }; 2790 2791 static const struct regname reg_names_n32n64[] = { 2792 N32N64_SYMBOLIC_REGISTER_NAMES, 2793 {0, 0} 2794 }; 2795 2796 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be 2797 interpreted as vector registers 0 and 1. If SYMVAL is the value of one 2798 of these register symbols, return the associated vector register, 2799 otherwise return SYMVAL itself. */ 2800 2801 static unsigned int 2802 mips_prefer_vec_regno (unsigned int symval) 2803 { 2804 if ((symval & -2) == (RTYPE_GP | 2)) 2805 return RTYPE_VEC | (symval & 1); 2806 return symval; 2807 } 2808 2809 /* Return true if string [S, E) is a valid register name, storing its 2810 symbol value in *SYMVAL_PTR if so. */ 2811 2812 static bfd_boolean 2813 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) 2814 { 2815 char save_c; 2816 symbolS *symbol; 2817 2818 /* Terminate name. */ 2819 save_c = *e; 2820 *e = '\0'; 2821 2822 /* Look up the name. */ 2823 symbol = symbol_find (s); 2824 *e = save_c; 2825 2826 if (!symbol || S_GET_SEGMENT (symbol) != reg_section) 2827 return FALSE; 2828 2829 *symval_ptr = S_GET_VALUE (symbol); 2830 return TRUE; 2831 } 2832 2833 /* Return true if the string at *SPTR is a valid register name. Allow it 2834 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR 2835 is nonnull. 2836 2837 When returning true, move *SPTR past the register, store the 2838 register's symbol value in *SYMVAL_PTR and the channel mask in 2839 *CHANNELS_PTR (if nonnull). The symbol value includes the register 2840 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask 2841 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ 2842 2843 static bfd_boolean 2844 mips_parse_register (char **sptr, unsigned int *symval_ptr, 2845 unsigned int *channels_ptr) 2846 { 2847 char *s, *e, *m; 2848 const char *q; 2849 unsigned int channels, symval, bit; 2850 2851 /* Find end of name. */ 2852 s = e = *sptr; 2853 if (is_name_beginner (*e)) 2854 ++e; 2855 while (is_part_of_name (*e)) 2856 ++e; 2857 2858 channels = 0; 2859 if (!mips_parse_register_1 (s, e, &symval)) 2860 { 2861 if (!channels_ptr) 2862 return FALSE; 2863 2864 /* Eat characters from the end of the string that are valid 2865 channel suffixes. The preceding register must be $ACC or 2866 end with a digit, so there is no ambiguity. */ 2867 bit = 1; 2868 m = e; 2869 for (q = "wzyx"; *q; q++, bit <<= 1) 2870 if (m > s && m[-1] == *q) 2871 { 2872 --m; 2873 channels |= bit; 2874 } 2875 2876 if (channels == 0 2877 || !mips_parse_register_1 (s, m, &symval) 2878 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) 2879 return FALSE; 2880 } 2881 2882 *sptr = e; 2883 *symval_ptr = symval; 2884 if (channels_ptr) 2885 *channels_ptr = channels; 2886 return TRUE; 2887 } 2888 2889 /* Check if SPTR points at a valid register specifier according to TYPES. 2890 If so, then return 1, advance S to consume the specifier and store 2891 the register's number in REGNOP, otherwise return 0. */ 2892 2893 static int 2894 reg_lookup (char **s, unsigned int types, unsigned int *regnop) 2895 { 2896 unsigned int regno; 2897 2898 if (mips_parse_register (s, ®no, NULL)) 2899 { 2900 if (types & RTYPE_VEC) 2901 regno = mips_prefer_vec_regno (regno); 2902 if (regno & types) 2903 regno &= RNUM_MASK; 2904 else 2905 regno = ~0; 2906 } 2907 else 2908 { 2909 if (types & RWARN) 2910 as_warn (_("unrecognized register name `%s'"), *s); 2911 regno = ~0; 2912 } 2913 if (regnop) 2914 *regnop = regno; 2915 return regno <= RNUM_MASK; 2916 } 2917 2918 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated 2919 mask in *CHANNELS. Return a pointer to the first unconsumed character. */ 2920 2921 static char * 2922 mips_parse_vu0_channels (char *s, unsigned int *channels) 2923 { 2924 unsigned int i; 2925 2926 *channels = 0; 2927 for (i = 0; i < 4; i++) 2928 if (*s == "xyzw"[i]) 2929 { 2930 *channels |= 1 << (3 - i); 2931 ++s; 2932 } 2933 return s; 2934 } 2935 2936 /* Token types for parsed operand lists. */ 2937 enum mips_operand_token_type { 2938 /* A plain register, e.g. $f2. */ 2939 OT_REG, 2940 2941 /* A 4-bit XYZW channel mask. */ 2942 OT_CHANNELS, 2943 2944 /* A constant vector index, e.g. [1]. */ 2945 OT_INTEGER_INDEX, 2946 2947 /* A register vector index, e.g. [$2]. */ 2948 OT_REG_INDEX, 2949 2950 /* A continuous range of registers, e.g. $s0-$s4. */ 2951 OT_REG_RANGE, 2952 2953 /* A (possibly relocated) expression. */ 2954 OT_INTEGER, 2955 2956 /* A floating-point value. */ 2957 OT_FLOAT, 2958 2959 /* A single character. This can be '(', ')' or ',', but '(' only appears 2960 before OT_REGs. */ 2961 OT_CHAR, 2962 2963 /* A doubled character, either "--" or "++". */ 2964 OT_DOUBLE_CHAR, 2965 2966 /* The end of the operand list. */ 2967 OT_END 2968 }; 2969 2970 /* A parsed operand token. */ 2971 struct mips_operand_token 2972 { 2973 /* The type of token. */ 2974 enum mips_operand_token_type type; 2975 union 2976 { 2977 /* The register symbol value for an OT_REG or OT_REG_INDEX. */ 2978 unsigned int regno; 2979 2980 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ 2981 unsigned int channels; 2982 2983 /* The integer value of an OT_INTEGER_INDEX. */ 2984 addressT index; 2985 2986 /* The two register symbol values involved in an OT_REG_RANGE. */ 2987 struct { 2988 unsigned int regno1; 2989 unsigned int regno2; 2990 } reg_range; 2991 2992 /* The value of an OT_INTEGER. The value is represented as an 2993 expression and the relocation operators that were applied to 2994 that expression. The reloc entries are BFD_RELOC_UNUSED if no 2995 relocation operators were used. */ 2996 struct { 2997 expressionS value; 2998 bfd_reloc_code_real_type relocs[3]; 2999 } integer; 3000 3001 /* The binary data for an OT_FLOAT constant, and the number of bytes 3002 in the constant. */ 3003 struct { 3004 unsigned char data[8]; 3005 int length; 3006 } flt; 3007 3008 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ 3009 char ch; 3010 } u; 3011 }; 3012 3013 /* An obstack used to construct lists of mips_operand_tokens. */ 3014 static struct obstack mips_operand_tokens; 3015 3016 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ 3017 3018 static void 3019 mips_add_token (struct mips_operand_token *token, 3020 enum mips_operand_token_type type) 3021 { 3022 token->type = type; 3023 obstack_grow (&mips_operand_tokens, token, sizeof (*token)); 3024 } 3025 3026 /* Check whether S is '(' followed by a register name. Add OT_CHAR 3027 and OT_REG tokens for them if so, and return a pointer to the first 3028 unconsumed character. Return null otherwise. */ 3029 3030 static char * 3031 mips_parse_base_start (char *s) 3032 { 3033 struct mips_operand_token token; 3034 unsigned int regno, channels; 3035 bfd_boolean decrement_p; 3036 3037 if (*s != '(') 3038 return 0; 3039 3040 ++s; 3041 SKIP_SPACE_TABS (s); 3042 3043 /* Only match "--" as part of a base expression. In other contexts "--X" 3044 is a double negative. */ 3045 decrement_p = (s[0] == '-' && s[1] == '-'); 3046 if (decrement_p) 3047 { 3048 s += 2; 3049 SKIP_SPACE_TABS (s); 3050 } 3051 3052 /* Allow a channel specifier because that leads to better error messages 3053 than treating something like "$vf0x++" as an expression. */ 3054 if (!mips_parse_register (&s, ®no, &channels)) 3055 return 0; 3056 3057 token.u.ch = '('; 3058 mips_add_token (&token, OT_CHAR); 3059 3060 if (decrement_p) 3061 { 3062 token.u.ch = '-'; 3063 mips_add_token (&token, OT_DOUBLE_CHAR); 3064 } 3065 3066 token.u.regno = regno; 3067 mips_add_token (&token, OT_REG); 3068 3069 if (channels) 3070 { 3071 token.u.channels = channels; 3072 mips_add_token (&token, OT_CHANNELS); 3073 } 3074 3075 /* For consistency, only match "++" as part of base expressions too. */ 3076 SKIP_SPACE_TABS (s); 3077 if (s[0] == '+' && s[1] == '+') 3078 { 3079 s += 2; 3080 token.u.ch = '+'; 3081 mips_add_token (&token, OT_DOUBLE_CHAR); 3082 } 3083 3084 return s; 3085 } 3086 3087 /* Parse one or more tokens from S. Return a pointer to the first 3088 unconsumed character on success. Return null if an error was found 3089 and store the error text in insn_error. FLOAT_FORMAT is as for 3090 mips_parse_arguments. */ 3091 3092 static char * 3093 mips_parse_argument_token (char *s, char float_format) 3094 { 3095 char *end, *save_in, *err; 3096 unsigned int regno1, regno2, channels; 3097 struct mips_operand_token token; 3098 3099 /* First look for "($reg", since we want to treat that as an 3100 OT_CHAR and OT_REG rather than an expression. */ 3101 end = mips_parse_base_start (s); 3102 if (end) 3103 return end; 3104 3105 /* Handle other characters that end up as OT_CHARs. */ 3106 if (*s == ')' || *s == ',') 3107 { 3108 token.u.ch = *s; 3109 mips_add_token (&token, OT_CHAR); 3110 ++s; 3111 return s; 3112 } 3113 3114 /* Handle tokens that start with a register. */ 3115 if (mips_parse_register (&s, ®no1, &channels)) 3116 { 3117 if (channels) 3118 { 3119 /* A register and a VU0 channel suffix. */ 3120 token.u.regno = regno1; 3121 mips_add_token (&token, OT_REG); 3122 3123 token.u.channels = channels; 3124 mips_add_token (&token, OT_CHANNELS); 3125 return s; 3126 } 3127 3128 SKIP_SPACE_TABS (s); 3129 if (*s == '-') 3130 { 3131 /* A register range. */ 3132 ++s; 3133 SKIP_SPACE_TABS (s); 3134 if (!mips_parse_register (&s, ®no2, NULL)) 3135 { 3136 set_insn_error (0, _("invalid register range")); 3137 return 0; 3138 } 3139 3140 token.u.reg_range.regno1 = regno1; 3141 token.u.reg_range.regno2 = regno2; 3142 mips_add_token (&token, OT_REG_RANGE); 3143 return s; 3144 } 3145 3146 /* Add the register itself. */ 3147 token.u.regno = regno1; 3148 mips_add_token (&token, OT_REG); 3149 3150 /* Check for a vector index. */ 3151 if (*s == '[') 3152 { 3153 ++s; 3154 SKIP_SPACE_TABS (s); 3155 if (mips_parse_register (&s, &token.u.regno, NULL)) 3156 mips_add_token (&token, OT_REG_INDEX); 3157 else 3158 { 3159 expressionS element; 3160 3161 my_getExpression (&element, s); 3162 if (element.X_op != O_constant) 3163 { 3164 set_insn_error (0, _("vector element must be constant")); 3165 return 0; 3166 } 3167 s = expr_end; 3168 token.u.index = element.X_add_number; 3169 mips_add_token (&token, OT_INTEGER_INDEX); 3170 } 3171 SKIP_SPACE_TABS (s); 3172 if (*s != ']') 3173 { 3174 set_insn_error (0, _("missing `]'")); 3175 return 0; 3176 } 3177 ++s; 3178 } 3179 return s; 3180 } 3181 3182 if (float_format) 3183 { 3184 /* First try to treat expressions as floats. */ 3185 save_in = input_line_pointer; 3186 input_line_pointer = s; 3187 err = md_atof (float_format, (char *) token.u.flt.data, 3188 &token.u.flt.length); 3189 end = input_line_pointer; 3190 input_line_pointer = save_in; 3191 if (err && *err) 3192 { 3193 set_insn_error (0, err); 3194 return 0; 3195 } 3196 if (s != end) 3197 { 3198 mips_add_token (&token, OT_FLOAT); 3199 return end; 3200 } 3201 } 3202 3203 /* Treat everything else as an integer expression. */ 3204 token.u.integer.relocs[0] = BFD_RELOC_UNUSED; 3205 token.u.integer.relocs[1] = BFD_RELOC_UNUSED; 3206 token.u.integer.relocs[2] = BFD_RELOC_UNUSED; 3207 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); 3208 s = expr_end; 3209 mips_add_token (&token, OT_INTEGER); 3210 return s; 3211 } 3212 3213 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' 3214 if expressions should be treated as 32-bit floating-point constants, 3215 'd' if they should be treated as 64-bit floating-point constants, 3216 or 0 if they should be treated as integer expressions (the usual case). 3217 3218 Return a list of tokens on success, otherwise return 0. The caller 3219 must obstack_free the list after use. */ 3220 3221 static struct mips_operand_token * 3222 mips_parse_arguments (char *s, char float_format) 3223 { 3224 struct mips_operand_token token; 3225 3226 SKIP_SPACE_TABS (s); 3227 while (*s) 3228 { 3229 s = mips_parse_argument_token (s, float_format); 3230 if (!s) 3231 { 3232 obstack_free (&mips_operand_tokens, 3233 obstack_finish (&mips_operand_tokens)); 3234 return 0; 3235 } 3236 SKIP_SPACE_TABS (s); 3237 } 3238 mips_add_token (&token, OT_END); 3239 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); 3240 } 3241 3242 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE 3243 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ 3244 3245 static bfd_boolean 3246 is_opcode_valid (const struct mips_opcode *mo) 3247 { 3248 int isa = mips_opts.isa; 3249 int ase = mips_opts.ase; 3250 int fp_s, fp_d; 3251 unsigned int i; 3252 3253 if (ISA_HAS_64BIT_REGS (mips_opts.isa)) 3254 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 3255 if ((ase & mips_ases[i].flags) == mips_ases[i].flags) 3256 ase |= mips_ases[i].flags64; 3257 3258 if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) 3259 return FALSE; 3260 3261 /* Check whether the instruction or macro requires single-precision or 3262 double-precision floating-point support. Note that this information is 3263 stored differently in the opcode table for insns and macros. */ 3264 if (mo->pinfo == INSN_MACRO) 3265 { 3266 fp_s = mo->pinfo2 & INSN2_M_FP_S; 3267 fp_d = mo->pinfo2 & INSN2_M_FP_D; 3268 } 3269 else 3270 { 3271 fp_s = mo->pinfo & FP_S; 3272 fp_d = mo->pinfo & FP_D; 3273 } 3274 3275 if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) 3276 return FALSE; 3277 3278 if (fp_s && mips_opts.soft_float) 3279 return FALSE; 3280 3281 return TRUE; 3282 } 3283 3284 /* Return TRUE if the MIPS16 opcode MO is valid on the currently 3285 selected ISA and architecture. */ 3286 3287 static bfd_boolean 3288 is_opcode_valid_16 (const struct mips_opcode *mo) 3289 { 3290 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); 3291 } 3292 3293 /* Return TRUE if the size of the microMIPS opcode MO matches one 3294 explicitly requested. Always TRUE in the standard MIPS mode. */ 3295 3296 static bfd_boolean 3297 is_size_valid (const struct mips_opcode *mo) 3298 { 3299 if (!mips_opts.micromips) 3300 return TRUE; 3301 3302 if (mips_opts.insn32) 3303 { 3304 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) 3305 return FALSE; 3306 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) 3307 return FALSE; 3308 } 3309 if (!forced_insn_length) 3310 return TRUE; 3311 if (mo->pinfo == INSN_MACRO) 3312 return FALSE; 3313 return forced_insn_length == micromips_insn_length (mo); 3314 } 3315 3316 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot 3317 of the preceding instruction. Always TRUE in the standard MIPS mode. 3318 3319 We don't accept macros in 16-bit delay slots to avoid a case where 3320 a macro expansion fails because it relies on a preceding 32-bit real 3321 instruction to have matched and does not handle the operands correctly. 3322 The only macros that may expand to 16-bit instructions are JAL that 3323 cannot be placed in a delay slot anyway, and corner cases of BALIGN 3324 and BGT (that likewise cannot be placed in a delay slot) that decay to 3325 a NOP. In all these cases the macros precede any corresponding real 3326 instruction definitions in the opcode table, so they will match in the 3327 second pass where the size of the delay slot is ignored and therefore 3328 produce correct code. */ 3329 3330 static bfd_boolean 3331 is_delay_slot_valid (const struct mips_opcode *mo) 3332 { 3333 if (!mips_opts.micromips) 3334 return TRUE; 3335 3336 if (mo->pinfo == INSN_MACRO) 3337 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; 3338 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 3339 && micromips_insn_length (mo) != 4) 3340 return FALSE; 3341 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 3342 && micromips_insn_length (mo) != 2) 3343 return FALSE; 3344 3345 return TRUE; 3346 } 3347 3348 /* For consistency checking, verify that all bits of OPCODE are specified 3349 either by the match/mask part of the instruction definition, or by the 3350 operand list. Also build up a list of operands in OPERANDS. 3351 3352 INSN_BITS says which bits of the instruction are significant. 3353 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND 3354 provides the mips_operand description of each operand. DECODE_OPERAND 3355 is null for MIPS16 instructions. */ 3356 3357 static int 3358 validate_mips_insn (const struct mips_opcode *opcode, 3359 unsigned long insn_bits, 3360 const struct mips_operand *(*decode_operand) (const char *), 3361 struct mips_operand_array *operands) 3362 { 3363 const char *s; 3364 unsigned long used_bits, doubled, undefined, opno, mask; 3365 const struct mips_operand *operand; 3366 3367 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); 3368 if ((mask & opcode->match) != opcode->match) 3369 { 3370 as_bad (_("internal: bad mips opcode (mask error): %s %s"), 3371 opcode->name, opcode->args); 3372 return 0; 3373 } 3374 used_bits = 0; 3375 opno = 0; 3376 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 3377 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); 3378 for (s = opcode->args; *s; ++s) 3379 switch (*s) 3380 { 3381 case ',': 3382 case '(': 3383 case ')': 3384 break; 3385 3386 case '#': 3387 s++; 3388 break; 3389 3390 default: 3391 if (!decode_operand) 3392 operand = decode_mips16_operand (*s, FALSE); 3393 else 3394 operand = decode_operand (s); 3395 if (!operand && opcode->pinfo != INSN_MACRO) 3396 { 3397 as_bad (_("internal: unknown operand type: %s %s"), 3398 opcode->name, opcode->args); 3399 return 0; 3400 } 3401 gas_assert (opno < MAX_OPERANDS); 3402 operands->operand[opno] = operand; 3403 if (operand && operand->type != OP_VU0_MATCH_SUFFIX) 3404 { 3405 used_bits = mips_insert_operand (operand, used_bits, -1); 3406 if (operand->type == OP_MDMX_IMM_REG) 3407 /* Bit 5 is the format selector (OB vs QH). The opcode table 3408 has separate entries for each format. */ 3409 used_bits &= ~(1 << (operand->lsb + 5)); 3410 if (operand->type == OP_ENTRY_EXIT_LIST) 3411 used_bits &= ~(mask & 0x700); 3412 } 3413 /* Skip prefix characters. */ 3414 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-' || *s == '`')) 3415 ++s; 3416 opno += 1; 3417 break; 3418 } 3419 doubled = used_bits & mask & insn_bits; 3420 if (doubled) 3421 { 3422 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" 3423 " %s %s"), doubled, opcode->name, opcode->args); 3424 return 0; 3425 } 3426 used_bits |= mask; 3427 undefined = ~used_bits & insn_bits; 3428 if (opcode->pinfo != INSN_MACRO && undefined) 3429 { 3430 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), 3431 undefined, opcode->name, opcode->args); 3432 return 0; 3433 } 3434 used_bits &= ~insn_bits; 3435 if (used_bits) 3436 { 3437 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), 3438 used_bits, opcode->name, opcode->args); 3439 return 0; 3440 } 3441 return 1; 3442 } 3443 3444 /* The MIPS16 version of validate_mips_insn. */ 3445 3446 static int 3447 validate_mips16_insn (const struct mips_opcode *opcode, 3448 struct mips_operand_array *operands) 3449 { 3450 if (opcode->args[0] == 'a' || opcode->args[0] == 'i') 3451 { 3452 /* In this case OPCODE defines the first 16 bits in a 32-bit jump 3453 instruction. Use TMP to describe the full instruction. */ 3454 struct mips_opcode tmp; 3455 3456 tmp = *opcode; 3457 tmp.match <<= 16; 3458 tmp.mask <<= 16; 3459 return validate_mips_insn (&tmp, 0xffffffff, 0, operands); 3460 } 3461 return validate_mips_insn (opcode, 0xffff, 0, operands); 3462 } 3463 3464 /* The microMIPS version of validate_mips_insn. */ 3465 3466 static int 3467 validate_micromips_insn (const struct mips_opcode *opc, 3468 struct mips_operand_array *operands) 3469 { 3470 unsigned long insn_bits; 3471 unsigned long major; 3472 unsigned int length; 3473 3474 if (opc->pinfo == INSN_MACRO) 3475 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, 3476 operands); 3477 3478 length = micromips_insn_length (opc); 3479 if (length != 2 && length != 4) 3480 { 3481 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " 3482 "%s %s"), length, opc->name, opc->args); 3483 return 0; 3484 } 3485 major = opc->match >> (10 + 8 * (length - 2)); 3486 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) 3487 || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) 3488 { 3489 as_bad (_("internal error: bad microMIPS opcode " 3490 "(opcode/length mismatch): %s %s"), opc->name, opc->args); 3491 return 0; 3492 } 3493 3494 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ 3495 insn_bits = 1 << 4 * length; 3496 insn_bits <<= 4 * length; 3497 insn_bits -= 1; 3498 return validate_mips_insn (opc, insn_bits, decode_micromips_operand, 3499 operands); 3500 } 3501 3502 /* This function is called once, at assembler startup time. It should set up 3503 all the tables, etc. that the MD part of the assembler will need. */ 3504 3505 void 3506 md_begin (void) 3507 { 3508 const char *retval = NULL; 3509 int i = 0; 3510 int broken = 0; 3511 3512 if (mips_pic != NO_PIC) 3513 { 3514 if (g_switch_seen && g_switch_value != 0) 3515 as_bad (_("-G may not be used in position-independent code")); 3516 g_switch_value = 0; 3517 } 3518 3519 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 3520 as_warn (_("could not set architecture and machine")); 3521 3522 op_hash = hash_new (); 3523 3524 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); 3525 for (i = 0; i < NUMOPCODES;) 3526 { 3527 const char *name = mips_opcodes[i].name; 3528 3529 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); 3530 if (retval != NULL) 3531 { 3532 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 3533 mips_opcodes[i].name, retval); 3534 /* Probably a memory allocation problem? Give up now. */ 3535 as_fatal (_("broken assembler, no assembly attempted")); 3536 } 3537 do 3538 { 3539 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, 3540 decode_mips_operand, &mips_operands[i])) 3541 broken = 1; 3542 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3543 { 3544 create_insn (&nop_insn, mips_opcodes + i); 3545 if (mips_fix_loongson2f_nop) 3546 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; 3547 nop_insn.fixed_p = 1; 3548 } 3549 ++i; 3550 } 3551 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); 3552 } 3553 3554 mips16_op_hash = hash_new (); 3555 mips16_operands = XCNEWVEC (struct mips_operand_array, 3556 bfd_mips16_num_opcodes); 3557 3558 i = 0; 3559 while (i < bfd_mips16_num_opcodes) 3560 { 3561 const char *name = mips16_opcodes[i].name; 3562 3563 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); 3564 if (retval != NULL) 3565 as_fatal (_("internal: can't hash `%s': %s"), 3566 mips16_opcodes[i].name, retval); 3567 do 3568 { 3569 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) 3570 broken = 1; 3571 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3572 { 3573 create_insn (&mips16_nop_insn, mips16_opcodes + i); 3574 mips16_nop_insn.fixed_p = 1; 3575 } 3576 ++i; 3577 } 3578 while (i < bfd_mips16_num_opcodes 3579 && strcmp (mips16_opcodes[i].name, name) == 0); 3580 } 3581 3582 micromips_op_hash = hash_new (); 3583 micromips_operands = XCNEWVEC (struct mips_operand_array, 3584 bfd_micromips_num_opcodes); 3585 3586 i = 0; 3587 while (i < bfd_micromips_num_opcodes) 3588 { 3589 const char *name = micromips_opcodes[i].name; 3590 3591 retval = hash_insert (micromips_op_hash, name, 3592 (void *) µmips_opcodes[i]); 3593 if (retval != NULL) 3594 as_fatal (_("internal: can't hash `%s': %s"), 3595 micromips_opcodes[i].name, retval); 3596 do 3597 { 3598 struct mips_cl_insn *micromips_nop_insn; 3599 3600 if (!validate_micromips_insn (µmips_opcodes[i], 3601 µmips_operands[i])) 3602 broken = 1; 3603 3604 if (micromips_opcodes[i].pinfo != INSN_MACRO) 3605 { 3606 if (micromips_insn_length (micromips_opcodes + i) == 2) 3607 micromips_nop_insn = µmips_nop16_insn; 3608 else if (micromips_insn_length (micromips_opcodes + i) == 4) 3609 micromips_nop_insn = µmips_nop32_insn; 3610 else 3611 continue; 3612 3613 if (micromips_nop_insn->insn_mo == NULL 3614 && strcmp (name, "nop") == 0) 3615 { 3616 create_insn (micromips_nop_insn, micromips_opcodes + i); 3617 micromips_nop_insn->fixed_p = 1; 3618 } 3619 } 3620 } 3621 while (++i < bfd_micromips_num_opcodes 3622 && strcmp (micromips_opcodes[i].name, name) == 0); 3623 } 3624 3625 if (broken) 3626 as_fatal (_("broken assembler, no assembly attempted")); 3627 3628 /* We add all the general register names to the symbol table. This 3629 helps us detect invalid uses of them. */ 3630 for (i = 0; reg_names[i].name; i++) 3631 symbol_table_insert (symbol_new (reg_names[i].name, reg_section, 3632 reg_names[i].num, /* & RNUM_MASK, */ 3633 &zero_address_frag)); 3634 if (HAVE_NEWABI) 3635 for (i = 0; reg_names_n32n64[i].name; i++) 3636 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, 3637 reg_names_n32n64[i].num, /* & RNUM_MASK, */ 3638 &zero_address_frag)); 3639 else 3640 for (i = 0; reg_names_o32[i].name; i++) 3641 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, 3642 reg_names_o32[i].num, /* & RNUM_MASK, */ 3643 &zero_address_frag)); 3644 3645 for (i = 0; i < 32; i++) 3646 { 3647 char regname[7]; 3648 3649 /* R5900 VU0 floating-point register. */ 3650 regname[sizeof (rename) - 1] = 0; 3651 snprintf (regname, sizeof (regname) - 1, "$vf%d", i); 3652 symbol_table_insert (symbol_new (regname, reg_section, 3653 RTYPE_VF | i, &zero_address_frag)); 3654 3655 /* R5900 VU0 integer register. */ 3656 snprintf (regname, sizeof (regname) - 1, "$vi%d", i); 3657 symbol_table_insert (symbol_new (regname, reg_section, 3658 RTYPE_VI | i, &zero_address_frag)); 3659 3660 /* MSA register. */ 3661 snprintf (regname, sizeof (regname) - 1, "$w%d", i); 3662 symbol_table_insert (symbol_new (regname, reg_section, 3663 RTYPE_MSA | i, &zero_address_frag)); 3664 } 3665 3666 obstack_init (&mips_operand_tokens); 3667 3668 mips_no_prev_insn (); 3669 3670 mips_gprmask = 0; 3671 mips_cprmask[0] = 0; 3672 mips_cprmask[1] = 0; 3673 mips_cprmask[2] = 0; 3674 mips_cprmask[3] = 0; 3675 3676 /* set the default alignment for the text section (2**2) */ 3677 record_alignment (text_section, 2); 3678 3679 bfd_set_gp_size (stdoutput, g_switch_value); 3680 3681 /* On a native system other than VxWorks, sections must be aligned 3682 to 16 byte boundaries. When configured for an embedded ELF 3683 target, we don't bother. */ 3684 if (strncmp (TARGET_OS, "elf", 3) != 0 3685 && strncmp (TARGET_OS, "vxworks", 7) != 0) 3686 { 3687 (void) bfd_set_section_alignment (stdoutput, text_section, 4); 3688 (void) bfd_set_section_alignment (stdoutput, data_section, 4); 3689 (void) bfd_set_section_alignment (stdoutput, bss_section, 4); 3690 } 3691 3692 /* Create a .reginfo section for register masks and a .mdebug 3693 section for debugging information. */ 3694 { 3695 segT seg; 3696 subsegT subseg; 3697 flagword flags; 3698 segT sec; 3699 3700 seg = now_seg; 3701 subseg = now_subseg; 3702 3703 /* The ABI says this section should be loaded so that the 3704 running program can access it. However, we don't load it 3705 if we are configured for an embedded target */ 3706 flags = SEC_READONLY | SEC_DATA; 3707 if (strncmp (TARGET_OS, "elf", 3) != 0) 3708 flags |= SEC_ALLOC | SEC_LOAD; 3709 3710 if (mips_abi != N64_ABI) 3711 { 3712 sec = subseg_new (".reginfo", (subsegT) 0); 3713 3714 bfd_set_section_flags (stdoutput, sec, flags); 3715 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); 3716 3717 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); 3718 } 3719 else 3720 { 3721 /* The 64-bit ABI uses a .MIPS.options section rather than 3722 .reginfo section. */ 3723 sec = subseg_new (".MIPS.options", (subsegT) 0); 3724 bfd_set_section_flags (stdoutput, sec, flags); 3725 bfd_set_section_alignment (stdoutput, sec, 3); 3726 3727 /* Set up the option header. */ 3728 { 3729 Elf_Internal_Options opthdr; 3730 char *f; 3731 3732 opthdr.kind = ODK_REGINFO; 3733 opthdr.size = (sizeof (Elf_External_Options) 3734 + sizeof (Elf64_External_RegInfo)); 3735 opthdr.section = 0; 3736 opthdr.info = 0; 3737 f = frag_more (sizeof (Elf_External_Options)); 3738 bfd_mips_elf_swap_options_out (stdoutput, &opthdr, 3739 (Elf_External_Options *) f); 3740 3741 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); 3742 } 3743 } 3744 3745 sec = subseg_new (".MIPS.abiflags", (subsegT) 0); 3746 bfd_set_section_flags (stdoutput, sec, 3747 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); 3748 bfd_set_section_alignment (stdoutput, sec, 3); 3749 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); 3750 3751 if (ECOFF_DEBUGGING) 3752 { 3753 sec = subseg_new (".mdebug", (subsegT) 0); 3754 (void) bfd_set_section_flags (stdoutput, sec, 3755 SEC_HAS_CONTENTS | SEC_READONLY); 3756 (void) bfd_set_section_alignment (stdoutput, sec, 2); 3757 } 3758 else if (mips_flag_pdr) 3759 { 3760 pdr_seg = subseg_new (".pdr", (subsegT) 0); 3761 (void) bfd_set_section_flags (stdoutput, pdr_seg, 3762 SEC_READONLY | SEC_RELOC 3763 | SEC_DEBUGGING); 3764 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); 3765 } 3766 3767 subseg_set (seg, subseg); 3768 } 3769 3770 if (mips_fix_vr4120) 3771 init_vr4120_conflicts (); 3772 } 3773 3774 static inline void 3775 fpabi_incompatible_with (int fpabi, const char *what) 3776 { 3777 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), 3778 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3779 } 3780 3781 static inline void 3782 fpabi_requires (int fpabi, const char *what) 3783 { 3784 as_warn (_(".gnu_attribute %d,%d requires `%s'"), 3785 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3786 } 3787 3788 /* Check -mabi and register sizes against the specified FP ABI. */ 3789 static void 3790 check_fpabi (int fpabi) 3791 { 3792 switch (fpabi) 3793 { 3794 case Val_GNU_MIPS_ABI_FP_DOUBLE: 3795 if (file_mips_opts.soft_float) 3796 fpabi_incompatible_with (fpabi, "softfloat"); 3797 else if (file_mips_opts.single_float) 3798 fpabi_incompatible_with (fpabi, "singlefloat"); 3799 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) 3800 fpabi_incompatible_with (fpabi, "gp=64 fp=32"); 3801 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) 3802 fpabi_incompatible_with (fpabi, "gp=32 fp=64"); 3803 break; 3804 3805 case Val_GNU_MIPS_ABI_FP_XX: 3806 if (mips_abi != O32_ABI) 3807 fpabi_requires (fpabi, "-mabi=32"); 3808 else if (file_mips_opts.soft_float) 3809 fpabi_incompatible_with (fpabi, "softfloat"); 3810 else if (file_mips_opts.single_float) 3811 fpabi_incompatible_with (fpabi, "singlefloat"); 3812 else if (file_mips_opts.fp != 0) 3813 fpabi_requires (fpabi, "fp=xx"); 3814 break; 3815 3816 case Val_GNU_MIPS_ABI_FP_64A: 3817 case Val_GNU_MIPS_ABI_FP_64: 3818 if (mips_abi != O32_ABI) 3819 fpabi_requires (fpabi, "-mabi=32"); 3820 else if (file_mips_opts.soft_float) 3821 fpabi_incompatible_with (fpabi, "softfloat"); 3822 else if (file_mips_opts.single_float) 3823 fpabi_incompatible_with (fpabi, "singlefloat"); 3824 else if (file_mips_opts.fp != 64) 3825 fpabi_requires (fpabi, "fp=64"); 3826 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) 3827 fpabi_incompatible_with (fpabi, "nooddspreg"); 3828 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) 3829 fpabi_requires (fpabi, "nooddspreg"); 3830 break; 3831 3832 case Val_GNU_MIPS_ABI_FP_SINGLE: 3833 if (file_mips_opts.soft_float) 3834 fpabi_incompatible_with (fpabi, "softfloat"); 3835 else if (!file_mips_opts.single_float) 3836 fpabi_requires (fpabi, "singlefloat"); 3837 break; 3838 3839 case Val_GNU_MIPS_ABI_FP_SOFT: 3840 if (!file_mips_opts.soft_float) 3841 fpabi_requires (fpabi, "softfloat"); 3842 break; 3843 3844 case Val_GNU_MIPS_ABI_FP_OLD_64: 3845 as_warn (_(".gnu_attribute %d,%d is no longer supported"), 3846 Tag_GNU_MIPS_ABI_FP, fpabi); 3847 break; 3848 3849 default: 3850 as_warn (_(".gnu_attribute %d,%d is not a recognized" 3851 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); 3852 break; 3853 } 3854 } 3855 3856 /* Perform consistency checks on the current options. */ 3857 3858 static void 3859 mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) 3860 { 3861 /* Check the size of integer registers agrees with the ABI and ISA. */ 3862 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) 3863 as_bad (_("`gp=64' used with a 32-bit processor")); 3864 else if (abi_checks 3865 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) 3866 as_bad (_("`gp=32' used with a 64-bit ABI")); 3867 else if (abi_checks 3868 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) 3869 as_bad (_("`gp=64' used with a 32-bit ABI")); 3870 3871 /* Check the size of the float registers agrees with the ABI and ISA. */ 3872 switch (opts->fp) 3873 { 3874 case 0: 3875 if (!CPU_HAS_LDC1_SDC1 (opts->arch)) 3876 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); 3877 else if (opts->single_float == 1) 3878 as_bad (_("`fp=xx' cannot be used with `singlefloat'")); 3879 break; 3880 case 64: 3881 if (!ISA_HAS_64BIT_FPRS (opts->isa)) 3882 as_bad (_("`fp=64' used with a 32-bit fpu")); 3883 else if (abi_checks 3884 && ABI_NEEDS_32BIT_REGS (mips_abi) 3885 && !ISA_HAS_MXHC1 (opts->isa)) 3886 as_warn (_("`fp=64' used with a 32-bit ABI")); 3887 break; 3888 case 32: 3889 if (abi_checks 3890 && ABI_NEEDS_64BIT_REGS (mips_abi)) 3891 as_warn (_("`fp=32' used with a 64-bit ABI")); 3892 if (ISA_IS_R6 (mips_opts.isa) && opts->single_float == 0) 3893 as_bad (_("`fp=32' used with a MIPS R6 cpu")); 3894 break; 3895 default: 3896 as_bad (_("Unknown size of floating point registers")); 3897 break; 3898 } 3899 3900 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) 3901 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); 3902 3903 if (opts->micromips == 1 && opts->mips16 == 1) 3904 as_bad (_("`mips16' cannot be used with `micromips'")); 3905 else if (ISA_IS_R6 (mips_opts.isa) 3906 && (opts->micromips == 1 3907 || opts->mips16 == 1)) 3908 as_fatal (_("`%s' can not be used with `%s'"), 3909 opts->micromips ? "micromips" : "mips16", 3910 mips_cpu_info_from_isa (mips_opts.isa)->name); 3911 3912 if (ISA_IS_R6 (opts->isa) && mips_relax_branch) 3913 as_fatal (_("branch relaxation is not supported in `%s'"), 3914 mips_cpu_info_from_isa (opts->isa)->name); 3915 } 3916 3917 /* Perform consistency checks on the module level options exactly once. 3918 This is a deferred check that happens: 3919 at the first .set directive 3920 or, at the first pseudo op that generates code (inc .dc.a) 3921 or, at the first instruction 3922 or, at the end. */ 3923 3924 static void 3925 file_mips_check_options (void) 3926 { 3927 const struct mips_cpu_info *arch_info = 0; 3928 3929 if (file_mips_opts_checked) 3930 return; 3931 3932 /* The following code determines the register size. 3933 Similar code was added to GCC 3.3 (see override_options() in 3934 config/mips/mips.c). The GAS and GCC code should be kept in sync 3935 as much as possible. */ 3936 3937 if (file_mips_opts.gp < 0) 3938 { 3939 /* Infer the integer register size from the ABI and processor. 3940 Restrict ourselves to 32-bit registers if that's all the 3941 processor has, or if the ABI cannot handle 64-bit registers. */ 3942 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) 3943 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) 3944 ? 32 : 64; 3945 } 3946 3947 if (file_mips_opts.fp < 0) 3948 { 3949 /* No user specified float register size. 3950 ??? GAS treats single-float processors as though they had 64-bit 3951 float registers (although it complains when double-precision 3952 instructions are used). As things stand, saying they have 32-bit 3953 registers would lead to spurious "register must be even" messages. 3954 So here we assume float registers are never smaller than the 3955 integer ones. */ 3956 if (file_mips_opts.gp == 64) 3957 /* 64-bit integer registers implies 64-bit float registers. */ 3958 file_mips_opts.fp = 64; 3959 else if ((file_mips_opts.ase & FP64_ASES) 3960 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) 3961 /* Handle ASEs that require 64-bit float registers, if possible. */ 3962 file_mips_opts.fp = 64; 3963 else if (ISA_IS_R6 (mips_opts.isa)) 3964 /* R6 implies 64-bit float registers. */ 3965 file_mips_opts.fp = 64; 3966 else 3967 /* 32-bit float registers. */ 3968 file_mips_opts.fp = 32; 3969 } 3970 3971 arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); 3972 3973 /* Disable operations on odd-numbered floating-point registers by default 3974 when using the FPXX ABI. */ 3975 if (file_mips_opts.oddspreg < 0) 3976 { 3977 if (file_mips_opts.fp == 0) 3978 file_mips_opts.oddspreg = 0; 3979 else 3980 file_mips_opts.oddspreg = 1; 3981 } 3982 3983 /* End of GCC-shared inference code. */ 3984 3985 /* This flag is set when we have a 64-bit capable CPU but use only 3986 32-bit wide registers. Note that EABI does not use it. */ 3987 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) 3988 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) 3989 || mips_abi == O32_ABI)) 3990 mips_32bitmode = 1; 3991 3992 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) 3993 as_bad (_("trap exception not supported at ISA 1")); 3994 3995 /* If the selected architecture includes support for ASEs, enable 3996 generation of code for them. */ 3997 if (file_mips_opts.mips16 == -1) 3998 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; 3999 if (file_mips_opts.micromips == -1) 4000 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) 4001 ? 1 : 0; 4002 4003 if (mips_nan2008 == -1) 4004 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; 4005 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) 4006 as_fatal (_("`%s' does not support legacy NaN"), 4007 mips_cpu_info_from_arch (file_mips_opts.arch)->name); 4008 4009 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from 4010 being selected implicitly. */ 4011 if (file_mips_opts.fp != 64) 4012 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; 4013 4014 /* If the user didn't explicitly select or deselect a particular ASE, 4015 use the default setting for the CPU. */ 4016 file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); 4017 4018 /* Set up the current options. These may change throughout assembly. */ 4019 mips_opts = file_mips_opts; 4020 4021 mips_check_isa_supports_ases (); 4022 mips_check_options (&file_mips_opts, TRUE); 4023 file_mips_opts_checked = TRUE; 4024 4025 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 4026 as_warn (_("could not set architecture and machine")); 4027 } 4028 4029 void 4030 md_assemble (char *str) 4031 { 4032 struct mips_cl_insn insn; 4033 bfd_reloc_code_real_type unused_reloc[3] 4034 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 4035 4036 file_mips_check_options (); 4037 4038 imm_expr.X_op = O_absent; 4039 offset_expr.X_op = O_absent; 4040 offset_reloc[0] = BFD_RELOC_UNUSED; 4041 offset_reloc[1] = BFD_RELOC_UNUSED; 4042 offset_reloc[2] = BFD_RELOC_UNUSED; 4043 4044 mips_mark_labels (); 4045 mips_assembling_insn = TRUE; 4046 clear_insn_error (); 4047 4048 if (mips_opts.mips16) 4049 mips16_ip (str, &insn); 4050 else 4051 { 4052 mips_ip (str, &insn); 4053 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), 4054 str, insn.insn_opcode)); 4055 } 4056 4057 if (insn_error.msg) 4058 report_insn_error (str); 4059 else if (insn.insn_mo->pinfo == INSN_MACRO) 4060 { 4061 macro_start (); 4062 if (mips_opts.mips16) 4063 mips16_macro (&insn); 4064 else 4065 macro (&insn, str); 4066 macro_end (); 4067 } 4068 else 4069 { 4070 if (offset_expr.X_op != O_absent) 4071 append_insn (&insn, &offset_expr, offset_reloc, FALSE); 4072 else 4073 append_insn (&insn, NULL, unused_reloc, FALSE); 4074 } 4075 4076 mips_assembling_insn = FALSE; 4077 } 4078 4079 /* Convenience functions for abstracting away the differences between 4080 MIPS16 and non-MIPS16 relocations. */ 4081 4082 static inline bfd_boolean 4083 mips16_reloc_p (bfd_reloc_code_real_type reloc) 4084 { 4085 switch (reloc) 4086 { 4087 case BFD_RELOC_MIPS16_JMP: 4088 case BFD_RELOC_MIPS16_GPREL: 4089 case BFD_RELOC_MIPS16_GOT16: 4090 case BFD_RELOC_MIPS16_CALL16: 4091 case BFD_RELOC_MIPS16_HI16_S: 4092 case BFD_RELOC_MIPS16_HI16: 4093 case BFD_RELOC_MIPS16_LO16: 4094 return TRUE; 4095 4096 default: 4097 return FALSE; 4098 } 4099 } 4100 4101 static inline bfd_boolean 4102 micromips_reloc_p (bfd_reloc_code_real_type reloc) 4103 { 4104 switch (reloc) 4105 { 4106 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4107 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4108 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4109 case BFD_RELOC_MICROMIPS_GPREL16: 4110 case BFD_RELOC_MICROMIPS_JMP: 4111 case BFD_RELOC_MICROMIPS_HI16: 4112 case BFD_RELOC_MICROMIPS_HI16_S: 4113 case BFD_RELOC_MICROMIPS_LO16: 4114 case BFD_RELOC_MICROMIPS_LITERAL: 4115 case BFD_RELOC_MICROMIPS_GOT16: 4116 case BFD_RELOC_MICROMIPS_CALL16: 4117 case BFD_RELOC_MICROMIPS_GOT_HI16: 4118 case BFD_RELOC_MICROMIPS_GOT_LO16: 4119 case BFD_RELOC_MICROMIPS_CALL_HI16: 4120 case BFD_RELOC_MICROMIPS_CALL_LO16: 4121 case BFD_RELOC_MICROMIPS_SUB: 4122 case BFD_RELOC_MICROMIPS_GOT_PAGE: 4123 case BFD_RELOC_MICROMIPS_GOT_OFST: 4124 case BFD_RELOC_MICROMIPS_GOT_DISP: 4125 case BFD_RELOC_MICROMIPS_HIGHEST: 4126 case BFD_RELOC_MICROMIPS_HIGHER: 4127 case BFD_RELOC_MICROMIPS_SCN_DISP: 4128 case BFD_RELOC_MICROMIPS_JALR: 4129 return TRUE; 4130 4131 default: 4132 return FALSE; 4133 } 4134 } 4135 4136 static inline bfd_boolean 4137 jmp_reloc_p (bfd_reloc_code_real_type reloc) 4138 { 4139 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; 4140 } 4141 4142 static inline bfd_boolean 4143 got16_reloc_p (bfd_reloc_code_real_type reloc) 4144 { 4145 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 4146 || reloc == BFD_RELOC_MICROMIPS_GOT16); 4147 } 4148 4149 static inline bfd_boolean 4150 hi16_reloc_p (bfd_reloc_code_real_type reloc) 4151 { 4152 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S 4153 || reloc == BFD_RELOC_MICROMIPS_HI16_S); 4154 } 4155 4156 static inline bfd_boolean 4157 lo16_reloc_p (bfd_reloc_code_real_type reloc) 4158 { 4159 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 4160 || reloc == BFD_RELOC_MICROMIPS_LO16); 4161 } 4162 4163 static inline bfd_boolean 4164 jalr_reloc_p (bfd_reloc_code_real_type reloc) 4165 { 4166 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; 4167 } 4168 4169 static inline bfd_boolean 4170 gprel16_reloc_p (bfd_reloc_code_real_type reloc) 4171 { 4172 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL 4173 || reloc == BFD_RELOC_MICROMIPS_GPREL16); 4174 } 4175 4176 /* Return true if RELOC is a PC-relative relocation that does not have 4177 full address range. */ 4178 4179 static inline bfd_boolean 4180 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) 4181 { 4182 switch (reloc) 4183 { 4184 case BFD_RELOC_16_PCREL_S2: 4185 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4186 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4187 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4188 case BFD_RELOC_MIPS_21_PCREL_S2: 4189 case BFD_RELOC_MIPS_26_PCREL_S2: 4190 case BFD_RELOC_MIPS_18_PCREL_S3: 4191 case BFD_RELOC_MIPS_19_PCREL_S2: 4192 return TRUE; 4193 4194 case BFD_RELOC_32_PCREL: 4195 case BFD_RELOC_HI16_S_PCREL: 4196 case BFD_RELOC_LO16_PCREL: 4197 return HAVE_64BIT_ADDRESSES; 4198 4199 default: 4200 return FALSE; 4201 } 4202 } 4203 4204 /* Return true if the given relocation might need a matching %lo(). 4205 This is only "might" because SVR4 R_MIPS_GOT16 relocations only 4206 need a matching %lo() when applied to local symbols. */ 4207 4208 static inline bfd_boolean 4209 reloc_needs_lo_p (bfd_reloc_code_real_type reloc) 4210 { 4211 return (HAVE_IN_PLACE_ADDENDS 4212 && (hi16_reloc_p (reloc) 4213 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); 4214 all GOT16 relocations evaluate to "G". */ 4215 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); 4216 } 4217 4218 /* Return the type of %lo() reloc needed by RELOC, given that 4219 reloc_needs_lo_p. */ 4220 4221 static inline bfd_reloc_code_real_type 4222 matching_lo_reloc (bfd_reloc_code_real_type reloc) 4223 { 4224 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 4225 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 4226 : BFD_RELOC_LO16)); 4227 } 4228 4229 /* Return true if the given fixup is followed by a matching R_MIPS_LO16 4230 relocation. */ 4231 4232 static inline bfd_boolean 4233 fixup_has_matching_lo_p (fixS *fixp) 4234 { 4235 return (fixp->fx_next != NULL 4236 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) 4237 && fixp->fx_addsy == fixp->fx_next->fx_addsy 4238 && fixp->fx_offset == fixp->fx_next->fx_offset); 4239 } 4240 4241 /* Move all labels in LABELS to the current insertion point. TEXT_P 4242 says whether the labels refer to text or data. */ 4243 4244 static void 4245 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) 4246 { 4247 struct insn_label_list *l; 4248 valueT val; 4249 4250 for (l = labels; l != NULL; l = l->next) 4251 { 4252 gas_assert (S_GET_SEGMENT (l->label) == now_seg); 4253 symbol_set_frag (l->label, frag_now); 4254 val = (valueT) frag_now_fix (); 4255 /* MIPS16/microMIPS text labels are stored as odd. */ 4256 if (text_p && HAVE_CODE_COMPRESSION) 4257 ++val; 4258 S_SET_VALUE (l->label, val); 4259 } 4260 } 4261 4262 /* Move all labels in insn_labels to the current insertion point 4263 and treat them as text labels. */ 4264 4265 static void 4266 mips_move_text_labels (void) 4267 { 4268 mips_move_labels (seg_info (now_seg)->label_list, TRUE); 4269 } 4270 4271 static bfd_boolean 4272 s_is_linkonce (symbolS *sym, segT from_seg) 4273 { 4274 bfd_boolean linkonce = FALSE; 4275 segT symseg = S_GET_SEGMENT (sym); 4276 4277 if (symseg != from_seg && !S_IS_LOCAL (sym)) 4278 { 4279 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) 4280 linkonce = TRUE; 4281 /* The GNU toolchain uses an extension for ELF: a section 4282 beginning with the magic string .gnu.linkonce is a 4283 linkonce section. */ 4284 if (strncmp (segment_name (symseg), ".gnu.linkonce", 4285 sizeof ".gnu.linkonce" - 1) == 0) 4286 linkonce = TRUE; 4287 } 4288 return linkonce; 4289 } 4290 4291 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the 4292 linker to handle them specially, such as generating jalx instructions 4293 when needed. We also make them odd for the duration of the assembly, 4294 in order to generate the right sort of code. We will make them even 4295 in the adjust_symtab routine, while leaving them marked. This is 4296 convenient for the debugger and the disassembler. The linker knows 4297 to make them odd again. */ 4298 4299 static void 4300 mips_compressed_mark_label (symbolS *label) 4301 { 4302 gas_assert (HAVE_CODE_COMPRESSION); 4303 4304 if (mips_opts.mips16) 4305 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); 4306 else 4307 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); 4308 if ((S_GET_VALUE (label) & 1) == 0 4309 /* Don't adjust the address if the label is global or weak, or 4310 in a link-once section, since we'll be emitting symbol reloc 4311 references to it which will be patched up by the linker, and 4312 the final value of the symbol may or may not be MIPS16/microMIPS. */ 4313 && !S_IS_WEAK (label) 4314 && !S_IS_EXTERNAL (label) 4315 && !s_is_linkonce (label, now_seg)) 4316 S_SET_VALUE (label, S_GET_VALUE (label) | 1); 4317 } 4318 4319 /* Mark preceding MIPS16 or microMIPS instruction labels. */ 4320 4321 static void 4322 mips_compressed_mark_labels (void) 4323 { 4324 struct insn_label_list *l; 4325 4326 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) 4327 mips_compressed_mark_label (l->label); 4328 } 4329 4330 /* End the current frag. Make it a variant frag and record the 4331 relaxation info. */ 4332 4333 static void 4334 relax_close_frag (void) 4335 { 4336 mips_macro_warning.first_frag = frag_now; 4337 frag_var (rs_machine_dependent, 0, 0, 4338 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), 4339 mips_relax.symbol, 0, (char *) mips_relax.first_fixup); 4340 4341 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); 4342 mips_relax.first_fixup = 0; 4343 } 4344 4345 /* Start a new relaxation sequence whose expansion depends on SYMBOL. 4346 See the comment above RELAX_ENCODE for more details. */ 4347 4348 static void 4349 relax_start (symbolS *symbol) 4350 { 4351 gas_assert (mips_relax.sequence == 0); 4352 mips_relax.sequence = 1; 4353 mips_relax.symbol = symbol; 4354 } 4355 4356 /* Start generating the second version of a relaxable sequence. 4357 See the comment above RELAX_ENCODE for more details. */ 4358 4359 static void 4360 relax_switch (void) 4361 { 4362 gas_assert (mips_relax.sequence == 1); 4363 mips_relax.sequence = 2; 4364 } 4365 4366 /* End the current relaxable sequence. */ 4367 4368 static void 4369 relax_end (void) 4370 { 4371 gas_assert (mips_relax.sequence == 2); 4372 relax_close_frag (); 4373 mips_relax.sequence = 0; 4374 } 4375 4376 /* Return true if IP is a delayed branch or jump. */ 4377 4378 static inline bfd_boolean 4379 delayed_branch_p (const struct mips_cl_insn *ip) 4380 { 4381 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY 4382 | INSN_COND_BRANCH_DELAY 4383 | INSN_COND_BRANCH_LIKELY)) != 0; 4384 } 4385 4386 /* Return true if IP is a compact branch or jump. */ 4387 4388 static inline bfd_boolean 4389 compact_branch_p (const struct mips_cl_insn *ip) 4390 { 4391 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH 4392 | INSN2_COND_BRANCH)) != 0; 4393 } 4394 4395 /* Return true if IP is an unconditional branch or jump. */ 4396 4397 static inline bfd_boolean 4398 uncond_branch_p (const struct mips_cl_insn *ip) 4399 { 4400 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 4401 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); 4402 } 4403 4404 /* Return true if IP is a branch-likely instruction. */ 4405 4406 static inline bfd_boolean 4407 branch_likely_p (const struct mips_cl_insn *ip) 4408 { 4409 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; 4410 } 4411 4412 /* Return the type of nop that should be used to fill the delay slot 4413 of delayed branch IP. */ 4414 4415 static struct mips_cl_insn * 4416 get_delay_slot_nop (const struct mips_cl_insn *ip) 4417 { 4418 if (mips_opts.micromips 4419 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 4420 return µmips_nop32_insn; 4421 return NOP_INSN; 4422 } 4423 4424 /* Return a mask that has bit N set if OPCODE reads the register(s) 4425 in operand N. */ 4426 4427 static unsigned int 4428 insn_read_mask (const struct mips_opcode *opcode) 4429 { 4430 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; 4431 } 4432 4433 /* Return a mask that has bit N set if OPCODE writes to the register(s) 4434 in operand N. */ 4435 4436 static unsigned int 4437 insn_write_mask (const struct mips_opcode *opcode) 4438 { 4439 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; 4440 } 4441 4442 /* Return a mask of the registers specified by operand OPERAND of INSN. 4443 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4444 is set. */ 4445 4446 static unsigned int 4447 operand_reg_mask (const struct mips_cl_insn *insn, 4448 const struct mips_operand *operand, 4449 unsigned int type_mask) 4450 { 4451 unsigned int uval, vsel; 4452 4453 switch (operand->type) 4454 { 4455 case OP_INT: 4456 case OP_MAPPED_INT: 4457 case OP_MSB: 4458 case OP_PCREL: 4459 case OP_PERF_REG: 4460 case OP_ADDIUSP_INT: 4461 case OP_ENTRY_EXIT_LIST: 4462 case OP_REPEAT_DEST_REG: 4463 case OP_REPEAT_PREV_REG: 4464 case OP_PC: 4465 case OP_VU0_SUFFIX: 4466 case OP_VU0_MATCH_SUFFIX: 4467 case OP_IMM_INDEX: 4468 case OP_MAPPED_STRING: 4469 case OP_MXU_STRIDE: 4470 abort (); 4471 4472 case OP_REG: 4473 case OP_OPTIONAL_REG: 4474 { 4475 const struct mips_reg_operand *reg_op; 4476 4477 reg_op = (const struct mips_reg_operand *) operand; 4478 if (!(type_mask & (1 << reg_op->reg_type))) 4479 return 0; 4480 uval = insn_extract_operand (insn, operand); 4481 return 1 << mips_decode_reg_operand (reg_op, uval); 4482 } 4483 4484 case OP_REG_PAIR: 4485 { 4486 const struct mips_reg_pair_operand *pair_op; 4487 4488 pair_op = (const struct mips_reg_pair_operand *) operand; 4489 if (!(type_mask & (1 << pair_op->reg_type))) 4490 return 0; 4491 uval = insn_extract_operand (insn, operand); 4492 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); 4493 } 4494 4495 case OP_CLO_CLZ_DEST: 4496 if (!(type_mask & (1 << OP_REG_GP))) 4497 return 0; 4498 uval = insn_extract_operand (insn, operand); 4499 return (1 << (uval & 31)) | (1 << (uval >> 5)); 4500 4501 case OP_SAME_RS_RT: 4502 if (!(type_mask & (1 << OP_REG_GP))) 4503 return 0; 4504 uval = insn_extract_operand (insn, operand); 4505 gas_assert ((uval & 31) == (uval >> 5)); 4506 return 1 << (uval & 31); 4507 4508 case OP_CHECK_PREV: 4509 case OP_NON_ZERO_REG: 4510 if (!(type_mask & (1 << OP_REG_GP))) 4511 return 0; 4512 uval = insn_extract_operand (insn, operand); 4513 return 1 << (uval & 31); 4514 4515 case OP_LWM_SWM_LIST: 4516 abort (); 4517 4518 case OP_SAVE_RESTORE_LIST: 4519 abort (); 4520 4521 case OP_MDMX_IMM_REG: 4522 if (!(type_mask & (1 << OP_REG_VEC))) 4523 return 0; 4524 uval = insn_extract_operand (insn, operand); 4525 vsel = uval >> 5; 4526 if ((vsel & 0x18) == 0x18) 4527 return 0; 4528 return 1 << (uval & 31); 4529 4530 case OP_REG_INDEX: 4531 if (!(type_mask & (1 << OP_REG_GP))) 4532 return 0; 4533 return 1 << insn_extract_operand (insn, operand); 4534 } 4535 abort (); 4536 } 4537 4538 /* Return a mask of the registers specified by operands OPNO_MASK of INSN, 4539 where bit N of OPNO_MASK is set if operand N should be included. 4540 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4541 is set. */ 4542 4543 static unsigned int 4544 insn_reg_mask (const struct mips_cl_insn *insn, 4545 unsigned int type_mask, unsigned int opno_mask) 4546 { 4547 unsigned int opno, reg_mask; 4548 4549 opno = 0; 4550 reg_mask = 0; 4551 while (opno_mask != 0) 4552 { 4553 if (opno_mask & 1) 4554 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); 4555 opno_mask >>= 1; 4556 opno += 1; 4557 } 4558 return reg_mask; 4559 } 4560 4561 /* Return the mask of core registers that IP reads. */ 4562 4563 static unsigned int 4564 gpr_read_mask (const struct mips_cl_insn *ip) 4565 { 4566 unsigned long pinfo, pinfo2; 4567 unsigned int mask; 4568 4569 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); 4570 pinfo = ip->insn_mo->pinfo; 4571 pinfo2 = ip->insn_mo->pinfo2; 4572 if (pinfo & INSN_UDI) 4573 { 4574 /* UDI instructions have traditionally been assumed to read RS 4575 and RT. */ 4576 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); 4577 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); 4578 } 4579 if (pinfo & INSN_READ_GPR_24) 4580 mask |= 1 << 24; 4581 if (pinfo2 & INSN2_READ_GPR_16) 4582 mask |= 1 << 16; 4583 if (pinfo2 & INSN2_READ_SP) 4584 mask |= 1 << SP; 4585 if (pinfo2 & INSN2_READ_GPR_31) 4586 mask |= 1 << 31; 4587 /* Don't include register 0. */ 4588 return mask & ~1; 4589 } 4590 4591 /* Return the mask of core registers that IP writes. */ 4592 4593 static unsigned int 4594 gpr_write_mask (const struct mips_cl_insn *ip) 4595 { 4596 unsigned long pinfo, pinfo2; 4597 unsigned int mask; 4598 4599 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); 4600 pinfo = ip->insn_mo->pinfo; 4601 pinfo2 = ip->insn_mo->pinfo2; 4602 if (pinfo & INSN_WRITE_GPR_24) 4603 mask |= 1 << 24; 4604 if (pinfo & INSN_WRITE_GPR_31) 4605 mask |= 1 << 31; 4606 if (pinfo & INSN_UDI) 4607 /* UDI instructions have traditionally been assumed to write to RD. */ 4608 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); 4609 if (pinfo2 & INSN2_WRITE_SP) 4610 mask |= 1 << SP; 4611 /* Don't include register 0. */ 4612 return mask & ~1; 4613 } 4614 4615 /* Return the mask of floating-point registers that IP reads. */ 4616 4617 static unsigned int 4618 fpr_read_mask (const struct mips_cl_insn *ip) 4619 { 4620 unsigned long pinfo; 4621 unsigned int mask; 4622 4623 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4624 | (1 << OP_REG_MSA)), 4625 insn_read_mask (ip->insn_mo)); 4626 pinfo = ip->insn_mo->pinfo; 4627 /* Conservatively treat all operands to an FP_D instruction are doubles. 4628 (This is overly pessimistic for things like cvt.d.s.) */ 4629 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4630 mask |= mask << 1; 4631 return mask; 4632 } 4633 4634 /* Return the mask of floating-point registers that IP writes. */ 4635 4636 static unsigned int 4637 fpr_write_mask (const struct mips_cl_insn *ip) 4638 { 4639 unsigned long pinfo; 4640 unsigned int mask; 4641 4642 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4643 | (1 << OP_REG_MSA)), 4644 insn_write_mask (ip->insn_mo)); 4645 pinfo = ip->insn_mo->pinfo; 4646 /* Conservatively treat all operands to an FP_D instruction are doubles. 4647 (This is overly pessimistic for things like cvt.s.d.) */ 4648 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4649 mask |= mask << 1; 4650 return mask; 4651 } 4652 4653 /* Operand OPNUM of INSN is an odd-numbered floating-point register. 4654 Check whether that is allowed. */ 4655 4656 static bfd_boolean 4657 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) 4658 { 4659 const char *s = insn->name; 4660 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) 4661 || FPR_SIZE == 64) 4662 && mips_opts.oddspreg; 4663 4664 if (insn->pinfo == INSN_MACRO) 4665 /* Let a macro pass, we'll catch it later when it is expanded. */ 4666 return TRUE; 4667 4668 /* Single-precision coprocessor loads and moves are OK for 32-bit registers, 4669 otherwise it depends on oddspreg. */ 4670 if ((insn->pinfo & FP_S) 4671 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY 4672 | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) 4673 return FPR_SIZE == 32 || oddspreg; 4674 4675 /* Allow odd registers for single-precision ops and double-precision if the 4676 floating-point registers are 64-bit wide. */ 4677 switch (insn->pinfo & (FP_S | FP_D)) 4678 { 4679 case FP_S: 4680 case 0: 4681 return oddspreg; 4682 case FP_D: 4683 return FPR_SIZE == 64; 4684 default: 4685 break; 4686 } 4687 4688 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ 4689 s = strchr (insn->name, '.'); 4690 if (s != NULL && opnum == 2) 4691 s = strchr (s + 1, '.'); 4692 if (s != NULL && (s[1] == 'w' || s[1] == 's')) 4693 return oddspreg; 4694 4695 return FPR_SIZE == 64; 4696 } 4697 4698 /* Information about an instruction argument that we're trying to match. */ 4699 struct mips_arg_info 4700 { 4701 /* The instruction so far. */ 4702 struct mips_cl_insn *insn; 4703 4704 /* The first unconsumed operand token. */ 4705 struct mips_operand_token *token; 4706 4707 /* The 1-based operand number, in terms of insn->insn_mo->args. */ 4708 int opnum; 4709 4710 /* The 1-based argument number, for error reporting. This does not 4711 count elided optional registers, etc.. */ 4712 int argnum; 4713 4714 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ 4715 unsigned int last_regno; 4716 4717 /* If the first operand was an OP_REG, this is the register that it 4718 specified, otherwise it is ILLEGAL_REG. */ 4719 unsigned int dest_regno; 4720 4721 /* The value of the last OP_INT operand. Only used for OP_MSB, 4722 where it gives the lsb position. */ 4723 unsigned int last_op_int; 4724 4725 /* If true, match routines should assume that no later instruction 4726 alternative matches and should therefore be as accomodating as 4727 possible. Match routines should not report errors if something 4728 is only invalid for !LAX_MATCH. */ 4729 bfd_boolean lax_match; 4730 4731 /* True if a reference to the current AT register was seen. */ 4732 bfd_boolean seen_at; 4733 }; 4734 4735 /* Record that the argument is out of range. */ 4736 4737 static void 4738 match_out_of_range (struct mips_arg_info *arg) 4739 { 4740 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); 4741 } 4742 4743 /* Record that the argument isn't constant but needs to be. */ 4744 4745 static void 4746 match_not_constant (struct mips_arg_info *arg) 4747 { 4748 set_insn_error_i (arg->argnum, _("operand %d must be constant"), 4749 arg->argnum); 4750 } 4751 4752 /* Try to match an OT_CHAR token for character CH. Consume the token 4753 and return true on success, otherwise return false. */ 4754 4755 static bfd_boolean 4756 match_char (struct mips_arg_info *arg, char ch) 4757 { 4758 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) 4759 { 4760 ++arg->token; 4761 if (ch == ',') 4762 arg->argnum += 1; 4763 return TRUE; 4764 } 4765 return FALSE; 4766 } 4767 4768 /* Try to get an expression from the next tokens in ARG. Consume the 4769 tokens and return true on success, storing the expression value in 4770 VALUE and relocation types in R. */ 4771 4772 static bfd_boolean 4773 match_expression (struct mips_arg_info *arg, expressionS *value, 4774 bfd_reloc_code_real_type *r) 4775 { 4776 /* If the next token is a '(' that was parsed as being part of a base 4777 expression, assume we have an elided offset. The later match will fail 4778 if this turns out to be wrong. */ 4779 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') 4780 { 4781 value->X_op = O_constant; 4782 value->X_add_number = 0; 4783 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; 4784 return TRUE; 4785 } 4786 4787 /* Reject register-based expressions such as "0+$2" and "(($2))". 4788 For plain registers the default error seems more appropriate. */ 4789 if (arg->token->type == OT_INTEGER 4790 && arg->token->u.integer.value.X_op == O_register) 4791 { 4792 set_insn_error (arg->argnum, _("register value used as expression")); 4793 return FALSE; 4794 } 4795 4796 if (arg->token->type == OT_INTEGER) 4797 { 4798 *value = arg->token->u.integer.value; 4799 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); 4800 ++arg->token; 4801 return TRUE; 4802 } 4803 4804 set_insn_error_i 4805 (arg->argnum, _("operand %d must be an immediate expression"), 4806 arg->argnum); 4807 return FALSE; 4808 } 4809 4810 /* Try to get a constant expression from the next tokens in ARG. Consume 4811 the tokens and return return true on success, storing the constant value 4812 in *VALUE. Use FALLBACK as the value if the match succeeded with an 4813 error. */ 4814 4815 static bfd_boolean 4816 match_const_int (struct mips_arg_info *arg, offsetT *value) 4817 { 4818 expressionS ex; 4819 bfd_reloc_code_real_type r[3]; 4820 4821 if (!match_expression (arg, &ex, r)) 4822 return FALSE; 4823 4824 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) 4825 *value = ex.X_add_number; 4826 else 4827 { 4828 match_not_constant (arg); 4829 return FALSE; 4830 } 4831 return TRUE; 4832 } 4833 4834 /* Return the RTYPE_* flags for a register operand of type TYPE that 4835 appears in instruction OPCODE. */ 4836 4837 static unsigned int 4838 convert_reg_type (const struct mips_opcode *opcode, 4839 enum mips_reg_operand_type type) 4840 { 4841 switch (type) 4842 { 4843 case OP_REG_MXU: 4844 return RTYPE_NUM | RTYPE_MXU; 4845 4846 case OP_REG_MXU_GP: 4847 return RTYPE_GP | RTYPE_MXU; 4848 4849 case OP_REG_GP: 4850 return RTYPE_NUM | RTYPE_GP; 4851 4852 case OP_REG_FP: 4853 /* Allow vector register names for MDMX if the instruction is a 64-bit 4854 FPR load, store or move (including moves to and from GPRs). */ 4855 if ((mips_opts.ase & ASE_MDMX) 4856 && (opcode->pinfo & FP_D) 4857 && (opcode->pinfo & (INSN_COPROC_MOVE 4858 | INSN_COPROC_MEMORY_DELAY 4859 | INSN_LOAD_COPROC 4860 | INSN_LOAD_MEMORY 4861 | INSN_STORE_MEMORY))) 4862 return RTYPE_FPU | RTYPE_VEC; 4863 return RTYPE_FPU; 4864 4865 case OP_REG_CCC: 4866 if (opcode->pinfo & (FP_D | FP_S)) 4867 return RTYPE_CCC | RTYPE_FCC; 4868 return RTYPE_CCC; 4869 4870 case OP_REG_VEC: 4871 if (opcode->membership & INSN_5400) 4872 return RTYPE_FPU; 4873 return RTYPE_FPU | RTYPE_VEC; 4874 4875 case OP_REG_ACC: 4876 return RTYPE_ACC; 4877 4878 case OP_REG_COPRO: 4879 if (opcode->name[strlen (opcode->name) - 1] == '0') 4880 return RTYPE_NUM | RTYPE_CP0; 4881 return RTYPE_NUM; 4882 4883 case OP_REG_HW: 4884 return RTYPE_NUM; 4885 4886 case OP_REG_VI: 4887 return RTYPE_NUM | RTYPE_VI; 4888 4889 case OP_REG_VF: 4890 return RTYPE_NUM | RTYPE_VF; 4891 4892 case OP_REG_R5900_I: 4893 return RTYPE_R5900_I; 4894 4895 case OP_REG_R5900_Q: 4896 return RTYPE_R5900_Q; 4897 4898 case OP_REG_R5900_R: 4899 return RTYPE_R5900_R; 4900 4901 case OP_REG_R5900_ACC: 4902 return RTYPE_R5900_ACC; 4903 4904 case OP_REG_MSA: 4905 return RTYPE_MSA; 4906 4907 case OP_REG_MSA_CTRL: 4908 return RTYPE_NUM; 4909 } 4910 abort (); 4911 } 4912 4913 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ 4914 4915 static void 4916 check_regno (struct mips_arg_info *arg, 4917 enum mips_reg_operand_type type, unsigned int regno) 4918 { 4919 if (AT && type == OP_REG_GP && regno == AT) 4920 arg->seen_at = TRUE; 4921 4922 if (type == OP_REG_FP 4923 && (regno & 1) != 0 4924 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) 4925 { 4926 /* This was a warning prior to introducing O32 FPXX and FP64 support 4927 so maintain a warning for FP32 but raise an error for the new 4928 cases. */ 4929 if (FPR_SIZE == 32) 4930 as_warn (_("float register should be even, was %d"), regno); 4931 else 4932 as_bad (_("float register should be even, was %d"), regno); 4933 } 4934 4935 if (type == OP_REG_CCC) 4936 { 4937 const char *name; 4938 size_t length; 4939 4940 name = arg->insn->insn_mo->name; 4941 length = strlen (name); 4942 if ((regno & 1) != 0 4943 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) 4944 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) 4945 as_warn (_("condition code register should be even for %s, was %d"), 4946 name, regno); 4947 4948 if ((regno & 3) != 0 4949 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) 4950 as_warn (_("condition code register should be 0 or 4 for %s, was %d"), 4951 name, regno); 4952 } 4953 } 4954 4955 /* ARG is a register with symbol value SYMVAL. Try to interpret it as 4956 a register of type TYPE. Return true on success, storing the register 4957 number in *REGNO and warning about any dubious uses. */ 4958 4959 static bfd_boolean 4960 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4961 unsigned int symval, unsigned int *regno) 4962 { 4963 if (type == OP_REG_VEC) 4964 symval = mips_prefer_vec_regno (symval); 4965 if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) 4966 return FALSE; 4967 4968 *regno = symval & RNUM_MASK; 4969 check_regno (arg, type, *regno); 4970 return TRUE; 4971 } 4972 4973 /* Try to interpret the next token in ARG as a register of type TYPE. 4974 Consume the token and return true on success, storing the register 4975 number in *REGNO. Return false on failure. */ 4976 4977 static bfd_boolean 4978 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4979 unsigned int *regno) 4980 { 4981 if (arg->token->type == OT_REG 4982 && match_regno (arg, type, arg->token->u.regno, regno)) 4983 { 4984 ++arg->token; 4985 return TRUE; 4986 } 4987 return FALSE; 4988 } 4989 4990 /* Try to interpret the next token in ARG as a range of registers of type TYPE. 4991 Consume the token and return true on success, storing the register numbers 4992 in *REGNO1 and *REGNO2. Return false on failure. */ 4993 4994 static bfd_boolean 4995 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, 4996 unsigned int *regno1, unsigned int *regno2) 4997 { 4998 if (match_reg (arg, type, regno1)) 4999 { 5000 *regno2 = *regno1; 5001 return TRUE; 5002 } 5003 if (arg->token->type == OT_REG_RANGE 5004 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) 5005 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) 5006 && *regno1 <= *regno2) 5007 { 5008 ++arg->token; 5009 return TRUE; 5010 } 5011 return FALSE; 5012 } 5013 5014 /* OP_INT matcher. */ 5015 5016 static bfd_boolean 5017 match_int_operand (struct mips_arg_info *arg, 5018 const struct mips_operand *operand_base) 5019 { 5020 const struct mips_int_operand *operand; 5021 unsigned int uval; 5022 int min_val, max_val, factor; 5023 offsetT sval; 5024 5025 operand = (const struct mips_int_operand *) operand_base; 5026 factor = 1 << operand->shift; 5027 min_val = mips_int_operand_min (operand); 5028 max_val = mips_int_operand_max (operand); 5029 5030 if (operand_base->lsb == 0 5031 && operand_base->size == 16 5032 && operand->shift == 0 5033 && operand->bias == 0 5034 && (operand->max_val == 32767 || operand->max_val == 65535)) 5035 { 5036 /* The operand can be relocated. */ 5037 if (!match_expression (arg, &offset_expr, offset_reloc)) 5038 return FALSE; 5039 5040 if (offset_reloc[0] != BFD_RELOC_UNUSED) 5041 /* Relocation operators were used. Accept the arguent and 5042 leave the relocation value in offset_expr and offset_relocs 5043 for the caller to process. */ 5044 return TRUE; 5045 5046 if (offset_expr.X_op != O_constant) 5047 { 5048 /* Accept non-constant operands if no later alternative matches, 5049 leaving it for the caller to process. */ 5050 if (!arg->lax_match) 5051 return FALSE; 5052 offset_reloc[0] = BFD_RELOC_LO16; 5053 return TRUE; 5054 } 5055 5056 /* Clear the global state; we're going to install the operand 5057 ourselves. */ 5058 sval = offset_expr.X_add_number; 5059 offset_expr.X_op = O_absent; 5060 5061 /* For compatibility with older assemblers, we accept 5062 0x8000-0xffff as signed 16-bit numbers when only 5063 signed numbers are allowed. */ 5064 if (sval > max_val) 5065 { 5066 max_val = ((1 << operand_base->size) - 1) << operand->shift; 5067 if (!arg->lax_match && sval <= max_val) 5068 return FALSE; 5069 } 5070 } 5071 else 5072 { 5073 if (!match_const_int (arg, &sval)) 5074 return FALSE; 5075 } 5076 5077 arg->last_op_int = sval; 5078 5079 if (sval < min_val || sval > max_val || sval % factor) 5080 { 5081 match_out_of_range (arg); 5082 return FALSE; 5083 } 5084 5085 uval = (unsigned int) sval >> operand->shift; 5086 uval -= operand->bias; 5087 5088 /* Handle -mfix-cn63xxp1. */ 5089 if (arg->opnum == 1 5090 && mips_fix_cn63xxp1 5091 && !mips_opts.micromips 5092 && strcmp ("pref", arg->insn->insn_mo->name) == 0) 5093 switch (uval) 5094 { 5095 case 5: 5096 case 25: 5097 case 26: 5098 case 27: 5099 case 28: 5100 case 29: 5101 case 30: 5102 case 31: 5103 /* These are ok. */ 5104 break; 5105 5106 default: 5107 /* The rest must be changed to 28. */ 5108 uval = 28; 5109 break; 5110 } 5111 5112 insn_insert_operand (arg->insn, operand_base, uval); 5113 return TRUE; 5114 } 5115 5116 /* OP_MAPPED_INT matcher. */ 5117 5118 static bfd_boolean 5119 match_mapped_int_operand (struct mips_arg_info *arg, 5120 const struct mips_operand *operand_base) 5121 { 5122 const struct mips_mapped_int_operand *operand; 5123 unsigned int uval, num_vals; 5124 offsetT sval; 5125 5126 operand = (const struct mips_mapped_int_operand *) operand_base; 5127 if (!match_const_int (arg, &sval)) 5128 return FALSE; 5129 5130 num_vals = 1 << operand_base->size; 5131 for (uval = 0; uval < num_vals; uval++) 5132 if (operand->int_map[uval] == sval) 5133 break; 5134 if (uval == num_vals) 5135 { 5136 match_out_of_range (arg); 5137 return FALSE; 5138 } 5139 5140 insn_insert_operand (arg->insn, operand_base, uval); 5141 return TRUE; 5142 } 5143 5144 /* OP_MSB matcher. */ 5145 5146 static bfd_boolean 5147 match_msb_operand (struct mips_arg_info *arg, 5148 const struct mips_operand *operand_base) 5149 { 5150 const struct mips_msb_operand *operand; 5151 int min_val, max_val, max_high; 5152 offsetT size, sval, high; 5153 5154 operand = (const struct mips_msb_operand *) operand_base; 5155 min_val = operand->bias; 5156 max_val = min_val + (1 << operand_base->size) - 1; 5157 max_high = operand->opsize; 5158 5159 if (!match_const_int (arg, &size)) 5160 return FALSE; 5161 5162 high = size + arg->last_op_int; 5163 sval = operand->add_lsb ? high : size; 5164 5165 if (size < 0 || high > max_high || sval < min_val || sval > max_val) 5166 { 5167 match_out_of_range (arg); 5168 return FALSE; 5169 } 5170 insn_insert_operand (arg->insn, operand_base, sval - min_val); 5171 return TRUE; 5172 } 5173 5174 5175 /* OP_MAPPED_STRING matcher. */ 5176 5177 static bfd_boolean 5178 match_string_operand (struct mips_arg_info *arg, 5179 const struct mips_operand *operand_base) 5180 { 5181 const struct mips_mapped_string_operand *operand; 5182 expressionS ex; 5183 bfd_reloc_code_real_type r[3]; 5184 int i; 5185 unsigned int store_val; 5186 const char * symbol_name; 5187 bfd_boolean match; 5188 5189 operand = (const struct mips_mapped_string_operand *) operand_base; 5190 5191 if (!match_expression (arg, &ex, r)) 5192 return FALSE; 5193 5194 if (operand->allow_constants && ex.X_op == O_constant 5195 && r[0] == BFD_RELOC_UNUSED) 5196 store_val = ex.X_add_number; 5197 else if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_symbol 5198 && ex.X_add_number == 0 && ex.X_op_symbol == NULL) 5199 { 5200 symbol_name = S_GET_NAME (ex.X_add_symbol); 5201 match = FALSE; 5202 5203 for (i = 0 ; i < (1 << operand_base->size) ; i++) 5204 { 5205 if (strcmp (operand->strings[i], symbol_name) == 0) 5206 { 5207 store_val = i; 5208 match = TRUE; 5209 break; 5210 } 5211 } 5212 5213 if (!match) 5214 { 5215 set_insn_error (arg->argnum, _("Invalid string in operand")); 5216 return FALSE; 5217 } 5218 } 5219 else 5220 return FALSE; 5221 5222 if (store_val >= (unsigned int) (1 << operand_base->size)) 5223 { 5224 match_out_of_range (arg); 5225 return FALSE; 5226 } 5227 5228 insn_insert_operand (arg->insn, operand_base, store_val); 5229 return TRUE; 5230 } 5231 5232 5233 /* OP_REG matcher. */ 5234 5235 static bfd_boolean 5236 match_reg_operand (struct mips_arg_info *arg, 5237 const struct mips_operand *operand_base) 5238 { 5239 const struct mips_reg_operand *operand; 5240 unsigned int regno, uval, num_vals; 5241 5242 operand = (const struct mips_reg_operand *) operand_base; 5243 if (!match_reg (arg, operand->reg_type, ®no)) 5244 return FALSE; 5245 5246 if (operand->reg_map) 5247 { 5248 num_vals = 1 << operand->root.size; 5249 for (uval = 0; uval < num_vals; uval++) 5250 if (operand->reg_map[uval] == regno) 5251 break; 5252 if (num_vals == uval) 5253 return FALSE; 5254 } 5255 else 5256 uval = regno; 5257 5258 if (operand_base->size > 0 5259 && uval >= (unsigned int) (1 << operand_base->size)) 5260 { 5261 match_out_of_range (arg); 5262 return FALSE; 5263 } 5264 5265 arg->last_regno = regno; 5266 if (arg->opnum == 1) 5267 arg->dest_regno = regno; 5268 insn_insert_operand (arg->insn, operand_base, uval); 5269 return TRUE; 5270 } 5271 5272 /* OP_REG_PAIR matcher. */ 5273 5274 static bfd_boolean 5275 match_reg_pair_operand (struct mips_arg_info *arg, 5276 const struct mips_operand *operand_base) 5277 { 5278 const struct mips_reg_pair_operand *operand; 5279 unsigned int regno1, regno2, uval, num_vals; 5280 5281 operand = (const struct mips_reg_pair_operand *) operand_base; 5282 if (!match_reg (arg, operand->reg_type, ®no1) 5283 || !match_char (arg, ',') 5284 || !match_reg (arg, operand->reg_type, ®no2)) 5285 return FALSE; 5286 5287 num_vals = 1 << operand_base->size; 5288 for (uval = 0; uval < num_vals; uval++) 5289 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) 5290 break; 5291 if (uval == num_vals) 5292 return FALSE; 5293 5294 insn_insert_operand (arg->insn, operand_base, uval); 5295 return TRUE; 5296 } 5297 5298 /* OP_PCREL matcher. The caller chooses the relocation type. */ 5299 5300 static bfd_boolean 5301 match_pcrel_operand (struct mips_arg_info *arg) 5302 { 5303 bfd_reloc_code_real_type r[3]; 5304 5305 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; 5306 } 5307 5308 /* OP_PERF_REG matcher. */ 5309 5310 static bfd_boolean 5311 match_perf_reg_operand (struct mips_arg_info *arg, 5312 const struct mips_operand *operand) 5313 { 5314 offsetT sval; 5315 5316 if (!match_const_int (arg, &sval)) 5317 return FALSE; 5318 5319 if (sval != 0 5320 && (sval != 1 5321 || (mips_opts.arch == CPU_R5900 5322 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 5323 || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) 5324 { 5325 set_insn_error (arg->argnum, _("invalid performance register")); 5326 return FALSE; 5327 } 5328 5329 insn_insert_operand (arg->insn, operand, sval); 5330 return TRUE; 5331 } 5332 5333 /* OP_ADDIUSP matcher. */ 5334 5335 static bfd_boolean 5336 match_addiusp_operand (struct mips_arg_info *arg, 5337 const struct mips_operand *operand) 5338 { 5339 offsetT sval; 5340 unsigned int uval; 5341 5342 if (!match_const_int (arg, &sval)) 5343 return FALSE; 5344 5345 if (sval % 4) 5346 { 5347 match_out_of_range (arg); 5348 return FALSE; 5349 } 5350 5351 sval /= 4; 5352 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) 5353 { 5354 match_out_of_range (arg); 5355 return FALSE; 5356 } 5357 5358 uval = (unsigned int) sval; 5359 uval = ((uval >> 1) & ~0xff) | (uval & 0xff); 5360 insn_insert_operand (arg->insn, operand, uval); 5361 return TRUE; 5362 } 5363 5364 /* OP_CLO_CLZ_DEST matcher. */ 5365 5366 static bfd_boolean 5367 match_clo_clz_dest_operand (struct mips_arg_info *arg, 5368 const struct mips_operand *operand) 5369 { 5370 unsigned int regno; 5371 5372 if (!match_reg (arg, OP_REG_GP, ®no)) 5373 return FALSE; 5374 5375 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5376 return TRUE; 5377 } 5378 5379 /* OP_CHECK_PREV matcher. */ 5380 5381 static bfd_boolean 5382 match_check_prev_operand (struct mips_arg_info *arg, 5383 const struct mips_operand *operand_base) 5384 { 5385 const struct mips_check_prev_operand *operand; 5386 unsigned int regno; 5387 5388 operand = (const struct mips_check_prev_operand *) operand_base; 5389 5390 if (!match_reg (arg, OP_REG_GP, ®no)) 5391 return FALSE; 5392 5393 if (!operand->zero_ok && regno == 0) 5394 return FALSE; 5395 5396 if ((operand->less_than_ok && regno < arg->last_regno) 5397 || (operand->greater_than_ok && regno > arg->last_regno) 5398 || (operand->equal_ok && regno == arg->last_regno)) 5399 { 5400 arg->last_regno = regno; 5401 insn_insert_operand (arg->insn, operand_base, regno); 5402 return TRUE; 5403 } 5404 5405 return FALSE; 5406 } 5407 5408 /* OP_SAME_RS_RT matcher. */ 5409 5410 static bfd_boolean 5411 match_same_rs_rt_operand (struct mips_arg_info *arg, 5412 const struct mips_operand *operand) 5413 { 5414 unsigned int regno; 5415 5416 if (!match_reg (arg, OP_REG_GP, ®no)) 5417 return FALSE; 5418 5419 if (regno == 0) 5420 { 5421 set_insn_error (arg->argnum, _("the source register must not be $0")); 5422 return FALSE; 5423 } 5424 5425 arg->last_regno = regno; 5426 5427 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5428 return TRUE; 5429 } 5430 5431 /* OP_LWM_SWM_LIST matcher. */ 5432 5433 static bfd_boolean 5434 match_lwm_swm_list_operand (struct mips_arg_info *arg, 5435 const struct mips_operand *operand) 5436 { 5437 unsigned int reglist, sregs, ra, regno1, regno2; 5438 struct mips_arg_info reset; 5439 5440 reglist = 0; 5441 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5442 return FALSE; 5443 do 5444 { 5445 if (regno2 == FP && regno1 >= S0 && regno1 <= S7) 5446 { 5447 reglist |= 1 << FP; 5448 regno2 = S7; 5449 } 5450 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); 5451 reset = *arg; 5452 } 5453 while (match_char (arg, ',') 5454 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); 5455 *arg = reset; 5456 5457 if (operand->size == 2) 5458 { 5459 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: 5460 5461 s0, ra 5462 s0, s1, ra, s2, s3 5463 s0-s2, ra 5464 5465 and any permutations of these. */ 5466 if ((reglist & 0xfff1ffff) != 0x80010000) 5467 return FALSE; 5468 5469 sregs = (reglist >> 17) & 7; 5470 ra = 0; 5471 } 5472 else 5473 { 5474 /* The list must include at least one of ra and s0-sN, 5475 for 0 <= N <= 8. (Note that there is a gap between s7 and s8, 5476 which are $23 and $30 respectively.) E.g.: 5477 5478 ra 5479 s0 5480 ra, s0, s1, s2 5481 s0-s8 5482 s0-s5, ra 5483 5484 and any permutations of these. */ 5485 if ((reglist & 0x3f00ffff) != 0) 5486 return FALSE; 5487 5488 ra = (reglist >> 27) & 0x10; 5489 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); 5490 } 5491 sregs += 1; 5492 if ((sregs & -sregs) != sregs) 5493 return FALSE; 5494 5495 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); 5496 return TRUE; 5497 } 5498 5499 /* OP_ENTRY_EXIT_LIST matcher. */ 5500 5501 static unsigned int 5502 match_entry_exit_operand (struct mips_arg_info *arg, 5503 const struct mips_operand *operand) 5504 { 5505 unsigned int mask; 5506 bfd_boolean is_exit; 5507 5508 /* The format is the same for both ENTRY and EXIT, but the constraints 5509 are different. */ 5510 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; 5511 mask = (is_exit ? 7 << 3 : 0); 5512 do 5513 { 5514 unsigned int regno1, regno2; 5515 bfd_boolean is_freg; 5516 5517 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5518 is_freg = FALSE; 5519 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) 5520 is_freg = TRUE; 5521 else 5522 return FALSE; 5523 5524 if (is_exit && is_freg && regno1 == 0 && regno2 < 2) 5525 { 5526 mask &= ~(7 << 3); 5527 mask |= (5 + regno2) << 3; 5528 } 5529 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) 5530 mask |= (regno2 - 3) << 3; 5531 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) 5532 mask |= (regno2 - 15) << 1; 5533 else if (regno1 == RA && regno2 == RA) 5534 mask |= 1; 5535 else 5536 return FALSE; 5537 } 5538 while (match_char (arg, ',')); 5539 5540 insn_insert_operand (arg->insn, operand, mask); 5541 return TRUE; 5542 } 5543 5544 /* OP_SAVE_RESTORE_LIST matcher. */ 5545 5546 static bfd_boolean 5547 match_save_restore_list_operand (struct mips_arg_info *arg) 5548 { 5549 unsigned int opcode, args, statics, sregs; 5550 unsigned int num_frame_sizes, num_args, num_statics, num_sregs; 5551 offsetT frame_size; 5552 5553 opcode = arg->insn->insn_opcode; 5554 frame_size = 0; 5555 num_frame_sizes = 0; 5556 args = 0; 5557 statics = 0; 5558 sregs = 0; 5559 do 5560 { 5561 unsigned int regno1, regno2; 5562 5563 if (arg->token->type == OT_INTEGER) 5564 { 5565 /* Handle the frame size. */ 5566 if (!match_const_int (arg, &frame_size)) 5567 return FALSE; 5568 num_frame_sizes += 1; 5569 } 5570 else 5571 { 5572 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5573 return FALSE; 5574 5575 while (regno1 <= regno2) 5576 { 5577 if (regno1 >= 4 && regno1 <= 7) 5578 { 5579 if (num_frame_sizes == 0) 5580 /* args $a0-$a3 */ 5581 args |= 1 << (regno1 - 4); 5582 else 5583 /* statics $a0-$a3 */ 5584 statics |= 1 << (regno1 - 4); 5585 } 5586 else if (regno1 >= 16 && regno1 <= 23) 5587 /* $s0-$s7 */ 5588 sregs |= 1 << (regno1 - 16); 5589 else if (regno1 == 30) 5590 /* $s8 */ 5591 sregs |= 1 << 8; 5592 else if (regno1 == 31) 5593 /* Add $ra to insn. */ 5594 opcode |= 0x40; 5595 else 5596 return FALSE; 5597 regno1 += 1; 5598 if (regno1 == 24) 5599 regno1 = 30; 5600 } 5601 } 5602 } 5603 while (match_char (arg, ',')); 5604 5605 /* Encode args/statics combination. */ 5606 if (args & statics) 5607 return FALSE; 5608 else if (args == 0xf) 5609 /* All $a0-$a3 are args. */ 5610 opcode |= MIPS16_ALL_ARGS << 16; 5611 else if (statics == 0xf) 5612 /* All $a0-$a3 are statics. */ 5613 opcode |= MIPS16_ALL_STATICS << 16; 5614 else 5615 { 5616 /* Count arg registers. */ 5617 num_args = 0; 5618 while (args & 0x1) 5619 { 5620 args >>= 1; 5621 num_args += 1; 5622 } 5623 if (args != 0) 5624 return FALSE; 5625 5626 /* Count static registers. */ 5627 num_statics = 0; 5628 while (statics & 0x8) 5629 { 5630 statics = (statics << 1) & 0xf; 5631 num_statics += 1; 5632 } 5633 if (statics != 0) 5634 return FALSE; 5635 5636 /* Encode args/statics. */ 5637 opcode |= ((num_args << 2) | num_statics) << 16; 5638 } 5639 5640 /* Encode $s0/$s1. */ 5641 if (sregs & (1 << 0)) /* $s0 */ 5642 opcode |= 0x20; 5643 if (sregs & (1 << 1)) /* $s1 */ 5644 opcode |= 0x10; 5645 sregs >>= 2; 5646 5647 /* Encode $s2-$s8. */ 5648 num_sregs = 0; 5649 while (sregs & 1) 5650 { 5651 sregs >>= 1; 5652 num_sregs += 1; 5653 } 5654 if (sregs != 0) 5655 return FALSE; 5656 opcode |= num_sregs << 24; 5657 5658 /* Encode frame size. */ 5659 if (num_frame_sizes == 0) 5660 { 5661 set_insn_error (arg->argnum, _("missing frame size")); 5662 return FALSE; 5663 } 5664 if (num_frame_sizes > 1) 5665 { 5666 set_insn_error (arg->argnum, _("frame size specified twice")); 5667 return FALSE; 5668 } 5669 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) 5670 { 5671 set_insn_error (arg->argnum, _("invalid frame size")); 5672 return FALSE; 5673 } 5674 if (frame_size != 128 || (opcode >> 16) != 0) 5675 { 5676 frame_size /= 8; 5677 opcode |= (((frame_size & 0xf0) << 16) 5678 | (frame_size & 0x0f)); 5679 } 5680 5681 /* Finally build the instruction. */ 5682 if ((opcode >> 16) != 0 || frame_size == 0) 5683 opcode |= MIPS16_EXTEND; 5684 arg->insn->insn_opcode = opcode; 5685 return TRUE; 5686 } 5687 5688 /* OP_MDMX_IMM_REG matcher. */ 5689 5690 static bfd_boolean 5691 match_mdmx_imm_reg_operand (struct mips_arg_info *arg, 5692 const struct mips_operand *operand) 5693 { 5694 unsigned int regno, uval; 5695 bfd_boolean is_qh; 5696 const struct mips_opcode *opcode; 5697 5698 /* The mips_opcode records whether this is an octobyte or quadhalf 5699 instruction. Start out with that bit in place. */ 5700 opcode = arg->insn->insn_mo; 5701 uval = mips_extract_operand (operand, opcode->match); 5702 is_qh = (uval != 0); 5703 5704 if (arg->token->type == OT_REG) 5705 { 5706 if ((opcode->membership & INSN_5400) 5707 && strcmp (opcode->name, "rzu.ob") == 0) 5708 { 5709 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), 5710 arg->argnum); 5711 return FALSE; 5712 } 5713 5714 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) 5715 return FALSE; 5716 ++arg->token; 5717 5718 /* Check whether this is a vector register or a broadcast of 5719 a single element. */ 5720 if (arg->token->type == OT_INTEGER_INDEX) 5721 { 5722 if (arg->token->u.index > (is_qh ? 3 : 7)) 5723 { 5724 set_insn_error (arg->argnum, _("invalid element selector")); 5725 return FALSE; 5726 } 5727 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; 5728 ++arg->token; 5729 } 5730 else 5731 { 5732 /* A full vector. */ 5733 if ((opcode->membership & INSN_5400) 5734 && (strcmp (opcode->name, "sll.ob") == 0 5735 || strcmp (opcode->name, "srl.ob") == 0)) 5736 { 5737 set_insn_error_i (arg->argnum, _("operand %d must be scalar"), 5738 arg->argnum); 5739 return FALSE; 5740 } 5741 5742 if (is_qh) 5743 uval |= MDMX_FMTSEL_VEC_QH << 5; 5744 else 5745 uval |= MDMX_FMTSEL_VEC_OB << 5; 5746 } 5747 uval |= regno; 5748 } 5749 else 5750 { 5751 offsetT sval; 5752 5753 if (!match_const_int (arg, &sval)) 5754 return FALSE; 5755 if (sval < 0 || sval > 31) 5756 { 5757 match_out_of_range (arg); 5758 return FALSE; 5759 } 5760 uval |= (sval & 31); 5761 if (is_qh) 5762 uval |= MDMX_FMTSEL_IMM_QH << 5; 5763 else 5764 uval |= MDMX_FMTSEL_IMM_OB << 5; 5765 } 5766 insn_insert_operand (arg->insn, operand, uval); 5767 return TRUE; 5768 } 5769 5770 /* OP_IMM_INDEX matcher. */ 5771 5772 static bfd_boolean 5773 match_imm_index_operand (struct mips_arg_info *arg, 5774 const struct mips_operand *operand) 5775 { 5776 unsigned int max_val; 5777 5778 if (arg->token->type != OT_INTEGER_INDEX) 5779 return FALSE; 5780 5781 max_val = (1 << operand->size) - 1; 5782 if (arg->token->u.index > max_val) 5783 { 5784 match_out_of_range (arg); 5785 return FALSE; 5786 } 5787 insn_insert_operand (arg->insn, operand, arg->token->u.index); 5788 ++arg->token; 5789 return TRUE; 5790 } 5791 5792 /* OP_MXU_STRIDE matcher. */ 5793 5794 static bfd_boolean 5795 match_mxu_stride_operand (struct mips_arg_info *arg, 5796 const struct mips_operand *operand) 5797 { 5798 offsetT sval; 5799 5800 if (!match_const_int (arg, &sval)) 5801 return FALSE; 5802 5803 if (sval < 0 || sval > 2) 5804 return FALSE; 5805 5806 insn_insert_operand (arg->insn, operand, sval); 5807 return TRUE; 5808 } 5809 5810 /* OP_REG_INDEX matcher. */ 5811 5812 static bfd_boolean 5813 match_reg_index_operand (struct mips_arg_info *arg, 5814 const struct mips_operand *operand) 5815 { 5816 unsigned int regno; 5817 5818 if (arg->token->type != OT_REG_INDEX) 5819 return FALSE; 5820 5821 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) 5822 return FALSE; 5823 5824 insn_insert_operand (arg->insn, operand, regno); 5825 ++arg->token; 5826 return TRUE; 5827 } 5828 5829 /* OP_PC matcher. */ 5830 5831 static bfd_boolean 5832 match_pc_operand (struct mips_arg_info *arg) 5833 { 5834 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) 5835 { 5836 ++arg->token; 5837 return TRUE; 5838 } 5839 return FALSE; 5840 } 5841 5842 /* OP_NON_ZERO_REG matcher. */ 5843 5844 static bfd_boolean 5845 match_non_zero_reg_operand (struct mips_arg_info *arg, 5846 const struct mips_operand *operand) 5847 { 5848 unsigned int regno; 5849 5850 if (!match_reg (arg, OP_REG_GP, ®no)) 5851 return FALSE; 5852 5853 if (regno == 0) 5854 return FALSE; 5855 5856 arg->last_regno = regno; 5857 insn_insert_operand (arg->insn, operand, regno); 5858 return TRUE; 5859 } 5860 5861 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the 5862 register that we need to match. */ 5863 5864 static bfd_boolean 5865 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) 5866 { 5867 unsigned int regno; 5868 5869 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; 5870 } 5871 5872 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is 5873 the length of the value in bytes (4 for float, 8 for double) and 5874 USING_GPRS says whether the destination is a GPR rather than an FPR. 5875 5876 Return the constant in IMM and OFFSET as follows: 5877 5878 - If the constant should be loaded via memory, set IMM to O_absent and 5879 OFFSET to the memory address. 5880 5881 - Otherwise, if the constant should be loaded into two 32-bit registers, 5882 set IMM to the O_constant to load into the high register and OFFSET 5883 to the corresponding value for the low register. 5884 5885 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. 5886 5887 These constants only appear as the last operand in an instruction, 5888 and every instruction that accepts them in any variant accepts them 5889 in all variants. This means we don't have to worry about backing out 5890 any changes if the instruction does not match. We just match 5891 unconditionally and report an error if the constant is invalid. */ 5892 5893 static bfd_boolean 5894 match_float_constant (struct mips_arg_info *arg, expressionS *imm, 5895 expressionS *offset, int length, bfd_boolean using_gprs) 5896 { 5897 char *p; 5898 segT seg, new_seg; 5899 subsegT subseg; 5900 const char *newname; 5901 unsigned char *data; 5902 5903 /* Where the constant is placed is based on how the MIPS assembler 5904 does things: 5905 5906 length == 4 && using_gprs -- immediate value only 5907 length == 8 && using_gprs -- .rdata or immediate value 5908 length == 4 && !using_gprs -- .lit4 or immediate value 5909 length == 8 && !using_gprs -- .lit8 or immediate value 5910 5911 The .lit4 and .lit8 sections are only used if permitted by the 5912 -G argument. */ 5913 if (arg->token->type != OT_FLOAT) 5914 { 5915 set_insn_error (arg->argnum, _("floating-point expression required")); 5916 return FALSE; 5917 } 5918 5919 gas_assert (arg->token->u.flt.length == length); 5920 data = arg->token->u.flt.data; 5921 ++arg->token; 5922 5923 /* Handle 32-bit constants for which an immediate value is best. */ 5924 if (length == 4 5925 && (using_gprs 5926 || g_switch_value < 4 5927 || (data[0] == 0 && data[1] == 0) 5928 || (data[2] == 0 && data[3] == 0))) 5929 { 5930 imm->X_op = O_constant; 5931 if (!target_big_endian) 5932 imm->X_add_number = bfd_getl32 (data); 5933 else 5934 imm->X_add_number = bfd_getb32 (data); 5935 offset->X_op = O_absent; 5936 return TRUE; 5937 } 5938 5939 /* Handle 64-bit constants for which an immediate value is best. */ 5940 if (length == 8 5941 && !mips_disable_float_construction 5942 /* Constants can only be constructed in GPRs and copied to FPRs if the 5943 GPRs are at least as wide as the FPRs or MTHC1 is available. 5944 Unlike most tests for 32-bit floating-point registers this check 5945 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not 5946 permit 64-bit moves without MXHC1. 5947 Force the constant into memory otherwise. */ 5948 && (using_gprs 5949 || GPR_SIZE == 64 5950 || ISA_HAS_MXHC1 (mips_opts.isa) 5951 || FPR_SIZE == 32) 5952 && ((data[0] == 0 && data[1] == 0) 5953 || (data[2] == 0 && data[3] == 0)) 5954 && ((data[4] == 0 && data[5] == 0) 5955 || (data[6] == 0 && data[7] == 0))) 5956 { 5957 /* The value is simple enough to load with a couple of instructions. 5958 If using 32-bit registers, set IMM to the high order 32 bits and 5959 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire 5960 64 bit constant. */ 5961 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) 5962 { 5963 imm->X_op = O_constant; 5964 offset->X_op = O_constant; 5965 if (!target_big_endian) 5966 { 5967 imm->X_add_number = bfd_getl32 (data + 4); 5968 offset->X_add_number = bfd_getl32 (data); 5969 } 5970 else 5971 { 5972 imm->X_add_number = bfd_getb32 (data); 5973 offset->X_add_number = bfd_getb32 (data + 4); 5974 } 5975 if (offset->X_add_number == 0) 5976 offset->X_op = O_absent; 5977 } 5978 else 5979 { 5980 imm->X_op = O_constant; 5981 if (!target_big_endian) 5982 imm->X_add_number = bfd_getl64 (data); 5983 else 5984 imm->X_add_number = bfd_getb64 (data); 5985 offset->X_op = O_absent; 5986 } 5987 return TRUE; 5988 } 5989 5990 /* Switch to the right section. */ 5991 seg = now_seg; 5992 subseg = now_subseg; 5993 if (length == 4) 5994 { 5995 gas_assert (!using_gprs && g_switch_value >= 4); 5996 newname = ".lit4"; 5997 } 5998 else 5999 { 6000 if (using_gprs || g_switch_value < 8) 6001 newname = RDATA_SECTION_NAME; 6002 else 6003 newname = ".lit8"; 6004 } 6005 6006 new_seg = subseg_new (newname, (subsegT) 0); 6007 bfd_set_section_flags (stdoutput, new_seg, 6008 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); 6009 frag_align (length == 4 ? 2 : 3, 0, 0); 6010 if (strncmp (TARGET_OS, "elf", 3) != 0) 6011 record_alignment (new_seg, 4); 6012 else 6013 record_alignment (new_seg, length == 4 ? 2 : 3); 6014 if (seg == now_seg) 6015 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); 6016 6017 /* Set the argument to the current address in the section. */ 6018 imm->X_op = O_absent; 6019 offset->X_op = O_symbol; 6020 offset->X_add_symbol = symbol_temp_new_now (); 6021 offset->X_add_number = 0; 6022 6023 /* Put the floating point number into the section. */ 6024 p = frag_more (length); 6025 memcpy (p, data, length); 6026 6027 /* Switch back to the original section. */ 6028 subseg_set (seg, subseg); 6029 return TRUE; 6030 } 6031 6032 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between 6033 them. */ 6034 6035 static bfd_boolean 6036 match_vu0_suffix_operand (struct mips_arg_info *arg, 6037 const struct mips_operand *operand, 6038 bfd_boolean match_p) 6039 { 6040 unsigned int uval; 6041 6042 /* The operand can be an XYZW mask or a single 2-bit channel index 6043 (with X being 0). */ 6044 gas_assert (operand->size == 2 || operand->size == 4); 6045 6046 /* The suffix can be omitted when it is already part of the opcode. */ 6047 if (arg->token->type != OT_CHANNELS) 6048 return match_p; 6049 6050 uval = arg->token->u.channels; 6051 if (operand->size == 2) 6052 { 6053 /* Check that a single bit is set and convert it into a 2-bit index. */ 6054 if ((uval & -uval) != uval) 6055 return FALSE; 6056 uval = 4 - ffs (uval); 6057 } 6058 6059 if (match_p && insn_extract_operand (arg->insn, operand) != uval) 6060 return FALSE; 6061 6062 ++arg->token; 6063 if (!match_p) 6064 insn_insert_operand (arg->insn, operand, uval); 6065 return TRUE; 6066 } 6067 6068 /* S is the text seen for ARG. Match it against OPERAND. Return the end 6069 of the argument text if the match is successful, otherwise return null. */ 6070 6071 static bfd_boolean 6072 match_operand (struct mips_arg_info *arg, 6073 const struct mips_operand *operand) 6074 { 6075 switch (operand->type) 6076 { 6077 case OP_INT: 6078 return match_int_operand (arg, operand); 6079 6080 case OP_MAPPED_INT: 6081 return match_mapped_int_operand (arg, operand); 6082 6083 case OP_MSB: 6084 return match_msb_operand (arg, operand); 6085 6086 case OP_MAPPED_STRING: 6087 return match_string_operand (arg, operand); 6088 6089 case OP_REG: 6090 case OP_OPTIONAL_REG: 6091 return match_reg_operand (arg, operand); 6092 6093 case OP_REG_PAIR: 6094 return match_reg_pair_operand (arg, operand); 6095 6096 case OP_PCREL: 6097 return match_pcrel_operand (arg); 6098 6099 case OP_PERF_REG: 6100 return match_perf_reg_operand (arg, operand); 6101 6102 case OP_ADDIUSP_INT: 6103 return match_addiusp_operand (arg, operand); 6104 6105 case OP_CLO_CLZ_DEST: 6106 return match_clo_clz_dest_operand (arg, operand); 6107 6108 case OP_LWM_SWM_LIST: 6109 return match_lwm_swm_list_operand (arg, operand); 6110 6111 case OP_ENTRY_EXIT_LIST: 6112 return match_entry_exit_operand (arg, operand); 6113 6114 case OP_SAVE_RESTORE_LIST: 6115 return match_save_restore_list_operand (arg); 6116 6117 case OP_MDMX_IMM_REG: 6118 return match_mdmx_imm_reg_operand (arg, operand); 6119 6120 case OP_REPEAT_DEST_REG: 6121 return match_tied_reg_operand (arg, arg->dest_regno); 6122 6123 case OP_REPEAT_PREV_REG: 6124 return match_tied_reg_operand (arg, arg->last_regno); 6125 6126 case OP_PC: 6127 return match_pc_operand (arg); 6128 6129 case OP_VU0_SUFFIX: 6130 return match_vu0_suffix_operand (arg, operand, FALSE); 6131 6132 case OP_VU0_MATCH_SUFFIX: 6133 return match_vu0_suffix_operand (arg, operand, TRUE); 6134 6135 case OP_IMM_INDEX: 6136 return match_imm_index_operand (arg, operand); 6137 6138 case OP_REG_INDEX: 6139 return match_reg_index_operand (arg, operand); 6140 6141 case OP_SAME_RS_RT: 6142 return match_same_rs_rt_operand (arg, operand); 6143 6144 case OP_CHECK_PREV: 6145 return match_check_prev_operand (arg, operand); 6146 6147 case OP_NON_ZERO_REG: 6148 return match_non_zero_reg_operand (arg, operand); 6149 6150 case OP_MXU_STRIDE: 6151 return match_mxu_stride_operand (arg, operand); 6152 } 6153 abort (); 6154 } 6155 6156 /* ARG is the state after successfully matching an instruction. 6157 Issue any queued-up warnings. */ 6158 6159 static void 6160 check_completed_insn (struct mips_arg_info *arg) 6161 { 6162 if (arg->seen_at) 6163 { 6164 if (AT == ATREG) 6165 as_warn (_("used $at without \".set noat\"")); 6166 else 6167 as_warn (_("used $%u with \".set at=$%u\""), AT, AT); 6168 } 6169 } 6170 6171 /* Return true if modifying general-purpose register REG needs a delay. */ 6172 6173 static bfd_boolean 6174 reg_needs_delay (unsigned int reg) 6175 { 6176 unsigned long prev_pinfo; 6177 6178 prev_pinfo = history[0].insn_mo->pinfo; 6179 if (!mips_opts.noreorder 6180 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) 6181 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) 6182 && (gpr_write_mask (&history[0]) & (1 << reg))) 6183 return TRUE; 6184 6185 return FALSE; 6186 } 6187 6188 /* Classify an instruction according to the FIX_VR4120_* enumeration. 6189 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected 6190 by VR4120 errata. */ 6191 6192 static unsigned int 6193 classify_vr4120_insn (const char *name) 6194 { 6195 if (strncmp (name, "macc", 4) == 0) 6196 return FIX_VR4120_MACC; 6197 if (strncmp (name, "dmacc", 5) == 0) 6198 return FIX_VR4120_DMACC; 6199 if (strncmp (name, "mult", 4) == 0) 6200 return FIX_VR4120_MULT; 6201 if (strncmp (name, "dmult", 5) == 0) 6202 return FIX_VR4120_DMULT; 6203 if (strstr (name, "div")) 6204 return FIX_VR4120_DIV; 6205 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) 6206 return FIX_VR4120_MTHILO; 6207 return NUM_FIX_VR4120_CLASSES; 6208 } 6209 6210 #define INSN_ERET 0x42000018 6211 #define INSN_DERET 0x4200001f 6212 #define INSN_DMULT 0x1c 6213 #define INSN_DMULTU 0x1d 6214 6215 /* Return the number of instructions that must separate INSN1 and INSN2, 6216 where INSN1 is the earlier instruction. Return the worst-case value 6217 for any INSN2 if INSN2 is null. */ 6218 6219 static unsigned int 6220 insns_between (const struct mips_cl_insn *insn1, 6221 const struct mips_cl_insn *insn2) 6222 { 6223 unsigned long pinfo1, pinfo2; 6224 unsigned int mask; 6225 6226 /* If INFO2 is null, pessimistically assume that all flags are set for 6227 the second instruction. */ 6228 pinfo1 = insn1->insn_mo->pinfo; 6229 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; 6230 6231 /* For most targets, write-after-read dependencies on the HI and LO 6232 registers must be separated by at least two instructions. */ 6233 if (!hilo_interlocks) 6234 { 6235 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) 6236 return 2; 6237 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) 6238 return 2; 6239 } 6240 6241 /* If we're working around r7000 errata, there must be two instructions 6242 between an mfhi or mflo and any instruction that uses the result. */ 6243 if (mips_7000_hilo_fix 6244 && !mips_opts.micromips 6245 && MF_HILO_INSN (pinfo1) 6246 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) 6247 return 2; 6248 6249 /* If we're working around 24K errata, one instruction is required 6250 if an ERET or DERET is followed by a branch instruction. */ 6251 if (mips_fix_24k && !mips_opts.micromips) 6252 { 6253 if (insn1->insn_opcode == INSN_ERET 6254 || insn1->insn_opcode == INSN_DERET) 6255 { 6256 if (insn2 == NULL 6257 || insn2->insn_opcode == INSN_ERET 6258 || insn2->insn_opcode == INSN_DERET 6259 || delayed_branch_p (insn2)) 6260 return 1; 6261 } 6262 } 6263 6264 /* If we're working around PMC RM7000 errata, there must be three 6265 nops between a dmult and a load instruction. */ 6266 if (mips_fix_rm7000 && !mips_opts.micromips) 6267 { 6268 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT 6269 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) 6270 { 6271 if (pinfo2 & INSN_LOAD_MEMORY) 6272 return 3; 6273 } 6274 } 6275 6276 /* If working around VR4120 errata, check for combinations that need 6277 a single intervening instruction. */ 6278 if (mips_fix_vr4120 && !mips_opts.micromips) 6279 { 6280 unsigned int class1, class2; 6281 6282 class1 = classify_vr4120_insn (insn1->insn_mo->name); 6283 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) 6284 { 6285 if (insn2 == NULL) 6286 return 1; 6287 class2 = classify_vr4120_insn (insn2->insn_mo->name); 6288 if (vr4120_conflicts[class1] & (1 << class2)) 6289 return 1; 6290 } 6291 } 6292 6293 if (!HAVE_CODE_COMPRESSION) 6294 { 6295 /* Check for GPR or coprocessor load delays. All such delays 6296 are on the RT register. */ 6297 /* Itbl support may require additional care here. */ 6298 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) 6299 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) 6300 { 6301 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) 6302 return 1; 6303 } 6304 6305 /* Check for generic coprocessor hazards. 6306 6307 This case is not handled very well. There is no special 6308 knowledge of CP0 handling, and the coprocessors other than 6309 the floating point unit are not distinguished at all. */ 6310 /* Itbl support may require additional care here. FIXME! 6311 Need to modify this to include knowledge about 6312 user specified delays! */ 6313 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) 6314 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) 6315 { 6316 /* Handle cases where INSN1 writes to a known general coprocessor 6317 register. There must be a one instruction delay before INSN2 6318 if INSN2 reads that register, otherwise no delay is needed. */ 6319 mask = fpr_write_mask (insn1); 6320 if (mask != 0) 6321 { 6322 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) 6323 return 1; 6324 } 6325 else 6326 { 6327 /* Read-after-write dependencies on the control registers 6328 require a two-instruction gap. */ 6329 if ((pinfo1 & INSN_WRITE_COND_CODE) 6330 && (pinfo2 & INSN_READ_COND_CODE)) 6331 return 2; 6332 6333 /* We don't know exactly what INSN1 does. If INSN2 is 6334 also a coprocessor instruction, assume there must be 6335 a one instruction gap. */ 6336 if (pinfo2 & INSN_COP) 6337 return 1; 6338 } 6339 } 6340 6341 /* Check for read-after-write dependencies on the coprocessor 6342 control registers in cases where INSN1 does not need a general 6343 coprocessor delay. This means that INSN1 is a floating point 6344 comparison instruction. */ 6345 /* Itbl support may require additional care here. */ 6346 else if (!cop_interlocks 6347 && (pinfo1 & INSN_WRITE_COND_CODE) 6348 && (pinfo2 & INSN_READ_COND_CODE)) 6349 return 1; 6350 } 6351 6352 /* Forbidden slots can not contain Control Transfer Instructions (CTIs) 6353 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait 6354 and pause. */ 6355 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) 6356 && ((pinfo2 & INSN_NO_DELAY_SLOT) 6357 || (insn2 && delayed_branch_p (insn2)))) 6358 return 1; 6359 6360 return 0; 6361 } 6362 6363 /* Return the number of nops that would be needed to work around the 6364 VR4130 mflo/mfhi errata if instruction INSN immediately followed 6365 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards 6366 that are contained within the first IGNORE instructions of HIST. */ 6367 6368 static int 6369 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, 6370 const struct mips_cl_insn *insn) 6371 { 6372 int i, j; 6373 unsigned int mask; 6374 6375 /* Check if the instruction writes to HI or LO. MTHI and MTLO 6376 are not affected by the errata. */ 6377 if (insn != 0 6378 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 6379 || strcmp (insn->insn_mo->name, "mtlo") == 0 6380 || strcmp (insn->insn_mo->name, "mthi") == 0)) 6381 return 0; 6382 6383 /* Search for the first MFLO or MFHI. */ 6384 for (i = 0; i < MAX_VR4130_NOPS; i++) 6385 if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) 6386 { 6387 /* Extract the destination register. */ 6388 mask = gpr_write_mask (&hist[i]); 6389 6390 /* No nops are needed if INSN reads that register. */ 6391 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) 6392 return 0; 6393 6394 /* ...or if any of the intervening instructions do. */ 6395 for (j = 0; j < i; j++) 6396 if (gpr_read_mask (&hist[j]) & mask) 6397 return 0; 6398 6399 if (i >= ignore) 6400 return MAX_VR4130_NOPS - i; 6401 } 6402 return 0; 6403 } 6404 6405 #define BASE_REG_EQ(INSN1, INSN2) \ 6406 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ 6407 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) 6408 6409 /* Return the minimum alignment for this store instruction. */ 6410 6411 static int 6412 fix_24k_align_to (const struct mips_opcode *mo) 6413 { 6414 if (strcmp (mo->name, "sh") == 0) 6415 return 2; 6416 6417 if (strcmp (mo->name, "swc1") == 0 6418 || strcmp (mo->name, "swc2") == 0 6419 || strcmp (mo->name, "sw") == 0 6420 || strcmp (mo->name, "sc") == 0 6421 || strcmp (mo->name, "s.s") == 0) 6422 return 4; 6423 6424 if (strcmp (mo->name, "sdc1") == 0 6425 || strcmp (mo->name, "sdc2") == 0 6426 || strcmp (mo->name, "s.d") == 0) 6427 return 8; 6428 6429 /* sb, swl, swr */ 6430 return 1; 6431 } 6432 6433 struct fix_24k_store_info 6434 { 6435 /* Immediate offset, if any, for this store instruction. */ 6436 short off; 6437 /* Alignment required by this store instruction. */ 6438 int align_to; 6439 /* True for register offsets. */ 6440 int register_offset; 6441 }; 6442 6443 /* Comparison function used by qsort. */ 6444 6445 static int 6446 fix_24k_sort (const void *a, const void *b) 6447 { 6448 const struct fix_24k_store_info *pos1 = a; 6449 const struct fix_24k_store_info *pos2 = b; 6450 6451 return (pos1->off - pos2->off); 6452 } 6453 6454 /* INSN is a store instruction. Try to record the store information 6455 in STINFO. Return false if the information isn't known. */ 6456 6457 static bfd_boolean 6458 fix_24k_record_store_info (struct fix_24k_store_info *stinfo, 6459 const struct mips_cl_insn *insn) 6460 { 6461 /* The instruction must have a known offset. */ 6462 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) 6463 return FALSE; 6464 6465 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; 6466 stinfo->align_to = fix_24k_align_to (insn->insn_mo); 6467 return TRUE; 6468 } 6469 6470 /* Return the number of nops that would be needed to work around the 24k 6471 "lost data on stores during refill" errata if instruction INSN 6472 immediately followed the 2 instructions described by HIST. 6473 Ignore hazards that are contained within the first IGNORE 6474 instructions of HIST. 6475 6476 Problem: The FSB (fetch store buffer) acts as an intermediate buffer 6477 for the data cache refills and store data. The following describes 6478 the scenario where the store data could be lost. 6479 6480 * A data cache miss, due to either a load or a store, causing fill 6481 data to be supplied by the memory subsystem 6482 * The first three doublewords of fill data are returned and written 6483 into the cache 6484 * A sequence of four stores occurs in consecutive cycles around the 6485 final doubleword of the fill: 6486 * Store A 6487 * Store B 6488 * Store C 6489 * Zero, One or more instructions 6490 * Store D 6491 6492 The four stores A-D must be to different doublewords of the line that 6493 is being filled. The fourth instruction in the sequence above permits 6494 the fill of the final doubleword to be transferred from the FSB into 6495 the cache. In the sequence above, the stores may be either integer 6496 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, 6497 swxc1, sdxc1, suxc1) stores, as long as the four stores are to 6498 different doublewords on the line. If the floating point unit is 6499 running in 1:2 mode, it is not possible to create the sequence above 6500 using only floating point store instructions. 6501 6502 In this case, the cache line being filled is incorrectly marked 6503 invalid, thereby losing the data from any store to the line that 6504 occurs between the original miss and the completion of the five 6505 cycle sequence shown above. 6506 6507 The workarounds are: 6508 6509 * Run the data cache in write-through mode. 6510 * Insert a non-store instruction between 6511 Store A and Store B or Store B and Store C. */ 6512 6513 static int 6514 nops_for_24k (int ignore, const struct mips_cl_insn *hist, 6515 const struct mips_cl_insn *insn) 6516 { 6517 struct fix_24k_store_info pos[3]; 6518 int align, i, base_offset; 6519 6520 if (ignore >= 2) 6521 return 0; 6522 6523 /* If the previous instruction wasn't a store, there's nothing to 6524 worry about. */ 6525 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6526 return 0; 6527 6528 /* If the instructions after the previous one are unknown, we have 6529 to assume the worst. */ 6530 if (!insn) 6531 return 1; 6532 6533 /* Check whether we are dealing with three consecutive stores. */ 6534 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 6535 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6536 return 0; 6537 6538 /* If we don't know the relationship between the store addresses, 6539 assume the worst. */ 6540 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) 6541 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) 6542 return 1; 6543 6544 if (!fix_24k_record_store_info (&pos[0], insn) 6545 || !fix_24k_record_store_info (&pos[1], &hist[0]) 6546 || !fix_24k_record_store_info (&pos[2], &hist[1])) 6547 return 1; 6548 6549 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); 6550 6551 /* Pick a value of ALIGN and X such that all offsets are adjusted by 6552 X bytes and such that the base register + X is known to be aligned 6553 to align bytes. */ 6554 6555 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) 6556 align = 8; 6557 else 6558 { 6559 align = pos[0].align_to; 6560 base_offset = pos[0].off; 6561 for (i = 1; i < 3; i++) 6562 if (align < pos[i].align_to) 6563 { 6564 align = pos[i].align_to; 6565 base_offset = pos[i].off; 6566 } 6567 for (i = 0; i < 3; i++) 6568 pos[i].off -= base_offset; 6569 } 6570 6571 pos[0].off &= ~align + 1; 6572 pos[1].off &= ~align + 1; 6573 pos[2].off &= ~align + 1; 6574 6575 /* If any two stores write to the same chunk, they also write to the 6576 same doubleword. The offsets are still sorted at this point. */ 6577 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) 6578 return 0; 6579 6580 /* A range of at least 9 bytes is needed for the stores to be in 6581 non-overlapping doublewords. */ 6582 if (pos[2].off - pos[0].off <= 8) 6583 return 0; 6584 6585 if (pos[2].off - pos[1].off >= 24 6586 || pos[1].off - pos[0].off >= 24 6587 || pos[2].off - pos[0].off >= 32) 6588 return 0; 6589 6590 return 1; 6591 } 6592 6593 /* Return the number of nops that would be needed if instruction INSN 6594 immediately followed the MAX_NOPS instructions given by HIST, 6595 where HIST[0] is the most recent instruction. Ignore hazards 6596 between INSN and the first IGNORE instructions in HIST. 6597 6598 If INSN is null, return the worse-case number of nops for any 6599 instruction. */ 6600 6601 static int 6602 nops_for_insn (int ignore, const struct mips_cl_insn *hist, 6603 const struct mips_cl_insn *insn) 6604 { 6605 int i, nops, tmp_nops; 6606 6607 nops = 0; 6608 for (i = ignore; i < MAX_DELAY_NOPS; i++) 6609 { 6610 tmp_nops = insns_between (hist + i, insn) - i; 6611 if (tmp_nops > nops) 6612 nops = tmp_nops; 6613 } 6614 6615 if (mips_fix_vr4130 && !mips_opts.micromips) 6616 { 6617 tmp_nops = nops_for_vr4130 (ignore, hist, insn); 6618 if (tmp_nops > nops) 6619 nops = tmp_nops; 6620 } 6621 6622 if (mips_fix_24k && !mips_opts.micromips) 6623 { 6624 tmp_nops = nops_for_24k (ignore, hist, insn); 6625 if (tmp_nops > nops) 6626 nops = tmp_nops; 6627 } 6628 6629 return nops; 6630 } 6631 6632 /* The variable arguments provide NUM_INSNS extra instructions that 6633 might be added to HIST. Return the largest number of nops that 6634 would be needed after the extended sequence, ignoring hazards 6635 in the first IGNORE instructions. */ 6636 6637 static int 6638 nops_for_sequence (int num_insns, int ignore, 6639 const struct mips_cl_insn *hist, ...) 6640 { 6641 va_list args; 6642 struct mips_cl_insn buffer[MAX_NOPS]; 6643 struct mips_cl_insn *cursor; 6644 int nops; 6645 6646 va_start (args, hist); 6647 cursor = buffer + num_insns; 6648 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); 6649 while (cursor > buffer) 6650 *--cursor = *va_arg (args, const struct mips_cl_insn *); 6651 6652 nops = nops_for_insn (ignore, buffer, NULL); 6653 va_end (args); 6654 return nops; 6655 } 6656 6657 /* Like nops_for_insn, but if INSN is a branch, take into account the 6658 worst-case delay for the branch target. */ 6659 6660 static int 6661 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, 6662 const struct mips_cl_insn *insn) 6663 { 6664 int nops, tmp_nops; 6665 6666 nops = nops_for_insn (ignore, hist, insn); 6667 if (delayed_branch_p (insn)) 6668 { 6669 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, 6670 hist, insn, get_delay_slot_nop (insn)); 6671 if (tmp_nops > nops) 6672 nops = tmp_nops; 6673 } 6674 else if (compact_branch_p (insn)) 6675 { 6676 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); 6677 if (tmp_nops > nops) 6678 nops = tmp_nops; 6679 } 6680 return nops; 6681 } 6682 6683 /* Fix NOP issue: Replace nops by "or at,at,zero". */ 6684 6685 static void 6686 fix_loongson2f_nop (struct mips_cl_insn * ip) 6687 { 6688 gas_assert (!HAVE_CODE_COMPRESSION); 6689 if (strcmp (ip->insn_mo->name, "nop") == 0) 6690 ip->insn_opcode = LOONGSON2F_NOP_INSN; 6691 } 6692 6693 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region 6694 jr target pc &= 'hffff_ffff_cfff_ffff. */ 6695 6696 static void 6697 fix_loongson2f_jump (struct mips_cl_insn * ip) 6698 { 6699 gas_assert (!HAVE_CODE_COMPRESSION); 6700 if (strcmp (ip->insn_mo->name, "j") == 0 6701 || strcmp (ip->insn_mo->name, "jr") == 0 6702 || strcmp (ip->insn_mo->name, "jalr") == 0) 6703 { 6704 int sreg; 6705 expressionS ep; 6706 6707 if (! mips_opts.at) 6708 return; 6709 6710 sreg = EXTRACT_OPERAND (0, RS, *ip); 6711 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) 6712 return; 6713 6714 ep.X_op = O_constant; 6715 ep.X_add_number = 0xcfff0000; 6716 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); 6717 ep.X_add_number = 0xffff; 6718 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); 6719 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); 6720 } 6721 } 6722 6723 static void 6724 fix_loongson2f (struct mips_cl_insn * ip) 6725 { 6726 if (mips_fix_loongson2f_nop) 6727 fix_loongson2f_nop (ip); 6728 6729 if (mips_fix_loongson2f_jump) 6730 fix_loongson2f_jump (ip); 6731 } 6732 6733 /* IP is a branch that has a delay slot, and we need to fill it 6734 automatically. Return true if we can do that by swapping IP 6735 with the previous instruction. 6736 ADDRESS_EXPR is an operand of the instruction to be used with 6737 RELOC_TYPE. */ 6738 6739 static bfd_boolean 6740 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, 6741 bfd_reloc_code_real_type *reloc_type) 6742 { 6743 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; 6744 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; 6745 unsigned int fpr_read, prev_fpr_write; 6746 6747 /* -O2 and above is required for this optimization. */ 6748 if (mips_optimize < 2) 6749 return FALSE; 6750 6751 /* If we have seen .set volatile or .set nomove, don't optimize. */ 6752 if (mips_opts.nomove) 6753 return FALSE; 6754 6755 /* We can't swap if the previous instruction's position is fixed. */ 6756 if (history[0].fixed_p) 6757 return FALSE; 6758 6759 /* If the previous previous insn was in a .set noreorder, we can't 6760 swap. Actually, the MIPS assembler will swap in this situation. 6761 However, gcc configured -with-gnu-as will generate code like 6762 6763 .set noreorder 6764 lw $4,XXX 6765 .set reorder 6766 INSN 6767 bne $4,$0,foo 6768 6769 in which we can not swap the bne and INSN. If gcc is not configured 6770 -with-gnu-as, it does not output the .set pseudo-ops. */ 6771 if (history[1].noreorder_p) 6772 return FALSE; 6773 6774 /* If the previous instruction had a fixup in mips16 mode, we can not swap. 6775 This means that the previous instruction was a 4-byte one anyhow. */ 6776 if (mips_opts.mips16 && history[0].fixp[0]) 6777 return FALSE; 6778 6779 /* If the branch is itself the target of a branch, we can not swap. 6780 We cheat on this; all we check for is whether there is a label on 6781 this instruction. If there are any branches to anything other than 6782 a label, users must use .set noreorder. */ 6783 if (seg_info (now_seg)->label_list) 6784 return FALSE; 6785 6786 /* If the previous instruction is in a variant frag other than this 6787 branch's one, we cannot do the swap. This does not apply to 6788 MIPS16 code, which uses variant frags for different purposes. */ 6789 if (!mips_opts.mips16 6790 && history[0].frag 6791 && history[0].frag->fr_type == rs_machine_dependent) 6792 return FALSE; 6793 6794 /* We do not swap with instructions that cannot architecturally 6795 be placed in a branch delay slot, such as SYNC or ERET. We 6796 also refrain from swapping with a trap instruction, since it 6797 complicates trap handlers to have the trap instruction be in 6798 a delay slot. */ 6799 prev_pinfo = history[0].insn_mo->pinfo; 6800 if (prev_pinfo & INSN_NO_DELAY_SLOT) 6801 return FALSE; 6802 6803 /* Check for conflicts between the branch and the instructions 6804 before the candidate delay slot. */ 6805 if (nops_for_insn (0, history + 1, ip) > 0) 6806 return FALSE; 6807 6808 /* Check for conflicts between the swapped sequence and the 6809 target of the branch. */ 6810 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) 6811 return FALSE; 6812 6813 /* If the branch reads a register that the previous 6814 instruction sets, we can not swap. */ 6815 gpr_read = gpr_read_mask (ip); 6816 prev_gpr_write = gpr_write_mask (&history[0]); 6817 if (gpr_read & prev_gpr_write) 6818 return FALSE; 6819 6820 fpr_read = fpr_read_mask (ip); 6821 prev_fpr_write = fpr_write_mask (&history[0]); 6822 if (fpr_read & prev_fpr_write) 6823 return FALSE; 6824 6825 /* If the branch writes a register that the previous 6826 instruction sets, we can not swap. */ 6827 gpr_write = gpr_write_mask (ip); 6828 if (gpr_write & prev_gpr_write) 6829 return FALSE; 6830 6831 /* If the branch writes a register that the previous 6832 instruction reads, we can not swap. */ 6833 prev_gpr_read = gpr_read_mask (&history[0]); 6834 if (gpr_write & prev_gpr_read) 6835 return FALSE; 6836 6837 /* If one instruction sets a condition code and the 6838 other one uses a condition code, we can not swap. */ 6839 pinfo = ip->insn_mo->pinfo; 6840 if ((pinfo & INSN_READ_COND_CODE) 6841 && (prev_pinfo & INSN_WRITE_COND_CODE)) 6842 return FALSE; 6843 if ((pinfo & INSN_WRITE_COND_CODE) 6844 && (prev_pinfo & INSN_READ_COND_CODE)) 6845 return FALSE; 6846 6847 /* If the previous instruction uses the PC, we can not swap. */ 6848 prev_pinfo2 = history[0].insn_mo->pinfo2; 6849 if (prev_pinfo2 & INSN2_READ_PC) 6850 return FALSE; 6851 6852 /* If the previous instruction has an incorrect size for a fixed 6853 branch delay slot in microMIPS mode, we cannot swap. */ 6854 pinfo2 = ip->insn_mo->pinfo2; 6855 if (mips_opts.micromips 6856 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) 6857 && insn_length (history) != 2) 6858 return FALSE; 6859 if (mips_opts.micromips 6860 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) 6861 && insn_length (history) != 4) 6862 return FALSE; 6863 6864 /* On R5900 short loops need to be fixed by inserting a nop in 6865 the branch delay slots. 6866 A short loop can be terminated too early. */ 6867 if (mips_opts.arch == CPU_R5900 6868 /* Check if instruction has a parameter, ignore "j $31". */ 6869 && (address_expr != NULL) 6870 /* Parameter must be 16 bit. */ 6871 && (*reloc_type == BFD_RELOC_16_PCREL_S2) 6872 /* Branch to same segment. */ 6873 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) 6874 /* Branch to same code fragment. */ 6875 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) 6876 /* Can only calculate branch offset if value is known. */ 6877 && symbol_constant_p(address_expr->X_add_symbol) 6878 /* Check if branch is really conditional. */ 6879 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 6880 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ 6881 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 6882 { 6883 int distance; 6884 /* Check if loop is shorter than 6 instructions including 6885 branch and delay slot. */ 6886 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); 6887 if (distance <= 20) 6888 { 6889 int i; 6890 int rv; 6891 6892 rv = FALSE; 6893 /* When the loop includes branches or jumps, 6894 it is not a short loop. */ 6895 for (i = 0; i < (distance / 4); i++) 6896 { 6897 if ((history[i].cleared_p) 6898 || delayed_branch_p(&history[i])) 6899 { 6900 rv = TRUE; 6901 break; 6902 } 6903 } 6904 if (rv == FALSE) 6905 { 6906 /* Insert nop after branch to fix short loop. */ 6907 return FALSE; 6908 } 6909 } 6910 } 6911 6912 return TRUE; 6913 } 6914 6915 /* Decide how we should add IP to the instruction stream. 6916 ADDRESS_EXPR is an operand of the instruction to be used with 6917 RELOC_TYPE. */ 6918 6919 static enum append_method 6920 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, 6921 bfd_reloc_code_real_type *reloc_type) 6922 { 6923 /* The relaxed version of a macro sequence must be inherently 6924 hazard-free. */ 6925 if (mips_relax.sequence == 2) 6926 return APPEND_ADD; 6927 6928 /* Convert a non-compact to compact branch/jump instruction. */ 6929 if (ISA_IS_R6 (mips_opts.isa) 6930 && (ip->insn_mo->pinfo2 & INSN2_CONVERTED_TO_COMPACT)) 6931 return APPEND_ADD_COMPACT; 6932 6933 /* We must not dabble with instructions in a ".set norerorder" block. */ 6934 if (mips_opts.noreorder) 6935 return APPEND_ADD; 6936 6937 /* Otherwise, it's our responsibility to fill branch delay slots. */ 6938 if (delayed_branch_p (ip)) 6939 { 6940 if (!branch_likely_p (ip) 6941 && can_swap_branch_p (ip, address_expr, reloc_type)) 6942 return APPEND_SWAP; 6943 6944 if (mips_opts.mips16 6945 && ISA_SUPPORTS_MIPS16E 6946 && gpr_read_mask (ip) != 0) 6947 return APPEND_ADD_COMPACT; 6948 6949 return APPEND_ADD_WITH_NOP; 6950 } 6951 6952 return APPEND_ADD; 6953 } 6954 6955 /* IP is a MIPS16 instruction whose opcode we have just changed. 6956 Point IP->insn_mo to the new opcode's definition. */ 6957 6958 static void 6959 find_altered_mips16_opcode (struct mips_cl_insn *ip) 6960 { 6961 const struct mips_opcode *mo, *end; 6962 6963 end = &mips16_opcodes[bfd_mips16_num_opcodes]; 6964 for (mo = ip->insn_mo; mo < end; mo++) 6965 if ((ip->insn_opcode & mo->mask) == mo->match) 6966 { 6967 ip->insn_mo = mo; 6968 return; 6969 } 6970 abort (); 6971 } 6972 6973 /* For microMIPS macros, we need to generate a local number label 6974 as the target of branches. */ 6975 #define MICROMIPS_LABEL_CHAR '\037' 6976 static unsigned long micromips_target_label; 6977 static char micromips_target_name[32]; 6978 6979 static char * 6980 micromips_label_name (void) 6981 { 6982 char *p = micromips_target_name; 6983 char symbol_name_temporary[24]; 6984 unsigned long l; 6985 int i; 6986 6987 if (*p) 6988 return p; 6989 6990 i = 0; 6991 l = micromips_target_label; 6992 #ifdef LOCAL_LABEL_PREFIX 6993 *p++ = LOCAL_LABEL_PREFIX; 6994 #endif 6995 *p++ = 'L'; 6996 *p++ = MICROMIPS_LABEL_CHAR; 6997 do 6998 { 6999 symbol_name_temporary[i++] = l % 10 + '0'; 7000 l /= 10; 7001 } 7002 while (l != 0); 7003 while (i > 0) 7004 *p++ = symbol_name_temporary[--i]; 7005 *p = '\0'; 7006 7007 return micromips_target_name; 7008 } 7009 7010 static void 7011 micromips_label_expr (expressionS *label_expr) 7012 { 7013 label_expr->X_op = O_symbol; 7014 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); 7015 label_expr->X_add_number = 0; 7016 } 7017 7018 static void 7019 micromips_label_inc (void) 7020 { 7021 micromips_target_label++; 7022 *micromips_target_name = '\0'; 7023 } 7024 7025 static void 7026 micromips_add_label (void) 7027 { 7028 symbolS *s; 7029 7030 s = colon (micromips_label_name ()); 7031 micromips_label_inc (); 7032 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); 7033 } 7034 7035 /* If assembling microMIPS code, then return the microMIPS reloc 7036 corresponding to the requested one if any. Otherwise return 7037 the reloc unchanged. */ 7038 7039 static bfd_reloc_code_real_type 7040 micromips_map_reloc (bfd_reloc_code_real_type reloc) 7041 { 7042 static const bfd_reloc_code_real_type relocs[][2] = 7043 { 7044 /* Keep sorted incrementally by the left-hand key. */ 7045 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, 7046 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, 7047 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, 7048 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, 7049 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, 7050 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, 7051 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, 7052 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, 7053 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, 7054 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, 7055 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, 7056 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, 7057 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, 7058 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, 7059 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, 7060 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, 7061 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, 7062 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, 7063 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, 7064 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, 7065 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, 7066 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, 7067 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, 7068 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, 7069 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, 7070 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, 7071 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } 7072 }; 7073 bfd_reloc_code_real_type r; 7074 size_t i; 7075 7076 if (!mips_opts.micromips) 7077 return reloc; 7078 for (i = 0; i < ARRAY_SIZE (relocs); i++) 7079 { 7080 r = relocs[i][0]; 7081 if (r > reloc) 7082 return reloc; 7083 if (r == reloc) 7084 return relocs[i][1]; 7085 } 7086 return reloc; 7087 } 7088 7089 /* Try to resolve relocation RELOC against constant OPERAND at assembly time. 7090 Return true on success, storing the resolved value in RESULT. */ 7091 7092 static bfd_boolean 7093 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, 7094 offsetT *result) 7095 { 7096 switch (reloc) 7097 { 7098 case BFD_RELOC_MIPS_HIGHEST: 7099 case BFD_RELOC_MICROMIPS_HIGHEST: 7100 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; 7101 return TRUE; 7102 7103 case BFD_RELOC_MIPS_HIGHER: 7104 case BFD_RELOC_MICROMIPS_HIGHER: 7105 *result = ((operand + 0x80008000ull) >> 32) & 0xffff; 7106 return TRUE; 7107 7108 case BFD_RELOC_HI16_S: 7109 case BFD_RELOC_MICROMIPS_HI16_S: 7110 case BFD_RELOC_MIPS16_HI16_S: 7111 *result = ((operand + 0x8000) >> 16) & 0xffff; 7112 return TRUE; 7113 7114 case BFD_RELOC_HI16: 7115 case BFD_RELOC_MICROMIPS_HI16: 7116 case BFD_RELOC_MIPS16_HI16: 7117 *result = (operand >> 16) & 0xffff; 7118 return TRUE; 7119 7120 case BFD_RELOC_LO16: 7121 case BFD_RELOC_MICROMIPS_LO16: 7122 case BFD_RELOC_MIPS16_LO16: 7123 *result = operand & 0xffff; 7124 return TRUE; 7125 7126 case BFD_RELOC_UNUSED: 7127 *result = operand; 7128 return TRUE; 7129 7130 default: 7131 return FALSE; 7132 } 7133 } 7134 7135 /* Output an instruction. IP is the instruction information. 7136 ADDRESS_EXPR is an operand of the instruction to be used with 7137 RELOC_TYPE. EXPANSIONP is true if the instruction is part of 7138 a macro expansion. */ 7139 7140 static void 7141 append_insn (struct mips_cl_insn *ip, expressionS *address_expr, 7142 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) 7143 { 7144 unsigned long prev_pinfo2, pinfo; 7145 bfd_boolean relaxed_branch = FALSE; 7146 enum append_method method; 7147 bfd_boolean relax32; 7148 int branch_disp; 7149 7150 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) 7151 fix_loongson2f (ip); 7152 7153 file_ase_mips16 |= mips_opts.mips16; 7154 file_ase_micromips |= mips_opts.micromips; 7155 7156 prev_pinfo2 = history[0].insn_mo->pinfo2; 7157 pinfo = ip->insn_mo->pinfo; 7158 7159 if (mips_opts.micromips 7160 && !expansionp 7161 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 7162 && micromips_insn_length (ip->insn_mo) != 2) 7163 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 7164 && micromips_insn_length (ip->insn_mo) != 4))) 7165 as_warn (_("wrong size instruction in a %u-bit branch delay slot"), 7166 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); 7167 7168 if (address_expr == NULL) 7169 ip->complete_p = 1; 7170 else if (reloc_type[0] <= BFD_RELOC_UNUSED 7171 && reloc_type[1] == BFD_RELOC_UNUSED 7172 && reloc_type[2] == BFD_RELOC_UNUSED 7173 && address_expr->X_op == O_constant) 7174 { 7175 switch (*reloc_type) 7176 { 7177 case BFD_RELOC_MIPS_JMP: 7178 { 7179 int shift; 7180 7181 shift = mips_opts.micromips ? 1 : 2; 7182 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7183 as_bad (_("jump to misaligned address (0x%lx)"), 7184 (unsigned long) address_expr->X_add_number); 7185 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7186 & 0x3ffffff); 7187 ip->complete_p = 1; 7188 } 7189 break; 7190 7191 case BFD_RELOC_MIPS16_JMP: 7192 if ((address_expr->X_add_number & 3) != 0) 7193 as_bad (_("jump to misaligned address (0x%lx)"), 7194 (unsigned long) address_expr->X_add_number); 7195 ip->insn_opcode |= 7196 (((address_expr->X_add_number & 0x7c0000) << 3) 7197 | ((address_expr->X_add_number & 0xf800000) >> 7) 7198 | ((address_expr->X_add_number & 0x3fffc) >> 2)); 7199 ip->complete_p = 1; 7200 break; 7201 7202 case BFD_RELOC_16_PCREL_S2: 7203 { 7204 int shift; 7205 7206 shift = mips_opts.micromips ? 1 : 2; 7207 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7208 as_bad (_("branch to misaligned address (0x%lx)"), 7209 (unsigned long) address_expr->X_add_number); 7210 if (!mips_relax_branch) 7211 { 7212 if ((address_expr->X_add_number + (1 << (shift + 15))) 7213 & ~((1 << (shift + 16)) - 1)) 7214 as_bad (_("branch address range overflow (0x%lx)"), 7215 (unsigned long) address_expr->X_add_number); 7216 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7217 & 0xffff); 7218 } 7219 } 7220 break; 7221 7222 case BFD_RELOC_MIPS_21_PCREL_S2: 7223 { 7224 int shift; 7225 7226 shift = 2; 7227 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7228 as_bad (_("branch to misaligned address (0x%lx)"), 7229 (unsigned long) address_expr->X_add_number); 7230 if ((address_expr->X_add_number + (1 << (shift + 20))) 7231 & ~((1 << (shift + 21)) - 1)) 7232 as_bad (_("branch address range overflow (0x%lx)"), 7233 (unsigned long) address_expr->X_add_number); 7234 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7235 & 0x1fffff); 7236 } 7237 break; 7238 7239 case BFD_RELOC_MIPS_26_PCREL_S2: 7240 { 7241 int shift; 7242 7243 shift = 2; 7244 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7245 as_bad (_("branch to misaligned address (0x%lx)"), 7246 (unsigned long) address_expr->X_add_number); 7247 if ((address_expr->X_add_number + (1 << (shift + 25))) 7248 & ~((1 << (shift + 26)) - 1)) 7249 as_bad (_("branch address range overflow (0x%lx)"), 7250 (unsigned long) address_expr->X_add_number); 7251 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7252 & 0x3ffffff); 7253 } 7254 break; 7255 7256 default: 7257 { 7258 offsetT value; 7259 7260 if (calculate_reloc (*reloc_type, address_expr->X_add_number, 7261 &value)) 7262 { 7263 ip->insn_opcode |= value & 0xffff; 7264 ip->complete_p = 1; 7265 } 7266 } 7267 break; 7268 } 7269 } 7270 7271 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 7272 { 7273 /* There are a lot of optimizations we could do that we don't. 7274 In particular, we do not, in general, reorder instructions. 7275 If you use gcc with optimization, it will reorder 7276 instructions and generally do much more optimization then we 7277 do here; repeating all that work in the assembler would only 7278 benefit hand written assembly code, and does not seem worth 7279 it. */ 7280 int nops = (mips_optimize == 0 7281 ? nops_for_insn (0, history, NULL) 7282 : nops_for_insn_or_target (0, history, ip)); 7283 if (nops > 0) 7284 { 7285 fragS *old_frag; 7286 unsigned long old_frag_offset; 7287 int i; 7288 7289 old_frag = frag_now; 7290 old_frag_offset = frag_now_fix (); 7291 7292 for (i = 0; i < nops; i++) 7293 add_fixed_insn (NOP_INSN); 7294 insert_into_history (0, nops, NOP_INSN); 7295 7296 if (listing) 7297 { 7298 listing_prev_line (); 7299 /* We may be at the start of a variant frag. In case we 7300 are, make sure there is enough space for the frag 7301 after the frags created by listing_prev_line. The 7302 argument to frag_grow here must be at least as large 7303 as the argument to all other calls to frag_grow in 7304 this file. We don't have to worry about being in the 7305 middle of a variant frag, because the variants insert 7306 all needed nop instructions themselves. */ 7307 frag_grow (40); 7308 } 7309 7310 mips_move_text_labels (); 7311 7312 #ifndef NO_ECOFF_DEBUGGING 7313 if (ECOFF_DEBUGGING) 7314 ecoff_fix_loc (old_frag, old_frag_offset); 7315 #endif 7316 } 7317 } 7318 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) 7319 { 7320 int nops; 7321 7322 /* Work out how many nops in prev_nop_frag are needed by IP, 7323 ignoring hazards generated by the first prev_nop_frag_since 7324 instructions. */ 7325 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); 7326 gas_assert (nops <= prev_nop_frag_holds); 7327 7328 /* Enforce NOPS as a minimum. */ 7329 if (nops > prev_nop_frag_required) 7330 prev_nop_frag_required = nops; 7331 7332 if (prev_nop_frag_holds == prev_nop_frag_required) 7333 { 7334 /* Settle for the current number of nops. Update the history 7335 accordingly (for the benefit of any future .set reorder code). */ 7336 prev_nop_frag = NULL; 7337 insert_into_history (prev_nop_frag_since, 7338 prev_nop_frag_holds, NOP_INSN); 7339 } 7340 else 7341 { 7342 /* Allow this instruction to replace one of the nops that was 7343 tentatively added to prev_nop_frag. */ 7344 prev_nop_frag->fr_fix -= NOP_INSN_SIZE; 7345 prev_nop_frag_holds--; 7346 prev_nop_frag_since++; 7347 } 7348 } 7349 7350 method = get_append_method (ip, address_expr, reloc_type); 7351 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; 7352 7353 dwarf2_emit_insn (0); 7354 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, 7355 so "move" the instruction address accordingly. 7356 7357 Also, it doesn't seem appropriate for the assembler to reorder .loc 7358 entries. If this instruction is a branch that we are going to swap 7359 with the previous instruction, the two instructions should be 7360 treated as a unit, and the debug information for both instructions 7361 should refer to the start of the branch sequence. Using the 7362 current position is certainly wrong when swapping a 32-bit branch 7363 and a 16-bit delay slot, since the current position would then be 7364 in the middle of a branch. */ 7365 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); 7366 7367 relax32 = (mips_relax_branch 7368 /* Don't try branch relaxation within .set nomacro, or within 7369 .set noat if we use $at for PIC computations. If it turns 7370 out that the branch was out-of-range, we'll get an error. */ 7371 && !mips_opts.warn_about_macros 7372 && (mips_opts.at || mips_pic == NO_PIC) 7373 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F 7374 as they have no complementing branches. */ 7375 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); 7376 7377 if (!HAVE_CODE_COMPRESSION 7378 && address_expr 7379 && relax32 7380 && *reloc_type == BFD_RELOC_16_PCREL_S2 7381 && delayed_branch_p (ip)) 7382 { 7383 relaxed_branch = TRUE; 7384 add_relaxed_insn (ip, (relaxed_branch_length 7385 (NULL, NULL, 7386 uncond_branch_p (ip) ? -1 7387 : branch_likely_p (ip) ? 1 7388 : 0)), 4, 7389 RELAX_BRANCH_ENCODE 7390 (AT, 7391 uncond_branch_p (ip), 7392 branch_likely_p (ip), 7393 pinfo & INSN_WRITE_GPR_31, 7394 0), 7395 address_expr->X_add_symbol, 7396 address_expr->X_add_number); 7397 *reloc_type = BFD_RELOC_UNUSED; 7398 } 7399 else if (mips_opts.micromips 7400 && address_expr 7401 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) 7402 || *reloc_type > BFD_RELOC_UNUSED) 7403 && (delayed_branch_p (ip) || compact_branch_p (ip)) 7404 /* Don't try branch relaxation when users specify 7405 16-bit/32-bit instructions. */ 7406 && !forced_insn_length) 7407 { 7408 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; 7409 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; 7410 int uncond = uncond_branch_p (ip) ? -1 : 0; 7411 int compact = compact_branch_p (ip); 7412 int al = pinfo & INSN_WRITE_GPR_31; 7413 int length32; 7414 7415 gas_assert (address_expr != NULL); 7416 gas_assert (!mips_relax.sequence); 7417 7418 relaxed_branch = TRUE; 7419 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); 7420 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, 7421 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, 7422 relax32, 0, 0), 7423 address_expr->X_add_symbol, 7424 address_expr->X_add_number); 7425 *reloc_type = BFD_RELOC_UNUSED; 7426 } 7427 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) 7428 { 7429 /* We need to set up a variant frag. */ 7430 gas_assert (address_expr != NULL); 7431 add_relaxed_insn (ip, 4, 0, 7432 RELAX_MIPS16_ENCODE 7433 (*reloc_type - BFD_RELOC_UNUSED, 7434 forced_insn_length == 2, forced_insn_length == 4, 7435 delayed_branch_p (&history[0]), 7436 history[0].mips16_absolute_jump_p), 7437 make_expr_symbol (address_expr), 0); 7438 } 7439 else if (mips_opts.mips16 && insn_length (ip) == 2) 7440 { 7441 if (!delayed_branch_p (ip)) 7442 /* Make sure there is enough room to swap this instruction with 7443 a following jump instruction. */ 7444 frag_grow (6); 7445 add_fixed_insn (ip); 7446 } 7447 else 7448 { 7449 if (mips_opts.mips16 7450 && mips_opts.noreorder 7451 && delayed_branch_p (&history[0])) 7452 as_warn (_("extended instruction in delay slot")); 7453 7454 if (mips_relax.sequence) 7455 { 7456 /* If we've reached the end of this frag, turn it into a variant 7457 frag and record the information for the instructions we've 7458 written so far. */ 7459 if (frag_room () < 4) 7460 relax_close_frag (); 7461 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); 7462 } 7463 7464 if (mips_relax.sequence != 2) 7465 { 7466 if (mips_macro_warning.first_insn_sizes[0] == 0) 7467 mips_macro_warning.first_insn_sizes[0] = insn_length (ip); 7468 mips_macro_warning.sizes[0] += insn_length (ip); 7469 mips_macro_warning.insns[0]++; 7470 } 7471 if (mips_relax.sequence != 1) 7472 { 7473 if (mips_macro_warning.first_insn_sizes[1] == 0) 7474 mips_macro_warning.first_insn_sizes[1] = insn_length (ip); 7475 mips_macro_warning.sizes[1] += insn_length (ip); 7476 mips_macro_warning.insns[1]++; 7477 } 7478 7479 if (mips_opts.mips16) 7480 { 7481 ip->fixed_p = 1; 7482 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); 7483 } 7484 add_fixed_insn (ip); 7485 } 7486 7487 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) 7488 { 7489 bfd_reloc_code_real_type final_type[3]; 7490 reloc_howto_type *howto0; 7491 reloc_howto_type *howto; 7492 int i; 7493 7494 /* Perform any necessary conversion to microMIPS relocations 7495 and find out how many relocations there actually are. */ 7496 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) 7497 final_type[i] = micromips_map_reloc (reloc_type[i]); 7498 7499 /* In a compound relocation, it is the final (outermost) 7500 operator that determines the relocated field. */ 7501 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); 7502 if (!howto) 7503 abort (); 7504 7505 if (i > 1) 7506 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); 7507 ip->fixp[0] = fix_new_exp (ip->frag, ip->where, 7508 bfd_get_reloc_size (howto), 7509 address_expr, 7510 howto0 && howto0->pc_relative, 7511 final_type[0]); 7512 7513 /* Tag symbols that have a R_MIPS16_26 relocation against them. */ 7514 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) 7515 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; 7516 7517 /* These relocations can have an addend that won't fit in 7518 4 octets for 64bit assembly. */ 7519 if (GPR_SIZE == 64 7520 && ! howto->partial_inplace 7521 && (reloc_type[0] == BFD_RELOC_16 7522 || reloc_type[0] == BFD_RELOC_32 7523 || reloc_type[0] == BFD_RELOC_MIPS_JMP 7524 || reloc_type[0] == BFD_RELOC_GPREL16 7525 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL 7526 || reloc_type[0] == BFD_RELOC_GPREL32 7527 || reloc_type[0] == BFD_RELOC_64 7528 || reloc_type[0] == BFD_RELOC_CTOR 7529 || reloc_type[0] == BFD_RELOC_MIPS_SUB 7530 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST 7531 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER 7532 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP 7533 || reloc_type[0] == BFD_RELOC_MIPS_REL16 7534 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT 7535 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL 7536 || hi16_reloc_p (reloc_type[0]) 7537 || lo16_reloc_p (reloc_type[0]))) 7538 ip->fixp[0]->fx_no_overflow = 1; 7539 7540 /* These relocations can have an addend that won't fit in 2 octets. */ 7541 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 7542 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) 7543 ip->fixp[0]->fx_no_overflow = 1; 7544 7545 if (mips_relax.sequence) 7546 { 7547 if (mips_relax.first_fixup == 0) 7548 mips_relax.first_fixup = ip->fixp[0]; 7549 } 7550 else if (reloc_needs_lo_p (*reloc_type)) 7551 { 7552 struct mips_hi_fixup *hi_fixup; 7553 7554 /* Reuse the last entry if it already has a matching %lo. */ 7555 hi_fixup = mips_hi_fixup_list; 7556 if (hi_fixup == 0 7557 || !fixup_has_matching_lo_p (hi_fixup->fixp)) 7558 { 7559 hi_fixup = ((struct mips_hi_fixup *) 7560 xmalloc (sizeof (struct mips_hi_fixup))); 7561 hi_fixup->next = mips_hi_fixup_list; 7562 mips_hi_fixup_list = hi_fixup; 7563 } 7564 hi_fixup->fixp = ip->fixp[0]; 7565 hi_fixup->seg = now_seg; 7566 } 7567 7568 /* Add fixups for the second and third relocations, if given. 7569 Note that the ABI allows the second relocation to be 7570 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the 7571 moment we only use RSS_UNDEF, but we could add support 7572 for the others if it ever becomes necessary. */ 7573 for (i = 1; i < 3; i++) 7574 if (reloc_type[i] != BFD_RELOC_UNUSED) 7575 { 7576 ip->fixp[i] = fix_new (ip->frag, ip->where, 7577 ip->fixp[0]->fx_size, NULL, 0, 7578 FALSE, final_type[i]); 7579 7580 /* Use fx_tcbit to mark compound relocs. */ 7581 ip->fixp[0]->fx_tcbit = 1; 7582 ip->fixp[i]->fx_tcbit = 1; 7583 } 7584 } 7585 install_insn (ip); 7586 7587 /* Update the register mask information. */ 7588 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); 7589 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); 7590 7591 switch (method) 7592 { 7593 case APPEND_ADD: 7594 insert_into_history (0, 1, ip); 7595 break; 7596 7597 case APPEND_ADD_WITH_NOP: 7598 { 7599 struct mips_cl_insn *nop; 7600 7601 insert_into_history (0, 1, ip); 7602 nop = get_delay_slot_nop (ip); 7603 add_fixed_insn (nop); 7604 insert_into_history (0, 1, nop); 7605 if (mips_relax.sequence) 7606 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); 7607 } 7608 break; 7609 7610 case APPEND_ADD_COMPACT: 7611 gas_assert(mips_opts.mips16 || ISA_IS_R6 (mips_opts.isa)); 7612 if (mips_opts.mips16) 7613 { 7614 /* Convert MIPS16 jr/jalr into a "compact" jump. */ 7615 ip->insn_opcode |= 0x0080; 7616 find_altered_mips16_opcode (ip); 7617 install_insn (ip); 7618 insert_into_history (0, 1, ip); 7619 } 7620 else 7621 { 7622 install_insn (ip); 7623 insert_into_history (0, 1, ip); 7624 } 7625 break; 7626 7627 case APPEND_SWAP: 7628 { 7629 struct mips_cl_insn delay = history[0]; 7630 if (mips_opts.mips16) 7631 { 7632 know (delay.frag == ip->frag); 7633 move_insn (ip, delay.frag, delay.where); 7634 move_insn (&delay, ip->frag, ip->where + insn_length (ip)); 7635 } 7636 else if (relaxed_branch || delay.frag != ip->frag) 7637 { 7638 /* Add the delay slot instruction to the end of the 7639 current frag and shrink the fixed part of the 7640 original frag. If the branch occupies the tail of 7641 the latter, move it backwards to cover the gap. */ 7642 delay.frag->fr_fix -= branch_disp; 7643 if (delay.frag == ip->frag) 7644 move_insn (ip, ip->frag, ip->where - branch_disp); 7645 add_fixed_insn (&delay); 7646 } 7647 else 7648 { 7649 move_insn (&delay, ip->frag, 7650 ip->where - branch_disp + insn_length (ip)); 7651 move_insn (ip, history[0].frag, history[0].where); 7652 } 7653 history[0] = *ip; 7654 delay.fixed_p = 1; 7655 insert_into_history (0, 1, &delay); 7656 } 7657 break; 7658 } 7659 7660 /* If we have just completed an unconditional branch, clear the history. */ 7661 if (((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) 7662 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) 7663 && !(history[0].insn_mo->pinfo2 & INSN2_CONVERTED_TO_COMPACT)) 7664 { 7665 unsigned int i; 7666 7667 mips_no_prev_insn (); 7668 7669 for (i = 0; i < ARRAY_SIZE (history); i++) 7670 history[i].cleared_p = 1; 7671 } 7672 7673 /* We need to emit a label at the end of branch-likely macros. */ 7674 if (emit_branch_likely_macro) 7675 { 7676 emit_branch_likely_macro = FALSE; 7677 micromips_add_label (); 7678 } 7679 7680 /* We just output an insn, so the next one doesn't have a label. */ 7681 mips_clear_insn_labels (); 7682 } 7683 7684 /* Forget that there was any previous instruction or label. 7685 When BRANCH is true, the branch history is also flushed. */ 7686 7687 static void 7688 mips_no_prev_insn (void) 7689 { 7690 prev_nop_frag = NULL; 7691 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); 7692 mips_clear_insn_labels (); 7693 } 7694 7695 /* This function must be called before we emit something other than 7696 instructions. It is like mips_no_prev_insn except that it inserts 7697 any NOPS that might be needed by previous instructions. */ 7698 7699 void 7700 mips_emit_delays (void) 7701 { 7702 if (! mips_opts.noreorder) 7703 { 7704 int nops = nops_for_insn (0, history, NULL); 7705 if (nops > 0) 7706 { 7707 while (nops-- > 0) 7708 add_fixed_insn (NOP_INSN); 7709 mips_move_text_labels (); 7710 } 7711 } 7712 mips_no_prev_insn (); 7713 } 7714 7715 /* Start a (possibly nested) noreorder block. */ 7716 7717 static void 7718 start_noreorder (void) 7719 { 7720 if (mips_opts.noreorder == 0) 7721 { 7722 unsigned int i; 7723 int nops; 7724 7725 /* None of the instructions before the .set noreorder can be moved. */ 7726 for (i = 0; i < ARRAY_SIZE (history); i++) 7727 history[i].fixed_p = 1; 7728 7729 /* Insert any nops that might be needed between the .set noreorder 7730 block and the previous instructions. We will later remove any 7731 nops that turn out not to be needed. */ 7732 nops = nops_for_insn (0, history, NULL); 7733 if (nops > 0) 7734 { 7735 if (mips_optimize != 0) 7736 { 7737 /* Record the frag which holds the nop instructions, so 7738 that we can remove them if we don't need them. */ 7739 frag_grow (nops * NOP_INSN_SIZE); 7740 prev_nop_frag = frag_now; 7741 prev_nop_frag_holds = nops; 7742 prev_nop_frag_required = 0; 7743 prev_nop_frag_since = 0; 7744 } 7745 7746 for (; nops > 0; --nops) 7747 add_fixed_insn (NOP_INSN); 7748 7749 /* Move on to a new frag, so that it is safe to simply 7750 decrease the size of prev_nop_frag. */ 7751 frag_wane (frag_now); 7752 frag_new (0); 7753 mips_move_text_labels (); 7754 } 7755 mips_mark_labels (); 7756 mips_clear_insn_labels (); 7757 } 7758 mips_opts.noreorder++; 7759 mips_any_noreorder = 1; 7760 } 7761 7762 /* End a nested noreorder block. */ 7763 7764 static void 7765 end_noreorder (void) 7766 { 7767 mips_opts.noreorder--; 7768 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) 7769 { 7770 /* Commit to inserting prev_nop_frag_required nops and go back to 7771 handling nop insertion the .set reorder way. */ 7772 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) 7773 * NOP_INSN_SIZE); 7774 insert_into_history (prev_nop_frag_since, 7775 prev_nop_frag_required, NOP_INSN); 7776 prev_nop_frag = NULL; 7777 } 7778 } 7779 7780 /* Sign-extend 32-bit mode constants that have bit 31 set and all 7781 higher bits unset. */ 7782 7783 static void 7784 normalize_constant_expr (expressionS *ex) 7785 { 7786 if (ex->X_op == O_constant 7787 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 7788 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 7789 - 0x80000000); 7790 } 7791 7792 /* Sign-extend 32-bit mode address offsets that have bit 31 set and 7793 all higher bits unset. */ 7794 7795 static void 7796 normalize_address_expr (expressionS *ex) 7797 { 7798 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) 7799 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) 7800 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 7801 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 7802 - 0x80000000); 7803 } 7804 7805 /* Try to match TOKENS against OPCODE, storing the result in INSN. 7806 Return true if the match was successful. 7807 7808 OPCODE_EXTRA is a value that should be ORed into the opcode 7809 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if 7810 there are more alternatives after OPCODE and SOFT_MATCH is 7811 as for mips_arg_info. */ 7812 7813 static bfd_boolean 7814 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 7815 struct mips_operand_token *tokens, unsigned int opcode_extra, 7816 bfd_boolean lax_match, bfd_boolean complete_p) 7817 { 7818 const char *args; 7819 struct mips_arg_info arg; 7820 const struct mips_operand *operand; 7821 char c; 7822 7823 imm_expr.X_op = O_absent; 7824 offset_expr.X_op = O_absent; 7825 offset_reloc[0] = BFD_RELOC_UNUSED; 7826 offset_reloc[1] = BFD_RELOC_UNUSED; 7827 offset_reloc[2] = BFD_RELOC_UNUSED; 7828 7829 create_insn (insn, opcode); 7830 /* When no opcode suffix is specified, assume ".xyzw". */ 7831 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) 7832 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; 7833 else 7834 insn->insn_opcode |= opcode_extra; 7835 memset (&arg, 0, sizeof (arg)); 7836 arg.insn = insn; 7837 arg.token = tokens; 7838 arg.argnum = 1; 7839 arg.last_regno = ILLEGAL_REG; 7840 arg.dest_regno = ILLEGAL_REG; 7841 arg.lax_match = lax_match; 7842 for (args = opcode->args;; ++args) 7843 { 7844 if (arg.token->type == OT_END) 7845 { 7846 /* Handle unary instructions in which only one operand is given. 7847 The source is then the same as the destination. */ 7848 if (arg.opnum == 1 && *args == ',') 7849 { 7850 operand = (mips_opts.micromips 7851 ? decode_micromips_operand (args + 1) 7852 : decode_mips_operand (args + 1)); 7853 if (operand && mips_optional_operand_p (operand)) 7854 { 7855 arg.token = tokens; 7856 arg.argnum = 1; 7857 continue; 7858 } 7859 } 7860 7861 /* Treat elided base registers as $0. */ 7862 if (strcmp (args, "(b)") == 0) 7863 args += 3; 7864 7865 if (args[0] == '+') 7866 switch (args[1]) 7867 { 7868 case 'K': 7869 case 'N': 7870 /* The register suffix is optional. */ 7871 args += 2; 7872 break; 7873 } 7874 7875 /* Fail the match if there were too few operands. */ 7876 if (*args) 7877 return FALSE; 7878 7879 /* Successful match. */ 7880 if (!complete_p) 7881 return TRUE; 7882 clear_insn_error (); 7883 if (arg.dest_regno == arg.last_regno 7884 && strncmp (insn->insn_mo->name, "jalr", 4) == 0) 7885 { 7886 if (arg.opnum == 2) 7887 set_insn_error 7888 (0, _("source and destination must be different")); 7889 else if (arg.last_regno == 31) 7890 set_insn_error 7891 (0, _("a destination register must be supplied")); 7892 } 7893 else if (arg.last_regno == 31 7894 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 7895 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) 7896 set_insn_error (0, _("the source register must not be $31")); 7897 check_completed_insn (&arg); 7898 return TRUE; 7899 } 7900 7901 /* Fail the match if the line has too many operands. */ 7902 if (*args == 0) 7903 return FALSE; 7904 7905 /* Handle characters that need to match exactly. */ 7906 if (*args == '(' || *args == ')' || *args == ',') 7907 { 7908 if (match_char (&arg, *args)) 7909 continue; 7910 return FALSE; 7911 } 7912 if (*args == '#') 7913 { 7914 ++args; 7915 if (arg.token->type == OT_DOUBLE_CHAR 7916 && arg.token->u.ch == *args) 7917 { 7918 ++arg.token; 7919 continue; 7920 } 7921 return FALSE; 7922 } 7923 7924 /* Handle special macro operands. Work out the properties of 7925 other operands. */ 7926 arg.opnum += 1; 7927 switch (*args) 7928 { 7929 case '-': 7930 switch (args[1]) 7931 { 7932 case 'A': 7933 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; 7934 break; 7935 7936 case 'B': 7937 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; 7938 break; 7939 } 7940 break; 7941 7942 case '+': 7943 switch (args[1]) 7944 { 7945 case 'i': 7946 *offset_reloc = BFD_RELOC_MIPS_JMP; 7947 break; 7948 7949 case '\'': 7950 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; 7951 break; 7952 7953 case '\"': 7954 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; 7955 break; 7956 } 7957 break; 7958 7959 case 'I': 7960 if (!match_const_int (&arg, &imm_expr.X_add_number)) 7961 return FALSE; 7962 imm_expr.X_op = O_constant; 7963 if (GPR_SIZE == 32) 7964 normalize_constant_expr (&imm_expr); 7965 continue; 7966 7967 case 'A': 7968 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 7969 { 7970 /* Assume that the offset has been elided and that what 7971 we saw was a base register. The match will fail later 7972 if that assumption turns out to be wrong. */ 7973 offset_expr.X_op = O_constant; 7974 offset_expr.X_add_number = 0; 7975 } 7976 else 7977 { 7978 if (!match_expression (&arg, &offset_expr, offset_reloc)) 7979 return FALSE; 7980 normalize_address_expr (&offset_expr); 7981 } 7982 continue; 7983 7984 case 'F': 7985 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7986 8, TRUE)) 7987 return FALSE; 7988 continue; 7989 7990 case 'L': 7991 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7992 8, FALSE)) 7993 return FALSE; 7994 continue; 7995 7996 case 'f': 7997 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 7998 4, TRUE)) 7999 return FALSE; 8000 continue; 8001 8002 case 'l': 8003 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8004 4, FALSE)) 8005 return FALSE; 8006 continue; 8007 8008 case 'p': 8009 *offset_reloc = BFD_RELOC_16_PCREL_S2; 8010 break; 8011 8012 case 'a': 8013 *offset_reloc = BFD_RELOC_MIPS_JMP; 8014 break; 8015 8016 case 'm': 8017 gas_assert (mips_opts.micromips); 8018 c = args[1]; 8019 switch (c) 8020 { 8021 case 'D': 8022 case 'E': 8023 if (!forced_insn_length) 8024 *offset_reloc = (int) BFD_RELOC_UNUSED + c; 8025 else if (c == 'D') 8026 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; 8027 else 8028 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; 8029 break; 8030 } 8031 break; 8032 } 8033 8034 operand = (mips_opts.micromips 8035 ? decode_micromips_operand (args) 8036 : decode_mips_operand (args)); 8037 if (!operand) 8038 abort (); 8039 8040 /* Skip prefixes. */ 8041 if (*args == '+' || *args == 'm' || *args == '-' || *args == '`') 8042 args++; 8043 8044 if (mips_optional_operand_p (operand) 8045 && args[1] == ',' 8046 && (arg.token[0].type != OT_REG 8047 || arg.token[1].type == OT_END)) 8048 { 8049 /* Assume that the register has been elided and is the 8050 same as the first operand. */ 8051 arg.token = tokens; 8052 arg.argnum = 1; 8053 } 8054 8055 if (!match_operand (&arg, operand)) 8056 return FALSE; 8057 } 8058 } 8059 8060 /* Like match_insn, but for MIPS16. */ 8061 8062 static bfd_boolean 8063 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 8064 struct mips_operand_token *tokens) 8065 { 8066 const char *args; 8067 const struct mips_operand *operand; 8068 const struct mips_operand *ext_operand; 8069 struct mips_arg_info arg; 8070 int relax_char; 8071 8072 create_insn (insn, opcode); 8073 imm_expr.X_op = O_absent; 8074 offset_expr.X_op = O_absent; 8075 offset_reloc[0] = BFD_RELOC_UNUSED; 8076 offset_reloc[1] = BFD_RELOC_UNUSED; 8077 offset_reloc[2] = BFD_RELOC_UNUSED; 8078 relax_char = 0; 8079 8080 memset (&arg, 0, sizeof (arg)); 8081 arg.insn = insn; 8082 arg.token = tokens; 8083 arg.argnum = 1; 8084 arg.last_regno = ILLEGAL_REG; 8085 arg.dest_regno = ILLEGAL_REG; 8086 relax_char = 0; 8087 for (args = opcode->args;; ++args) 8088 { 8089 int c; 8090 8091 if (arg.token->type == OT_END) 8092 { 8093 offsetT value; 8094 8095 /* Handle unary instructions in which only one operand is given. 8096 The source is then the same as the destination. */ 8097 if (arg.opnum == 1 && *args == ',') 8098 { 8099 operand = decode_mips16_operand (args[1], FALSE); 8100 if (operand && mips_optional_operand_p (operand)) 8101 { 8102 arg.token = tokens; 8103 arg.argnum = 1; 8104 continue; 8105 } 8106 } 8107 8108 /* Fail the match if there were too few operands. */ 8109 if (*args) 8110 return FALSE; 8111 8112 /* Successful match. Stuff the immediate value in now, if 8113 we can. */ 8114 clear_insn_error (); 8115 if (opcode->pinfo == INSN_MACRO) 8116 { 8117 gas_assert (relax_char == 0 || relax_char == 'p'); 8118 gas_assert (*offset_reloc == BFD_RELOC_UNUSED); 8119 } 8120 else if (relax_char 8121 && offset_expr.X_op == O_constant 8122 && calculate_reloc (*offset_reloc, 8123 offset_expr.X_add_number, 8124 &value)) 8125 { 8126 mips16_immed (NULL, 0, relax_char, *offset_reloc, value, 8127 forced_insn_length, &insn->insn_opcode); 8128 offset_expr.X_op = O_absent; 8129 *offset_reloc = BFD_RELOC_UNUSED; 8130 } 8131 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) 8132 { 8133 if (forced_insn_length == 2) 8134 set_insn_error (0, _("invalid unextended operand value")); 8135 forced_insn_length = 4; 8136 insn->insn_opcode |= MIPS16_EXTEND; 8137 } 8138 else if (relax_char) 8139 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; 8140 8141 check_completed_insn (&arg); 8142 return TRUE; 8143 } 8144 8145 /* Fail the match if the line has too many operands. */ 8146 if (*args == 0) 8147 return FALSE; 8148 8149 /* Handle characters that need to match exactly. */ 8150 if (*args == '(' || *args == ')' || *args == ',') 8151 { 8152 if (match_char (&arg, *args)) 8153 continue; 8154 return FALSE; 8155 } 8156 8157 arg.opnum += 1; 8158 c = *args; 8159 switch (c) 8160 { 8161 case 'p': 8162 case 'q': 8163 case 'A': 8164 case 'B': 8165 case 'E': 8166 relax_char = c; 8167 break; 8168 8169 case 'I': 8170 if (!match_const_int (&arg, &imm_expr.X_add_number)) 8171 return FALSE; 8172 imm_expr.X_op = O_constant; 8173 if (GPR_SIZE == 32) 8174 normalize_constant_expr (&imm_expr); 8175 continue; 8176 8177 case 'a': 8178 case 'i': 8179 *offset_reloc = BFD_RELOC_MIPS16_JMP; 8180 insn->insn_opcode <<= 16; 8181 break; 8182 } 8183 8184 operand = decode_mips16_operand (c, FALSE); 8185 if (!operand) 8186 abort (); 8187 8188 /* '6' is a special case. It is used for BREAK and SDBBP, 8189 whose operands are only meaningful to the software that decodes 8190 them. This means that there is no architectural reason why 8191 they cannot be prefixed by EXTEND, but in practice, 8192 exception handlers will only look at the instruction 8193 itself. We therefore allow '6' to be extended when 8194 disassembling but not when assembling. */ 8195 if (operand->type != OP_PCREL && c != '6') 8196 { 8197 ext_operand = decode_mips16_operand (c, TRUE); 8198 if (operand != ext_operand) 8199 { 8200 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 8201 { 8202 offset_expr.X_op = O_constant; 8203 offset_expr.X_add_number = 0; 8204 relax_char = c; 8205 continue; 8206 } 8207 8208 /* We need the OT_INTEGER check because some MIPS16 8209 immediate variants are listed before the register ones. */ 8210 if (arg.token->type != OT_INTEGER 8211 || !match_expression (&arg, &offset_expr, offset_reloc)) 8212 return FALSE; 8213 8214 /* '8' is used for SLTI(U) and has traditionally not 8215 been allowed to take relocation operators. */ 8216 if (offset_reloc[0] != BFD_RELOC_UNUSED 8217 && (ext_operand->size != 16 || c == '8')) 8218 return FALSE; 8219 8220 relax_char = c; 8221 continue; 8222 } 8223 } 8224 8225 if (mips_optional_operand_p (operand) 8226 && args[1] == ',' 8227 && (arg.token[0].type != OT_REG 8228 || arg.token[1].type == OT_END)) 8229 { 8230 /* Assume that the register has been elided and is the 8231 same as the first operand. */ 8232 arg.token = tokens; 8233 arg.argnum = 1; 8234 } 8235 8236 if (!match_operand (&arg, operand)) 8237 return FALSE; 8238 } 8239 } 8240 8241 /* Record that the current instruction is invalid for the current ISA. */ 8242 8243 static void 8244 match_invalid_for_isa (void) 8245 { 8246 set_insn_error_ss 8247 (0, _("opcode not supported on this processor: %s (%s)"), 8248 mips_cpu_info_from_arch (mips_opts.arch)->name, 8249 mips_cpu_info_from_isa (mips_opts.isa)->name); 8250 } 8251 8252 /* Try to match TOKENS against a series of opcode entries, starting at FIRST. 8253 Return true if a definite match or failure was found, storing any match 8254 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode 8255 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already 8256 tried and failed to match under normal conditions and now want to try a 8257 more relaxed match. */ 8258 8259 static bfd_boolean 8260 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8261 const struct mips_opcode *past, struct mips_operand_token *tokens, 8262 int opcode_extra, bfd_boolean lax_match) 8263 { 8264 const struct mips_opcode *opcode; 8265 const struct mips_opcode *invalid_delay_slot; 8266 bfd_boolean seen_valid_for_isa, seen_valid_for_size; 8267 8268 /* Search for a match, ignoring alternatives that don't satisfy the 8269 current ISA or forced_length. */ 8270 invalid_delay_slot = 0; 8271 seen_valid_for_isa = FALSE; 8272 seen_valid_for_size = FALSE; 8273 opcode = first; 8274 do 8275 { 8276 gas_assert (strcmp (opcode->name, first->name) == 0); 8277 if (is_opcode_valid (opcode)) 8278 { 8279 seen_valid_for_isa = TRUE; 8280 if (is_size_valid (opcode)) 8281 { 8282 bfd_boolean delay_slot_ok; 8283 8284 seen_valid_for_size = TRUE; 8285 delay_slot_ok = is_delay_slot_valid (opcode); 8286 if (match_insn (insn, opcode, tokens, opcode_extra, 8287 lax_match, delay_slot_ok)) 8288 { 8289 if (!delay_slot_ok) 8290 { 8291 if (!invalid_delay_slot) 8292 invalid_delay_slot = opcode; 8293 } 8294 else 8295 return TRUE; 8296 } 8297 } 8298 } 8299 ++opcode; 8300 } 8301 while (opcode < past && strcmp (opcode->name, first->name) == 0); 8302 8303 /* If the only matches we found had the wrong length for the delay slot, 8304 pick the first such match. We'll issue an appropriate warning later. */ 8305 if (invalid_delay_slot) 8306 { 8307 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, 8308 lax_match, TRUE)) 8309 return TRUE; 8310 abort (); 8311 } 8312 8313 /* Handle the case where we didn't try to match an instruction because 8314 all the alternatives were incompatible with the current ISA. */ 8315 if (!seen_valid_for_isa) 8316 { 8317 match_invalid_for_isa (); 8318 return TRUE; 8319 } 8320 8321 /* Handle the case where we didn't try to match an instruction because 8322 all the alternatives were of the wrong size. */ 8323 if (!seen_valid_for_size) 8324 { 8325 if (mips_opts.insn32) 8326 set_insn_error (0, _("opcode not supported in the `insn32' mode")); 8327 else 8328 set_insn_error_i 8329 (0, _("unrecognized %d-bit version of microMIPS opcode"), 8330 8 * forced_insn_length); 8331 return TRUE; 8332 } 8333 8334 return FALSE; 8335 } 8336 8337 /* Like match_insns, but for MIPS16. */ 8338 8339 static bfd_boolean 8340 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8341 struct mips_operand_token *tokens) 8342 { 8343 const struct mips_opcode *opcode; 8344 bfd_boolean seen_valid_for_isa; 8345 8346 /* Search for a match, ignoring alternatives that don't satisfy the 8347 current ISA. There are no separate entries for extended forms so 8348 we deal with forced_length later. */ 8349 seen_valid_for_isa = FALSE; 8350 opcode = first; 8351 do 8352 { 8353 gas_assert (strcmp (opcode->name, first->name) == 0); 8354 if (is_opcode_valid_16 (opcode)) 8355 { 8356 seen_valid_for_isa = TRUE; 8357 if (match_mips16_insn (insn, opcode, tokens)) 8358 return TRUE; 8359 } 8360 ++opcode; 8361 } 8362 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] 8363 && strcmp (opcode->name, first->name) == 0); 8364 8365 /* Handle the case where we didn't try to match an instruction because 8366 all the alternatives were incompatible with the current ISA. */ 8367 if (!seen_valid_for_isa) 8368 { 8369 match_invalid_for_isa (); 8370 return TRUE; 8371 } 8372 8373 return FALSE; 8374 } 8375 8376 /* Set up global variables for the start of a new macro. */ 8377 8378 static void 8379 macro_start (void) 8380 { 8381 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); 8382 memset (&mips_macro_warning.first_insn_sizes, 0, 8383 sizeof (mips_macro_warning.first_insn_sizes)); 8384 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); 8385 mips_macro_warning.delay_slot_p = (mips_opts.noreorder 8386 && delayed_branch_p (&history[0])); 8387 switch (history[0].insn_mo->pinfo2 8388 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) 8389 { 8390 case INSN2_BRANCH_DELAY_32BIT: 8391 mips_macro_warning.delay_slot_length = 4; 8392 break; 8393 case INSN2_BRANCH_DELAY_16BIT: 8394 mips_macro_warning.delay_slot_length = 2; 8395 break; 8396 default: 8397 mips_macro_warning.delay_slot_length = 0; 8398 break; 8399 } 8400 mips_macro_warning.first_frag = NULL; 8401 } 8402 8403 /* Given that a macro is longer than one instruction or of the wrong size, 8404 return the appropriate warning for it. Return null if no warning is 8405 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, 8406 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, 8407 and RELAX_NOMACRO. */ 8408 8409 static const char * 8410 macro_warning (relax_substateT subtype) 8411 { 8412 if (subtype & RELAX_DELAY_SLOT) 8413 return _("macro instruction expanded into multiple instructions" 8414 " in a branch delay slot"); 8415 else if (subtype & RELAX_NOMACRO) 8416 return _("macro instruction expanded into multiple instructions"); 8417 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST 8418 | RELAX_DELAY_SLOT_SIZE_SECOND)) 8419 return ((subtype & RELAX_DELAY_SLOT_16BIT) 8420 ? _("macro instruction expanded into a wrong size instruction" 8421 " in a 16-bit branch delay slot") 8422 : _("macro instruction expanded into a wrong size instruction" 8423 " in a 32-bit branch delay slot")); 8424 else 8425 return 0; 8426 } 8427 8428 /* Finish up a macro. Emit warnings as appropriate. */ 8429 8430 static void 8431 macro_end (void) 8432 { 8433 /* Relaxation warning flags. */ 8434 relax_substateT subtype = 0; 8435 8436 /* Check delay slot size requirements. */ 8437 if (mips_macro_warning.delay_slot_length == 2) 8438 subtype |= RELAX_DELAY_SLOT_16BIT; 8439 if (mips_macro_warning.delay_slot_length != 0) 8440 { 8441 if (mips_macro_warning.delay_slot_length 8442 != mips_macro_warning.first_insn_sizes[0]) 8443 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; 8444 if (mips_macro_warning.delay_slot_length 8445 != mips_macro_warning.first_insn_sizes[1]) 8446 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; 8447 } 8448 8449 /* Check instruction count requirements. */ 8450 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) 8451 { 8452 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) 8453 subtype |= RELAX_SECOND_LONGER; 8454 if (mips_opts.warn_about_macros) 8455 subtype |= RELAX_NOMACRO; 8456 if (mips_macro_warning.delay_slot_p) 8457 subtype |= RELAX_DELAY_SLOT; 8458 } 8459 8460 /* If both alternatives fail to fill a delay slot correctly, 8461 emit the warning now. */ 8462 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 8463 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) 8464 { 8465 relax_substateT s; 8466 const char *msg; 8467 8468 s = subtype & (RELAX_DELAY_SLOT_16BIT 8469 | RELAX_DELAY_SLOT_SIZE_FIRST 8470 | RELAX_DELAY_SLOT_SIZE_SECOND); 8471 msg = macro_warning (s); 8472 if (msg != NULL) 8473 as_warn ("%s", msg); 8474 subtype &= ~s; 8475 } 8476 8477 /* If both implementations are longer than 1 instruction, then emit the 8478 warning now. */ 8479 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) 8480 { 8481 relax_substateT s; 8482 const char *msg; 8483 8484 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); 8485 msg = macro_warning (s); 8486 if (msg != NULL) 8487 as_warn ("%s", msg); 8488 subtype &= ~s; 8489 } 8490 8491 /* If any flags still set, then one implementation might need a warning 8492 and the other either will need one of a different kind or none at all. 8493 Pass any remaining flags over to relaxation. */ 8494 if (mips_macro_warning.first_frag != NULL) 8495 mips_macro_warning.first_frag->fr_subtype |= subtype; 8496 } 8497 8498 /* Instruction operand formats used in macros that vary between 8499 standard MIPS and microMIPS code. */ 8500 8501 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; 8502 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; 8503 static const char * const jalr_fmt[2] = { "d,s", "t,s" }; 8504 static const char * const lui_fmt[2] = { "t,u", "s,u" }; 8505 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; 8506 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; 8507 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; 8508 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; 8509 8510 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) 8511 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ 8512 : cop12_fmt[mips_opts.micromips]) 8513 #define JALR_FMT (jalr_fmt[mips_opts.micromips]) 8514 #define LUI_FMT (lui_fmt[mips_opts.micromips]) 8515 #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) 8516 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ 8517 : mem12_fmt[mips_opts.micromips]) 8518 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) 8519 #define SHFT_FMT (shft_fmt[mips_opts.micromips]) 8520 #define TRAP_FMT (trap_fmt[mips_opts.micromips]) 8521 8522 /* Read a macro's relocation codes from *ARGS and store them in *R. 8523 The first argument in *ARGS will be either the code for a single 8524 relocation or -1 followed by the three codes that make up a 8525 composite relocation. */ 8526 8527 static void 8528 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) 8529 { 8530 int i, next; 8531 8532 next = va_arg (*args, int); 8533 if (next >= 0) 8534 r[0] = (bfd_reloc_code_real_type) next; 8535 else 8536 { 8537 for (i = 0; i < 3; i++) 8538 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); 8539 /* This function is only used for 16-bit relocation fields. 8540 To make the macro code simpler, treat an unrelocated value 8541 in the same way as BFD_RELOC_LO16. */ 8542 if (r[0] == BFD_RELOC_UNUSED) 8543 r[0] = BFD_RELOC_LO16; 8544 } 8545 } 8546 8547 /* Build an instruction created by a macro expansion. This is passed 8548 a pointer to the count of instructions created so far, an 8549 expression, the name of the instruction to build, an operand format 8550 string, and corresponding arguments. */ 8551 8552 static void 8553 macro_build (expressionS *ep, const char *name, const char *fmt, ...) 8554 { 8555 const struct mips_opcode *mo = NULL; 8556 bfd_reloc_code_real_type r[3]; 8557 const struct mips_opcode *amo; 8558 const struct mips_operand *operand; 8559 struct hash_control *hash; 8560 struct mips_cl_insn insn; 8561 va_list args; 8562 unsigned int uval; 8563 8564 va_start (args, fmt); 8565 8566 if (mips_opts.mips16) 8567 { 8568 mips16_macro_build (ep, name, fmt, &args); 8569 va_end (args); 8570 return; 8571 } 8572 8573 r[0] = BFD_RELOC_UNUSED; 8574 r[1] = BFD_RELOC_UNUSED; 8575 r[2] = BFD_RELOC_UNUSED; 8576 hash = mips_opts.micromips ? micromips_op_hash : op_hash; 8577 amo = (struct mips_opcode *) hash_find (hash, name); 8578 gas_assert (amo); 8579 gas_assert (strcmp (name, amo->name) == 0); 8580 8581 do 8582 { 8583 /* Search until we get a match for NAME. It is assumed here that 8584 macros will never generate MDMX, MIPS-3D, or MT instructions. 8585 We try to match an instruction that fulfils the branch delay 8586 slot instruction length requirement (if any) of the previous 8587 instruction. While doing this we record the first instruction 8588 seen that matches all the other conditions and use it anyway 8589 if the requirement cannot be met; we will issue an appropriate 8590 warning later on. */ 8591 if (strcmp (fmt, amo->args) == 0 8592 && amo->pinfo != INSN_MACRO 8593 && is_opcode_valid (amo) 8594 && is_size_valid (amo)) 8595 { 8596 if (is_delay_slot_valid (amo)) 8597 { 8598 mo = amo; 8599 break; 8600 } 8601 else if (!mo) 8602 mo = amo; 8603 } 8604 8605 ++amo; 8606 gas_assert (amo->name); 8607 } 8608 while (strcmp (name, amo->name) == 0); 8609 8610 gas_assert (mo); 8611 create_insn (&insn, mo); 8612 for (; *fmt; ++fmt) 8613 { 8614 switch (*fmt) 8615 { 8616 case ',': 8617 case '(': 8618 case ')': 8619 case 'z': 8620 break; 8621 8622 case 'i': 8623 case 'j': 8624 macro_read_relocs (&args, r); 8625 gas_assert (*r == BFD_RELOC_GPREL16 8626 || *r == BFD_RELOC_MIPS_HIGHER 8627 || *r == BFD_RELOC_HI16_S 8628 || *r == BFD_RELOC_LO16 8629 || *r == BFD_RELOC_MIPS_GOT_OFST); 8630 break; 8631 8632 case 'o': 8633 macro_read_relocs (&args, r); 8634 break; 8635 8636 case 'u': 8637 macro_read_relocs (&args, r); 8638 gas_assert (ep != NULL 8639 && (ep->X_op == O_constant 8640 || (ep->X_op == O_symbol 8641 && (*r == BFD_RELOC_MIPS_HIGHEST 8642 || *r == BFD_RELOC_HI16_S 8643 || *r == BFD_RELOC_HI16 8644 || *r == BFD_RELOC_GPREL16 8645 || *r == BFD_RELOC_MIPS_GOT_HI16 8646 || *r == BFD_RELOC_MIPS_CALL_HI16)))); 8647 break; 8648 8649 case 'p': 8650 gas_assert (ep != NULL); 8651 8652 /* 8653 * This allows macro() to pass an immediate expression for 8654 * creating short branches without creating a symbol. 8655 * 8656 * We don't allow branch relaxation for these branches, as 8657 * they should only appear in ".set nomacro" anyway. 8658 */ 8659 if (ep->X_op == O_constant) 8660 { 8661 /* For microMIPS we always use relocations for branches. 8662 So we should not resolve immediate values. */ 8663 gas_assert (!mips_opts.micromips); 8664 8665 if ((ep->X_add_number & 3) != 0) 8666 as_bad (_("branch to misaligned address (0x%lx)"), 8667 (unsigned long) ep->X_add_number); 8668 if ((ep->X_add_number + 0x20000) & ~0x3ffff) 8669 as_bad (_("branch address range overflow (0x%lx)"), 8670 (unsigned long) ep->X_add_number); 8671 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; 8672 ep = NULL; 8673 } 8674 else 8675 *r = BFD_RELOC_16_PCREL_S2; 8676 break; 8677 8678 case 'a': 8679 gas_assert (ep != NULL); 8680 *r = BFD_RELOC_MIPS_JMP; 8681 break; 8682 8683 default: 8684 operand = (mips_opts.micromips 8685 ? decode_micromips_operand (fmt) 8686 : decode_mips_operand (fmt)); 8687 if (!operand) 8688 abort (); 8689 8690 uval = va_arg (args, int); 8691 if (operand->type == OP_CLO_CLZ_DEST) 8692 uval |= (uval << 5); 8693 insn_insert_operand (&insn, operand, uval); 8694 8695 if (*fmt == '+' || *fmt == 'm' || *fmt == '-' || *fmt == '`') 8696 ++fmt; 8697 break; 8698 } 8699 } 8700 va_end (args); 8701 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 8702 8703 append_insn (&insn, ep, r, TRUE); 8704 } 8705 8706 static void 8707 mips16_macro_build (expressionS *ep, const char *name, const char *fmt, 8708 va_list *args) 8709 { 8710 struct mips_opcode *mo; 8711 struct mips_cl_insn insn; 8712 const struct mips_operand *operand; 8713 bfd_reloc_code_real_type r[3] 8714 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 8715 8716 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); 8717 gas_assert (mo); 8718 gas_assert (strcmp (name, mo->name) == 0); 8719 8720 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) 8721 { 8722 ++mo; 8723 gas_assert (mo->name); 8724 gas_assert (strcmp (name, mo->name) == 0); 8725 } 8726 8727 create_insn (&insn, mo); 8728 for (; *fmt; ++fmt) 8729 { 8730 int c; 8731 8732 c = *fmt; 8733 switch (c) 8734 { 8735 case ',': 8736 case '(': 8737 case ')': 8738 break; 8739 8740 case '0': 8741 case 'S': 8742 case 'P': 8743 case 'R': 8744 break; 8745 8746 case '<': 8747 case '>': 8748 case '4': 8749 case '5': 8750 case 'H': 8751 case 'W': 8752 case 'D': 8753 case 'j': 8754 case '8': 8755 case 'V': 8756 case 'C': 8757 case 'U': 8758 case 'k': 8759 case 'K': 8760 case 'p': 8761 case 'q': 8762 { 8763 offsetT value; 8764 8765 gas_assert (ep != NULL); 8766 8767 if (ep->X_op != O_constant) 8768 *r = (int) BFD_RELOC_UNUSED + c; 8769 else if (calculate_reloc (*r, ep->X_add_number, &value)) 8770 { 8771 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); 8772 ep = NULL; 8773 *r = BFD_RELOC_UNUSED; 8774 } 8775 } 8776 break; 8777 8778 default: 8779 operand = decode_mips16_operand (c, FALSE); 8780 if (!operand) 8781 abort (); 8782 8783 insn_insert_operand (&insn, operand, va_arg (*args, int)); 8784 break; 8785 } 8786 } 8787 8788 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 8789 8790 append_insn (&insn, ep, r, TRUE); 8791 } 8792 8793 /* 8794 * Generate a "jalr" instruction with a relocation hint to the called 8795 * function. This occurs in NewABI PIC code. 8796 */ 8797 static void 8798 macro_build_jalr (expressionS *ep, int cprestore) 8799 { 8800 static const bfd_reloc_code_real_type jalr_relocs[2] 8801 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; 8802 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; 8803 const char *jalr; 8804 char *f = NULL; 8805 8806 if (MIPS_JALR_HINT_P (ep)) 8807 { 8808 frag_grow (8); 8809 f = frag_more (0); 8810 } 8811 if (mips_opts.micromips) 8812 { 8813 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 8814 ? "jalr" : "jalrs"); 8815 if (MIPS_JALR_HINT_P (ep) 8816 || mips_opts.insn32 8817 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 8818 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); 8819 else 8820 macro_build (NULL, jalr, "mj", PIC_CALL_REG); 8821 } 8822 else 8823 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); 8824 if (MIPS_JALR_HINT_P (ep)) 8825 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); 8826 } 8827 8828 /* 8829 * Generate a "lui" instruction. 8830 */ 8831 static void 8832 macro_build_lui (expressionS *ep, int regnum) 8833 { 8834 gas_assert (! mips_opts.mips16); 8835 8836 if (ep->X_op != O_constant) 8837 { 8838 gas_assert (ep->X_op == O_symbol); 8839 /* _gp_disp is a special case, used from s_cpload. 8840 __gnu_local_gp is used if mips_no_shared. */ 8841 gas_assert (mips_pic == NO_PIC 8842 || (! HAVE_NEWABI 8843 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) 8844 || (! mips_in_shared 8845 && strcmp (S_GET_NAME (ep->X_add_symbol), 8846 "__gnu_local_gp") == 0)); 8847 } 8848 8849 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); 8850 } 8851 8852 /* Generate a sequence of instructions to do a load or store from a constant 8853 offset off of a base register (breg) into/from a target register (treg), 8854 using AT if necessary. */ 8855 static void 8856 macro_build_ldst_constoffset (expressionS *ep, const char *op, 8857 int treg, int breg, int dbl) 8858 { 8859 gas_assert (ep->X_op == O_constant); 8860 8861 /* Sign-extending 32-bit constants makes their handling easier. */ 8862 if (!dbl) 8863 normalize_constant_expr (ep); 8864 8865 /* Right now, this routine can only handle signed 32-bit constants. */ 8866 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) 8867 as_warn (_("operand overflow")); 8868 8869 if (IS_SEXT_16BIT_NUM(ep->X_add_number)) 8870 { 8871 /* Signed 16-bit offset will fit in the op. Easy! */ 8872 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); 8873 } 8874 else 8875 { 8876 /* 32-bit offset, need multiple instructions and AT, like: 8877 lui $tempreg,const_hi (BFD_RELOC_HI16_S) 8878 addu $tempreg,$tempreg,$breg 8879 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) 8880 to handle the complete offset. */ 8881 macro_build_lui (ep, AT); 8882 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 8883 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); 8884 8885 if (!mips_opts.at) 8886 as_bad (_("macro used $at after \".set noat\"")); 8887 } 8888 } 8889 8890 /* set_at() 8891 * Generates code to set the $at register to true (one) 8892 * if reg is less than the immediate expression. 8893 */ 8894 static void 8895 set_at (int reg, int unsignedp) 8896 { 8897 if (imm_expr.X_add_number >= -0x8000 8898 && imm_expr.X_add_number < 0x8000) 8899 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", 8900 AT, reg, BFD_RELOC_LO16); 8901 else 8902 { 8903 load_register (AT, &imm_expr, GPR_SIZE == 64); 8904 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); 8905 } 8906 } 8907 8908 /* Count the leading zeroes by performing a binary chop. This is a 8909 bulky bit of source, but performance is a LOT better for the 8910 majority of values than a simple loop to count the bits: 8911 for (lcnt = 0; (lcnt < 32); lcnt++) 8912 if ((v) & (1 << (31 - lcnt))) 8913 break; 8914 However it is not code size friendly, and the gain will drop a bit 8915 on certain cached systems. 8916 */ 8917 #define COUNT_TOP_ZEROES(v) \ 8918 (((v) & ~0xffff) == 0 \ 8919 ? ((v) & ~0xff) == 0 \ 8920 ? ((v) & ~0xf) == 0 \ 8921 ? ((v) & ~0x3) == 0 \ 8922 ? ((v) & ~0x1) == 0 \ 8923 ? !(v) \ 8924 ? 32 \ 8925 : 31 \ 8926 : 30 \ 8927 : ((v) & ~0x7) == 0 \ 8928 ? 29 \ 8929 : 28 \ 8930 : ((v) & ~0x3f) == 0 \ 8931 ? ((v) & ~0x1f) == 0 \ 8932 ? 27 \ 8933 : 26 \ 8934 : ((v) & ~0x7f) == 0 \ 8935 ? 25 \ 8936 : 24 \ 8937 : ((v) & ~0xfff) == 0 \ 8938 ? ((v) & ~0x3ff) == 0 \ 8939 ? ((v) & ~0x1ff) == 0 \ 8940 ? 23 \ 8941 : 22 \ 8942 : ((v) & ~0x7ff) == 0 \ 8943 ? 21 \ 8944 : 20 \ 8945 : ((v) & ~0x3fff) == 0 \ 8946 ? ((v) & ~0x1fff) == 0 \ 8947 ? 19 \ 8948 : 18 \ 8949 : ((v) & ~0x7fff) == 0 \ 8950 ? 17 \ 8951 : 16 \ 8952 : ((v) & ~0xffffff) == 0 \ 8953 ? ((v) & ~0xfffff) == 0 \ 8954 ? ((v) & ~0x3ffff) == 0 \ 8955 ? ((v) & ~0x1ffff) == 0 \ 8956 ? 15 \ 8957 : 14 \ 8958 : ((v) & ~0x7ffff) == 0 \ 8959 ? 13 \ 8960 : 12 \ 8961 : ((v) & ~0x3fffff) == 0 \ 8962 ? ((v) & ~0x1fffff) == 0 \ 8963 ? 11 \ 8964 : 10 \ 8965 : ((v) & ~0x7fffff) == 0 \ 8966 ? 9 \ 8967 : 8 \ 8968 : ((v) & ~0xfffffff) == 0 \ 8969 ? ((v) & ~0x3ffffff) == 0 \ 8970 ? ((v) & ~0x1ffffff) == 0 \ 8971 ? 7 \ 8972 : 6 \ 8973 : ((v) & ~0x7ffffff) == 0 \ 8974 ? 5 \ 8975 : 4 \ 8976 : ((v) & ~0x3fffffff) == 0 \ 8977 ? ((v) & ~0x1fffffff) == 0 \ 8978 ? 3 \ 8979 : 2 \ 8980 : ((v) & ~0x7fffffff) == 0 \ 8981 ? 1 \ 8982 : 0) 8983 8984 /* load_register() 8985 * This routine generates the least number of instructions necessary to load 8986 * an absolute expression value into a register. 8987 */ 8988 static void 8989 load_register (int reg, expressionS *ep, int dbl) 8990 { 8991 int freg; 8992 expressionS hi32, lo32; 8993 8994 if (ep->X_op != O_big) 8995 { 8996 gas_assert (ep->X_op == O_constant); 8997 8998 /* Sign-extending 32-bit constants makes their handling easier. */ 8999 if (!dbl) 9000 normalize_constant_expr (ep); 9001 9002 if (IS_SEXT_16BIT_NUM (ep->X_add_number)) 9003 { 9004 /* We can handle 16 bit signed values with an addiu to 9005 $zero. No need to ever use daddiu here, since $zero and 9006 the result are always correct in 32 bit mode. */ 9007 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9008 return; 9009 } 9010 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) 9011 { 9012 /* We can handle 16 bit unsigned values with an ori to 9013 $zero. */ 9014 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 9015 return; 9016 } 9017 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) 9018 { 9019 /* 32 bit values require an lui. */ 9020 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9021 if ((ep->X_add_number & 0xffff) != 0) 9022 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 9023 return; 9024 } 9025 } 9026 9027 /* The value is larger than 32 bits. */ 9028 9029 if (!dbl || GPR_SIZE == 32) 9030 { 9031 char value[32]; 9032 9033 sprintf_vma (value, ep->X_add_number); 9034 as_bad (_("number (0x%s) larger than 32 bits"), value); 9035 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9036 return; 9037 } 9038 9039 if (ep->X_op != O_big) 9040 { 9041 hi32 = *ep; 9042 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 9043 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 9044 hi32.X_add_number &= 0xffffffff; 9045 lo32 = *ep; 9046 lo32.X_add_number &= 0xffffffff; 9047 } 9048 else 9049 { 9050 gas_assert (ep->X_add_number > 2); 9051 if (ep->X_add_number == 3) 9052 generic_bignum[3] = 0; 9053 else if (ep->X_add_number > 4) 9054 as_bad (_("number larger than 64 bits")); 9055 lo32.X_op = O_constant; 9056 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); 9057 hi32.X_op = O_constant; 9058 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); 9059 } 9060 9061 if (hi32.X_add_number == 0) 9062 freg = 0; 9063 else 9064 { 9065 int shift, bit; 9066 unsigned long hi, lo; 9067 9068 if (hi32.X_add_number == (offsetT) 0xffffffff) 9069 { 9070 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) 9071 { 9072 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9073 return; 9074 } 9075 if (lo32.X_add_number & 0x80000000) 9076 { 9077 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9078 if (lo32.X_add_number & 0xffff) 9079 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 9080 return; 9081 } 9082 } 9083 9084 /* Check for 16bit shifted constant. We know that hi32 is 9085 non-zero, so start the mask on the first bit of the hi32 9086 value. */ 9087 shift = 17; 9088 do 9089 { 9090 unsigned long himask, lomask; 9091 9092 if (shift < 32) 9093 { 9094 himask = 0xffff >> (32 - shift); 9095 lomask = (0xffff << shift) & 0xffffffff; 9096 } 9097 else 9098 { 9099 himask = 0xffff << (shift - 32); 9100 lomask = 0; 9101 } 9102 if ((hi32.X_add_number & ~(offsetT) himask) == 0 9103 && (lo32.X_add_number & ~(offsetT) lomask) == 0) 9104 { 9105 expressionS tmp; 9106 9107 tmp.X_op = O_constant; 9108 if (shift < 32) 9109 tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) 9110 | (lo32.X_add_number >> shift)); 9111 else 9112 tmp.X_add_number = hi32.X_add_number >> (shift - 32); 9113 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 9114 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9115 reg, reg, (shift >= 32) ? shift - 32 : shift); 9116 return; 9117 } 9118 ++shift; 9119 } 9120 while (shift <= (64 - 16)); 9121 9122 /* Find the bit number of the lowest one bit, and store the 9123 shifted value in hi/lo. */ 9124 hi = (unsigned long) (hi32.X_add_number & 0xffffffff); 9125 lo = (unsigned long) (lo32.X_add_number & 0xffffffff); 9126 if (lo != 0) 9127 { 9128 bit = 0; 9129 while ((lo & 1) == 0) 9130 { 9131 lo >>= 1; 9132 ++bit; 9133 } 9134 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); 9135 hi >>= bit; 9136 } 9137 else 9138 { 9139 bit = 32; 9140 while ((hi & 1) == 0) 9141 { 9142 hi >>= 1; 9143 ++bit; 9144 } 9145 lo = hi; 9146 hi = 0; 9147 } 9148 9149 /* Optimize if the shifted value is a (power of 2) - 1. */ 9150 if ((hi == 0 && ((lo + 1) & lo) == 0) 9151 || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) 9152 { 9153 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); 9154 if (shift != 0) 9155 { 9156 expressionS tmp; 9157 9158 /* This instruction will set the register to be all 9159 ones. */ 9160 tmp.X_op = O_constant; 9161 tmp.X_add_number = (offsetT) -1; 9162 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9163 if (bit != 0) 9164 { 9165 bit += shift; 9166 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9167 reg, reg, (bit >= 32) ? bit - 32 : bit); 9168 } 9169 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, 9170 reg, reg, (shift >= 32) ? shift - 32 : shift); 9171 return; 9172 } 9173 } 9174 9175 /* Sign extend hi32 before calling load_register, because we can 9176 generally get better code when we load a sign extended value. */ 9177 if ((hi32.X_add_number & 0x80000000) != 0) 9178 hi32.X_add_number |= ~(offsetT) 0xffffffff; 9179 load_register (reg, &hi32, 0); 9180 freg = reg; 9181 } 9182 if ((lo32.X_add_number & 0xffff0000) == 0) 9183 { 9184 if (freg != 0) 9185 { 9186 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); 9187 freg = reg; 9188 } 9189 } 9190 else 9191 { 9192 expressionS mid16; 9193 9194 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) 9195 { 9196 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9197 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); 9198 return; 9199 } 9200 9201 if (freg != 0) 9202 { 9203 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); 9204 freg = reg; 9205 } 9206 mid16 = lo32; 9207 mid16.X_add_number >>= 16; 9208 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9209 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9210 freg = reg; 9211 } 9212 if ((lo32.X_add_number & 0xffff) != 0) 9213 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9214 } 9215 9216 static inline void 9217 load_delay_nop (void) 9218 { 9219 if (!gpr_interlocks) 9220 macro_build (NULL, "nop", ""); 9221 } 9222 9223 /* Load an address into a register. */ 9224 9225 static void 9226 load_address (int reg, expressionS *ep, int *used_at) 9227 { 9228 if (ep->X_op != O_constant 9229 && ep->X_op != O_symbol) 9230 { 9231 as_bad (_("expression too complex")); 9232 ep->X_op = O_constant; 9233 } 9234 9235 if (ep->X_op == O_constant) 9236 { 9237 load_register (reg, ep, HAVE_64BIT_ADDRESSES); 9238 return; 9239 } 9240 9241 if (mips_pic == NO_PIC) 9242 { 9243 /* If this is a reference to a GP relative symbol, we want 9244 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 9245 Otherwise we want 9246 lui $reg,<sym> (BFD_RELOC_HI16_S) 9247 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9248 If we have an addend, we always use the latter form. 9249 9250 With 64bit address space and a usable $at we want 9251 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9252 lui $at,<sym> (BFD_RELOC_HI16_S) 9253 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9254 daddiu $at,<sym> (BFD_RELOC_LO16) 9255 dsll32 $reg,0 9256 daddu $reg,$reg,$at 9257 9258 If $at is already in use, we use a path which is suboptimal 9259 on superscalar processors. 9260 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9261 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9262 dsll $reg,16 9263 daddiu $reg,<sym> (BFD_RELOC_HI16_S) 9264 dsll $reg,16 9265 daddiu $reg,<sym> (BFD_RELOC_LO16) 9266 9267 For GP relative symbols in 64bit address space we can use 9268 the same sequence as in 32bit address space. */ 9269 if (HAVE_64BIT_SYMBOLS) 9270 { 9271 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9272 && !nopic_need_relax (ep->X_add_symbol, 1)) 9273 { 9274 relax_start (ep->X_add_symbol); 9275 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9276 mips_gp_register, BFD_RELOC_GPREL16); 9277 relax_switch (); 9278 } 9279 9280 if (*used_at == 0 && mips_opts.at) 9281 { 9282 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9283 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); 9284 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9285 BFD_RELOC_MIPS_HIGHER); 9286 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); 9287 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); 9288 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); 9289 *used_at = 1; 9290 } 9291 else 9292 { 9293 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9294 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9295 BFD_RELOC_MIPS_HIGHER); 9296 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9297 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); 9298 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9299 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); 9300 } 9301 9302 if (mips_relax.sequence) 9303 relax_end (); 9304 } 9305 else 9306 { 9307 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9308 && !nopic_need_relax (ep->X_add_symbol, 1)) 9309 { 9310 relax_start (ep->X_add_symbol); 9311 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9312 mips_gp_register, BFD_RELOC_GPREL16); 9313 relax_switch (); 9314 } 9315 macro_build_lui (ep, reg); 9316 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 9317 reg, reg, BFD_RELOC_LO16); 9318 if (mips_relax.sequence) 9319 relax_end (); 9320 } 9321 } 9322 else if (!mips_big_got) 9323 { 9324 expressionS ex; 9325 9326 /* If this is a reference to an external symbol, we want 9327 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9328 Otherwise we want 9329 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9330 nop 9331 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9332 If there is a constant, it must be added in after. 9333 9334 If we have NewABI, we want 9335 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) 9336 unless we're referencing a global symbol with a non-zero 9337 offset, in which case cst must be added separately. */ 9338 if (HAVE_NEWABI) 9339 { 9340 if (ep->X_add_number) 9341 { 9342 ex.X_add_number = ep->X_add_number; 9343 ep->X_add_number = 0; 9344 relax_start (ep->X_add_symbol); 9345 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9346 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9347 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9348 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9349 ex.X_op = O_constant; 9350 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9351 reg, reg, BFD_RELOC_LO16); 9352 ep->X_add_number = ex.X_add_number; 9353 relax_switch (); 9354 } 9355 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9356 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9357 if (mips_relax.sequence) 9358 relax_end (); 9359 } 9360 else 9361 { 9362 ex.X_add_number = ep->X_add_number; 9363 ep->X_add_number = 0; 9364 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9365 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9366 load_delay_nop (); 9367 relax_start (ep->X_add_symbol); 9368 relax_switch (); 9369 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9370 BFD_RELOC_LO16); 9371 relax_end (); 9372 9373 if (ex.X_add_number != 0) 9374 { 9375 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9376 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9377 ex.X_op = O_constant; 9378 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9379 reg, reg, BFD_RELOC_LO16); 9380 } 9381 } 9382 } 9383 else if (mips_big_got) 9384 { 9385 expressionS ex; 9386 9387 /* This is the large GOT case. If this is a reference to an 9388 external symbol, we want 9389 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 9390 addu $reg,$reg,$gp 9391 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) 9392 9393 Otherwise, for a reference to a local symbol in old ABI, we want 9394 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9395 nop 9396 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9397 If there is a constant, it must be added in after. 9398 9399 In the NewABI, for local symbols, with or without offsets, we want: 9400 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 9401 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 9402 */ 9403 if (HAVE_NEWABI) 9404 { 9405 ex.X_add_number = ep->X_add_number; 9406 ep->X_add_number = 0; 9407 relax_start (ep->X_add_symbol); 9408 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9409 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9410 reg, reg, mips_gp_register); 9411 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9412 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9413 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9414 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9415 else if (ex.X_add_number) 9416 { 9417 ex.X_op = O_constant; 9418 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9419 BFD_RELOC_LO16); 9420 } 9421 9422 ep->X_add_number = ex.X_add_number; 9423 relax_switch (); 9424 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9425 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 9426 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9427 BFD_RELOC_MIPS_GOT_OFST); 9428 relax_end (); 9429 } 9430 else 9431 { 9432 ex.X_add_number = ep->X_add_number; 9433 ep->X_add_number = 0; 9434 relax_start (ep->X_add_symbol); 9435 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9436 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9437 reg, reg, mips_gp_register); 9438 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9439 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9440 relax_switch (); 9441 if (reg_needs_delay (mips_gp_register)) 9442 { 9443 /* We need a nop before loading from $gp. This special 9444 check is required because the lui which starts the main 9445 instruction stream does not refer to $gp, and so will not 9446 insert the nop which may be required. */ 9447 macro_build (NULL, "nop", ""); 9448 } 9449 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9450 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9451 load_delay_nop (); 9452 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9453 BFD_RELOC_LO16); 9454 relax_end (); 9455 9456 if (ex.X_add_number != 0) 9457 { 9458 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9459 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9460 ex.X_op = O_constant; 9461 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9462 BFD_RELOC_LO16); 9463 } 9464 } 9465 } 9466 else 9467 abort (); 9468 9469 if (!mips_opts.at && *used_at == 1) 9470 as_bad (_("macro used $at after \".set noat\"")); 9471 } 9472 9473 /* Move the contents of register SOURCE into register DEST. */ 9474 9475 static void 9476 move_register (int dest, int source) 9477 { 9478 /* Prefer to use a 16-bit microMIPS instruction unless the previous 9479 instruction specifically requires a 32-bit one. */ 9480 if (mips_opts.micromips 9481 && !mips_opts.insn32 9482 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 9483 macro_build (NULL, "move", "mp,mj", dest, source); 9484 else 9485 macro_build (NULL, GPR_SIZE == 32 ? "addu" : "daddu", "d,v,t", 9486 dest, source, 0); 9487 } 9488 9489 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where 9490 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. 9491 The two alternatives are: 9492 9493 Global symbol Local sybmol 9494 ------------- ------------ 9495 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) 9496 ... ... 9497 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) 9498 9499 load_got_offset emits the first instruction and add_got_offset 9500 emits the second for a 16-bit offset or add_got_offset_hilo emits 9501 a sequence to add a 32-bit offset using a scratch register. */ 9502 9503 static void 9504 load_got_offset (int dest, expressionS *local) 9505 { 9506 expressionS global; 9507 9508 global = *local; 9509 global.X_add_number = 0; 9510 9511 relax_start (local->X_add_symbol); 9512 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, 9513 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9514 relax_switch (); 9515 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, 9516 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9517 relax_end (); 9518 } 9519 9520 static void 9521 add_got_offset (int dest, expressionS *local) 9522 { 9523 expressionS global; 9524 9525 global.X_op = O_constant; 9526 global.X_op_symbol = NULL; 9527 global.X_add_symbol = NULL; 9528 global.X_add_number = local->X_add_number; 9529 9530 relax_start (local->X_add_symbol); 9531 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", 9532 dest, dest, BFD_RELOC_LO16); 9533 relax_switch (); 9534 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); 9535 relax_end (); 9536 } 9537 9538 static void 9539 add_got_offset_hilo (int dest, expressionS *local, int tmp) 9540 { 9541 expressionS global; 9542 int hold_mips_optimize; 9543 9544 global.X_op = O_constant; 9545 global.X_op_symbol = NULL; 9546 global.X_add_symbol = NULL; 9547 global.X_add_number = local->X_add_number; 9548 9549 relax_start (local->X_add_symbol); 9550 load_register (tmp, &global, HAVE_64BIT_ADDRESSES); 9551 relax_switch (); 9552 /* Set mips_optimize around the lui instruction to avoid 9553 inserting an unnecessary nop after the lw. */ 9554 hold_mips_optimize = mips_optimize; 9555 mips_optimize = 2; 9556 macro_build_lui (&global, tmp); 9557 mips_optimize = hold_mips_optimize; 9558 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); 9559 relax_end (); 9560 9561 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); 9562 } 9563 9564 /* Emit a sequence of instructions to emulate a branch likely operation. 9565 BR is an ordinary branch corresponding to one to be emulated. BRNEG 9566 is its complementing branch with the original condition negated. 9567 CALL is set if the original branch specified the link operation. 9568 EP, FMT, SREG and TREG specify the usual macro_build() parameters. 9569 9570 Code like this is produced in the noreorder mode: 9571 9572 BRNEG <args>, 1f 9573 nop 9574 b <sym> 9575 delay slot (executed only if branch taken) 9576 1: 9577 9578 or, if CALL is set: 9579 9580 BRNEG <args>, 1f 9581 nop 9582 bal <sym> 9583 delay slot (executed only if branch taken) 9584 1: 9585 9586 In the reorder mode the delay slot would be filled with a nop anyway, 9587 so code produced is simply: 9588 9589 BR <args>, <sym> 9590 nop 9591 9592 This function is used when producing code for the microMIPS ASE that 9593 does not implement branch likely instructions in hardware. */ 9594 9595 static void 9596 macro_build_branch_likely (const char *br, const char *brneg, 9597 int call, expressionS *ep, const char *fmt, 9598 unsigned int sreg, unsigned int treg) 9599 { 9600 int noreorder = mips_opts.noreorder; 9601 expressionS expr1; 9602 9603 gas_assert (mips_opts.micromips); 9604 start_noreorder (); 9605 if (noreorder) 9606 { 9607 micromips_label_expr (&expr1); 9608 macro_build (&expr1, brneg, fmt, sreg, treg); 9609 macro_build (NULL, "nop", ""); 9610 macro_build (ep, call ? "bal" : "b", "p"); 9611 9612 /* Set to true so that append_insn adds a label. */ 9613 emit_branch_likely_macro = TRUE; 9614 } 9615 else 9616 { 9617 macro_build (ep, br, fmt, sreg, treg); 9618 macro_build (NULL, "nop", ""); 9619 } 9620 end_noreorder (); 9621 } 9622 9623 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as 9624 the condition code tested. EP specifies the branch target. */ 9625 9626 static void 9627 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) 9628 { 9629 const int call = 0; 9630 const char *brneg; 9631 const char *br; 9632 9633 switch (type) 9634 { 9635 case M_BC1FL: 9636 br = "bc1f"; 9637 brneg = "bc1t"; 9638 break; 9639 case M_BC1TL: 9640 br = "bc1t"; 9641 brneg = "bc1f"; 9642 break; 9643 case M_BC2FL: 9644 br = "bc2f"; 9645 brneg = "bc2t"; 9646 break; 9647 case M_BC2TL: 9648 br = "bc2t"; 9649 brneg = "bc2f"; 9650 break; 9651 default: 9652 abort (); 9653 } 9654 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); 9655 } 9656 9657 /* Emit a two-argument branch macro specified by TYPE, using SREG as 9658 the register tested. EP specifies the branch target. */ 9659 9660 static void 9661 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) 9662 { 9663 const char *brneg = NULL; 9664 const char *br; 9665 int call = 0; 9666 9667 switch (type) 9668 { 9669 case M_BGEZ: 9670 br = "bgez"; 9671 break; 9672 case M_BGEZL: 9673 br = mips_opts.micromips ? "bgez" : "bgezl"; 9674 brneg = "bltz"; 9675 break; 9676 case M_BGEZALL: 9677 gas_assert (mips_opts.micromips); 9678 br = mips_opts.insn32 ? "bgezal" : "bgezals"; 9679 brneg = "bltz"; 9680 call = 1; 9681 break; 9682 case M_BGTZ: 9683 br = "bgtz"; 9684 break; 9685 case M_BGTZL: 9686 br = mips_opts.micromips ? "bgtz" : "bgtzl"; 9687 brneg = "blez"; 9688 break; 9689 case M_BLEZ: 9690 br = "blez"; 9691 break; 9692 case M_BLEZL: 9693 br = mips_opts.micromips ? "blez" : "blezl"; 9694 brneg = "bgtz"; 9695 break; 9696 case M_BLTZ: 9697 br = "bltz"; 9698 break; 9699 case M_BLTZL: 9700 br = mips_opts.micromips ? "bltz" : "bltzl"; 9701 brneg = "bgez"; 9702 break; 9703 case M_BLTZALL: 9704 gas_assert (mips_opts.micromips); 9705 br = mips_opts.insn32 ? "bltzal" : "bltzals"; 9706 brneg = "bgez"; 9707 call = 1; 9708 break; 9709 default: 9710 abort (); 9711 } 9712 if (mips_opts.micromips && brneg) 9713 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); 9714 else 9715 macro_build (ep, br, "s,p", sreg); 9716 } 9717 9718 /* Emit a three-argument branch macro specified by TYPE, using SREG and 9719 TREG as the registers tested. EP specifies the branch target. */ 9720 9721 static void 9722 macro_build_branch_rsrt (int type, expressionS *ep, 9723 unsigned int sreg, unsigned int treg) 9724 { 9725 const char *brneg = NULL; 9726 const int call = 0; 9727 const char *br; 9728 9729 switch (type) 9730 { 9731 case M_BEQ: 9732 case M_BEQ_I: 9733 br = "beq"; 9734 break; 9735 case M_BEQL: 9736 case M_BEQL_I: 9737 br = mips_opts.micromips ? "beq" : "beql"; 9738 brneg = "bne"; 9739 break; 9740 case M_BNE: 9741 case M_BNE_I: 9742 br = "bne"; 9743 break; 9744 case M_BNEL: 9745 case M_BNEL_I: 9746 br = mips_opts.micromips ? "bne" : "bnel"; 9747 brneg = "beq"; 9748 break; 9749 default: 9750 abort (); 9751 } 9752 if (mips_opts.micromips && brneg) 9753 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); 9754 else 9755 macro_build (ep, br, "s,t,p", sreg, treg); 9756 } 9757 9758 /* Return the high part that should be loaded in order to make the low 9759 part of VALUE accessible using an offset of OFFBITS bits. */ 9760 9761 static offsetT 9762 offset_high_part (offsetT value, unsigned int offbits) 9763 { 9764 offsetT bias; 9765 addressT low_mask; 9766 9767 if (offbits == 0) 9768 return value; 9769 bias = 1 << (offbits - 1); 9770 low_mask = bias * 2 - 1; 9771 return (value + bias) & ~low_mask; 9772 } 9773 9774 /* Return true if the value stored in offset_expr and offset_reloc 9775 fits into a signed offset of OFFBITS bits. RANGE is the maximum 9776 amount that the caller wants to add without inducing overflow 9777 and ALIGN is the known alignment of the value in bytes. */ 9778 9779 static bfd_boolean 9780 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) 9781 { 9782 if (offbits == 16) 9783 { 9784 /* Accept any relocation operator if overflow isn't a concern. */ 9785 if (range < align && *offset_reloc != BFD_RELOC_UNUSED) 9786 return TRUE; 9787 9788 /* These relocations are guaranteed not to overflow in correct links. */ 9789 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL 9790 || gprel16_reloc_p (*offset_reloc)) 9791 return TRUE; 9792 } 9793 if (offset_expr.X_op == O_constant 9794 && offset_high_part (offset_expr.X_add_number, offbits) == 0 9795 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) 9796 return TRUE; 9797 return FALSE; 9798 } 9799 9800 /* 9801 * Build macros 9802 * This routine implements the seemingly endless macro or synthesized 9803 * instructions and addressing modes in the mips assembly language. Many 9804 * of these macros are simple and are similar to each other. These could 9805 * probably be handled by some kind of table or grammar approach instead of 9806 * this verbose method. Others are not simple macros but are more like 9807 * optimizing code generation. 9808 * One interesting optimization is when several store macros appear 9809 * consecutively that would load AT with the upper half of the same address. 9810 * The ensuing load upper instructions are ommited. This implies some kind 9811 * of global optimization. We currently only optimize within a single macro. 9812 * For many of the load and store macros if the address is specified as a 9813 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we 9814 * first load register 'at' with zero and use it as the base register. The 9815 * mips assembler simply uses register $zero. Just one tiny optimization 9816 * we're missing. 9817 */ 9818 static void 9819 macro (struct mips_cl_insn *ip, char *str) 9820 { 9821 const struct mips_operand_array *operands; 9822 unsigned int breg, i; 9823 unsigned int tempreg; 9824 int mask; 9825 int used_at = 0; 9826 expressionS label_expr; 9827 expressionS expr1; 9828 expressionS *ep; 9829 const char *s; 9830 const char *s2; 9831 const char *fmt; 9832 int likely = 0; 9833 int coproc = 0; 9834 int offbits = 16; 9835 int call = 0; 9836 int jals = 0; 9837 int dbl = 0; 9838 int imm = 0; 9839 int ust = 0; 9840 int lp = 0; 9841 bfd_boolean large_offset; 9842 int off; 9843 int hold_mips_optimize; 9844 unsigned int align; 9845 unsigned int op[MAX_OPERANDS]; 9846 9847 gas_assert (! mips_opts.mips16); 9848 9849 operands = insn_operands (ip); 9850 for (i = 0; i < MAX_OPERANDS; i++) 9851 if (operands->operand[i]) 9852 op[i] = insn_extract_operand (ip, operands->operand[i]); 9853 else 9854 op[i] = -1; 9855 9856 mask = ip->insn_mo->mask; 9857 9858 label_expr.X_op = O_constant; 9859 label_expr.X_op_symbol = NULL; 9860 label_expr.X_add_symbol = NULL; 9861 label_expr.X_add_number = 0; 9862 9863 expr1.X_op = O_constant; 9864 expr1.X_op_symbol = NULL; 9865 expr1.X_add_symbol = NULL; 9866 expr1.X_add_number = 1; 9867 align = 1; 9868 9869 switch (mask) 9870 { 9871 case M_DABS: 9872 dbl = 1; 9873 case M_ABS: 9874 /* bgez $a0,1f 9875 move v0,$a0 9876 sub v0,$zero,$a0 9877 1: 9878 */ 9879 9880 start_noreorder (); 9881 9882 if (mips_opts.micromips) 9883 micromips_label_expr (&label_expr); 9884 else 9885 label_expr.X_add_number = 8; 9886 macro_build (&label_expr, "bgez", "s,p", op[1]); 9887 if (op[0] == op[1]) 9888 macro_build (NULL, "nop", ""); 9889 else 9890 move_register (op[0], op[1]); 9891 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); 9892 if (mips_opts.micromips) 9893 micromips_add_label (); 9894 9895 end_noreorder (); 9896 break; 9897 9898 case M_ADD_I: 9899 s = "addi"; 9900 s2 = "add"; 9901 goto do_addi; 9902 case M_ADDU_I: 9903 s = "addiu"; 9904 s2 = "addu"; 9905 goto do_addi; 9906 case M_DADD_I: 9907 dbl = 1; 9908 s = "daddi"; 9909 s2 = "dadd"; 9910 if (!mips_opts.micromips) 9911 goto do_addi; 9912 if (imm_expr.X_add_number >= -0x200 9913 && imm_expr.X_add_number < 0x200) 9914 { 9915 macro_build (NULL, s, "t,r,.", op[0], op[1], 9916 (int) imm_expr.X_add_number); 9917 break; 9918 } 9919 goto do_addi_i; 9920 case M_DADDU_I: 9921 dbl = 1; 9922 s = "daddiu"; 9923 s2 = "daddu"; 9924 do_addi: 9925 if (imm_expr.X_add_number >= -0x8000 9926 && imm_expr.X_add_number < 0x8000) 9927 { 9928 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 9929 break; 9930 } 9931 do_addi_i: 9932 used_at = 1; 9933 load_register (AT, &imm_expr, dbl); 9934 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 9935 break; 9936 9937 case M_AND_I: 9938 s = "andi"; 9939 s2 = "and"; 9940 goto do_bit; 9941 case M_OR_I: 9942 s = "ori"; 9943 s2 = "or"; 9944 goto do_bit; 9945 case M_NOR_I: 9946 s = ""; 9947 s2 = "nor"; 9948 goto do_bit; 9949 case M_XOR_I: 9950 s = "xori"; 9951 s2 = "xor"; 9952 do_bit: 9953 if (imm_expr.X_add_number >= 0 9954 && imm_expr.X_add_number < 0x10000) 9955 { 9956 if (mask != M_NOR_I) 9957 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); 9958 else 9959 { 9960 macro_build (&imm_expr, "ori", "t,r,i", 9961 op[0], op[1], BFD_RELOC_LO16); 9962 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); 9963 } 9964 break; 9965 } 9966 9967 used_at = 1; 9968 load_register (AT, &imm_expr, GPR_SIZE == 64); 9969 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 9970 break; 9971 9972 case M_BALIGN: 9973 switch (imm_expr.X_add_number) 9974 { 9975 case 0: 9976 macro_build (NULL, "nop", ""); 9977 break; 9978 case 2: 9979 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); 9980 break; 9981 case 1: 9982 case 3: 9983 macro_build (NULL, "balign", "t,s,2", op[0], op[1], 9984 (int) imm_expr.X_add_number); 9985 break; 9986 default: 9987 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), 9988 (unsigned long) imm_expr.X_add_number); 9989 break; 9990 } 9991 break; 9992 9993 case M_BC1FL: 9994 case M_BC1TL: 9995 case M_BC2FL: 9996 case M_BC2TL: 9997 gas_assert (mips_opts.micromips); 9998 macro_build_branch_ccl (mask, &offset_expr, 9999 EXTRACT_OPERAND (1, BCC, *ip)); 10000 break; 10001 10002 case M_BEQ_I: 10003 case M_BEQL_I: 10004 case M_BNE_I: 10005 case M_BNEL_I: 10006 if (imm_expr.X_add_number == 0) 10007 op[1] = 0; 10008 else 10009 { 10010 op[1] = AT; 10011 used_at = 1; 10012 load_register (op[1], &imm_expr, GPR_SIZE == 64); 10013 } 10014 /* Fall through. */ 10015 case M_BEQL: 10016 case M_BNEL: 10017 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); 10018 break; 10019 10020 case M_BGEL: 10021 likely = 1; 10022 case M_BGE: 10023 if (op[1] == 0) 10024 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); 10025 else if (op[0] == 0) 10026 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); 10027 else 10028 { 10029 used_at = 1; 10030 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 10031 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10032 &offset_expr, AT, ZERO); 10033 } 10034 break; 10035 10036 case M_BGEZL: 10037 case M_BGEZALL: 10038 case M_BGTZL: 10039 case M_BLEZL: 10040 case M_BLTZL: 10041 case M_BLTZALL: 10042 macro_build_branch_rs (mask, &offset_expr, op[0]); 10043 break; 10044 10045 case M_BGTL_I: 10046 likely = 1; 10047 case M_BGT_I: 10048 /* Check for > max integer. */ 10049 if (imm_expr.X_add_number >= GPR_SMAX) 10050 { 10051 do_false: 10052 /* Result is always false. */ 10053 if (! likely) 10054 macro_build (NULL, "nop", ""); 10055 else 10056 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); 10057 break; 10058 } 10059 ++imm_expr.X_add_number; 10060 /* FALLTHROUGH */ 10061 case M_BGE_I: 10062 case M_BGEL_I: 10063 if (mask == M_BGEL_I) 10064 likely = 1; 10065 if (imm_expr.X_add_number == 0) 10066 { 10067 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, 10068 &offset_expr, op[0]); 10069 break; 10070 } 10071 if (imm_expr.X_add_number == 1) 10072 { 10073 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, 10074 &offset_expr, op[0]); 10075 break; 10076 } 10077 if (imm_expr.X_add_number <= GPR_SMIN) 10078 { 10079 do_true: 10080 /* result is always true */ 10081 as_warn (_("branch %s is always true"), ip->insn_mo->name); 10082 macro_build (&offset_expr, "b", "p"); 10083 break; 10084 } 10085 used_at = 1; 10086 set_at (op[0], 0); 10087 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10088 &offset_expr, AT, ZERO); 10089 break; 10090 10091 case M_BGEUL: 10092 likely = 1; 10093 case M_BGEU: 10094 if (op[1] == 0) 10095 goto do_true; 10096 else if (op[0] == 0) 10097 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10098 &offset_expr, ZERO, op[1]); 10099 else 10100 { 10101 used_at = 1; 10102 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 10103 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10104 &offset_expr, AT, ZERO); 10105 } 10106 break; 10107 10108 case M_BGTUL_I: 10109 likely = 1; 10110 case M_BGTU_I: 10111 if (op[0] == 0 10112 || (GPR_SIZE == 32 10113 && imm_expr.X_add_number == -1)) 10114 goto do_false; 10115 ++imm_expr.X_add_number; 10116 /* FALLTHROUGH */ 10117 case M_BGEU_I: 10118 case M_BGEUL_I: 10119 if (mask == M_BGEUL_I) 10120 likely = 1; 10121 if (imm_expr.X_add_number == 0) 10122 goto do_true; 10123 else if (imm_expr.X_add_number == 1) 10124 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10125 &offset_expr, op[0], ZERO); 10126 else 10127 { 10128 used_at = 1; 10129 set_at (op[0], 1); 10130 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10131 &offset_expr, AT, ZERO); 10132 } 10133 break; 10134 10135 case M_BGTL: 10136 likely = 1; 10137 case M_BGT: 10138 if (op[1] == 0) 10139 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); 10140 else if (op[0] == 0) 10141 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); 10142 else 10143 { 10144 used_at = 1; 10145 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10146 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10147 &offset_expr, AT, ZERO); 10148 } 10149 break; 10150 10151 case M_BGTUL: 10152 likely = 1; 10153 case M_BGTU: 10154 if (op[1] == 0) 10155 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10156 &offset_expr, op[0], ZERO); 10157 else if (op[0] == 0) 10158 goto do_false; 10159 else 10160 { 10161 used_at = 1; 10162 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10163 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10164 &offset_expr, AT, ZERO); 10165 } 10166 break; 10167 10168 case M_BLEL: 10169 likely = 1; 10170 case M_BLE: 10171 if (op[1] == 0) 10172 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10173 else if (op[0] == 0) 10174 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); 10175 else 10176 { 10177 used_at = 1; 10178 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10179 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10180 &offset_expr, AT, ZERO); 10181 } 10182 break; 10183 10184 case M_BLEL_I: 10185 likely = 1; 10186 case M_BLE_I: 10187 if (imm_expr.X_add_number >= GPR_SMAX) 10188 goto do_true; 10189 ++imm_expr.X_add_number; 10190 /* FALLTHROUGH */ 10191 case M_BLT_I: 10192 case M_BLTL_I: 10193 if (mask == M_BLTL_I) 10194 likely = 1; 10195 if (imm_expr.X_add_number == 0) 10196 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10197 else if (imm_expr.X_add_number == 1) 10198 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10199 else 10200 { 10201 used_at = 1; 10202 set_at (op[0], 0); 10203 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10204 &offset_expr, AT, ZERO); 10205 } 10206 break; 10207 10208 case M_BLEUL: 10209 likely = 1; 10210 case M_BLEU: 10211 if (op[1] == 0) 10212 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10213 &offset_expr, op[0], ZERO); 10214 else if (op[0] == 0) 10215 goto do_true; 10216 else 10217 { 10218 used_at = 1; 10219 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10220 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10221 &offset_expr, AT, ZERO); 10222 } 10223 break; 10224 10225 case M_BLEUL_I: 10226 likely = 1; 10227 case M_BLEU_I: 10228 if (op[0] == 0 10229 || (GPR_SIZE == 32 10230 && imm_expr.X_add_number == -1)) 10231 goto do_true; 10232 ++imm_expr.X_add_number; 10233 /* FALLTHROUGH */ 10234 case M_BLTU_I: 10235 case M_BLTUL_I: 10236 if (mask == M_BLTUL_I) 10237 likely = 1; 10238 if (imm_expr.X_add_number == 0) 10239 goto do_false; 10240 else if (imm_expr.X_add_number == 1) 10241 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10242 &offset_expr, op[0], ZERO); 10243 else 10244 { 10245 used_at = 1; 10246 set_at (op[0], 1); 10247 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10248 &offset_expr, AT, ZERO); 10249 } 10250 break; 10251 10252 case M_BLTL: 10253 likely = 1; 10254 case M_BLT: 10255 if (op[1] == 0) 10256 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10257 else if (op[0] == 0) 10258 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); 10259 else 10260 { 10261 used_at = 1; 10262 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 10263 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10264 &offset_expr, AT, ZERO); 10265 } 10266 break; 10267 10268 case M_BLTUL: 10269 likely = 1; 10270 case M_BLTU: 10271 if (op[1] == 0) 10272 goto do_false; 10273 else if (op[0] == 0) 10274 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10275 &offset_expr, ZERO, op[1]); 10276 else 10277 { 10278 used_at = 1; 10279 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 10280 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10281 &offset_expr, AT, ZERO); 10282 } 10283 break; 10284 10285 case M_DDIV_3: 10286 dbl = 1; 10287 case M_DIV_3: 10288 s = "mflo"; 10289 goto do_div3; 10290 case M_DREM_3: 10291 dbl = 1; 10292 case M_REM_3: 10293 s = "mfhi"; 10294 do_div3: 10295 if (op[2] == 0) 10296 { 10297 as_warn (_("divide by zero")); 10298 if (mips_trap) 10299 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10300 else 10301 macro_build (NULL, "break", BRK_FMT, 7); 10302 break; 10303 } 10304 10305 start_noreorder (); 10306 if (mips_trap) 10307 { 10308 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 10309 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10310 } 10311 else 10312 { 10313 if (mips_opts.micromips) 10314 micromips_label_expr (&label_expr); 10315 else 10316 label_expr.X_add_number = 8; 10317 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 10318 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10319 macro_build (NULL, "break", BRK_FMT, 7); 10320 if (mips_opts.micromips) 10321 micromips_add_label (); 10322 } 10323 expr1.X_add_number = -1; 10324 used_at = 1; 10325 load_register (AT, &expr1, dbl); 10326 if (mips_opts.micromips) 10327 micromips_label_expr (&label_expr); 10328 else 10329 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); 10330 macro_build (&label_expr, "bne", "s,t,p", op[2], AT); 10331 if (dbl) 10332 { 10333 expr1.X_add_number = 1; 10334 load_register (AT, &expr1, dbl); 10335 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); 10336 } 10337 else 10338 { 10339 expr1.X_add_number = 0x80000000; 10340 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); 10341 } 10342 if (mips_trap) 10343 { 10344 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); 10345 /* We want to close the noreorder block as soon as possible, so 10346 that later insns are available for delay slot filling. */ 10347 end_noreorder (); 10348 } 10349 else 10350 { 10351 if (mips_opts.micromips) 10352 micromips_label_expr (&label_expr); 10353 else 10354 label_expr.X_add_number = 8; 10355 macro_build (&label_expr, "bne", "s,t,p", op[1], AT); 10356 macro_build (NULL, "nop", ""); 10357 10358 /* We want to close the noreorder block as soon as possible, so 10359 that later insns are available for delay slot filling. */ 10360 end_noreorder (); 10361 10362 macro_build (NULL, "break", BRK_FMT, 6); 10363 } 10364 if (mips_opts.micromips) 10365 micromips_add_label (); 10366 macro_build (NULL, s, MFHL_FMT, op[0]); 10367 break; 10368 10369 case M_DIV_3I: 10370 s = "div"; 10371 s2 = "mflo"; 10372 goto do_divi; 10373 case M_DIVU_3I: 10374 s = "divu"; 10375 s2 = "mflo"; 10376 goto do_divi; 10377 case M_REM_3I: 10378 s = "div"; 10379 s2 = "mfhi"; 10380 goto do_divi; 10381 case M_REMU_3I: 10382 s = "divu"; 10383 s2 = "mfhi"; 10384 goto do_divi; 10385 case M_DDIV_3I: 10386 dbl = 1; 10387 s = "ddiv"; 10388 s2 = "mflo"; 10389 goto do_divi; 10390 case M_DDIVU_3I: 10391 dbl = 1; 10392 s = "ddivu"; 10393 s2 = "mflo"; 10394 goto do_divi; 10395 case M_DREM_3I: 10396 dbl = 1; 10397 s = "ddiv"; 10398 s2 = "mfhi"; 10399 goto do_divi; 10400 case M_DREMU_3I: 10401 dbl = 1; 10402 s = "ddivu"; 10403 s2 = "mfhi"; 10404 do_divi: 10405 if (imm_expr.X_add_number == 0) 10406 { 10407 as_warn (_("divide by zero")); 10408 if (mips_trap) 10409 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10410 else 10411 macro_build (NULL, "break", BRK_FMT, 7); 10412 break; 10413 } 10414 if (imm_expr.X_add_number == 1) 10415 { 10416 if (strcmp (s2, "mflo") == 0) 10417 move_register (op[0], op[1]); 10418 else 10419 move_register (op[0], ZERO); 10420 break; 10421 } 10422 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') 10423 { 10424 if (strcmp (s2, "mflo") == 0) 10425 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); 10426 else 10427 move_register (op[0], ZERO); 10428 break; 10429 } 10430 10431 used_at = 1; 10432 load_register (AT, &imm_expr, dbl); 10433 macro_build (NULL, s, "z,s,t", op[1], AT); 10434 macro_build (NULL, s2, MFHL_FMT, op[0]); 10435 break; 10436 10437 case M_DIVU_3: 10438 s = "divu"; 10439 s2 = "mflo"; 10440 goto do_divu3; 10441 case M_REMU_3: 10442 s = "divu"; 10443 s2 = "mfhi"; 10444 goto do_divu3; 10445 case M_DDIVU_3: 10446 s = "ddivu"; 10447 s2 = "mflo"; 10448 goto do_divu3; 10449 case M_DREMU_3: 10450 s = "ddivu"; 10451 s2 = "mfhi"; 10452 do_divu3: 10453 start_noreorder (); 10454 if (mips_trap) 10455 { 10456 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 10457 macro_build (NULL, s, "z,s,t", op[1], op[2]); 10458 /* We want to close the noreorder block as soon as possible, so 10459 that later insns are available for delay slot filling. */ 10460 end_noreorder (); 10461 } 10462 else 10463 { 10464 if (mips_opts.micromips) 10465 micromips_label_expr (&label_expr); 10466 else 10467 label_expr.X_add_number = 8; 10468 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 10469 macro_build (NULL, s, "z,s,t", op[1], op[2]); 10470 10471 /* We want to close the noreorder block as soon as possible, so 10472 that later insns are available for delay slot filling. */ 10473 end_noreorder (); 10474 macro_build (NULL, "break", BRK_FMT, 7); 10475 if (mips_opts.micromips) 10476 micromips_add_label (); 10477 } 10478 macro_build (NULL, s2, MFHL_FMT, op[0]); 10479 break; 10480 10481 case M_DLCA_AB: 10482 dbl = 1; 10483 case M_LCA_AB: 10484 call = 1; 10485 goto do_la; 10486 case M_DLA_AB: 10487 dbl = 1; 10488 case M_LA_AB: 10489 do_la: 10490 /* Load the address of a symbol into a register. If breg is not 10491 zero, we then add a base register to it. */ 10492 10493 breg = op[2]; 10494 if (dbl && GPR_SIZE == 32) 10495 as_warn (_("dla used to load 32-bit register")); 10496 10497 if (!dbl && HAVE_64BIT_OBJECTS) 10498 as_warn (_("la used to load 64-bit address")); 10499 10500 if (small_offset_p (0, align, 16)) 10501 { 10502 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, 10503 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); 10504 break; 10505 } 10506 10507 if (mips_opts.at && (op[0] == breg)) 10508 { 10509 tempreg = AT; 10510 used_at = 1; 10511 } 10512 else 10513 tempreg = op[0]; 10514 10515 if (offset_expr.X_op != O_symbol 10516 && offset_expr.X_op != O_constant) 10517 { 10518 as_bad (_("expression too complex")); 10519 offset_expr.X_op = O_constant; 10520 } 10521 10522 if (offset_expr.X_op == O_constant) 10523 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); 10524 else if (mips_pic == NO_PIC) 10525 { 10526 /* If this is a reference to a GP relative symbol, we want 10527 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 10528 Otherwise we want 10529 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 10530 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10531 If we have a constant, we need two instructions anyhow, 10532 so we may as well always use the latter form. 10533 10534 With 64bit address space and a usable $at we want 10535 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 10536 lui $at,<sym> (BFD_RELOC_HI16_S) 10537 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 10538 daddiu $at,<sym> (BFD_RELOC_LO16) 10539 dsll32 $tempreg,0 10540 daddu $tempreg,$tempreg,$at 10541 10542 If $at is already in use, we use a path which is suboptimal 10543 on superscalar processors. 10544 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 10545 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 10546 dsll $tempreg,16 10547 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 10548 dsll $tempreg,16 10549 daddiu $tempreg,<sym> (BFD_RELOC_LO16) 10550 10551 For GP relative symbols in 64bit address space we can use 10552 the same sequence as in 32bit address space. */ 10553 if (HAVE_64BIT_SYMBOLS) 10554 { 10555 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 10556 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 10557 { 10558 relax_start (offset_expr.X_add_symbol); 10559 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10560 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 10561 relax_switch (); 10562 } 10563 10564 if (used_at == 0 && mips_opts.at) 10565 { 10566 macro_build (&offset_expr, "lui", LUI_FMT, 10567 tempreg, BFD_RELOC_MIPS_HIGHEST); 10568 macro_build (&offset_expr, "lui", LUI_FMT, 10569 AT, BFD_RELOC_HI16_S); 10570 macro_build (&offset_expr, "daddiu", "t,r,j", 10571 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 10572 macro_build (&offset_expr, "daddiu", "t,r,j", 10573 AT, AT, BFD_RELOC_LO16); 10574 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 10575 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 10576 used_at = 1; 10577 } 10578 else 10579 { 10580 macro_build (&offset_expr, "lui", LUI_FMT, 10581 tempreg, BFD_RELOC_MIPS_HIGHEST); 10582 macro_build (&offset_expr, "daddiu", "t,r,j", 10583 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 10584 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 10585 macro_build (&offset_expr, "daddiu", "t,r,j", 10586 tempreg, tempreg, BFD_RELOC_HI16_S); 10587 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 10588 macro_build (&offset_expr, "daddiu", "t,r,j", 10589 tempreg, tempreg, BFD_RELOC_LO16); 10590 } 10591 10592 if (mips_relax.sequence) 10593 relax_end (); 10594 } 10595 else 10596 { 10597 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 10598 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 10599 { 10600 relax_start (offset_expr.X_add_symbol); 10601 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10602 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 10603 relax_switch (); 10604 } 10605 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 10606 as_bad (_("offset too large")); 10607 macro_build_lui (&offset_expr, tempreg); 10608 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10609 tempreg, tempreg, BFD_RELOC_LO16); 10610 if (mips_relax.sequence) 10611 relax_end (); 10612 } 10613 } 10614 else if (!mips_big_got && !HAVE_NEWABI) 10615 { 10616 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 10617 10618 /* If this is a reference to an external symbol, and there 10619 is no constant, we want 10620 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10621 or for lca or if tempreg is PIC_CALL_REG 10622 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 10623 For a local symbol, we want 10624 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10625 nop 10626 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10627 10628 If we have a small constant, and this is a reference to 10629 an external symbol, we want 10630 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10631 nop 10632 addiu $tempreg,$tempreg,<constant> 10633 For a local symbol, we want the same instruction 10634 sequence, but we output a BFD_RELOC_LO16 reloc on the 10635 addiu instruction. 10636 10637 If we have a large constant, and this is a reference to 10638 an external symbol, we want 10639 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10640 lui $at,<hiconstant> 10641 addiu $at,$at,<loconstant> 10642 addu $tempreg,$tempreg,$at 10643 For a local symbol, we want the same instruction 10644 sequence, but we output a BFD_RELOC_LO16 reloc on the 10645 addiu instruction. 10646 */ 10647 10648 if (offset_expr.X_add_number == 0) 10649 { 10650 if (mips_pic == SVR4_PIC 10651 && breg == 0 10652 && (call || tempreg == PIC_CALL_REG)) 10653 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; 10654 10655 relax_start (offset_expr.X_add_symbol); 10656 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10657 lw_reloc_type, mips_gp_register); 10658 if (breg != 0) 10659 { 10660 /* We're going to put in an addu instruction using 10661 tempreg, so we may as well insert the nop right 10662 now. */ 10663 load_delay_nop (); 10664 } 10665 relax_switch (); 10666 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 10667 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); 10668 load_delay_nop (); 10669 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10670 tempreg, tempreg, BFD_RELOC_LO16); 10671 relax_end (); 10672 /* FIXME: If breg == 0, and the next instruction uses 10673 $tempreg, then if this variant case is used an extra 10674 nop will be generated. */ 10675 } 10676 else if (offset_expr.X_add_number >= -0x8000 10677 && offset_expr.X_add_number < 0x8000) 10678 { 10679 load_got_offset (tempreg, &offset_expr); 10680 load_delay_nop (); 10681 add_got_offset (tempreg, &offset_expr); 10682 } 10683 else 10684 { 10685 expr1.X_add_number = offset_expr.X_add_number; 10686 offset_expr.X_add_number = 10687 SEXT_16BIT (offset_expr.X_add_number); 10688 load_got_offset (tempreg, &offset_expr); 10689 offset_expr.X_add_number = expr1.X_add_number; 10690 /* If we are going to add in a base register, and the 10691 target register and the base register are the same, 10692 then we are using AT as a temporary register. Since 10693 we want to load the constant into AT, we add our 10694 current AT (from the global offset table) and the 10695 register into the register now, and pretend we were 10696 not using a base register. */ 10697 if (breg == op[0]) 10698 { 10699 load_delay_nop (); 10700 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10701 op[0], AT, breg); 10702 breg = 0; 10703 tempreg = op[0]; 10704 } 10705 add_got_offset_hilo (tempreg, &offset_expr, AT); 10706 used_at = 1; 10707 } 10708 } 10709 else if (!mips_big_got && HAVE_NEWABI) 10710 { 10711 int add_breg_early = 0; 10712 10713 /* If this is a reference to an external, and there is no 10714 constant, or local symbol (*), with or without a 10715 constant, we want 10716 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10717 or for lca or if tempreg is PIC_CALL_REG 10718 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 10719 10720 If we have a small constant, and this is a reference to 10721 an external symbol, we want 10722 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10723 addiu $tempreg,$tempreg,<constant> 10724 10725 If we have a large constant, and this is a reference to 10726 an external symbol, we want 10727 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 10728 lui $at,<hiconstant> 10729 addiu $at,$at,<loconstant> 10730 addu $tempreg,$tempreg,$at 10731 10732 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for 10733 local symbols, even though it introduces an additional 10734 instruction. */ 10735 10736 if (offset_expr.X_add_number) 10737 { 10738 expr1.X_add_number = offset_expr.X_add_number; 10739 offset_expr.X_add_number = 0; 10740 10741 relax_start (offset_expr.X_add_symbol); 10742 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10743 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10744 10745 if (expr1.X_add_number >= -0x8000 10746 && expr1.X_add_number < 0x8000) 10747 { 10748 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 10749 tempreg, tempreg, BFD_RELOC_LO16); 10750 } 10751 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 10752 { 10753 unsigned int dreg; 10754 10755 /* If we are going to add in a base register, and the 10756 target register and the base register are the same, 10757 then we are using AT as a temporary register. Since 10758 we want to load the constant into AT, we add our 10759 current AT (from the global offset table) and the 10760 register into the register now, and pretend we were 10761 not using a base register. */ 10762 if (breg != op[0]) 10763 dreg = tempreg; 10764 else 10765 { 10766 gas_assert (tempreg == AT); 10767 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10768 op[0], AT, breg); 10769 dreg = op[0]; 10770 add_breg_early = 1; 10771 } 10772 10773 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 10774 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10775 dreg, dreg, AT); 10776 10777 used_at = 1; 10778 } 10779 else 10780 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 10781 10782 relax_switch (); 10783 offset_expr.X_add_number = expr1.X_add_number; 10784 10785 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10786 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10787 if (add_breg_early) 10788 { 10789 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10790 op[0], tempreg, breg); 10791 breg = 0; 10792 tempreg = op[0]; 10793 } 10794 relax_end (); 10795 } 10796 else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 10797 { 10798 relax_start (offset_expr.X_add_symbol); 10799 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10800 BFD_RELOC_MIPS_CALL16, mips_gp_register); 10801 relax_switch (); 10802 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10803 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10804 relax_end (); 10805 } 10806 else 10807 { 10808 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10809 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 10810 } 10811 } 10812 else if (mips_big_got && !HAVE_NEWABI) 10813 { 10814 int gpdelay; 10815 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 10816 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 10817 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 10818 10819 /* This is the large GOT case. If this is a reference to an 10820 external symbol, and there is no constant, we want 10821 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10822 addu $tempreg,$tempreg,$gp 10823 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10824 or for lca or if tempreg is PIC_CALL_REG 10825 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 10826 addu $tempreg,$tempreg,$gp 10827 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 10828 For a local symbol, we want 10829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10830 nop 10831 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 10832 10833 If we have a small constant, and this is a reference to 10834 an external symbol, we want 10835 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10836 addu $tempreg,$tempreg,$gp 10837 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10838 nop 10839 addiu $tempreg,$tempreg,<constant> 10840 For a local symbol, we want 10841 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10842 nop 10843 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) 10844 10845 If we have a large constant, and this is a reference to 10846 an external symbol, we want 10847 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10848 addu $tempreg,$tempreg,$gp 10849 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10850 lui $at,<hiconstant> 10851 addiu $at,$at,<loconstant> 10852 addu $tempreg,$tempreg,$at 10853 For a local symbol, we want 10854 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 10855 lui $at,<hiconstant> 10856 addiu $at,$at,<loconstant> (BFD_RELOC_LO16) 10857 addu $tempreg,$tempreg,$at 10858 */ 10859 10860 expr1.X_add_number = offset_expr.X_add_number; 10861 offset_expr.X_add_number = 0; 10862 relax_start (offset_expr.X_add_symbol); 10863 gpdelay = reg_needs_delay (mips_gp_register); 10864 if (expr1.X_add_number == 0 && breg == 0 10865 && (call || tempreg == PIC_CALL_REG)) 10866 { 10867 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 10868 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 10869 } 10870 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 10871 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10872 tempreg, tempreg, mips_gp_register); 10873 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 10874 tempreg, lw_reloc_type, tempreg); 10875 if (expr1.X_add_number == 0) 10876 { 10877 if (breg != 0) 10878 { 10879 /* We're going to put in an addu instruction using 10880 tempreg, so we may as well insert the nop right 10881 now. */ 10882 load_delay_nop (); 10883 } 10884 } 10885 else if (expr1.X_add_number >= -0x8000 10886 && expr1.X_add_number < 0x8000) 10887 { 10888 load_delay_nop (); 10889 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 10890 tempreg, tempreg, BFD_RELOC_LO16); 10891 } 10892 else 10893 { 10894 unsigned int dreg; 10895 10896 /* If we are going to add in a base register, and the 10897 target register and the base register are the same, 10898 then we are using AT as a temporary register. Since 10899 we want to load the constant into AT, we add our 10900 current AT (from the global offset table) and the 10901 register into the register now, and pretend we were 10902 not using a base register. */ 10903 if (breg != op[0]) 10904 dreg = tempreg; 10905 else 10906 { 10907 gas_assert (tempreg == AT); 10908 load_delay_nop (); 10909 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10910 op[0], AT, breg); 10911 dreg = op[0]; 10912 } 10913 10914 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 10915 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 10916 10917 used_at = 1; 10918 } 10919 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); 10920 relax_switch (); 10921 10922 if (gpdelay) 10923 { 10924 /* This is needed because this instruction uses $gp, but 10925 the first instruction on the main stream does not. */ 10926 macro_build (NULL, "nop", ""); 10927 } 10928 10929 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 10930 local_reloc_type, mips_gp_register); 10931 if (expr1.X_add_number >= -0x8000 10932 && expr1.X_add_number < 0x8000) 10933 { 10934 load_delay_nop (); 10935 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10936 tempreg, tempreg, BFD_RELOC_LO16); 10937 /* FIXME: If add_number is 0, and there was no base 10938 register, the external symbol case ended with a load, 10939 so if the symbol turns out to not be external, and 10940 the next instruction uses tempreg, an unnecessary nop 10941 will be inserted. */ 10942 } 10943 else 10944 { 10945 if (breg == op[0]) 10946 { 10947 /* We must add in the base register now, as in the 10948 external symbol case. */ 10949 gas_assert (tempreg == AT); 10950 load_delay_nop (); 10951 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10952 op[0], AT, breg); 10953 tempreg = op[0]; 10954 /* We set breg to 0 because we have arranged to add 10955 it in in both cases. */ 10956 breg = 0; 10957 } 10958 10959 macro_build_lui (&expr1, AT); 10960 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 10961 AT, AT, BFD_RELOC_LO16); 10962 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 10963 tempreg, tempreg, AT); 10964 used_at = 1; 10965 } 10966 relax_end (); 10967 } 10968 else if (mips_big_got && HAVE_NEWABI) 10969 { 10970 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 10971 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 10972 int add_breg_early = 0; 10973 10974 /* This is the large GOT case. If this is a reference to an 10975 external symbol, and there is no constant, we want 10976 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10977 add $tempreg,$tempreg,$gp 10978 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10979 or for lca or if tempreg is PIC_CALL_REG 10980 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 10981 add $tempreg,$tempreg,$gp 10982 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 10983 10984 If we have a small constant, and this is a reference to 10985 an external symbol, we want 10986 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10987 add $tempreg,$tempreg,$gp 10988 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10989 addi $tempreg,$tempreg,<constant> 10990 10991 If we have a large constant, and this is a reference to 10992 an external symbol, we want 10993 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 10994 addu $tempreg,$tempreg,$gp 10995 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 10996 lui $at,<hiconstant> 10997 addi $at,$at,<loconstant> 10998 add $tempreg,$tempreg,$at 10999 11000 If we have NewABI, and we know it's a local symbol, we want 11001 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 11002 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 11003 otherwise we have to resort to GOT_HI16/GOT_LO16. */ 11004 11005 relax_start (offset_expr.X_add_symbol); 11006 11007 expr1.X_add_number = offset_expr.X_add_number; 11008 offset_expr.X_add_number = 0; 11009 11010 if (expr1.X_add_number == 0 && breg == 0 11011 && (call || tempreg == PIC_CALL_REG)) 11012 { 11013 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 11014 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 11015 } 11016 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 11017 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11018 tempreg, tempreg, mips_gp_register); 11019 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11020 tempreg, lw_reloc_type, tempreg); 11021 11022 if (expr1.X_add_number == 0) 11023 ; 11024 else if (expr1.X_add_number >= -0x8000 11025 && expr1.X_add_number < 0x8000) 11026 { 11027 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 11028 tempreg, tempreg, BFD_RELOC_LO16); 11029 } 11030 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 11031 { 11032 unsigned int dreg; 11033 11034 /* If we are going to add in a base register, and the 11035 target register and the base register are the same, 11036 then we are using AT as a temporary register. Since 11037 we want to load the constant into AT, we add our 11038 current AT (from the global offset table) and the 11039 register into the register now, and pretend we were 11040 not using a base register. */ 11041 if (breg != op[0]) 11042 dreg = tempreg; 11043 else 11044 { 11045 gas_assert (tempreg == AT); 11046 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11047 op[0], AT, breg); 11048 dreg = op[0]; 11049 add_breg_early = 1; 11050 } 11051 11052 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 11053 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 11054 11055 used_at = 1; 11056 } 11057 else 11058 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 11059 11060 relax_switch (); 11061 offset_expr.X_add_number = expr1.X_add_number; 11062 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11063 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 11064 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 11065 tempreg, BFD_RELOC_MIPS_GOT_OFST); 11066 if (add_breg_early) 11067 { 11068 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11069 op[0], tempreg, breg); 11070 breg = 0; 11071 tempreg = op[0]; 11072 } 11073 relax_end (); 11074 } 11075 else 11076 abort (); 11077 11078 if (breg != 0) 11079 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); 11080 break; 11081 11082 case M_MSGSND: 11083 gas_assert (!mips_opts.micromips); 11084 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); 11085 break; 11086 11087 case M_MSGLD: 11088 gas_assert (!mips_opts.micromips); 11089 macro_build (NULL, "c2", "C", 0x02); 11090 break; 11091 11092 case M_MSGLD_T: 11093 gas_assert (!mips_opts.micromips); 11094 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); 11095 break; 11096 11097 case M_MSGWAIT: 11098 gas_assert (!mips_opts.micromips); 11099 macro_build (NULL, "c2", "C", 3); 11100 break; 11101 11102 case M_MSGWAIT_T: 11103 gas_assert (!mips_opts.micromips); 11104 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); 11105 break; 11106 11107 case M_J_A: 11108 /* The j instruction may not be used in PIC code, since it 11109 requires an absolute address. We convert it to a b 11110 instruction. */ 11111 if (mips_pic == NO_PIC) 11112 macro_build (&offset_expr, "j", "a"); 11113 else 11114 macro_build (&offset_expr, "b", "p"); 11115 break; 11116 11117 /* The jal instructions must be handled as macros because when 11118 generating PIC code they expand to multi-instruction 11119 sequences. Normally they are simple instructions. */ 11120 case M_JALS_1: 11121 op[1] = op[0]; 11122 op[0] = RA; 11123 /* Fall through. */ 11124 case M_JALS_2: 11125 gas_assert (mips_opts.micromips); 11126 if (mips_opts.insn32) 11127 { 11128 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11129 break; 11130 } 11131 jals = 1; 11132 goto jal; 11133 case M_JAL_1: 11134 op[1] = op[0]; 11135 op[0] = RA; 11136 /* Fall through. */ 11137 case M_JAL_2: 11138 jal: 11139 if (mips_pic == NO_PIC) 11140 { 11141 s = jals ? "jalrs" : "jalr"; 11142 if (mips_opts.micromips 11143 && !mips_opts.insn32 11144 && op[0] == RA 11145 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11146 macro_build (NULL, s, "mj", op[1]); 11147 else 11148 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11149 } 11150 else 11151 { 11152 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI 11153 && mips_cprestore_offset >= 0); 11154 11155 if (op[1] != PIC_CALL_REG) 11156 as_warn (_("MIPS PIC call to register other than $25")); 11157 11158 s = ((mips_opts.micromips 11159 && !mips_opts.insn32 11160 && (!mips_opts.noreorder || cprestore)) 11161 ? "jalrs" : "jalr"); 11162 if (mips_opts.micromips 11163 && !mips_opts.insn32 11164 && op[0] == RA 11165 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11166 macro_build (NULL, s, "mj", op[1]); 11167 else 11168 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11169 if (mips_pic == SVR4_PIC && !HAVE_NEWABI) 11170 { 11171 if (mips_cprestore_offset < 0) 11172 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11173 else 11174 { 11175 if (!mips_frame_reg_valid) 11176 { 11177 as_warn (_("no .frame pseudo-op used in PIC code")); 11178 /* Quiet this warning. */ 11179 mips_frame_reg_valid = 1; 11180 } 11181 if (!mips_cprestore_valid) 11182 { 11183 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11184 /* Quiet this warning. */ 11185 mips_cprestore_valid = 1; 11186 } 11187 if (mips_opts.noreorder) 11188 macro_build (NULL, "nop", ""); 11189 expr1.X_add_number = mips_cprestore_offset; 11190 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11191 mips_gp_register, 11192 mips_frame_reg, 11193 HAVE_64BIT_ADDRESSES); 11194 } 11195 } 11196 } 11197 11198 break; 11199 11200 case M_JALS_A: 11201 gas_assert (mips_opts.micromips); 11202 if (mips_opts.insn32) 11203 { 11204 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11205 break; 11206 } 11207 jals = 1; 11208 /* Fall through. */ 11209 case M_JAL_A: 11210 if (mips_pic == NO_PIC) 11211 macro_build (&offset_expr, jals ? "jals" : "jal", "a"); 11212 else if (mips_pic == SVR4_PIC) 11213 { 11214 /* If this is a reference to an external symbol, and we are 11215 using a small GOT, we want 11216 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 11217 nop 11218 jalr $ra,$25 11219 nop 11220 lw $gp,cprestore($sp) 11221 The cprestore value is set using the .cprestore 11222 pseudo-op. If we are using a big GOT, we want 11223 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) 11224 addu $25,$25,$gp 11225 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) 11226 nop 11227 jalr $ra,$25 11228 nop 11229 lw $gp,cprestore($sp) 11230 If the symbol is not external, we want 11231 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11232 nop 11233 addiu $25,$25,<sym> (BFD_RELOC_LO16) 11234 jalr $ra,$25 11235 nop 11236 lw $gp,cprestore($sp) 11237 11238 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 11239 sequences above, minus nops, unless the symbol is local, 11240 which enables us to use GOT_PAGE/GOT_OFST (big got) or 11241 GOT_DISP. */ 11242 if (HAVE_NEWABI) 11243 { 11244 if (!mips_big_got) 11245 { 11246 relax_start (offset_expr.X_add_symbol); 11247 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11248 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11249 mips_gp_register); 11250 relax_switch (); 11251 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11252 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, 11253 mips_gp_register); 11254 relax_end (); 11255 } 11256 else 11257 { 11258 relax_start (offset_expr.X_add_symbol); 11259 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11260 BFD_RELOC_MIPS_CALL_HI16); 11261 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11262 PIC_CALL_REG, mips_gp_register); 11263 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11264 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11265 PIC_CALL_REG); 11266 relax_switch (); 11267 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11268 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, 11269 mips_gp_register); 11270 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11271 PIC_CALL_REG, PIC_CALL_REG, 11272 BFD_RELOC_MIPS_GOT_OFST); 11273 relax_end (); 11274 } 11275 11276 macro_build_jalr (&offset_expr, 0); 11277 } 11278 else 11279 { 11280 relax_start (offset_expr.X_add_symbol); 11281 if (!mips_big_got) 11282 { 11283 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11284 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11285 mips_gp_register); 11286 load_delay_nop (); 11287 relax_switch (); 11288 } 11289 else 11290 { 11291 int gpdelay; 11292 11293 gpdelay = reg_needs_delay (mips_gp_register); 11294 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11295 BFD_RELOC_MIPS_CALL_HI16); 11296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11297 PIC_CALL_REG, mips_gp_register); 11298 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11299 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11300 PIC_CALL_REG); 11301 load_delay_nop (); 11302 relax_switch (); 11303 if (gpdelay) 11304 macro_build (NULL, "nop", ""); 11305 } 11306 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11307 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, 11308 mips_gp_register); 11309 load_delay_nop (); 11310 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11311 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); 11312 relax_end (); 11313 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); 11314 11315 if (mips_cprestore_offset < 0) 11316 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11317 else 11318 { 11319 if (!mips_frame_reg_valid) 11320 { 11321 as_warn (_("no .frame pseudo-op used in PIC code")); 11322 /* Quiet this warning. */ 11323 mips_frame_reg_valid = 1; 11324 } 11325 if (!mips_cprestore_valid) 11326 { 11327 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11328 /* Quiet this warning. */ 11329 mips_cprestore_valid = 1; 11330 } 11331 if (mips_opts.noreorder) 11332 macro_build (NULL, "nop", ""); 11333 expr1.X_add_number = mips_cprestore_offset; 11334 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11335 mips_gp_register, 11336 mips_frame_reg, 11337 HAVE_64BIT_ADDRESSES); 11338 } 11339 } 11340 } 11341 else if (mips_pic == VXWORKS_PIC) 11342 as_bad (_("non-PIC jump used in PIC library")); 11343 else 11344 abort (); 11345 11346 break; 11347 11348 case M_LBUE_AB: 11349 s = "lbue"; 11350 fmt = "t,+j(b)"; 11351 offbits = 9; 11352 goto ld_st; 11353 case M_LHUE_AB: 11354 s = "lhue"; 11355 fmt = "t,+j(b)"; 11356 offbits = 9; 11357 goto ld_st; 11358 case M_LBE_AB: 11359 s = "lbe"; 11360 fmt = "t,+j(b)"; 11361 offbits = 9; 11362 goto ld_st; 11363 case M_LHE_AB: 11364 s = "lhe"; 11365 fmt = "t,+j(b)"; 11366 offbits = 9; 11367 goto ld_st; 11368 case M_LLE_AB: 11369 s = "lle"; 11370 fmt = "t,+j(b)"; 11371 offbits = 9; 11372 goto ld_st; 11373 case M_LWE_AB: 11374 s = "lwe"; 11375 fmt = "t,+j(b)"; 11376 offbits = 9; 11377 goto ld_st; 11378 case M_LWLE_AB: 11379 s = "lwle"; 11380 fmt = "t,+j(b)"; 11381 offbits = 9; 11382 goto ld_st; 11383 case M_LWRE_AB: 11384 s = "lwre"; 11385 fmt = "t,+j(b)"; 11386 offbits = 9; 11387 goto ld_st; 11388 case M_SBE_AB: 11389 s = "sbe"; 11390 fmt = "t,+j(b)"; 11391 offbits = 9; 11392 goto ld_st; 11393 case M_SCE_AB: 11394 s = "sce"; 11395 fmt = "t,+j(b)"; 11396 offbits = 9; 11397 goto ld_st; 11398 case M_SHE_AB: 11399 s = "she"; 11400 fmt = "t,+j(b)"; 11401 offbits = 9; 11402 goto ld_st; 11403 case M_SWE_AB: 11404 s = "swe"; 11405 fmt = "t,+j(b)"; 11406 offbits = 9; 11407 goto ld_st; 11408 case M_SWLE_AB: 11409 s = "swle"; 11410 fmt = "t,+j(b)"; 11411 offbits = 9; 11412 goto ld_st; 11413 case M_SWRE_AB: 11414 s = "swre"; 11415 fmt = "t,+j(b)"; 11416 offbits = 9; 11417 goto ld_st; 11418 case M_ACLR_AB: 11419 s = "aclr"; 11420 fmt = "\\,~(b)"; 11421 offbits = 12; 11422 goto ld_st; 11423 case M_ASET_AB: 11424 s = "aset"; 11425 fmt = "\\,~(b)"; 11426 offbits = 12; 11427 goto ld_st; 11428 case M_LB_AB: 11429 s = "lb"; 11430 fmt = "t,o(b)"; 11431 goto ld; 11432 case M_LBU_AB: 11433 s = "lbu"; 11434 fmt = "t,o(b)"; 11435 goto ld; 11436 case M_LH_AB: 11437 s = "lh"; 11438 fmt = "t,o(b)"; 11439 goto ld; 11440 case M_LHU_AB: 11441 s = "lhu"; 11442 fmt = "t,o(b)"; 11443 goto ld; 11444 case M_LW_AB: 11445 s = "lw"; 11446 fmt = "t,o(b)"; 11447 goto ld; 11448 case M_LWC0_AB: 11449 gas_assert (!mips_opts.micromips); 11450 s = "lwc0"; 11451 fmt = "E,o(b)"; 11452 /* Itbl support may require additional care here. */ 11453 coproc = 1; 11454 goto ld_st; 11455 case M_LWC1_AB: 11456 s = "lwc1"; 11457 fmt = "T,o(b)"; 11458 /* Itbl support may require additional care here. */ 11459 coproc = 1; 11460 goto ld_st; 11461 case M_LWC2_AB: 11462 s = "lwc2"; 11463 fmt = COP12_FMT; 11464 offbits = (mips_opts.micromips ? 12 11465 : ISA_IS_R6 (mips_opts.isa) ? 11 11466 : 16); 11467 /* Itbl support may require additional care here. */ 11468 coproc = 1; 11469 goto ld_st; 11470 case M_LWC3_AB: 11471 gas_assert (!mips_opts.micromips); 11472 s = "lwc3"; 11473 fmt = "E,o(b)"; 11474 /* Itbl support may require additional care here. */ 11475 coproc = 1; 11476 goto ld_st; 11477 case M_LWL_AB: 11478 s = "lwl"; 11479 fmt = MEM12_FMT; 11480 offbits = (mips_opts.micromips ? 12 : 16); 11481 goto ld_st; 11482 case M_LWR_AB: 11483 s = "lwr"; 11484 fmt = MEM12_FMT; 11485 offbits = (mips_opts.micromips ? 12 : 16); 11486 goto ld_st; 11487 case M_LDC1_AB: 11488 s = "ldc1"; 11489 fmt = "T,o(b)"; 11490 /* Itbl support may require additional care here. */ 11491 coproc = 1; 11492 goto ld_st; 11493 case M_LDC2_AB: 11494 s = "ldc2"; 11495 fmt = COP12_FMT; 11496 offbits = (mips_opts.micromips ? 12 11497 : ISA_IS_R6 (mips_opts.isa) ? 11 11498 : 16); 11499 /* Itbl support may require additional care here. */ 11500 coproc = 1; 11501 goto ld_st; 11502 case M_LQC2_AB: 11503 s = "lqc2"; 11504 fmt = "+7,o(b)"; 11505 /* Itbl support may require additional care here. */ 11506 coproc = 1; 11507 goto ld_st; 11508 case M_LDC3_AB: 11509 s = "ldc3"; 11510 fmt = "E,o(b)"; 11511 /* Itbl support may require additional care here. */ 11512 coproc = 1; 11513 goto ld_st; 11514 case M_LDL_AB: 11515 s = "ldl"; 11516 fmt = MEM12_FMT; 11517 offbits = (mips_opts.micromips ? 12 : 16); 11518 goto ld_st; 11519 case M_LDR_AB: 11520 s = "ldr"; 11521 fmt = MEM12_FMT; 11522 offbits = (mips_opts.micromips ? 12 : 16); 11523 goto ld_st; 11524 case M_LL_AB: 11525 s = "ll"; 11526 fmt = LL_SC_FMT; 11527 offbits = (mips_opts.micromips ? 12 11528 : ISA_IS_R6 (mips_opts.isa) ? 9 11529 : 16); 11530 goto ld; 11531 case M_LLD_AB: 11532 s = "lld"; 11533 fmt = LL_SC_FMT; 11534 offbits = (mips_opts.micromips ? 12 11535 : ISA_IS_R6 (mips_opts.isa) ? 9 11536 : 16); 11537 goto ld; 11538 case M_LWU_AB: 11539 s = "lwu"; 11540 fmt = MEM12_FMT; 11541 offbits = (mips_opts.micromips ? 12 : 16); 11542 goto ld; 11543 case M_LWP_AB: 11544 gas_assert (mips_opts.micromips); 11545 s = "lwp"; 11546 fmt = "t,~(b)"; 11547 offbits = 12; 11548 lp = 1; 11549 goto ld; 11550 case M_LDP_AB: 11551 gas_assert (mips_opts.micromips); 11552 s = "ldp"; 11553 fmt = "t,~(b)"; 11554 offbits = 12; 11555 lp = 1; 11556 goto ld; 11557 case M_LWM_AB: 11558 gas_assert (mips_opts.micromips); 11559 s = "lwm"; 11560 fmt = "n,~(b)"; 11561 offbits = 12; 11562 goto ld_st; 11563 case M_LDM_AB: 11564 gas_assert (mips_opts.micromips); 11565 s = "ldm"; 11566 fmt = "n,~(b)"; 11567 offbits = 12; 11568 goto ld_st; 11569 11570 ld: 11571 /* We don't want to use $0 as tempreg. */ 11572 if (op[2] == op[0] + lp || op[0] + lp == ZERO) 11573 goto ld_st; 11574 else 11575 tempreg = op[0] + lp; 11576 goto ld_noat; 11577 11578 case M_SB_AB: 11579 s = "sb"; 11580 fmt = "t,o(b)"; 11581 goto ld_st; 11582 case M_SH_AB: 11583 s = "sh"; 11584 fmt = "t,o(b)"; 11585 goto ld_st; 11586 case M_SW_AB: 11587 s = "sw"; 11588 fmt = "t,o(b)"; 11589 goto ld_st; 11590 case M_SWC0_AB: 11591 gas_assert (!mips_opts.micromips); 11592 s = "swc0"; 11593 fmt = "E,o(b)"; 11594 /* Itbl support may require additional care here. */ 11595 coproc = 1; 11596 goto ld_st; 11597 case M_SWC1_AB: 11598 s = "swc1"; 11599 fmt = "T,o(b)"; 11600 /* Itbl support may require additional care here. */ 11601 coproc = 1; 11602 goto ld_st; 11603 case M_SWC2_AB: 11604 s = "swc2"; 11605 fmt = COP12_FMT; 11606 offbits = (mips_opts.micromips ? 12 11607 : ISA_IS_R6 (mips_opts.isa) ? 11 11608 : 16); 11609 /* Itbl support may require additional care here. */ 11610 coproc = 1; 11611 goto ld_st; 11612 case M_SWC3_AB: 11613 gas_assert (!mips_opts.micromips); 11614 s = "swc3"; 11615 fmt = "E,o(b)"; 11616 /* Itbl support may require additional care here. */ 11617 coproc = 1; 11618 goto ld_st; 11619 case M_SWL_AB: 11620 s = "swl"; 11621 fmt = MEM12_FMT; 11622 offbits = (mips_opts.micromips ? 12 : 16); 11623 goto ld_st; 11624 case M_SWR_AB: 11625 s = "swr"; 11626 fmt = MEM12_FMT; 11627 offbits = (mips_opts.micromips ? 12 : 16); 11628 goto ld_st; 11629 case M_SC_AB: 11630 s = "sc"; 11631 fmt = LL_SC_FMT; 11632 offbits = (mips_opts.micromips ? 12 11633 : ISA_IS_R6 (mips_opts.isa) ? 9 11634 : 16); 11635 goto ld_st; 11636 case M_SCD_AB: 11637 s = "scd"; 11638 fmt = LL_SC_FMT; 11639 offbits = (mips_opts.micromips ? 12 11640 : ISA_IS_R6 (mips_opts.isa) ? 9 11641 : 16); 11642 goto ld_st; 11643 case M_CACHE_AB: 11644 s = "cache"; 11645 fmt = (mips_opts.micromips ? "k,~(b)" 11646 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 11647 : "k,o(b)"); 11648 offbits = (mips_opts.micromips ? 12 11649 : ISA_IS_R6 (mips_opts.isa) ? 9 11650 : 16); 11651 goto ld_st; 11652 case M_CACHEE_AB: 11653 s = "cachee"; 11654 fmt = "k,+j(b)"; 11655 offbits = 9; 11656 goto ld_st; 11657 case M_PREF_AB: 11658 s = "pref"; 11659 fmt = (mips_opts.micromips ? "k,~(b)" 11660 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 11661 : "k,o(b)"); 11662 offbits = (mips_opts.micromips ? 12 11663 : ISA_IS_R6 (mips_opts.isa) ? 9 11664 : 16); 11665 goto ld_st; 11666 case M_PREFE_AB: 11667 s = "prefe"; 11668 fmt = "k,+j(b)"; 11669 offbits = 9; 11670 goto ld_st; 11671 case M_SDC1_AB: 11672 s = "sdc1"; 11673 fmt = "T,o(b)"; 11674 coproc = 1; 11675 /* Itbl support may require additional care here. */ 11676 goto ld_st; 11677 case M_SDC2_AB: 11678 s = "sdc2"; 11679 fmt = COP12_FMT; 11680 offbits = (mips_opts.micromips ? 12 11681 : ISA_IS_R6 (mips_opts.isa) ? 11 11682 : 16); 11683 /* Itbl support may require additional care here. */ 11684 coproc = 1; 11685 goto ld_st; 11686 case M_SQC2_AB: 11687 s = "sqc2"; 11688 fmt = "+7,o(b)"; 11689 /* Itbl support may require additional care here. */ 11690 coproc = 1; 11691 goto ld_st; 11692 case M_SDC3_AB: 11693 gas_assert (!mips_opts.micromips); 11694 s = "sdc3"; 11695 fmt = "E,o(b)"; 11696 /* Itbl support may require additional care here. */ 11697 coproc = 1; 11698 goto ld_st; 11699 case M_SDL_AB: 11700 s = "sdl"; 11701 fmt = MEM12_FMT; 11702 offbits = (mips_opts.micromips ? 12 : 16); 11703 goto ld_st; 11704 case M_SDR_AB: 11705 s = "sdr"; 11706 fmt = MEM12_FMT; 11707 offbits = (mips_opts.micromips ? 12 : 16); 11708 goto ld_st; 11709 case M_SWP_AB: 11710 gas_assert (mips_opts.micromips); 11711 s = "swp"; 11712 fmt = "t,~(b)"; 11713 offbits = 12; 11714 goto ld_st; 11715 case M_SDP_AB: 11716 gas_assert (mips_opts.micromips); 11717 s = "sdp"; 11718 fmt = "t,~(b)"; 11719 offbits = 12; 11720 goto ld_st; 11721 case M_SWM_AB: 11722 gas_assert (mips_opts.micromips); 11723 s = "swm"; 11724 fmt = "n,~(b)"; 11725 offbits = 12; 11726 goto ld_st; 11727 case M_SDM_AB: 11728 gas_assert (mips_opts.micromips); 11729 s = "sdm"; 11730 fmt = "n,~(b)"; 11731 offbits = 12; 11732 11733 ld_st: 11734 tempreg = AT; 11735 ld_noat: 11736 breg = op[2]; 11737 if (small_offset_p (0, align, 16)) 11738 { 11739 /* The first case exists for M_LD_AB and M_SD_AB, which are 11740 macros for o32 but which should act like normal instructions 11741 otherwise. */ 11742 if (offbits == 16) 11743 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], 11744 offset_reloc[1], offset_reloc[2], breg); 11745 else if (small_offset_p (0, align, offbits)) 11746 { 11747 if (offbits == 0) 11748 macro_build (NULL, s, fmt, op[0], breg); 11749 else 11750 macro_build (NULL, s, fmt, op[0], 11751 (int) offset_expr.X_add_number, breg); 11752 } 11753 else 11754 { 11755 if (tempreg == AT) 11756 used_at = 1; 11757 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11758 tempreg, breg, -1, offset_reloc[0], 11759 offset_reloc[1], offset_reloc[2]); 11760 if (offbits == 0) 11761 macro_build (NULL, s, fmt, op[0], tempreg); 11762 else 11763 macro_build (NULL, s, fmt, op[0], 0, tempreg); 11764 } 11765 break; 11766 } 11767 11768 if (tempreg == AT) 11769 used_at = 1; 11770 11771 if (offset_expr.X_op != O_constant 11772 && offset_expr.X_op != O_symbol) 11773 { 11774 as_bad (_("expression too complex")); 11775 offset_expr.X_op = O_constant; 11776 } 11777 11778 if (HAVE_32BIT_ADDRESSES 11779 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 11780 { 11781 char value [32]; 11782 11783 sprintf_vma (value, offset_expr.X_add_number); 11784 as_bad (_("number (0x%s) larger than 32 bits"), value); 11785 } 11786 11787 /* A constant expression in PIC code can be handled just as it 11788 is in non PIC code. */ 11789 if (offset_expr.X_op == O_constant) 11790 { 11791 expr1.X_add_number = offset_high_part (offset_expr.X_add_number, 11792 offbits == 0 ? 16 : offbits); 11793 offset_expr.X_add_number -= expr1.X_add_number; 11794 11795 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); 11796 if (breg != 0) 11797 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11798 tempreg, tempreg, breg); 11799 if (offbits == 0) 11800 { 11801 if (offset_expr.X_add_number != 0) 11802 macro_build (&offset_expr, ADDRESS_ADDI_INSN, 11803 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); 11804 macro_build (NULL, s, fmt, op[0], tempreg); 11805 } 11806 else if (offbits == 16) 11807 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 11808 else 11809 macro_build (NULL, s, fmt, op[0], 11810 (int) offset_expr.X_add_number, tempreg); 11811 } 11812 else if (offbits != 16) 11813 { 11814 /* The offset field is too narrow to be used for a low-part 11815 relocation, so load the whole address into the auxillary 11816 register. */ 11817 load_address (tempreg, &offset_expr, &used_at); 11818 if (breg != 0) 11819 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11820 tempreg, tempreg, breg); 11821 if (offbits == 0) 11822 macro_build (NULL, s, fmt, op[0], tempreg); 11823 else 11824 macro_build (NULL, s, fmt, op[0], 0, tempreg); 11825 } 11826 else if (mips_pic == NO_PIC) 11827 { 11828 /* If this is a reference to a GP relative symbol, and there 11829 is no base register, we want 11830 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 11831 Otherwise, if there is no base register, we want 11832 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 11833 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11834 If we have a constant, we need two instructions anyhow, 11835 so we always use the latter form. 11836 11837 If we have a base register, and this is a reference to a 11838 GP relative symbol, we want 11839 addu $tempreg,$breg,$gp 11840 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) 11841 Otherwise we want 11842 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 11843 addu $tempreg,$tempreg,$breg 11844 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11845 With a constant we always use the latter case. 11846 11847 With 64bit address space and no base register and $at usable, 11848 we want 11849 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11850 lui $at,<sym> (BFD_RELOC_HI16_S) 11851 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11852 dsll32 $tempreg,0 11853 daddu $tempreg,$at 11854 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11855 If we have a base register, we want 11856 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11857 lui $at,<sym> (BFD_RELOC_HI16_S) 11858 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11859 daddu $at,$breg 11860 dsll32 $tempreg,0 11861 daddu $tempreg,$at 11862 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11863 11864 Without $at we can't generate the optimal path for superscalar 11865 processors here since this would require two temporary registers. 11866 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11867 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11868 dsll $tempreg,16 11869 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 11870 dsll $tempreg,16 11871 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11872 If we have a base register, we want 11873 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11874 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11875 dsll $tempreg,16 11876 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 11877 dsll $tempreg,16 11878 daddu $tempreg,$tempreg,$breg 11879 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 11880 11881 For GP relative symbols in 64bit address space we can use 11882 the same sequence as in 32bit address space. */ 11883 if (HAVE_64BIT_SYMBOLS) 11884 { 11885 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11886 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11887 { 11888 relax_start (offset_expr.X_add_symbol); 11889 if (breg == 0) 11890 { 11891 macro_build (&offset_expr, s, fmt, op[0], 11892 BFD_RELOC_GPREL16, mips_gp_register); 11893 } 11894 else 11895 { 11896 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11897 tempreg, breg, mips_gp_register); 11898 macro_build (&offset_expr, s, fmt, op[0], 11899 BFD_RELOC_GPREL16, tempreg); 11900 } 11901 relax_switch (); 11902 } 11903 11904 if (used_at == 0 && mips_opts.at) 11905 { 11906 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11907 BFD_RELOC_MIPS_HIGHEST); 11908 macro_build (&offset_expr, "lui", LUI_FMT, AT, 11909 BFD_RELOC_HI16_S); 11910 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11911 tempreg, BFD_RELOC_MIPS_HIGHER); 11912 if (breg != 0) 11913 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); 11914 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 11915 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 11916 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, 11917 tempreg); 11918 used_at = 1; 11919 } 11920 else 11921 { 11922 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 11923 BFD_RELOC_MIPS_HIGHEST); 11924 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11925 tempreg, BFD_RELOC_MIPS_HIGHER); 11926 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11927 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 11928 tempreg, BFD_RELOC_HI16_S); 11929 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11930 if (breg != 0) 11931 macro_build (NULL, "daddu", "d,v,t", 11932 tempreg, tempreg, breg); 11933 macro_build (&offset_expr, s, fmt, op[0], 11934 BFD_RELOC_LO16, tempreg); 11935 } 11936 11937 if (mips_relax.sequence) 11938 relax_end (); 11939 break; 11940 } 11941 11942 if (breg == 0) 11943 { 11944 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11945 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11946 { 11947 relax_start (offset_expr.X_add_symbol); 11948 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, 11949 mips_gp_register); 11950 relax_switch (); 11951 } 11952 macro_build_lui (&offset_expr, tempreg); 11953 macro_build (&offset_expr, s, fmt, op[0], 11954 BFD_RELOC_LO16, tempreg); 11955 if (mips_relax.sequence) 11956 relax_end (); 11957 } 11958 else 11959 { 11960 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11961 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11962 { 11963 relax_start (offset_expr.X_add_symbol); 11964 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11965 tempreg, breg, mips_gp_register); 11966 macro_build (&offset_expr, s, fmt, op[0], 11967 BFD_RELOC_GPREL16, tempreg); 11968 relax_switch (); 11969 } 11970 macro_build_lui (&offset_expr, tempreg); 11971 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11972 tempreg, tempreg, breg); 11973 macro_build (&offset_expr, s, fmt, op[0], 11974 BFD_RELOC_LO16, tempreg); 11975 if (mips_relax.sequence) 11976 relax_end (); 11977 } 11978 } 11979 else if (!mips_big_got) 11980 { 11981 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 11982 11983 /* If this is a reference to an external symbol, we want 11984 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11985 nop 11986 <op> op[0],0($tempreg) 11987 Otherwise we want 11988 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11989 nop 11990 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 11991 <op> op[0],0($tempreg) 11992 11993 For NewABI, we want 11994 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 11995 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) 11996 11997 If there is a base register, we add it to $tempreg before 11998 the <op>. If there is a constant, we stick it in the 11999 <op> instruction. We don't handle constants larger than 12000 16 bits, because we have no way to load the upper 16 bits 12001 (actually, we could handle them for the subset of cases 12002 in which we are not using $at). */ 12003 gas_assert (offset_expr.X_op == O_symbol); 12004 if (HAVE_NEWABI) 12005 { 12006 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12007 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 12008 if (breg != 0) 12009 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12010 tempreg, tempreg, breg); 12011 macro_build (&offset_expr, s, fmt, op[0], 12012 BFD_RELOC_MIPS_GOT_OFST, tempreg); 12013 break; 12014 } 12015 expr1.X_add_number = offset_expr.X_add_number; 12016 offset_expr.X_add_number = 0; 12017 if (expr1.X_add_number < -0x8000 12018 || expr1.X_add_number >= 0x8000) 12019 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12020 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12021 lw_reloc_type, mips_gp_register); 12022 load_delay_nop (); 12023 relax_start (offset_expr.X_add_symbol); 12024 relax_switch (); 12025 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 12026 tempreg, BFD_RELOC_LO16); 12027 relax_end (); 12028 if (breg != 0) 12029 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12030 tempreg, tempreg, breg); 12031 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12032 } 12033 else if (mips_big_got && !HAVE_NEWABI) 12034 { 12035 int gpdelay; 12036 12037 /* If this is a reference to an external symbol, we want 12038 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12039 addu $tempreg,$tempreg,$gp 12040 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 12041 <op> op[0],0($tempreg) 12042 Otherwise we want 12043 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12044 nop 12045 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 12046 <op> op[0],0($tempreg) 12047 If there is a base register, we add it to $tempreg before 12048 the <op>. If there is a constant, we stick it in the 12049 <op> instruction. We don't handle constants larger than 12050 16 bits, because we have no way to load the upper 16 bits 12051 (actually, we could handle them for the subset of cases 12052 in which we are not using $at). */ 12053 gas_assert (offset_expr.X_op == O_symbol); 12054 expr1.X_add_number = offset_expr.X_add_number; 12055 offset_expr.X_add_number = 0; 12056 if (expr1.X_add_number < -0x8000 12057 || expr1.X_add_number >= 0x8000) 12058 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12059 gpdelay = reg_needs_delay (mips_gp_register); 12060 relax_start (offset_expr.X_add_symbol); 12061 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12062 BFD_RELOC_MIPS_GOT_HI16); 12063 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 12064 mips_gp_register); 12065 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12066 BFD_RELOC_MIPS_GOT_LO16, tempreg); 12067 relax_switch (); 12068 if (gpdelay) 12069 macro_build (NULL, "nop", ""); 12070 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12071 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12072 load_delay_nop (); 12073 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 12074 tempreg, BFD_RELOC_LO16); 12075 relax_end (); 12076 12077 if (breg != 0) 12078 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12079 tempreg, tempreg, breg); 12080 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12081 } 12082 else if (mips_big_got && HAVE_NEWABI) 12083 { 12084 /* If this is a reference to an external symbol, we want 12085 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12086 add $tempreg,$tempreg,$gp 12087 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 12088 <op> op[0],<ofst>($tempreg) 12089 Otherwise, for local symbols, we want: 12090 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 12091 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ 12092 gas_assert (offset_expr.X_op == O_symbol); 12093 expr1.X_add_number = offset_expr.X_add_number; 12094 offset_expr.X_add_number = 0; 12095 if (expr1.X_add_number < -0x8000 12096 || expr1.X_add_number >= 0x8000) 12097 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12098 relax_start (offset_expr.X_add_symbol); 12099 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12100 BFD_RELOC_MIPS_GOT_HI16); 12101 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 12102 mips_gp_register); 12103 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12104 BFD_RELOC_MIPS_GOT_LO16, tempreg); 12105 if (breg != 0) 12106 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12107 tempreg, tempreg, breg); 12108 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12109 12110 relax_switch (); 12111 offset_expr.X_add_number = expr1.X_add_number; 12112 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12113 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 12114 if (breg != 0) 12115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12116 tempreg, tempreg, breg); 12117 macro_build (&offset_expr, s, fmt, op[0], 12118 BFD_RELOC_MIPS_GOT_OFST, tempreg); 12119 relax_end (); 12120 } 12121 else 12122 abort (); 12123 12124 break; 12125 12126 case M_JRADDIUSP: 12127 gas_assert (mips_opts.micromips); 12128 gas_assert (mips_opts.insn32); 12129 start_noreorder (); 12130 macro_build (NULL, "jr", "s", RA); 12131 expr1.X_add_number = op[0] << 2; 12132 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); 12133 end_noreorder (); 12134 break; 12135 12136 case M_JRC: 12137 gas_assert (mips_opts.micromips); 12138 gas_assert (mips_opts.insn32); 12139 macro_build (NULL, "jr", "s", op[0]); 12140 if (mips_opts.noreorder) 12141 macro_build (NULL, "nop", ""); 12142 break; 12143 12144 case M_LI: 12145 case M_LI_S: 12146 load_register (op[0], &imm_expr, 0); 12147 break; 12148 12149 case M_DLI: 12150 load_register (op[0], &imm_expr, 1); 12151 break; 12152 12153 case M_LI_SS: 12154 if (imm_expr.X_op == O_constant) 12155 { 12156 used_at = 1; 12157 load_register (AT, &imm_expr, 0); 12158 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12159 break; 12160 } 12161 else 12162 { 12163 gas_assert (imm_expr.X_op == O_absent 12164 && offset_expr.X_op == O_symbol 12165 && strcmp (segment_name (S_GET_SEGMENT 12166 (offset_expr.X_add_symbol)), 12167 ".lit4") == 0 12168 && offset_expr.X_add_number == 0); 12169 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], 12170 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 12171 break; 12172 } 12173 12174 case M_LI_D: 12175 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits 12176 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high 12177 order 32 bits of the value and the low order 32 bits are either 12178 zero or in OFFSET_EXPR. */ 12179 if (imm_expr.X_op == O_constant) 12180 { 12181 if (GPR_SIZE == 64) 12182 load_register (op[0], &imm_expr, 1); 12183 else 12184 { 12185 int hreg, lreg; 12186 12187 if (target_big_endian) 12188 { 12189 hreg = op[0]; 12190 lreg = op[0] + 1; 12191 } 12192 else 12193 { 12194 hreg = op[0] + 1; 12195 lreg = op[0]; 12196 } 12197 12198 if (hreg <= 31) 12199 load_register (hreg, &imm_expr, 0); 12200 if (lreg <= 31) 12201 { 12202 if (offset_expr.X_op == O_absent) 12203 move_register (lreg, 0); 12204 else 12205 { 12206 gas_assert (offset_expr.X_op == O_constant); 12207 load_register (lreg, &offset_expr, 0); 12208 } 12209 } 12210 } 12211 break; 12212 } 12213 gas_assert (imm_expr.X_op == O_absent); 12214 12215 /* We know that sym is in the .rdata section. First we get the 12216 upper 16 bits of the address. */ 12217 if (mips_pic == NO_PIC) 12218 { 12219 macro_build_lui (&offset_expr, AT); 12220 used_at = 1; 12221 } 12222 else 12223 { 12224 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12225 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12226 used_at = 1; 12227 } 12228 12229 /* Now we load the register(s). */ 12230 if (GPR_SIZE == 64) 12231 { 12232 used_at = 1; 12233 macro_build (&offset_expr, "ld", "t,o(b)", op[0], 12234 BFD_RELOC_LO16, AT); 12235 } 12236 else 12237 { 12238 used_at = 1; 12239 macro_build (&offset_expr, "lw", "t,o(b)", op[0], 12240 BFD_RELOC_LO16, AT); 12241 if (op[0] != RA) 12242 { 12243 /* FIXME: How in the world do we deal with the possible 12244 overflow here? */ 12245 offset_expr.X_add_number += 4; 12246 macro_build (&offset_expr, "lw", "t,o(b)", 12247 op[0] + 1, BFD_RELOC_LO16, AT); 12248 } 12249 } 12250 break; 12251 12252 case M_LI_DD: 12253 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits 12254 wide, IMM_EXPR is the entire value and the GPRs are known to be 64 12255 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of 12256 the value and the low order 32 bits are either zero or in 12257 OFFSET_EXPR. */ 12258 if (imm_expr.X_op == O_constant) 12259 { 12260 used_at = 1; 12261 load_register (AT, &imm_expr, FPR_SIZE == 64); 12262 if (FPR_SIZE == 64 && GPR_SIZE == 64) 12263 macro_build (NULL, "dmtc1", "t,S", AT, op[0]); 12264 else 12265 { 12266 if (ISA_HAS_MXHC1 (mips_opts.isa)) 12267 macro_build (NULL, "mthc1", "t,G", AT, op[0]); 12268 else if (FPR_SIZE != 32) 12269 as_bad (_("Unable to generate `%s' compliant code " 12270 "without mthc1"), 12271 (FPR_SIZE == 64) ? "fp64" : "fpxx"); 12272 else 12273 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); 12274 if (offset_expr.X_op == O_absent) 12275 macro_build (NULL, "mtc1", "t,G", 0, op[0]); 12276 else 12277 { 12278 gas_assert (offset_expr.X_op == O_constant); 12279 load_register (AT, &offset_expr, 0); 12280 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12281 } 12282 } 12283 break; 12284 } 12285 12286 gas_assert (imm_expr.X_op == O_absent 12287 && offset_expr.X_op == O_symbol 12288 && offset_expr.X_add_number == 0); 12289 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); 12290 if (strcmp (s, ".lit8") == 0) 12291 { 12292 op[2] = mips_gp_register; 12293 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; 12294 offset_reloc[1] = BFD_RELOC_UNUSED; 12295 offset_reloc[2] = BFD_RELOC_UNUSED; 12296 } 12297 else 12298 { 12299 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); 12300 used_at = 1; 12301 if (mips_pic != NO_PIC) 12302 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12303 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12304 else 12305 { 12306 /* FIXME: This won't work for a 64 bit address. */ 12307 macro_build_lui (&offset_expr, AT); 12308 } 12309 12310 op[2] = AT; 12311 offset_reloc[0] = BFD_RELOC_LO16; 12312 offset_reloc[1] = BFD_RELOC_UNUSED; 12313 offset_reloc[2] = BFD_RELOC_UNUSED; 12314 } 12315 align = 8; 12316 /* Fall through */ 12317 12318 case M_L_DAB: 12319 /* 12320 * The MIPS assembler seems to check for X_add_number not 12321 * being double aligned and generating: 12322 * lui at,%hi(foo+1) 12323 * addu at,at,v1 12324 * addiu at,at,%lo(foo+1) 12325 * lwc1 f2,0(at) 12326 * lwc1 f3,4(at) 12327 * But, the resulting address is the same after relocation so why 12328 * generate the extra instruction? 12329 */ 12330 /* Itbl support may require additional care here. */ 12331 coproc = 1; 12332 fmt = "T,o(b)"; 12333 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12334 { 12335 s = "ldc1"; 12336 goto ld_st; 12337 } 12338 s = "lwc1"; 12339 goto ldd_std; 12340 12341 case M_S_DAB: 12342 gas_assert (!mips_opts.micromips); 12343 /* Itbl support may require additional care here. */ 12344 coproc = 1; 12345 fmt = "T,o(b)"; 12346 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12347 { 12348 s = "sdc1"; 12349 goto ld_st; 12350 } 12351 s = "swc1"; 12352 goto ldd_std; 12353 12354 case M_LQ_AB: 12355 fmt = "t,o(b)"; 12356 s = "lq"; 12357 goto ld; 12358 12359 case M_SQ_AB: 12360 fmt = "t,o(b)"; 12361 s = "sq"; 12362 goto ld_st; 12363 12364 case M_LD_AB: 12365 fmt = "t,o(b)"; 12366 if (GPR_SIZE == 64) 12367 { 12368 s = "ld"; 12369 goto ld; 12370 } 12371 s = "lw"; 12372 goto ldd_std; 12373 12374 case M_SD_AB: 12375 fmt = "t,o(b)"; 12376 if (GPR_SIZE == 64) 12377 { 12378 s = "sd"; 12379 goto ld_st; 12380 } 12381 s = "sw"; 12382 12383 ldd_std: 12384 /* Even on a big endian machine $fn comes before $fn+1. We have 12385 to adjust when loading from memory. We set coproc if we must 12386 load $fn+1 first. */ 12387 /* Itbl support may require additional care here. */ 12388 if (!target_big_endian) 12389 coproc = 0; 12390 12391 breg = op[2]; 12392 if (small_offset_p (0, align, 16)) 12393 { 12394 ep = &offset_expr; 12395 if (!small_offset_p (4, align, 16)) 12396 { 12397 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, 12398 -1, offset_reloc[0], offset_reloc[1], 12399 offset_reloc[2]); 12400 expr1.X_add_number = 0; 12401 ep = &expr1; 12402 breg = AT; 12403 used_at = 1; 12404 offset_reloc[0] = BFD_RELOC_LO16; 12405 offset_reloc[1] = BFD_RELOC_UNUSED; 12406 offset_reloc[2] = BFD_RELOC_UNUSED; 12407 } 12408 if (strcmp (s, "lw") == 0 && op[0] == breg) 12409 { 12410 ep->X_add_number += 4; 12411 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], 12412 offset_reloc[1], offset_reloc[2], breg); 12413 ep->X_add_number -= 4; 12414 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], 12415 offset_reloc[1], offset_reloc[2], breg); 12416 } 12417 else 12418 { 12419 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, 12420 offset_reloc[0], offset_reloc[1], offset_reloc[2], 12421 breg); 12422 ep->X_add_number += 4; 12423 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, 12424 offset_reloc[0], offset_reloc[1], offset_reloc[2], 12425 breg); 12426 } 12427 break; 12428 } 12429 12430 if (offset_expr.X_op != O_symbol 12431 && offset_expr.X_op != O_constant) 12432 { 12433 as_bad (_("expression too complex")); 12434 offset_expr.X_op = O_constant; 12435 } 12436 12437 if (HAVE_32BIT_ADDRESSES 12438 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 12439 { 12440 char value [32]; 12441 12442 sprintf_vma (value, offset_expr.X_add_number); 12443 as_bad (_("number (0x%s) larger than 32 bits"), value); 12444 } 12445 12446 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) 12447 { 12448 /* If this is a reference to a GP relative symbol, we want 12449 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 12450 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 12451 If we have a base register, we use this 12452 addu $at,$breg,$gp 12453 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) 12454 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) 12455 If this is not a GP relative symbol, we want 12456 lui $at,<sym> (BFD_RELOC_HI16_S) 12457 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12458 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12459 If there is a base register, we add it to $at after the 12460 lui instruction. If there is a constant, we always use 12461 the last case. */ 12462 if (offset_expr.X_op == O_symbol 12463 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 12464 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 12465 { 12466 relax_start (offset_expr.X_add_symbol); 12467 if (breg == 0) 12468 { 12469 tempreg = mips_gp_register; 12470 } 12471 else 12472 { 12473 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12474 AT, breg, mips_gp_register); 12475 tempreg = AT; 12476 used_at = 1; 12477 } 12478 12479 /* Itbl support may require additional care here. */ 12480 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12481 BFD_RELOC_GPREL16, tempreg); 12482 offset_expr.X_add_number += 4; 12483 12484 /* Set mips_optimize to 2 to avoid inserting an 12485 undesired nop. */ 12486 hold_mips_optimize = mips_optimize; 12487 mips_optimize = 2; 12488 /* Itbl support may require additional care here. */ 12489 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12490 BFD_RELOC_GPREL16, tempreg); 12491 mips_optimize = hold_mips_optimize; 12492 12493 relax_switch (); 12494 12495 offset_expr.X_add_number -= 4; 12496 } 12497 used_at = 1; 12498 if (offset_high_part (offset_expr.X_add_number, 16) 12499 != offset_high_part (offset_expr.X_add_number + 4, 16)) 12500 { 12501 load_address (AT, &offset_expr, &used_at); 12502 offset_expr.X_op = O_constant; 12503 offset_expr.X_add_number = 0; 12504 } 12505 else 12506 macro_build_lui (&offset_expr, AT); 12507 if (breg != 0) 12508 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12509 /* Itbl support may require additional care here. */ 12510 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12511 BFD_RELOC_LO16, AT); 12512 /* FIXME: How do we handle overflow here? */ 12513 offset_expr.X_add_number += 4; 12514 /* Itbl support may require additional care here. */ 12515 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12516 BFD_RELOC_LO16, AT); 12517 if (mips_relax.sequence) 12518 relax_end (); 12519 } 12520 else if (!mips_big_got) 12521 { 12522 /* If this is a reference to an external symbol, we want 12523 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12524 nop 12525 <op> op[0],0($at) 12526 <op> op[0]+1,4($at) 12527 Otherwise we want 12528 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12529 nop 12530 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12531 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12532 If there is a base register we add it to $at before the 12533 lwc1 instructions. If there is a constant we include it 12534 in the lwc1 instructions. */ 12535 used_at = 1; 12536 expr1.X_add_number = offset_expr.X_add_number; 12537 if (expr1.X_add_number < -0x8000 12538 || expr1.X_add_number >= 0x8000 - 4) 12539 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12540 load_got_offset (AT, &offset_expr); 12541 load_delay_nop (); 12542 if (breg != 0) 12543 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12544 12545 /* Set mips_optimize to 2 to avoid inserting an undesired 12546 nop. */ 12547 hold_mips_optimize = mips_optimize; 12548 mips_optimize = 2; 12549 12550 /* Itbl support may require additional care here. */ 12551 relax_start (offset_expr.X_add_symbol); 12552 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 12553 BFD_RELOC_LO16, AT); 12554 expr1.X_add_number += 4; 12555 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 12556 BFD_RELOC_LO16, AT); 12557 relax_switch (); 12558 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12559 BFD_RELOC_LO16, AT); 12560 offset_expr.X_add_number += 4; 12561 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12562 BFD_RELOC_LO16, AT); 12563 relax_end (); 12564 12565 mips_optimize = hold_mips_optimize; 12566 } 12567 else if (mips_big_got) 12568 { 12569 int gpdelay; 12570 12571 /* If this is a reference to an external symbol, we want 12572 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12573 addu $at,$at,$gp 12574 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) 12575 nop 12576 <op> op[0],0($at) 12577 <op> op[0]+1,4($at) 12578 Otherwise we want 12579 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12580 nop 12581 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 12582 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 12583 If there is a base register we add it to $at before the 12584 lwc1 instructions. If there is a constant we include it 12585 in the lwc1 instructions. */ 12586 used_at = 1; 12587 expr1.X_add_number = offset_expr.X_add_number; 12588 offset_expr.X_add_number = 0; 12589 if (expr1.X_add_number < -0x8000 12590 || expr1.X_add_number >= 0x8000 - 4) 12591 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12592 gpdelay = reg_needs_delay (mips_gp_register); 12593 relax_start (offset_expr.X_add_symbol); 12594 macro_build (&offset_expr, "lui", LUI_FMT, 12595 AT, BFD_RELOC_MIPS_GOT_HI16); 12596 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12597 AT, AT, mips_gp_register); 12598 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 12599 AT, BFD_RELOC_MIPS_GOT_LO16, AT); 12600 load_delay_nop (); 12601 if (breg != 0) 12602 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12603 /* Itbl support may require additional care here. */ 12604 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 12605 BFD_RELOC_LO16, AT); 12606 expr1.X_add_number += 4; 12607 12608 /* Set mips_optimize to 2 to avoid inserting an undesired 12609 nop. */ 12610 hold_mips_optimize = mips_optimize; 12611 mips_optimize = 2; 12612 /* Itbl support may require additional care here. */ 12613 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 12614 BFD_RELOC_LO16, AT); 12615 mips_optimize = hold_mips_optimize; 12616 expr1.X_add_number -= 4; 12617 12618 relax_switch (); 12619 offset_expr.X_add_number = expr1.X_add_number; 12620 if (gpdelay) 12621 macro_build (NULL, "nop", ""); 12622 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12623 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12624 load_delay_nop (); 12625 if (breg != 0) 12626 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 12627 /* Itbl support may require additional care here. */ 12628 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 12629 BFD_RELOC_LO16, AT); 12630 offset_expr.X_add_number += 4; 12631 12632 /* Set mips_optimize to 2 to avoid inserting an undesired 12633 nop. */ 12634 hold_mips_optimize = mips_optimize; 12635 mips_optimize = 2; 12636 /* Itbl support may require additional care here. */ 12637 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 12638 BFD_RELOC_LO16, AT); 12639 mips_optimize = hold_mips_optimize; 12640 relax_end (); 12641 } 12642 else 12643 abort (); 12644 12645 break; 12646 12647 case M_SAA_AB: 12648 s = "saa"; 12649 goto saa_saad; 12650 case M_SAAD_AB: 12651 s = "saad"; 12652 saa_saad: 12653 gas_assert (!mips_opts.micromips); 12654 offbits = 0; 12655 fmt = "t,(b)"; 12656 goto ld_st; 12657 12658 /* New code added to support COPZ instructions. 12659 This code builds table entries out of the macros in mip_opcodes. 12660 R4000 uses interlocks to handle coproc delays. 12661 Other chips (like the R3000) require nops to be inserted for delays. 12662 12663 FIXME: Currently, we require that the user handle delays. 12664 In order to fill delay slots for non-interlocked chips, 12665 we must have a way to specify delays based on the coprocessor. 12666 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. 12667 What are the side-effects of the cop instruction? 12668 What cache support might we have and what are its effects? 12669 Both coprocessor & memory require delays. how long??? 12670 What registers are read/set/modified? 12671 12672 If an itbl is provided to interpret cop instructions, 12673 this knowledge can be encoded in the itbl spec. */ 12674 12675 case M_COP0: 12676 s = "c0"; 12677 goto copz; 12678 case M_COP1: 12679 s = "c1"; 12680 goto copz; 12681 case M_COP2: 12682 s = "c2"; 12683 goto copz; 12684 case M_COP3: 12685 s = "c3"; 12686 copz: 12687 gas_assert (!mips_opts.micromips); 12688 /* For now we just do C (same as Cz). The parameter will be 12689 stored in insn_opcode by mips_ip. */ 12690 macro_build (NULL, s, "C", (int) ip->insn_opcode); 12691 break; 12692 12693 case M_MOVE: 12694 move_register (op[0], op[1]); 12695 break; 12696 12697 case M_MOVEP: 12698 gas_assert (mips_opts.micromips); 12699 gas_assert (mips_opts.insn32); 12700 move_register (micromips_to_32_reg_h_map1[op[0]], 12701 micromips_to_32_reg_m_map[op[1]]); 12702 move_register (micromips_to_32_reg_h_map2[op[0]], 12703 micromips_to_32_reg_n_map[op[2]]); 12704 break; 12705 12706 case M_DMUL: 12707 dbl = 1; 12708 case M_MUL: 12709 if (mips_opts.arch == CPU_R5900) 12710 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], 12711 op[2]); 12712 else 12713 { 12714 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); 12715 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12716 } 12717 break; 12718 12719 case M_DMUL_I: 12720 dbl = 1; 12721 case M_MUL_I: 12722 /* The MIPS assembler some times generates shifts and adds. I'm 12723 not trying to be that fancy. GCC should do this for us 12724 anyway. */ 12725 used_at = 1; 12726 load_register (AT, &imm_expr, dbl); 12727 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); 12728 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12729 break; 12730 12731 case M_DMULO_I: 12732 dbl = 1; 12733 case M_MULO_I: 12734 imm = 1; 12735 goto do_mulo; 12736 12737 case M_DMULO: 12738 dbl = 1; 12739 case M_MULO: 12740 do_mulo: 12741 start_noreorder (); 12742 used_at = 1; 12743 if (imm) 12744 load_register (AT, &imm_expr, dbl); 12745 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", 12746 op[1], imm ? AT : op[2]); 12747 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12748 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); 12749 macro_build (NULL, "mfhi", MFHL_FMT, AT); 12750 if (mips_trap) 12751 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); 12752 else 12753 { 12754 if (mips_opts.micromips) 12755 micromips_label_expr (&label_expr); 12756 else 12757 label_expr.X_add_number = 8; 12758 macro_build (&label_expr, "beq", "s,t,p", op[0], AT); 12759 macro_build (NULL, "nop", ""); 12760 macro_build (NULL, "break", BRK_FMT, 6); 12761 if (mips_opts.micromips) 12762 micromips_add_label (); 12763 } 12764 end_noreorder (); 12765 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12766 break; 12767 12768 case M_DMULOU_I: 12769 dbl = 1; 12770 case M_MULOU_I: 12771 imm = 1; 12772 goto do_mulou; 12773 12774 case M_DMULOU: 12775 dbl = 1; 12776 case M_MULOU: 12777 do_mulou: 12778 start_noreorder (); 12779 used_at = 1; 12780 if (imm) 12781 load_register (AT, &imm_expr, dbl); 12782 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", 12783 op[1], imm ? AT : op[2]); 12784 macro_build (NULL, "mfhi", MFHL_FMT, AT); 12785 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 12786 if (mips_trap) 12787 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); 12788 else 12789 { 12790 if (mips_opts.micromips) 12791 micromips_label_expr (&label_expr); 12792 else 12793 label_expr.X_add_number = 8; 12794 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); 12795 macro_build (NULL, "nop", ""); 12796 macro_build (NULL, "break", BRK_FMT, 6); 12797 if (mips_opts.micromips) 12798 micromips_add_label (); 12799 } 12800 end_noreorder (); 12801 break; 12802 12803 case M_DROL: 12804 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12805 { 12806 if (op[0] == op[1]) 12807 { 12808 tempreg = AT; 12809 used_at = 1; 12810 } 12811 else 12812 tempreg = op[0]; 12813 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); 12814 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); 12815 break; 12816 } 12817 used_at = 1; 12818 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 12819 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); 12820 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); 12821 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12822 break; 12823 12824 case M_ROL: 12825 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12826 { 12827 if (op[0] == op[1]) 12828 { 12829 tempreg = AT; 12830 used_at = 1; 12831 } 12832 else 12833 tempreg = op[0]; 12834 macro_build (NULL, "negu", "d,w", tempreg, op[2]); 12835 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); 12836 break; 12837 } 12838 used_at = 1; 12839 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 12840 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); 12841 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); 12842 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12843 break; 12844 12845 case M_DROL_I: 12846 { 12847 unsigned int rot; 12848 char *l; 12849 char *rr; 12850 12851 rot = imm_expr.X_add_number & 0x3f; 12852 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12853 { 12854 rot = (64 - rot) & 0x3f; 12855 if (rot >= 32) 12856 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 12857 else 12858 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 12859 break; 12860 } 12861 if (rot == 0) 12862 { 12863 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 12864 break; 12865 } 12866 l = (rot < 0x20) ? "dsll" : "dsll32"; 12867 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; 12868 rot &= 0x1f; 12869 used_at = 1; 12870 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); 12871 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12872 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12873 } 12874 break; 12875 12876 case M_ROL_I: 12877 { 12878 unsigned int rot; 12879 12880 rot = imm_expr.X_add_number & 0x1f; 12881 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12882 { 12883 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], 12884 (32 - rot) & 0x1f); 12885 break; 12886 } 12887 if (rot == 0) 12888 { 12889 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 12890 break; 12891 } 12892 used_at = 1; 12893 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); 12894 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12895 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12896 } 12897 break; 12898 12899 case M_DROR: 12900 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12901 { 12902 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); 12903 break; 12904 } 12905 used_at = 1; 12906 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 12907 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); 12908 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); 12909 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12910 break; 12911 12912 case M_ROR: 12913 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12914 { 12915 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); 12916 break; 12917 } 12918 used_at = 1; 12919 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 12920 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); 12921 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); 12922 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12923 break; 12924 12925 case M_DROR_I: 12926 { 12927 unsigned int rot; 12928 char *l; 12929 char *rr; 12930 12931 rot = imm_expr.X_add_number & 0x3f; 12932 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 12933 { 12934 if (rot >= 32) 12935 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 12936 else 12937 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 12938 break; 12939 } 12940 if (rot == 0) 12941 { 12942 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 12943 break; 12944 } 12945 rr = (rot < 0x20) ? "dsrl" : "dsrl32"; 12946 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; 12947 rot &= 0x1f; 12948 used_at = 1; 12949 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); 12950 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12951 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12952 } 12953 break; 12954 12955 case M_ROR_I: 12956 { 12957 unsigned int rot; 12958 12959 rot = imm_expr.X_add_number & 0x1f; 12960 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 12961 { 12962 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); 12963 break; 12964 } 12965 if (rot == 0) 12966 { 12967 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 12968 break; 12969 } 12970 used_at = 1; 12971 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); 12972 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 12973 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 12974 } 12975 break; 12976 12977 case M_SEQ: 12978 if (op[1] == 0) 12979 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); 12980 else if (op[2] == 0) 12981 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 12982 else 12983 { 12984 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 12985 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 12986 } 12987 break; 12988 12989 case M_SEQ_I: 12990 if (imm_expr.X_add_number == 0) 12991 { 12992 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 12993 break; 12994 } 12995 if (op[1] == 0) 12996 { 12997 as_warn (_("instruction %s: result is always false"), 12998 ip->insn_mo->name); 12999 move_register (op[0], 0); 13000 break; 13001 } 13002 if (CPU_HAS_SEQ (mips_opts.arch) 13003 && -512 <= imm_expr.X_add_number 13004 && imm_expr.X_add_number < 512) 13005 { 13006 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], 13007 (int) imm_expr.X_add_number); 13008 break; 13009 } 13010 if (imm_expr.X_add_number >= 0 13011 && imm_expr.X_add_number < 0x10000) 13012 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); 13013 else if (imm_expr.X_add_number > -0x8000 13014 && imm_expr.X_add_number < 0) 13015 { 13016 imm_expr.X_add_number = -imm_expr.X_add_number; 13017 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 13018 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13019 } 13020 else if (CPU_HAS_SEQ (mips_opts.arch)) 13021 { 13022 used_at = 1; 13023 load_register (AT, &imm_expr, GPR_SIZE == 64); 13024 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); 13025 break; 13026 } 13027 else 13028 { 13029 load_register (AT, &imm_expr, GPR_SIZE == 64); 13030 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 13031 used_at = 1; 13032 } 13033 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 13034 break; 13035 13036 case M_SGE: /* X >= Y <==> not (X < Y) */ 13037 s = "slt"; 13038 goto sge; 13039 case M_SGEU: 13040 s = "sltu"; 13041 sge: 13042 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); 13043 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13044 break; 13045 13046 case M_SGE_I: /* X >= I <==> not (X < I) */ 13047 case M_SGEU_I: 13048 if (imm_expr.X_add_number >= -0x8000 13049 && imm_expr.X_add_number < 0x8000) 13050 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", 13051 op[0], op[1], BFD_RELOC_LO16); 13052 else 13053 { 13054 load_register (AT, &imm_expr, GPR_SIZE == 64); 13055 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", 13056 op[0], op[1], AT); 13057 used_at = 1; 13058 } 13059 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13060 break; 13061 13062 case M_SGT: /* X > Y <==> Y < X */ 13063 s = "slt"; 13064 goto sgt; 13065 case M_SGTU: 13066 s = "sltu"; 13067 sgt: 13068 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 13069 break; 13070 13071 case M_SGT_I: /* X > I <==> I < X */ 13072 s = "slt"; 13073 goto sgti; 13074 case M_SGTU_I: 13075 s = "sltu"; 13076 sgti: 13077 used_at = 1; 13078 load_register (AT, &imm_expr, GPR_SIZE == 64); 13079 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 13080 break; 13081 13082 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ 13083 s = "slt"; 13084 goto sle; 13085 case M_SLEU: 13086 s = "sltu"; 13087 sle: 13088 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 13089 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13090 break; 13091 13092 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ 13093 s = "slt"; 13094 goto slei; 13095 case M_SLEU_I: 13096 s = "sltu"; 13097 slei: 13098 used_at = 1; 13099 load_register (AT, &imm_expr, GPR_SIZE == 64); 13100 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 13101 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13102 break; 13103 13104 case M_SLT_I: 13105 if (imm_expr.X_add_number >= -0x8000 13106 && imm_expr.X_add_number < 0x8000) 13107 { 13108 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], 13109 BFD_RELOC_LO16); 13110 break; 13111 } 13112 used_at = 1; 13113 load_register (AT, &imm_expr, GPR_SIZE == 64); 13114 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); 13115 break; 13116 13117 case M_SLTU_I: 13118 if (imm_expr.X_add_number >= -0x8000 13119 && imm_expr.X_add_number < 0x8000) 13120 { 13121 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], 13122 BFD_RELOC_LO16); 13123 break; 13124 } 13125 used_at = 1; 13126 load_register (AT, &imm_expr, GPR_SIZE == 64); 13127 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); 13128 break; 13129 13130 case M_SNE: 13131 if (op[1] == 0) 13132 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); 13133 else if (op[2] == 0) 13134 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13135 else 13136 { 13137 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 13138 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13139 } 13140 break; 13141 13142 case M_SNE_I: 13143 if (imm_expr.X_add_number == 0) 13144 { 13145 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13146 break; 13147 } 13148 if (op[1] == 0) 13149 { 13150 as_warn (_("instruction %s: result is always true"), 13151 ip->insn_mo->name); 13152 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", 13153 op[0], 0, BFD_RELOC_LO16); 13154 break; 13155 } 13156 if (CPU_HAS_SEQ (mips_opts.arch) 13157 && -512 <= imm_expr.X_add_number 13158 && imm_expr.X_add_number < 512) 13159 { 13160 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], 13161 (int) imm_expr.X_add_number); 13162 break; 13163 } 13164 if (imm_expr.X_add_number >= 0 13165 && imm_expr.X_add_number < 0x10000) 13166 { 13167 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], 13168 BFD_RELOC_LO16); 13169 } 13170 else if (imm_expr.X_add_number > -0x8000 13171 && imm_expr.X_add_number < 0) 13172 { 13173 imm_expr.X_add_number = -imm_expr.X_add_number; 13174 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 13175 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13176 } 13177 else if (CPU_HAS_SEQ (mips_opts.arch)) 13178 { 13179 used_at = 1; 13180 load_register (AT, &imm_expr, GPR_SIZE == 64); 13181 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); 13182 break; 13183 } 13184 else 13185 { 13186 load_register (AT, &imm_expr, GPR_SIZE == 64); 13187 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 13188 used_at = 1; 13189 } 13190 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13191 break; 13192 13193 case M_SUB_I: 13194 s = "addi"; 13195 s2 = "sub"; 13196 goto do_subi; 13197 case M_SUBU_I: 13198 s = "addiu"; 13199 s2 = "subu"; 13200 goto do_subi; 13201 case M_DSUB_I: 13202 dbl = 1; 13203 s = "daddi"; 13204 s2 = "dsub"; 13205 if (!mips_opts.micromips) 13206 goto do_subi; 13207 if (imm_expr.X_add_number > -0x200 13208 && imm_expr.X_add_number <= 0x200) 13209 { 13210 macro_build (NULL, s, "t,r,.", op[0], op[1], 13211 (int) -imm_expr.X_add_number); 13212 break; 13213 } 13214 goto do_subi_i; 13215 case M_DSUBU_I: 13216 dbl = 1; 13217 s = "daddiu"; 13218 s2 = "dsubu"; 13219 do_subi: 13220 if (imm_expr.X_add_number > -0x8000 13221 && imm_expr.X_add_number <= 0x8000) 13222 { 13223 imm_expr.X_add_number = -imm_expr.X_add_number; 13224 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13225 break; 13226 } 13227 do_subi_i: 13228 used_at = 1; 13229 load_register (AT, &imm_expr, dbl); 13230 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 13231 break; 13232 13233 case M_TEQ_I: 13234 s = "teq"; 13235 goto trap; 13236 case M_TGE_I: 13237 s = "tge"; 13238 goto trap; 13239 case M_TGEU_I: 13240 s = "tgeu"; 13241 goto trap; 13242 case M_TLT_I: 13243 s = "tlt"; 13244 goto trap; 13245 case M_TLTU_I: 13246 s = "tltu"; 13247 goto trap; 13248 case M_TNE_I: 13249 s = "tne"; 13250 trap: 13251 used_at = 1; 13252 load_register (AT, &imm_expr, GPR_SIZE == 64); 13253 macro_build (NULL, s, "s,t", op[0], AT); 13254 break; 13255 13256 case M_TRUNCWS: 13257 case M_TRUNCWD: 13258 gas_assert (!mips_opts.micromips); 13259 gas_assert (mips_opts.isa == ISA_MIPS1); 13260 used_at = 1; 13261 13262 /* 13263 * Is the double cfc1 instruction a bug in the mips assembler; 13264 * or is there a reason for it? 13265 */ 13266 start_noreorder (); 13267 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13268 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13269 macro_build (NULL, "nop", ""); 13270 expr1.X_add_number = 3; 13271 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); 13272 expr1.X_add_number = 2; 13273 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); 13274 macro_build (NULL, "ctc1", "t,G", AT, RA); 13275 macro_build (NULL, "nop", ""); 13276 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", 13277 op[0], op[1]); 13278 macro_build (NULL, "ctc1", "t,G", op[2], RA); 13279 macro_build (NULL, "nop", ""); 13280 end_noreorder (); 13281 break; 13282 13283 case M_ULH_AB: 13284 s = "lb"; 13285 s2 = "lbu"; 13286 off = 1; 13287 goto uld_st; 13288 case M_ULHU_AB: 13289 s = "lbu"; 13290 s2 = "lbu"; 13291 off = 1; 13292 goto uld_st; 13293 case M_ULW_AB: 13294 s = "lwl"; 13295 s2 = "lwr"; 13296 offbits = (mips_opts.micromips ? 12 : 16); 13297 off = 3; 13298 goto uld_st; 13299 case M_ULD_AB: 13300 s = "ldl"; 13301 s2 = "ldr"; 13302 offbits = (mips_opts.micromips ? 12 : 16); 13303 off = 7; 13304 goto uld_st; 13305 case M_USH_AB: 13306 s = "sb"; 13307 s2 = "sb"; 13308 off = 1; 13309 ust = 1; 13310 goto uld_st; 13311 case M_USW_AB: 13312 s = "swl"; 13313 s2 = "swr"; 13314 offbits = (mips_opts.micromips ? 12 : 16); 13315 off = 3; 13316 ust = 1; 13317 goto uld_st; 13318 case M_USD_AB: 13319 s = "sdl"; 13320 s2 = "sdr"; 13321 offbits = (mips_opts.micromips ? 12 : 16); 13322 off = 7; 13323 ust = 1; 13324 13325 uld_st: 13326 breg = op[2]; 13327 large_offset = !small_offset_p (off, align, offbits); 13328 ep = &offset_expr; 13329 expr1.X_add_number = 0; 13330 if (large_offset) 13331 { 13332 used_at = 1; 13333 tempreg = AT; 13334 if (small_offset_p (0, align, 16)) 13335 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, 13336 offset_reloc[0], offset_reloc[1], offset_reloc[2]); 13337 else 13338 { 13339 load_address (tempreg, ep, &used_at); 13340 if (breg != 0) 13341 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 13342 tempreg, tempreg, breg); 13343 } 13344 offset_reloc[0] = BFD_RELOC_LO16; 13345 offset_reloc[1] = BFD_RELOC_UNUSED; 13346 offset_reloc[2] = BFD_RELOC_UNUSED; 13347 breg = tempreg; 13348 tempreg = op[0]; 13349 ep = &expr1; 13350 } 13351 else if (!ust && op[0] == breg) 13352 { 13353 used_at = 1; 13354 tempreg = AT; 13355 } 13356 else 13357 tempreg = op[0]; 13358 13359 if (off == 1) 13360 goto ulh_sh; 13361 13362 if (!target_big_endian) 13363 ep->X_add_number += off; 13364 if (offbits == 12) 13365 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); 13366 else 13367 macro_build (ep, s, "t,o(b)", tempreg, -1, 13368 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13369 13370 if (!target_big_endian) 13371 ep->X_add_number -= off; 13372 else 13373 ep->X_add_number += off; 13374 if (offbits == 12) 13375 macro_build (NULL, s2, "t,~(b)", 13376 tempreg, (int) ep->X_add_number, breg); 13377 else 13378 macro_build (ep, s2, "t,o(b)", tempreg, -1, 13379 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13380 13381 /* If necessary, move the result in tempreg to the final destination. */ 13382 if (!ust && op[0] != tempreg) 13383 { 13384 /* Protect second load's delay slot. */ 13385 load_delay_nop (); 13386 move_register (op[0], tempreg); 13387 } 13388 break; 13389 13390 ulh_sh: 13391 used_at = 1; 13392 if (target_big_endian == ust) 13393 ep->X_add_number += off; 13394 tempreg = ust || large_offset ? op[0] : AT; 13395 macro_build (ep, s, "t,o(b)", tempreg, -1, 13396 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13397 13398 /* For halfword transfers we need a temporary register to shuffle 13399 bytes. Unfortunately for M_USH_A we have none available before 13400 the next store as AT holds the base address. We deal with this 13401 case by clobbering TREG and then restoring it as with ULH. */ 13402 tempreg = ust == large_offset ? op[0] : AT; 13403 if (ust) 13404 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); 13405 13406 if (target_big_endian == ust) 13407 ep->X_add_number -= off; 13408 else 13409 ep->X_add_number += off; 13410 macro_build (ep, s2, "t,o(b)", tempreg, -1, 13411 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 13412 13413 /* For M_USH_A re-retrieve the LSB. */ 13414 if (ust && large_offset) 13415 { 13416 if (target_big_endian) 13417 ep->X_add_number += off; 13418 else 13419 ep->X_add_number -= off; 13420 macro_build (&expr1, "lbu", "t,o(b)", AT, -1, 13421 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); 13422 } 13423 /* For ULH and M_USH_A OR the LSB in. */ 13424 if (!ust || large_offset) 13425 { 13426 tempreg = !large_offset ? AT : op[0]; 13427 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); 13428 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13429 } 13430 break; 13431 13432 default: 13433 /* FIXME: Check if this is one of the itbl macros, since they 13434 are added dynamically. */ 13435 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); 13436 break; 13437 } 13438 if (!mips_opts.at && used_at) 13439 as_bad (_("macro used $at after \".set noat\"")); 13440 } 13441 13442 /* Implement macros in mips16 mode. */ 13443 13444 static void 13445 mips16_macro (struct mips_cl_insn *ip) 13446 { 13447 const struct mips_operand_array *operands; 13448 int mask; 13449 int tmp; 13450 expressionS expr1; 13451 int dbl; 13452 const char *s, *s2, *s3; 13453 unsigned int op[MAX_OPERANDS]; 13454 unsigned int i; 13455 13456 mask = ip->insn_mo->mask; 13457 13458 operands = insn_operands (ip); 13459 for (i = 0; i < MAX_OPERANDS; i++) 13460 if (operands->operand[i]) 13461 op[i] = insn_extract_operand (ip, operands->operand[i]); 13462 else 13463 op[i] = -1; 13464 13465 expr1.X_op = O_constant; 13466 expr1.X_op_symbol = NULL; 13467 expr1.X_add_symbol = NULL; 13468 expr1.X_add_number = 1; 13469 13470 dbl = 0; 13471 13472 switch (mask) 13473 { 13474 default: 13475 abort (); 13476 13477 case M_DDIV_3: 13478 dbl = 1; 13479 case M_DIV_3: 13480 s = "mflo"; 13481 goto do_div3; 13482 case M_DREM_3: 13483 dbl = 1; 13484 case M_REM_3: 13485 s = "mfhi"; 13486 do_div3: 13487 start_noreorder (); 13488 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]); 13489 expr1.X_add_number = 2; 13490 macro_build (&expr1, "bnez", "x,p", op[2]); 13491 macro_build (NULL, "break", "6", 7); 13492 13493 /* FIXME: The normal code checks for of -1 / -0x80000000 here, 13494 since that causes an overflow. We should do that as well, 13495 but I don't see how to do the comparisons without a temporary 13496 register. */ 13497 end_noreorder (); 13498 macro_build (NULL, s, "x", op[0]); 13499 break; 13500 13501 case M_DIVU_3: 13502 s = "divu"; 13503 s2 = "mflo"; 13504 goto do_divu3; 13505 case M_REMU_3: 13506 s = "divu"; 13507 s2 = "mfhi"; 13508 goto do_divu3; 13509 case M_DDIVU_3: 13510 s = "ddivu"; 13511 s2 = "mflo"; 13512 goto do_divu3; 13513 case M_DREMU_3: 13514 s = "ddivu"; 13515 s2 = "mfhi"; 13516 do_divu3: 13517 start_noreorder (); 13518 macro_build (NULL, s, "0,x,y", op[1], op[2]); 13519 expr1.X_add_number = 2; 13520 macro_build (&expr1, "bnez", "x,p", op[2]); 13521 macro_build (NULL, "break", "6", 7); 13522 end_noreorder (); 13523 macro_build (NULL, s2, "x", op[0]); 13524 break; 13525 13526 case M_DMUL: 13527 dbl = 1; 13528 case M_MUL: 13529 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); 13530 macro_build (NULL, "mflo", "x", op[0]); 13531 break; 13532 13533 case M_DSUBU_I: 13534 dbl = 1; 13535 goto do_subu; 13536 case M_SUBU_I: 13537 do_subu: 13538 imm_expr.X_add_number = -imm_expr.X_add_number; 13539 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]); 13540 break; 13541 13542 case M_SUBU_I_2: 13543 imm_expr.X_add_number = -imm_expr.X_add_number; 13544 macro_build (&imm_expr, "addiu", "x,k", op[0]); 13545 break; 13546 13547 case M_DSUBU_I_2: 13548 imm_expr.X_add_number = -imm_expr.X_add_number; 13549 macro_build (&imm_expr, "daddiu", "y,j", op[0]); 13550 break; 13551 13552 case M_BEQ: 13553 s = "cmp"; 13554 s2 = "bteqz"; 13555 goto do_branch; 13556 case M_BNE: 13557 s = "cmp"; 13558 s2 = "btnez"; 13559 goto do_branch; 13560 case M_BLT: 13561 s = "slt"; 13562 s2 = "btnez"; 13563 goto do_branch; 13564 case M_BLTU: 13565 s = "sltu"; 13566 s2 = "btnez"; 13567 goto do_branch; 13568 case M_BLE: 13569 s = "slt"; 13570 s2 = "bteqz"; 13571 goto do_reverse_branch; 13572 case M_BLEU: 13573 s = "sltu"; 13574 s2 = "bteqz"; 13575 goto do_reverse_branch; 13576 case M_BGE: 13577 s = "slt"; 13578 s2 = "bteqz"; 13579 goto do_branch; 13580 case M_BGEU: 13581 s = "sltu"; 13582 s2 = "bteqz"; 13583 goto do_branch; 13584 case M_BGT: 13585 s = "slt"; 13586 s2 = "btnez"; 13587 goto do_reverse_branch; 13588 case M_BGTU: 13589 s = "sltu"; 13590 s2 = "btnez"; 13591 13592 do_reverse_branch: 13593 tmp = op[1]; 13594 op[1] = op[0]; 13595 op[0] = tmp; 13596 13597 do_branch: 13598 macro_build (NULL, s, "x,y", op[0], op[1]); 13599 macro_build (&offset_expr, s2, "p"); 13600 break; 13601 13602 case M_BEQ_I: 13603 s = "cmpi"; 13604 s2 = "bteqz"; 13605 s3 = "x,U"; 13606 goto do_branch_i; 13607 case M_BNE_I: 13608 s = "cmpi"; 13609 s2 = "btnez"; 13610 s3 = "x,U"; 13611 goto do_branch_i; 13612 case M_BLT_I: 13613 s = "slti"; 13614 s2 = "btnez"; 13615 s3 = "x,8"; 13616 goto do_branch_i; 13617 case M_BLTU_I: 13618 s = "sltiu"; 13619 s2 = "btnez"; 13620 s3 = "x,8"; 13621 goto do_branch_i; 13622 case M_BLE_I: 13623 s = "slti"; 13624 s2 = "btnez"; 13625 s3 = "x,8"; 13626 goto do_addone_branch_i; 13627 case M_BLEU_I: 13628 s = "sltiu"; 13629 s2 = "btnez"; 13630 s3 = "x,8"; 13631 goto do_addone_branch_i; 13632 case M_BGE_I: 13633 s = "slti"; 13634 s2 = "bteqz"; 13635 s3 = "x,8"; 13636 goto do_branch_i; 13637 case M_BGEU_I: 13638 s = "sltiu"; 13639 s2 = "bteqz"; 13640 s3 = "x,8"; 13641 goto do_branch_i; 13642 case M_BGT_I: 13643 s = "slti"; 13644 s2 = "bteqz"; 13645 s3 = "x,8"; 13646 goto do_addone_branch_i; 13647 case M_BGTU_I: 13648 s = "sltiu"; 13649 s2 = "bteqz"; 13650 s3 = "x,8"; 13651 13652 do_addone_branch_i: 13653 ++imm_expr.X_add_number; 13654 13655 do_branch_i: 13656 macro_build (&imm_expr, s, s3, op[0]); 13657 macro_build (&offset_expr, s2, "p"); 13658 break; 13659 13660 case M_ABS: 13661 expr1.X_add_number = 0; 13662 macro_build (&expr1, "slti", "x,8", op[1]); 13663 if (op[0] != op[1]) 13664 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); 13665 expr1.X_add_number = 2; 13666 macro_build (&expr1, "bteqz", "p"); 13667 macro_build (NULL, "neg", "x,w", op[0], op[0]); 13668 break; 13669 } 13670 } 13671 13672 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra 13673 opcode bits in *OPCODE_EXTRA. */ 13674 13675 static struct mips_opcode * 13676 mips_lookup_insn (struct hash_control *hash, const char *start, 13677 ssize_t length, unsigned int *opcode_extra) 13678 { 13679 char *name, *dot, *p; 13680 unsigned int mask, suffix; 13681 ssize_t opend; 13682 struct mips_opcode *insn; 13683 13684 /* Make a copy of the instruction so that we can fiddle with it. */ 13685 name = alloca (length + 1); 13686 memcpy (name, start, length); 13687 name[length] = '\0'; 13688 13689 /* Look up the instruction as-is. */ 13690 insn = (struct mips_opcode *) hash_find (hash, name); 13691 if (insn) 13692 return insn; 13693 13694 dot = strchr (name, '.'); 13695 if (dot && dot[1]) 13696 { 13697 /* Try to interpret the text after the dot as a VU0 channel suffix. */ 13698 p = mips_parse_vu0_channels (dot + 1, &mask); 13699 if (*p == 0 && mask != 0) 13700 { 13701 *dot = 0; 13702 insn = (struct mips_opcode *) hash_find (hash, name); 13703 *dot = '.'; 13704 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) 13705 { 13706 *opcode_extra |= mask << mips_vu0_channel_mask.lsb; 13707 return insn; 13708 } 13709 } 13710 } 13711 13712 if (mips_opts.micromips) 13713 { 13714 /* See if there's an instruction size override suffix, 13715 either `16' or `32', at the end of the mnemonic proper, 13716 that defines the operation, i.e. before the first `.' 13717 character if any. Strip it and retry. */ 13718 opend = dot != NULL ? dot - name : length; 13719 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') 13720 suffix = 2; 13721 else if (name[opend - 2] == '3' && name[opend - 1] == '2') 13722 suffix = 4; 13723 else 13724 suffix = 0; 13725 if (suffix) 13726 { 13727 memcpy (name + opend - 2, name + opend, length - opend + 1); 13728 insn = (struct mips_opcode *) hash_find (hash, name); 13729 if (insn) 13730 { 13731 forced_insn_length = suffix; 13732 return insn; 13733 } 13734 } 13735 } 13736 13737 return NULL; 13738 } 13739 13740 /* Assemble an instruction into its binary format. If the instruction 13741 is a macro, set imm_expr and offset_expr to the values associated 13742 with "I" and "A" operands respectively. Otherwise store the value 13743 of the relocatable field (if any) in offset_expr. In both cases 13744 set offset_reloc to the relocation operators applied to offset_expr. */ 13745 13746 static void 13747 mips_ip (char *str, struct mips_cl_insn *insn) 13748 { 13749 const struct mips_opcode *first, *past; 13750 struct hash_control *hash; 13751 char format; 13752 size_t end; 13753 struct mips_operand_token *tokens; 13754 unsigned int opcode_extra; 13755 13756 if (mips_opts.micromips) 13757 { 13758 hash = micromips_op_hash; 13759 past = µmips_opcodes[bfd_micromips_num_opcodes]; 13760 } 13761 else 13762 { 13763 hash = op_hash; 13764 past = &mips_opcodes[NUMOPCODES]; 13765 } 13766 forced_insn_length = 0; 13767 opcode_extra = 0; 13768 13769 /* We first try to match an instruction up to a space or to the end. */ 13770 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) 13771 continue; 13772 13773 first = mips_lookup_insn (hash, str, end, &opcode_extra); 13774 if (first == NULL) 13775 { 13776 set_insn_error (0, _("unrecognized opcode")); 13777 return; 13778 } 13779 13780 if (strcmp (first->name, "li.s") == 0) 13781 format = 'f'; 13782 else if (strcmp (first->name, "li.d") == 0) 13783 format = 'd'; 13784 else 13785 format = 0; 13786 tokens = mips_parse_arguments (str + end, format); 13787 if (!tokens) 13788 return; 13789 13790 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) 13791 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) 13792 set_insn_error (0, _("invalid operands")); 13793 13794 obstack_free (&mips_operand_tokens, tokens); 13795 } 13796 13797 /* As for mips_ip, but used when assembling MIPS16 code. 13798 Also set forced_insn_length to the resulting instruction size in 13799 bytes if the user explicitly requested a small or extended instruction. */ 13800 13801 static void 13802 mips16_ip (char *str, struct mips_cl_insn *insn) 13803 { 13804 char *end, *s, c; 13805 struct mips_opcode *first; 13806 struct mips_operand_token *tokens; 13807 13808 forced_insn_length = 0; 13809 13810 for (s = str; ISLOWER (*s); ++s) 13811 ; 13812 end = s; 13813 c = *end; 13814 switch (c) 13815 { 13816 case '\0': 13817 break; 13818 13819 case ' ': 13820 s++; 13821 break; 13822 13823 case '.': 13824 if (s[1] == 't' && s[2] == ' ') 13825 { 13826 forced_insn_length = 2; 13827 s += 3; 13828 break; 13829 } 13830 else if (s[1] == 'e' && s[2] == ' ') 13831 { 13832 forced_insn_length = 4; 13833 s += 3; 13834 break; 13835 } 13836 /* Fall through. */ 13837 default: 13838 set_insn_error (0, _("unrecognized opcode")); 13839 return; 13840 } 13841 13842 if (mips_opts.noautoextend && !forced_insn_length) 13843 forced_insn_length = 2; 13844 13845 *end = 0; 13846 first = (struct mips_opcode *) hash_find (mips16_op_hash, str); 13847 *end = c; 13848 13849 if (!first) 13850 { 13851 set_insn_error (0, _("unrecognized opcode")); 13852 return; 13853 } 13854 13855 tokens = mips_parse_arguments (s, 0); 13856 if (!tokens) 13857 return; 13858 13859 if (!match_mips16_insns (insn, first, tokens)) 13860 set_insn_error (0, _("invalid operands")); 13861 13862 obstack_free (&mips_operand_tokens, tokens); 13863 } 13864 13865 /* Marshal immediate value VAL for an extended MIPS16 instruction. 13866 NBITS is the number of significant bits in VAL. */ 13867 13868 static unsigned long 13869 mips16_immed_extend (offsetT val, unsigned int nbits) 13870 { 13871 int extval; 13872 if (nbits == 16) 13873 { 13874 extval = ((val >> 11) & 0x1f) | (val & 0x7e0); 13875 val &= 0x1f; 13876 } 13877 else if (nbits == 15) 13878 { 13879 extval = ((val >> 11) & 0xf) | (val & 0x7f0); 13880 val &= 0xf; 13881 } 13882 else 13883 { 13884 extval = ((val & 0x1f) << 6) | (val & 0x20); 13885 val = 0; 13886 } 13887 return (extval << 16) | val; 13888 } 13889 13890 /* Like decode_mips16_operand, but require the operand to be defined and 13891 require it to be an integer. */ 13892 13893 static const struct mips_int_operand * 13894 mips16_immed_operand (int type, bfd_boolean extended_p) 13895 { 13896 const struct mips_operand *operand; 13897 13898 operand = decode_mips16_operand (type, extended_p); 13899 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) 13900 abort (); 13901 return (const struct mips_int_operand *) operand; 13902 } 13903 13904 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ 13905 13906 static bfd_boolean 13907 mips16_immed_in_range_p (const struct mips_int_operand *operand, 13908 bfd_reloc_code_real_type reloc, offsetT sval) 13909 { 13910 int min_val, max_val; 13911 13912 min_val = mips_int_operand_min (operand); 13913 max_val = mips_int_operand_max (operand); 13914 if (reloc != BFD_RELOC_UNUSED) 13915 { 13916 if (min_val < 0) 13917 sval = SEXT_16BIT (sval); 13918 else 13919 sval &= 0xffff; 13920 } 13921 13922 return (sval >= min_val 13923 && sval <= max_val 13924 && (sval & ((1 << operand->shift) - 1)) == 0); 13925 } 13926 13927 /* Install immediate value VAL into MIPS16 instruction *INSN, 13928 extending it if necessary. The instruction in *INSN may 13929 already be extended. 13930 13931 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED 13932 if none. In the former case, VAL is a 16-bit number with no 13933 defined signedness. 13934 13935 TYPE is the type of the immediate field. USER_INSN_LENGTH 13936 is the length that the user requested, or 0 if none. */ 13937 13938 static void 13939 mips16_immed (char *file, unsigned int line, int type, 13940 bfd_reloc_code_real_type reloc, offsetT val, 13941 unsigned int user_insn_length, unsigned long *insn) 13942 { 13943 const struct mips_int_operand *operand; 13944 unsigned int uval, length; 13945 13946 operand = mips16_immed_operand (type, FALSE); 13947 if (!mips16_immed_in_range_p (operand, reloc, val)) 13948 { 13949 /* We need an extended instruction. */ 13950 if (user_insn_length == 2) 13951 as_bad_where (file, line, _("invalid unextended operand value")); 13952 else 13953 *insn |= MIPS16_EXTEND; 13954 } 13955 else if (user_insn_length == 4) 13956 { 13957 /* The operand doesn't force an unextended instruction to be extended. 13958 Warn if the user wanted an extended instruction anyway. */ 13959 *insn |= MIPS16_EXTEND; 13960 as_warn_where (file, line, 13961 _("extended operand requested but not required")); 13962 } 13963 13964 length = mips16_opcode_length (*insn); 13965 if (length == 4) 13966 { 13967 operand = mips16_immed_operand (type, TRUE); 13968 if (!mips16_immed_in_range_p (operand, reloc, val)) 13969 as_bad_where (file, line, 13970 _("operand value out of range for instruction")); 13971 } 13972 uval = ((unsigned int) val >> operand->shift) - operand->bias; 13973 if (length == 2) 13974 *insn = mips_insert_operand (&operand->root, *insn, uval); 13975 else 13976 *insn |= mips16_immed_extend (uval, operand->root.size); 13977 } 13978 13979 struct percent_op_match 13981 { 13982 const char *str; 13983 bfd_reloc_code_real_type reloc; 13984 }; 13985 13986 static const struct percent_op_match mips_percent_op[] = 13987 { 13988 {"%lo", BFD_RELOC_LO16}, 13989 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, 13990 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, 13991 {"%call16", BFD_RELOC_MIPS_CALL16}, 13992 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, 13993 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, 13994 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, 13995 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, 13996 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, 13997 {"%got", BFD_RELOC_MIPS_GOT16}, 13998 {"%gp_rel", BFD_RELOC_GPREL16}, 13999 {"%half", BFD_RELOC_16}, 14000 {"%highest", BFD_RELOC_MIPS_HIGHEST}, 14001 {"%higher", BFD_RELOC_MIPS_HIGHER}, 14002 {"%neg", BFD_RELOC_MIPS_SUB}, 14003 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, 14004 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, 14005 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, 14006 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, 14007 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, 14008 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, 14009 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, 14010 {"%hi", BFD_RELOC_HI16_S}, 14011 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, 14012 {"%pcrel_lo", BFD_RELOC_LO16_PCREL} 14013 }; 14014 14015 static const struct percent_op_match mips16_percent_op[] = 14016 { 14017 {"%lo", BFD_RELOC_MIPS16_LO16}, 14018 {"%gprel", BFD_RELOC_MIPS16_GPREL}, 14019 {"%got", BFD_RELOC_MIPS16_GOT16}, 14020 {"%call16", BFD_RELOC_MIPS16_CALL16}, 14021 {"%hi", BFD_RELOC_MIPS16_HI16_S}, 14022 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, 14023 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, 14024 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, 14025 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, 14026 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, 14027 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, 14028 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} 14029 }; 14030 14031 14032 /* Return true if *STR points to a relocation operator. When returning true, 14033 move *STR over the operator and store its relocation code in *RELOC. 14034 Leave both *STR and *RELOC alone when returning false. */ 14035 14036 static bfd_boolean 14037 parse_relocation (char **str, bfd_reloc_code_real_type *reloc) 14038 { 14039 const struct percent_op_match *percent_op; 14040 size_t limit, i; 14041 14042 if (mips_opts.mips16) 14043 { 14044 percent_op = mips16_percent_op; 14045 limit = ARRAY_SIZE (mips16_percent_op); 14046 } 14047 else 14048 { 14049 percent_op = mips_percent_op; 14050 limit = ARRAY_SIZE (mips_percent_op); 14051 } 14052 14053 for (i = 0; i < limit; i++) 14054 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) 14055 { 14056 int len = strlen (percent_op[i].str); 14057 14058 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 14059 continue; 14060 14061 *str += strlen (percent_op[i].str); 14062 *reloc = percent_op[i].reloc; 14063 14064 /* Check whether the output BFD supports this relocation. 14065 If not, issue an error and fall back on something safe. */ 14066 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) 14067 { 14068 as_bad (_("relocation %s isn't supported by the current ABI"), 14069 percent_op[i].str); 14070 *reloc = BFD_RELOC_UNUSED; 14071 } 14072 return TRUE; 14073 } 14074 return FALSE; 14075 } 14076 14077 14078 /* Parse string STR as a 16-bit relocatable operand. Store the 14079 expression in *EP and the relocations in the array starting 14080 at RELOC. Return the number of relocation operators used. 14081 14082 On exit, EXPR_END points to the first character after the expression. */ 14083 14084 static size_t 14085 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 14086 char *str) 14087 { 14088 bfd_reloc_code_real_type reversed_reloc[3]; 14089 size_t reloc_index, i; 14090 int crux_depth, str_depth; 14091 char *crux; 14092 14093 /* Search for the start of the main expression, recoding relocations 14094 in REVERSED_RELOC. End the loop with CRUX pointing to the start 14095 of the main expression and with CRUX_DEPTH containing the number 14096 of open brackets at that point. */ 14097 reloc_index = -1; 14098 str_depth = 0; 14099 do 14100 { 14101 reloc_index++; 14102 crux = str; 14103 crux_depth = str_depth; 14104 14105 /* Skip over whitespace and brackets, keeping count of the number 14106 of brackets. */ 14107 while (*str == ' ' || *str == '\t' || *str == '(') 14108 if (*str++ == '(') 14109 str_depth++; 14110 } 14111 while (*str == '%' 14112 && reloc_index < (HAVE_NEWABI ? 3 : 1) 14113 && parse_relocation (&str, &reversed_reloc[reloc_index])); 14114 14115 my_getExpression (ep, crux); 14116 str = expr_end; 14117 14118 /* Match every open bracket. */ 14119 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 14120 if (*str++ == ')') 14121 crux_depth--; 14122 14123 if (crux_depth > 0) 14124 as_bad (_("unclosed '('")); 14125 14126 expr_end = str; 14127 14128 if (reloc_index != 0) 14129 { 14130 prev_reloc_op_frag = frag_now; 14131 for (i = 0; i < reloc_index; i++) 14132 reloc[i] = reversed_reloc[reloc_index - 1 - i]; 14133 } 14134 14135 return reloc_index; 14136 } 14137 14138 static void 14139 my_getExpression (expressionS *ep, char *str) 14140 { 14141 char *save_in; 14142 14143 save_in = input_line_pointer; 14144 input_line_pointer = str; 14145 expression (ep); 14146 expr_end = input_line_pointer; 14147 input_line_pointer = save_in; 14148 } 14149 14150 char * 14151 md_atof (int type, char *litP, int *sizeP) 14152 { 14153 return ieee_md_atof (type, litP, sizeP, target_big_endian); 14154 } 14155 14156 void 14157 md_number_to_chars (char *buf, valueT val, int n) 14158 { 14159 if (target_big_endian) 14160 number_to_chars_bigendian (buf, val, n); 14161 else 14162 number_to_chars_littleendian (buf, val, n); 14163 } 14164 14165 static int support_64bit_objects(void) 14167 { 14168 const char **list, **l; 14169 int yes; 14170 14171 list = bfd_target_list (); 14172 for (l = list; *l != NULL; l++) 14173 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 14174 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) 14175 break; 14176 yes = (*l != NULL); 14177 free (list); 14178 return yes; 14179 } 14180 14181 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to 14182 NEW_VALUE. Warn if another value was already specified. Note: 14183 we have to defer parsing the -march and -mtune arguments in order 14184 to handle 'from-abi' correctly, since the ABI might be specified 14185 in a later argument. */ 14186 14187 static void 14188 mips_set_option_string (const char **string_ptr, const char *new_value) 14189 { 14190 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) 14191 as_warn (_("a different %s was already specified, is now %s"), 14192 string_ptr == &mips_arch_string ? "-march" : "-mtune", 14193 new_value); 14194 14195 *string_ptr = new_value; 14196 } 14197 14198 int 14199 md_parse_option (int c, char *arg) 14200 { 14201 unsigned int i; 14202 14203 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 14204 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) 14205 { 14206 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, 14207 c == mips_ases[i].option_on); 14208 return 1; 14209 } 14210 14211 switch (c) 14212 { 14213 case OPTION_CONSTRUCT_FLOATS: 14214 mips_disable_float_construction = 0; 14215 break; 14216 14217 case OPTION_NO_CONSTRUCT_FLOATS: 14218 mips_disable_float_construction = 1; 14219 break; 14220 14221 case OPTION_TRAP: 14222 mips_trap = 1; 14223 break; 14224 14225 case OPTION_BREAK: 14226 mips_trap = 0; 14227 break; 14228 14229 case OPTION_EB: 14230 target_big_endian = 1; 14231 break; 14232 14233 case OPTION_EL: 14234 target_big_endian = 0; 14235 break; 14236 14237 case 'O': 14238 if (arg == NULL) 14239 mips_optimize = 1; 14240 else if (arg[0] == '0') 14241 mips_optimize = 0; 14242 else if (arg[0] == '1') 14243 mips_optimize = 1; 14244 else 14245 mips_optimize = 2; 14246 break; 14247 14248 case 'g': 14249 if (arg == NULL) 14250 mips_debug = 2; 14251 else 14252 mips_debug = atoi (arg); 14253 break; 14254 14255 case OPTION_MIPS1: 14256 file_mips_opts.isa = ISA_MIPS1; 14257 break; 14258 14259 case OPTION_MIPS2: 14260 file_mips_opts.isa = ISA_MIPS2; 14261 break; 14262 14263 case OPTION_MIPS3: 14264 file_mips_opts.isa = ISA_MIPS3; 14265 break; 14266 14267 case OPTION_MIPS4: 14268 file_mips_opts.isa = ISA_MIPS4; 14269 break; 14270 14271 case OPTION_MIPS5: 14272 file_mips_opts.isa = ISA_MIPS5; 14273 break; 14274 14275 case OPTION_MIPS32: 14276 file_mips_opts.isa = ISA_MIPS32; 14277 break; 14278 14279 case OPTION_MIPS32R2: 14280 file_mips_opts.isa = ISA_MIPS32R2; 14281 break; 14282 14283 case OPTION_MIPS32R3: 14284 file_mips_opts.isa = ISA_MIPS32R3; 14285 break; 14286 14287 case OPTION_MIPS32R5: 14288 file_mips_opts.isa = ISA_MIPS32R5; 14289 break; 14290 14291 case OPTION_MIPS32R6: 14292 file_mips_opts.isa = ISA_MIPS32R6; 14293 break; 14294 14295 case OPTION_MIPS64R2: 14296 file_mips_opts.isa = ISA_MIPS64R2; 14297 break; 14298 14299 case OPTION_MIPS64R3: 14300 file_mips_opts.isa = ISA_MIPS64R3; 14301 break; 14302 14303 case OPTION_MIPS64R5: 14304 file_mips_opts.isa = ISA_MIPS64R5; 14305 break; 14306 14307 case OPTION_MIPS64R6: 14308 file_mips_opts.isa = ISA_MIPS64R6; 14309 break; 14310 14311 case OPTION_MIPS64: 14312 file_mips_opts.isa = ISA_MIPS64; 14313 break; 14314 14315 case OPTION_MTUNE: 14316 mips_set_option_string (&mips_tune_string, arg); 14317 break; 14318 14319 case OPTION_MARCH: 14320 mips_set_option_string (&mips_arch_string, arg); 14321 break; 14322 14323 case OPTION_M4650: 14324 mips_set_option_string (&mips_arch_string, "4650"); 14325 mips_set_option_string (&mips_tune_string, "4650"); 14326 break; 14327 14328 case OPTION_NO_M4650: 14329 break; 14330 14331 case OPTION_M4010: 14332 mips_set_option_string (&mips_arch_string, "4010"); 14333 mips_set_option_string (&mips_tune_string, "4010"); 14334 break; 14335 14336 case OPTION_NO_M4010: 14337 break; 14338 14339 case OPTION_M4100: 14340 mips_set_option_string (&mips_arch_string, "4100"); 14341 mips_set_option_string (&mips_tune_string, "4100"); 14342 break; 14343 14344 case OPTION_NO_M4100: 14345 break; 14346 14347 case OPTION_M3900: 14348 mips_set_option_string (&mips_arch_string, "3900"); 14349 mips_set_option_string (&mips_tune_string, "3900"); 14350 break; 14351 14352 case OPTION_NO_M3900: 14353 break; 14354 14355 case OPTION_MICROMIPS: 14356 if (file_mips_opts.mips16 == 1) 14357 { 14358 as_bad (_("-mmicromips cannot be used with -mips16")); 14359 return 0; 14360 } 14361 file_mips_opts.micromips = 1; 14362 mips_no_prev_insn (); 14363 break; 14364 14365 case OPTION_NO_MICROMIPS: 14366 file_mips_opts.micromips = 0; 14367 mips_no_prev_insn (); 14368 break; 14369 14370 case OPTION_MIPS16: 14371 if (file_mips_opts.micromips == 1) 14372 { 14373 as_bad (_("-mips16 cannot be used with -micromips")); 14374 return 0; 14375 } 14376 file_mips_opts.mips16 = 1; 14377 mips_no_prev_insn (); 14378 break; 14379 14380 case OPTION_NO_MIPS16: 14381 file_mips_opts.mips16 = 0; 14382 mips_no_prev_insn (); 14383 break; 14384 14385 case OPTION_FIX_24K: 14386 mips_fix_24k = 1; 14387 break; 14388 14389 case OPTION_NO_FIX_24K: 14390 mips_fix_24k = 0; 14391 break; 14392 14393 case OPTION_FIX_RM7000: 14394 mips_fix_rm7000 = 1; 14395 break; 14396 14397 case OPTION_NO_FIX_RM7000: 14398 mips_fix_rm7000 = 0; 14399 break; 14400 14401 case OPTION_FIX_LOONGSON2F_JUMP: 14402 mips_fix_loongson2f_jump = TRUE; 14403 break; 14404 14405 case OPTION_NO_FIX_LOONGSON2F_JUMP: 14406 mips_fix_loongson2f_jump = FALSE; 14407 break; 14408 14409 case OPTION_FIX_LOONGSON2F_NOP: 14410 mips_fix_loongson2f_nop = TRUE; 14411 break; 14412 14413 case OPTION_NO_FIX_LOONGSON2F_NOP: 14414 mips_fix_loongson2f_nop = FALSE; 14415 break; 14416 14417 case OPTION_FIX_VR4120: 14418 mips_fix_vr4120 = 1; 14419 break; 14420 14421 case OPTION_NO_FIX_VR4120: 14422 mips_fix_vr4120 = 0; 14423 break; 14424 14425 case OPTION_FIX_VR4130: 14426 mips_fix_vr4130 = 1; 14427 break; 14428 14429 case OPTION_NO_FIX_VR4130: 14430 mips_fix_vr4130 = 0; 14431 break; 14432 14433 case OPTION_FIX_CN63XXP1: 14434 mips_fix_cn63xxp1 = TRUE; 14435 break; 14436 14437 case OPTION_NO_FIX_CN63XXP1: 14438 mips_fix_cn63xxp1 = FALSE; 14439 break; 14440 14441 case OPTION_RELAX_BRANCH: 14442 mips_relax_branch = 1; 14443 break; 14444 14445 case OPTION_NO_RELAX_BRANCH: 14446 mips_relax_branch = 0; 14447 break; 14448 14449 case OPTION_INSN32: 14450 file_mips_opts.insn32 = TRUE; 14451 break; 14452 14453 case OPTION_NO_INSN32: 14454 file_mips_opts.insn32 = FALSE; 14455 break; 14456 14457 case OPTION_MSHARED: 14458 mips_in_shared = TRUE; 14459 break; 14460 14461 case OPTION_MNO_SHARED: 14462 mips_in_shared = FALSE; 14463 break; 14464 14465 case OPTION_MSYM32: 14466 file_mips_opts.sym32 = TRUE; 14467 break; 14468 14469 case OPTION_MNO_SYM32: 14470 file_mips_opts.sym32 = FALSE; 14471 break; 14472 14473 /* When generating ELF code, we permit -KPIC and -call_shared to 14474 select SVR4_PIC, and -non_shared to select no PIC. This is 14475 intended to be compatible with Irix 5. */ 14476 case OPTION_CALL_SHARED: 14477 mips_pic = SVR4_PIC; 14478 mips_abicalls = TRUE; 14479 break; 14480 14481 case OPTION_CALL_NONPIC: 14482 mips_pic = NO_PIC; 14483 mips_abicalls = TRUE; 14484 break; 14485 14486 case OPTION_NON_SHARED: 14487 mips_pic = NO_PIC; 14488 mips_abicalls = FALSE; 14489 break; 14490 14491 /* The -xgot option tells the assembler to use 32 bit offsets 14492 when accessing the got in SVR4_PIC mode. It is for Irix 14493 compatibility. */ 14494 case OPTION_XGOT: 14495 mips_big_got = 1; 14496 break; 14497 14498 case 'G': 14499 g_switch_value = atoi (arg); 14500 g_switch_seen = 1; 14501 break; 14502 14503 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 14504 and -mabi=64. */ 14505 case OPTION_32: 14506 mips_abi = O32_ABI; 14507 break; 14508 14509 case OPTION_N32: 14510 mips_abi = N32_ABI; 14511 break; 14512 14513 case OPTION_64: 14514 mips_abi = N64_ABI; 14515 if (!support_64bit_objects()) 14516 as_fatal (_("no compiled in support for 64 bit object file format")); 14517 break; 14518 14519 case OPTION_GP32: 14520 file_mips_opts.gp = 32; 14521 break; 14522 14523 case OPTION_GP64: 14524 file_mips_opts.gp = 64; 14525 break; 14526 14527 case OPTION_FP32: 14528 file_mips_opts.fp = 32; 14529 break; 14530 14531 case OPTION_FPXX: 14532 file_mips_opts.fp = 0; 14533 break; 14534 14535 case OPTION_FP64: 14536 file_mips_opts.fp = 64; 14537 break; 14538 14539 case OPTION_ODD_SPREG: 14540 file_mips_opts.oddspreg = 1; 14541 break; 14542 14543 case OPTION_NO_ODD_SPREG: 14544 file_mips_opts.oddspreg = 0; 14545 break; 14546 14547 case OPTION_SINGLE_FLOAT: 14548 file_mips_opts.single_float = 1; 14549 break; 14550 14551 case OPTION_DOUBLE_FLOAT: 14552 file_mips_opts.single_float = 0; 14553 break; 14554 14555 case OPTION_SOFT_FLOAT: 14556 file_mips_opts.soft_float = 1; 14557 break; 14558 14559 case OPTION_HARD_FLOAT: 14560 file_mips_opts.soft_float = 0; 14561 break; 14562 14563 case OPTION_MABI: 14564 if (strcmp (arg, "32") == 0) 14565 mips_abi = O32_ABI; 14566 else if (strcmp (arg, "o64") == 0) 14567 mips_abi = O64_ABI; 14568 else if (strcmp (arg, "n32") == 0) 14569 mips_abi = N32_ABI; 14570 else if (strcmp (arg, "64") == 0) 14571 { 14572 mips_abi = N64_ABI; 14573 if (! support_64bit_objects()) 14574 as_fatal (_("no compiled in support for 64 bit object file " 14575 "format")); 14576 } 14577 else if (strcmp (arg, "eabi") == 0) 14578 mips_abi = EABI_ABI; 14579 else 14580 { 14581 as_fatal (_("invalid abi -mabi=%s"), arg); 14582 return 0; 14583 } 14584 break; 14585 14586 case OPTION_M7000_HILO_FIX: 14587 mips_7000_hilo_fix = TRUE; 14588 break; 14589 14590 case OPTION_MNO_7000_HILO_FIX: 14591 mips_7000_hilo_fix = FALSE; 14592 break; 14593 14594 case OPTION_MDEBUG: 14595 mips_flag_mdebug = TRUE; 14596 break; 14597 14598 case OPTION_NO_MDEBUG: 14599 mips_flag_mdebug = FALSE; 14600 break; 14601 14602 case OPTION_PDR: 14603 mips_flag_pdr = TRUE; 14604 break; 14605 14606 case OPTION_NO_PDR: 14607 mips_flag_pdr = FALSE; 14608 break; 14609 14610 case OPTION_MVXWORKS_PIC: 14611 mips_pic = VXWORKS_PIC; 14612 break; 14613 14614 case OPTION_NAN: 14615 if (strcmp (arg, "2008") == 0) 14616 mips_nan2008 = 1; 14617 else if (strcmp (arg, "legacy") == 0) 14618 mips_nan2008 = 0; 14619 else 14620 { 14621 as_fatal (_("invalid NaN setting -mnan=%s"), arg); 14622 return 0; 14623 } 14624 break; 14625 14626 default: 14627 return 0; 14628 } 14629 14630 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; 14631 14632 return 1; 14633 } 14634 14635 /* Set up globals to tune for the ISA or processor described by INFO. */ 14637 14638 static void 14639 mips_set_tune (const struct mips_cpu_info *info) 14640 { 14641 if (info != 0) 14642 mips_tune = info->cpu; 14643 } 14644 14645 14646 void 14647 mips_after_parse_args (void) 14648 { 14649 const struct mips_cpu_info *arch_info = 0; 14650 const struct mips_cpu_info *tune_info = 0; 14651 14652 /* GP relative stuff not working for PE */ 14653 if (strncmp (TARGET_OS, "pe", 2) == 0) 14654 { 14655 if (g_switch_seen && g_switch_value != 0) 14656 as_bad (_("-G not supported in this configuration")); 14657 g_switch_value = 0; 14658 } 14659 14660 if (mips_abi == NO_ABI) 14661 mips_abi = MIPS_DEFAULT_ABI; 14662 14663 /* The following code determines the architecture. 14664 Similar code was added to GCC 3.3 (see override_options() in 14665 config/mips/mips.c). The GAS and GCC code should be kept in sync 14666 as much as possible. */ 14667 14668 if (mips_arch_string != 0) 14669 arch_info = mips_parse_cpu ("-march", mips_arch_string); 14670 14671 if (file_mips_opts.isa != ISA_UNKNOWN) 14672 { 14673 /* Handle -mipsN. At this point, file_mips_opts.isa contains the 14674 ISA level specified by -mipsN, while arch_info->isa contains 14675 the -march selection (if any). */ 14676 if (arch_info != 0) 14677 { 14678 /* -march takes precedence over -mipsN, since it is more descriptive. 14679 There's no harm in specifying both as long as the ISA levels 14680 are the same. */ 14681 if (file_mips_opts.isa != arch_info->isa) 14682 as_bad (_("-%s conflicts with the other architecture options," 14683 " which imply -%s"), 14684 mips_cpu_info_from_isa (file_mips_opts.isa)->name, 14685 mips_cpu_info_from_isa (arch_info->isa)->name); 14686 } 14687 else 14688 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); 14689 } 14690 14691 if (arch_info == 0) 14692 { 14693 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); 14694 gas_assert (arch_info); 14695 } 14696 14697 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) 14698 as_bad (_("-march=%s is not compatible with the selected ABI"), 14699 arch_info->name); 14700 14701 file_mips_opts.arch = arch_info->cpu; 14702 file_mips_opts.isa = arch_info->isa; 14703 14704 /* Set up initial mips_opts state. */ 14705 mips_opts = file_mips_opts; 14706 14707 /* The register size inference code is now placed in 14708 file_mips_check_options. */ 14709 14710 /* Optimize for file_mips_opts.arch, unless -mtune selects a different 14711 processor. */ 14712 if (mips_tune_string != 0) 14713 tune_info = mips_parse_cpu ("-mtune", mips_tune_string); 14714 14715 if (tune_info == 0) 14716 mips_set_tune (arch_info); 14717 else 14718 mips_set_tune (tune_info); 14719 14720 if (mips_flag_mdebug < 0) 14721 mips_flag_mdebug = 0; 14722 } 14723 14724 void 14726 mips_init_after_args (void) 14727 { 14728 /* initialize opcodes */ 14729 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; 14730 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; 14731 } 14732 14733 long 14734 md_pcrel_from (fixS *fixP) 14735 { 14736 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 14737 switch (fixP->fx_r_type) 14738 { 14739 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 14740 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 14741 /* Return the address of the delay slot. */ 14742 return addr + 2; 14743 14744 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 14745 case BFD_RELOC_MICROMIPS_JMP: 14746 case BFD_RELOC_16_PCREL_S2: 14747 case BFD_RELOC_MIPS_21_PCREL_S2: 14748 case BFD_RELOC_MIPS_26_PCREL_S2: 14749 case BFD_RELOC_MIPS_JMP: 14750 /* Return the address of the delay slot. */ 14751 return addr + 4; 14752 14753 default: 14754 return addr; 14755 } 14756 } 14757 14758 /* This is called before the symbol table is processed. In order to 14759 work with gcc when using mips-tfile, we must keep all local labels. 14760 However, in other cases, we want to discard them. If we were 14761 called with -g, but we didn't see any debugging information, it may 14762 mean that gcc is smuggling debugging information through to 14763 mips-tfile, in which case we must generate all local labels. */ 14764 14765 void 14766 mips_frob_file_before_adjust (void) 14767 { 14768 #ifndef NO_ECOFF_DEBUGGING 14769 if (ECOFF_DEBUGGING 14770 && mips_debug != 0 14771 && ! ecoff_debugging_seen) 14772 flag_keep_locals = 1; 14773 #endif 14774 } 14775 14776 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede 14777 the corresponding LO16 reloc. This is called before md_apply_fix and 14778 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit 14779 relocation operators. 14780 14781 For our purposes, a %lo() expression matches a %got() or %hi() 14782 expression if: 14783 14784 (a) it refers to the same symbol; and 14785 (b) the offset applied in the %lo() expression is no lower than 14786 the offset applied in the %got() or %hi(). 14787 14788 (b) allows us to cope with code like: 14789 14790 lui $4,%hi(foo) 14791 lh $4,%lo(foo+2)($4) 14792 14793 ...which is legal on RELA targets, and has a well-defined behaviour 14794 if the user knows that adding 2 to "foo" will not induce a carry to 14795 the high 16 bits. 14796 14797 When several %lo()s match a particular %got() or %hi(), we use the 14798 following rules to distinguish them: 14799 14800 (1) %lo()s with smaller offsets are a better match than %lo()s with 14801 higher offsets. 14802 14803 (2) %lo()s with no matching %got() or %hi() are better than those 14804 that already have a matching %got() or %hi(). 14805 14806 (3) later %lo()s are better than earlier %lo()s. 14807 14808 These rules are applied in order. 14809 14810 (1) means, among other things, that %lo()s with identical offsets are 14811 chosen if they exist. 14812 14813 (2) means that we won't associate several high-part relocations with 14814 the same low-part relocation unless there's no alternative. Having 14815 several high parts for the same low part is a GNU extension; this rule 14816 allows careful users to avoid it. 14817 14818 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, 14819 with the last high-part relocation being at the front of the list. 14820 It therefore makes sense to choose the last matching low-part 14821 relocation, all other things being equal. It's also easier 14822 to code that way. */ 14823 14824 void 14825 mips_frob_file (void) 14826 { 14827 struct mips_hi_fixup *l; 14828 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; 14829 14830 for (l = mips_hi_fixup_list; l != NULL; l = l->next) 14831 { 14832 segment_info_type *seginfo; 14833 bfd_boolean matched_lo_p; 14834 fixS **hi_pos, **lo_pos, **pos; 14835 14836 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); 14837 14838 /* If a GOT16 relocation turns out to be against a global symbol, 14839 there isn't supposed to be a matching LO. Ignore %gots against 14840 constants; we'll report an error for those later. */ 14841 if (got16_reloc_p (l->fixp->fx_r_type) 14842 && !(l->fixp->fx_addsy 14843 && pic_need_relax (l->fixp->fx_addsy, l->seg))) 14844 continue; 14845 14846 /* Check quickly whether the next fixup happens to be a matching %lo. */ 14847 if (fixup_has_matching_lo_p (l->fixp)) 14848 continue; 14849 14850 seginfo = seg_info (l->seg); 14851 14852 /* Set HI_POS to the position of this relocation in the chain. 14853 Set LO_POS to the position of the chosen low-part relocation. 14854 MATCHED_LO_P is true on entry to the loop if *POS is a low-part 14855 relocation that matches an immediately-preceding high-part 14856 relocation. */ 14857 hi_pos = NULL; 14858 lo_pos = NULL; 14859 matched_lo_p = FALSE; 14860 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); 14861 14862 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) 14863 { 14864 if (*pos == l->fixp) 14865 hi_pos = pos; 14866 14867 if ((*pos)->fx_r_type == looking_for_rtype 14868 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) 14869 && (*pos)->fx_offset >= l->fixp->fx_offset 14870 && (lo_pos == NULL 14871 || (*pos)->fx_offset < (*lo_pos)->fx_offset 14872 || (!matched_lo_p 14873 && (*pos)->fx_offset == (*lo_pos)->fx_offset))) 14874 lo_pos = pos; 14875 14876 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) 14877 && fixup_has_matching_lo_p (*pos)); 14878 } 14879 14880 /* If we found a match, remove the high-part relocation from its 14881 current position and insert it before the low-part relocation. 14882 Make the offsets match so that fixup_has_matching_lo_p() 14883 will return true. 14884 14885 We don't warn about unmatched high-part relocations since some 14886 versions of gcc have been known to emit dead "lui ...%hi(...)" 14887 instructions. */ 14888 if (lo_pos != NULL) 14889 { 14890 l->fixp->fx_offset = (*lo_pos)->fx_offset; 14891 if (l->fixp->fx_next != *lo_pos) 14892 { 14893 *hi_pos = l->fixp->fx_next; 14894 l->fixp->fx_next = *lo_pos; 14895 *lo_pos = l->fixp; 14896 } 14897 } 14898 } 14899 } 14900 14901 int 14902 mips_force_relocation (fixS *fixp) 14903 { 14904 if (generic_force_reloc (fixp)) 14905 return 1; 14906 14907 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, 14908 so that the linker relaxation can update targets. */ 14909 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 14910 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 14911 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) 14912 return 1; 14913 14914 /* We want all PC-relative relocations to be kept for R6 relaxation. */ 14915 if (ISA_IS_R6 (mips_opts.isa) 14916 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 14917 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 14918 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 14919 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 14920 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 14921 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 14922 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) 14923 return 1; 14924 14925 return 0; 14926 } 14927 14928 /* Read the instruction associated with RELOC from BUF. */ 14929 14930 static unsigned int 14931 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) 14932 { 14933 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 14934 return read_compressed_insn (buf, 4); 14935 else 14936 return read_insn (buf); 14937 } 14938 14939 /* Write instruction INSN to BUF, given that it has been relocated 14940 by RELOC. */ 14941 14942 static void 14943 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, 14944 unsigned long insn) 14945 { 14946 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 14947 write_compressed_insn (buf, insn, 4); 14948 else 14949 write_insn (buf, insn); 14950 } 14951 14952 /* Apply a fixup to the object file. */ 14953 14954 void 14955 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 14956 { 14957 char *buf; 14958 unsigned long insn; 14959 reloc_howto_type *howto; 14960 14961 if (fixP->fx_pcrel) 14962 switch (fixP->fx_r_type) 14963 { 14964 case BFD_RELOC_16_PCREL_S2: 14965 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 14966 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 14967 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 14968 case BFD_RELOC_32_PCREL: 14969 case BFD_RELOC_MIPS_21_PCREL_S2: 14970 case BFD_RELOC_MIPS_26_PCREL_S2: 14971 case BFD_RELOC_MIPS_18_PCREL_S3: 14972 case BFD_RELOC_MIPS_19_PCREL_S2: 14973 case BFD_RELOC_HI16_S_PCREL: 14974 case BFD_RELOC_LO16_PCREL: 14975 break; 14976 14977 case BFD_RELOC_32: 14978 fixP->fx_r_type = BFD_RELOC_32_PCREL; 14979 break; 14980 14981 default: 14982 as_bad_where (fixP->fx_file, fixP->fx_line, 14983 _("PC-relative reference to a different section")); 14984 break; 14985 } 14986 14987 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations 14988 that have no MIPS ELF equivalent. */ 14989 if (fixP->fx_r_type != BFD_RELOC_8) 14990 { 14991 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 14992 if (!howto) 14993 return; 14994 } 14995 14996 gas_assert (fixP->fx_size == 2 14997 || fixP->fx_size == 4 14998 || fixP->fx_r_type == BFD_RELOC_8 14999 || fixP->fx_r_type == BFD_RELOC_16 15000 || fixP->fx_r_type == BFD_RELOC_64 15001 || fixP->fx_r_type == BFD_RELOC_CTOR 15002 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB 15003 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB 15004 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 15005 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 15006 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); 15007 15008 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15009 15010 /* Don't treat parts of a composite relocation as done. There are two 15011 reasons for this: 15012 15013 (1) The second and third parts will be against 0 (RSS_UNDEF) but 15014 should nevertheless be emitted if the first part is. 15015 15016 (2) In normal usage, composite relocations are never assembly-time 15017 constants. The easiest way of dealing with the pathological 15018 exceptions is to generate a relocation against STN_UNDEF and 15019 leave everything up to the linker. */ 15020 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) 15021 fixP->fx_done = 1; 15022 15023 switch (fixP->fx_r_type) 15024 { 15025 case BFD_RELOC_MIPS_TLS_GD: 15026 case BFD_RELOC_MIPS_TLS_LDM: 15027 case BFD_RELOC_MIPS_TLS_DTPREL32: 15028 case BFD_RELOC_MIPS_TLS_DTPREL64: 15029 case BFD_RELOC_MIPS_TLS_DTPREL_HI16: 15030 case BFD_RELOC_MIPS_TLS_DTPREL_LO16: 15031 case BFD_RELOC_MIPS_TLS_GOTTPREL: 15032 case BFD_RELOC_MIPS_TLS_TPREL32: 15033 case BFD_RELOC_MIPS_TLS_TPREL64: 15034 case BFD_RELOC_MIPS_TLS_TPREL_HI16: 15035 case BFD_RELOC_MIPS_TLS_TPREL_LO16: 15036 case BFD_RELOC_MICROMIPS_TLS_GD: 15037 case BFD_RELOC_MICROMIPS_TLS_LDM: 15038 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: 15039 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: 15040 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: 15041 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: 15042 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: 15043 case BFD_RELOC_MIPS16_TLS_GD: 15044 case BFD_RELOC_MIPS16_TLS_LDM: 15045 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: 15046 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: 15047 case BFD_RELOC_MIPS16_TLS_GOTTPREL: 15048 case BFD_RELOC_MIPS16_TLS_TPREL_HI16: 15049 case BFD_RELOC_MIPS16_TLS_TPREL_LO16: 15050 if (!fixP->fx_addsy) 15051 { 15052 as_bad_where (fixP->fx_file, fixP->fx_line, 15053 _("TLS relocation against a constant")); 15054 break; 15055 } 15056 S_SET_THREAD_LOCAL (fixP->fx_addsy); 15057 /* fall through */ 15058 15059 case BFD_RELOC_MIPS_JMP: 15060 case BFD_RELOC_MIPS_SHIFT5: 15061 case BFD_RELOC_MIPS_SHIFT6: 15062 case BFD_RELOC_MIPS_GOT_DISP: 15063 case BFD_RELOC_MIPS_GOT_PAGE: 15064 case BFD_RELOC_MIPS_GOT_OFST: 15065 case BFD_RELOC_MIPS_SUB: 15066 case BFD_RELOC_MIPS_INSERT_A: 15067 case BFD_RELOC_MIPS_INSERT_B: 15068 case BFD_RELOC_MIPS_DELETE: 15069 case BFD_RELOC_MIPS_HIGHEST: 15070 case BFD_RELOC_MIPS_HIGHER: 15071 case BFD_RELOC_MIPS_SCN_DISP: 15072 case BFD_RELOC_MIPS_REL16: 15073 case BFD_RELOC_MIPS_RELGOT: 15074 case BFD_RELOC_MIPS_JALR: 15075 case BFD_RELOC_HI16: 15076 case BFD_RELOC_HI16_S: 15077 case BFD_RELOC_LO16: 15078 case BFD_RELOC_GPREL16: 15079 case BFD_RELOC_MIPS_LITERAL: 15080 case BFD_RELOC_MIPS_CALL16: 15081 case BFD_RELOC_MIPS_GOT16: 15082 case BFD_RELOC_GPREL32: 15083 case BFD_RELOC_MIPS_GOT_HI16: 15084 case BFD_RELOC_MIPS_GOT_LO16: 15085 case BFD_RELOC_MIPS_CALL_HI16: 15086 case BFD_RELOC_MIPS_CALL_LO16: 15087 case BFD_RELOC_MIPS16_GPREL: 15088 case BFD_RELOC_MIPS16_GOT16: 15089 case BFD_RELOC_MIPS16_CALL16: 15090 case BFD_RELOC_MIPS16_HI16: 15091 case BFD_RELOC_MIPS16_HI16_S: 15092 case BFD_RELOC_MIPS16_LO16: 15093 case BFD_RELOC_MIPS16_JMP: 15094 case BFD_RELOC_MICROMIPS_JMP: 15095 case BFD_RELOC_MICROMIPS_GOT_DISP: 15096 case BFD_RELOC_MICROMIPS_GOT_PAGE: 15097 case BFD_RELOC_MICROMIPS_GOT_OFST: 15098 case BFD_RELOC_MICROMIPS_SUB: 15099 case BFD_RELOC_MICROMIPS_HIGHEST: 15100 case BFD_RELOC_MICROMIPS_HIGHER: 15101 case BFD_RELOC_MICROMIPS_SCN_DISP: 15102 case BFD_RELOC_MICROMIPS_JALR: 15103 case BFD_RELOC_MICROMIPS_HI16: 15104 case BFD_RELOC_MICROMIPS_HI16_S: 15105 case BFD_RELOC_MICROMIPS_LO16: 15106 case BFD_RELOC_MICROMIPS_GPREL16: 15107 case BFD_RELOC_MICROMIPS_LITERAL: 15108 case BFD_RELOC_MICROMIPS_CALL16: 15109 case BFD_RELOC_MICROMIPS_GOT16: 15110 case BFD_RELOC_MICROMIPS_GOT_HI16: 15111 case BFD_RELOC_MICROMIPS_GOT_LO16: 15112 case BFD_RELOC_MICROMIPS_CALL_HI16: 15113 case BFD_RELOC_MICROMIPS_CALL_LO16: 15114 case BFD_RELOC_MIPS_EH: 15115 if (fixP->fx_done) 15116 { 15117 offsetT value; 15118 15119 if (calculate_reloc (fixP->fx_r_type, *valP, &value)) 15120 { 15121 insn = read_reloc_insn (buf, fixP->fx_r_type); 15122 if (mips16_reloc_p (fixP->fx_r_type)) 15123 insn |= mips16_immed_extend (value, 16); 15124 else 15125 insn |= (value & 0xffff); 15126 write_reloc_insn (buf, fixP->fx_r_type, insn); 15127 } 15128 else 15129 as_bad_where (fixP->fx_file, fixP->fx_line, 15130 _("unsupported constant in relocation")); 15131 } 15132 break; 15133 15134 case BFD_RELOC_64: 15135 /* This is handled like BFD_RELOC_32, but we output a sign 15136 extended value if we are only 32 bits. */ 15137 if (fixP->fx_done) 15138 { 15139 if (8 <= sizeof (valueT)) 15140 md_number_to_chars (buf, *valP, 8); 15141 else 15142 { 15143 valueT hiv; 15144 15145 if ((*valP & 0x80000000) != 0) 15146 hiv = 0xffffffff; 15147 else 15148 hiv = 0; 15149 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); 15150 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); 15151 } 15152 } 15153 break; 15154 15155 case BFD_RELOC_RVA: 15156 case BFD_RELOC_32: 15157 case BFD_RELOC_32_PCREL: 15158 case BFD_RELOC_16: 15159 case BFD_RELOC_8: 15160 /* If we are deleting this reloc entry, we must fill in the 15161 value now. This can happen if we have a .word which is not 15162 resolved when it appears but is later defined. */ 15163 if (fixP->fx_done) 15164 md_number_to_chars (buf, *valP, fixP->fx_size); 15165 break; 15166 15167 case BFD_RELOC_MIPS_21_PCREL_S2: 15168 case BFD_RELOC_MIPS_26_PCREL_S2: 15169 if ((*valP & 0x3) != 0) 15170 as_bad_where (fixP->fx_file, fixP->fx_line, 15171 _("branch to misaligned address (%lx)"), (long) *valP); 15172 15173 gas_assert (!fixP->fx_done); 15174 break; 15175 15176 case BFD_RELOC_MIPS_18_PCREL_S3: 15177 if ((*valP & 0x7) != 0) 15178 as_bad_where (fixP->fx_file, fixP->fx_line, 15179 _("PC-relative access to misaligned address (%lx)"), 15180 (long) *valP); 15181 15182 gas_assert (!fixP->fx_done); 15183 break; 15184 15185 case BFD_RELOC_MIPS_19_PCREL_S2: 15186 if ((*valP & 0x3) != 0) 15187 as_bad_where (fixP->fx_file, fixP->fx_line, 15188 _("PC-relative access to misaligned address (%lx)"), 15189 (long) *valP); 15190 15191 gas_assert (!fixP->fx_done); 15192 break; 15193 15194 case BFD_RELOC_HI16_S_PCREL: 15195 case BFD_RELOC_LO16_PCREL: 15196 gas_assert (!fixP->fx_done); 15197 break; 15198 15199 case BFD_RELOC_16_PCREL_S2: 15200 if ((*valP & 0x3) != 0) 15201 as_bad_where (fixP->fx_file, fixP->fx_line, 15202 _("branch to misaligned address (%lx)"), (long) *valP); 15203 15204 /* We need to save the bits in the instruction since fixup_segment() 15205 might be deleting the relocation entry (i.e., a branch within 15206 the current segment). */ 15207 if (! fixP->fx_done) 15208 break; 15209 15210 /* Update old instruction data. */ 15211 insn = read_insn (buf); 15212 15213 if (*valP + 0x20000 <= 0x3ffff) 15214 { 15215 insn |= (*valP >> 2) & 0xffff; 15216 write_insn (buf, insn); 15217 } 15218 else if (mips_pic == NO_PIC 15219 && fixP->fx_done 15220 && fixP->fx_frag->fr_address >= text_section->vma 15221 && (fixP->fx_frag->fr_address 15222 < text_section->vma + bfd_get_section_size (text_section)) 15223 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 15224 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ 15225 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 15226 { 15227 /* The branch offset is too large. If this is an 15228 unconditional branch, and we are not generating PIC code, 15229 we can convert it to an absolute jump instruction. */ 15230 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ 15231 insn = 0x0c000000; /* jal */ 15232 else 15233 insn = 0x08000000; /* j */ 15234 fixP->fx_r_type = BFD_RELOC_MIPS_JMP; 15235 fixP->fx_done = 0; 15236 fixP->fx_addsy = section_symbol (text_section); 15237 *valP += md_pcrel_from (fixP); 15238 write_insn (buf, insn); 15239 } 15240 else 15241 { 15242 /* If we got here, we have branch-relaxation disabled, 15243 and there's nothing we can do to fix this instruction 15244 without turning it into a longer sequence. */ 15245 as_bad_where (fixP->fx_file, fixP->fx_line, 15246 _("branch out of range")); 15247 } 15248 break; 15249 15250 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15251 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15252 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15253 /* We adjust the offset back to even. */ 15254 if ((*valP & 0x1) != 0) 15255 --(*valP); 15256 15257 if (! fixP->fx_done) 15258 break; 15259 15260 /* Should never visit here, because we keep the relocation. */ 15261 abort (); 15262 break; 15263 15264 case BFD_RELOC_VTABLE_INHERIT: 15265 fixP->fx_done = 0; 15266 if (fixP->fx_addsy 15267 && !S_IS_DEFINED (fixP->fx_addsy) 15268 && !S_IS_WEAK (fixP->fx_addsy)) 15269 S_SET_WEAK (fixP->fx_addsy); 15270 break; 15271 15272 case BFD_RELOC_VTABLE_ENTRY: 15273 fixP->fx_done = 0; 15274 break; 15275 15276 default: 15277 abort (); 15278 } 15279 15280 /* Remember value for tc_gen_reloc. */ 15281 fixP->fx_addnumber = *valP; 15282 } 15283 15284 static symbolS * 15285 get_symbol (void) 15286 { 15287 int c; 15288 char *name; 15289 symbolS *p; 15290 15291 name = input_line_pointer; 15292 c = get_symbol_end (); 15293 p = (symbolS *) symbol_find_or_make (name); 15294 *input_line_pointer = c; 15295 return p; 15296 } 15297 15298 /* Align the current frag to a given power of two. If a particular 15299 fill byte should be used, FILL points to an integer that contains 15300 that byte, otherwise FILL is null. 15301 15302 This function used to have the comment: 15303 15304 The MIPS assembler also automatically adjusts any preceding label. 15305 15306 The implementation therefore applied the adjustment to a maximum of 15307 one label. However, other label adjustments are applied to batches 15308 of labels, and adjusting just one caused problems when new labels 15309 were added for the sake of debugging or unwind information. 15310 We therefore adjust all preceding labels (given as LABELS) instead. */ 15311 15312 static void 15313 mips_align (int to, int *fill, struct insn_label_list *labels) 15314 { 15315 mips_emit_delays (); 15316 mips_record_compressed_mode (); 15317 if (fill == NULL && subseg_text_p (now_seg)) 15318 frag_align_code (to, 0); 15319 else 15320 frag_align (to, fill ? *fill : 0, 0); 15321 record_alignment (now_seg, to); 15322 mips_move_labels (labels, FALSE); 15323 } 15324 15325 /* Align to a given power of two. .align 0 turns off the automatic 15326 alignment used by the data creating pseudo-ops. */ 15327 15328 static void 15329 s_align (int x ATTRIBUTE_UNUSED) 15330 { 15331 int temp, fill_value, *fill_ptr; 15332 long max_alignment = 28; 15333 15334 /* o Note that the assembler pulls down any immediately preceding label 15335 to the aligned address. 15336 o It's not documented but auto alignment is reinstated by 15337 a .align pseudo instruction. 15338 o Note also that after auto alignment is turned off the mips assembler 15339 issues an error on attempt to assemble an improperly aligned data item. 15340 We don't. */ 15341 15342 temp = get_absolute_expression (); 15343 if (temp > max_alignment) 15344 as_bad (_("alignment too large, %d assumed"), temp = max_alignment); 15345 else if (temp < 0) 15346 { 15347 as_warn (_("alignment negative, 0 assumed")); 15348 temp = 0; 15349 } 15350 if (*input_line_pointer == ',') 15351 { 15352 ++input_line_pointer; 15353 fill_value = get_absolute_expression (); 15354 fill_ptr = &fill_value; 15355 } 15356 else 15357 fill_ptr = 0; 15358 if (temp) 15359 { 15360 segment_info_type *si = seg_info (now_seg); 15361 struct insn_label_list *l = si->label_list; 15362 /* Auto alignment should be switched on by next section change. */ 15363 auto_align = 1; 15364 mips_align (temp, fill_ptr, l); 15365 } 15366 else 15367 { 15368 auto_align = 0; 15369 } 15370 15371 demand_empty_rest_of_line (); 15372 } 15373 15374 static void 15375 s_change_sec (int sec) 15376 { 15377 segT seg; 15378 15379 /* The ELF backend needs to know that we are changing sections, so 15380 that .previous works correctly. We could do something like check 15381 for an obj_section_change_hook macro, but that might be confusing 15382 as it would not be appropriate to use it in the section changing 15383 functions in read.c, since obj-elf.c intercepts those. FIXME: 15384 This should be cleaner, somehow. */ 15385 obj_elf_section_change_hook (); 15386 15387 mips_emit_delays (); 15388 15389 switch (sec) 15390 { 15391 case 't': 15392 s_text (0); 15393 break; 15394 case 'd': 15395 s_data (0); 15396 break; 15397 case 'b': 15398 subseg_set (bss_section, (subsegT) get_absolute_expression ()); 15399 demand_empty_rest_of_line (); 15400 break; 15401 15402 case 'r': 15403 seg = subseg_new (RDATA_SECTION_NAME, 15404 (subsegT) get_absolute_expression ()); 15405 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD 15406 | SEC_READONLY | SEC_RELOC 15407 | SEC_DATA)); 15408 if (strncmp (TARGET_OS, "elf", 3) != 0) 15409 record_alignment (seg, 4); 15410 demand_empty_rest_of_line (); 15411 break; 15412 15413 case 's': 15414 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); 15415 bfd_set_section_flags (stdoutput, seg, 15416 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); 15417 if (strncmp (TARGET_OS, "elf", 3) != 0) 15418 record_alignment (seg, 4); 15419 demand_empty_rest_of_line (); 15420 break; 15421 15422 case 'B': 15423 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); 15424 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); 15425 if (strncmp (TARGET_OS, "elf", 3) != 0) 15426 record_alignment (seg, 4); 15427 demand_empty_rest_of_line (); 15428 break; 15429 } 15430 15431 auto_align = 1; 15432 } 15433 15434 void 15435 s_change_section (int ignore ATTRIBUTE_UNUSED) 15436 { 15437 char *section_name; 15438 char c; 15439 char next_c = 0; 15440 int section_type; 15441 int section_flag; 15442 int section_entry_size; 15443 int section_alignment; 15444 15445 section_name = input_line_pointer; 15446 c = get_symbol_end (); 15447 if (c) 15448 next_c = *(input_line_pointer + 1); 15449 15450 /* Do we have .section Name<,"flags">? */ 15451 if (c != ',' || (c == ',' && next_c == '"')) 15452 { 15453 /* just after name is now '\0'. */ 15454 *input_line_pointer = c; 15455 input_line_pointer = section_name; 15456 obj_elf_section (ignore); 15457 return; 15458 } 15459 input_line_pointer++; 15460 15461 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ 15462 if (c == ',') 15463 section_type = get_absolute_expression (); 15464 else 15465 section_type = 0; 15466 if (*input_line_pointer++ == ',') 15467 section_flag = get_absolute_expression (); 15468 else 15469 section_flag = 0; 15470 if (*input_line_pointer++ == ',') 15471 section_entry_size = get_absolute_expression (); 15472 else 15473 section_entry_size = 0; 15474 if (*input_line_pointer++ == ',') 15475 section_alignment = get_absolute_expression (); 15476 else 15477 section_alignment = 0; 15478 /* FIXME: really ignore? */ 15479 (void) section_alignment; 15480 15481 section_name = xstrdup (section_name); 15482 15483 /* When using the generic form of .section (as implemented by obj-elf.c), 15484 there's no way to set the section type to SHT_MIPS_DWARF. Users have 15485 traditionally had to fall back on the more common @progbits instead. 15486 15487 There's nothing really harmful in this, since bfd will correct 15488 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it 15489 means that, for backwards compatibility, the special_section entries 15490 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. 15491 15492 Even so, we shouldn't force users of the MIPS .section syntax to 15493 incorrectly label the sections as SHT_PROGBITS. The best compromise 15494 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the 15495 generic type-checking code. */ 15496 if (section_type == SHT_MIPS_DWARF) 15497 section_type = SHT_PROGBITS; 15498 15499 obj_elf_change_section (section_name, section_type, section_flag, 15500 section_entry_size, 0, 0, 0); 15501 15502 if (now_seg->name != section_name) 15503 free (section_name); 15504 } 15505 15506 void 15507 mips_enable_auto_align (void) 15508 { 15509 auto_align = 1; 15510 } 15511 15512 static void 15513 s_cons (int log_size) 15514 { 15515 segment_info_type *si = seg_info (now_seg); 15516 struct insn_label_list *l = si->label_list; 15517 15518 mips_emit_delays (); 15519 if (log_size > 0 && auto_align) 15520 mips_align (log_size, 0, l); 15521 cons (1 << log_size); 15522 mips_clear_insn_labels (); 15523 } 15524 15525 static void 15526 s_float_cons (int type) 15527 { 15528 segment_info_type *si = seg_info (now_seg); 15529 struct insn_label_list *l = si->label_list; 15530 15531 mips_emit_delays (); 15532 15533 if (auto_align) 15534 { 15535 if (type == 'd') 15536 mips_align (3, 0, l); 15537 else 15538 mips_align (2, 0, l); 15539 } 15540 15541 float_cons (type); 15542 mips_clear_insn_labels (); 15543 } 15544 15545 /* Handle .globl. We need to override it because on Irix 5 you are 15546 permitted to say 15547 .globl foo .text 15548 where foo is an undefined symbol, to mean that foo should be 15549 considered to be the address of a function. */ 15550 15551 static void 15552 s_mips_globl (int x ATTRIBUTE_UNUSED) 15553 { 15554 char *name; 15555 int c; 15556 symbolS *symbolP; 15557 flagword flag; 15558 15559 do 15560 { 15561 name = input_line_pointer; 15562 c = get_symbol_end (); 15563 symbolP = symbol_find_or_make (name); 15564 S_SET_EXTERNAL (symbolP); 15565 15566 *input_line_pointer = c; 15567 SKIP_WHITESPACE (); 15568 15569 /* On Irix 5, every global symbol that is not explicitly labelled as 15570 being a function is apparently labelled as being an object. */ 15571 flag = BSF_OBJECT; 15572 15573 if (!is_end_of_line[(unsigned char) *input_line_pointer] 15574 && (*input_line_pointer != ',')) 15575 { 15576 char *secname; 15577 asection *sec; 15578 15579 secname = input_line_pointer; 15580 c = get_symbol_end (); 15581 sec = bfd_get_section_by_name (stdoutput, secname); 15582 if (sec == NULL) 15583 as_bad (_("%s: no such section"), secname); 15584 *input_line_pointer = c; 15585 15586 if (sec != NULL && (sec->flags & SEC_CODE) != 0) 15587 flag = BSF_FUNCTION; 15588 } 15589 15590 symbol_get_bfdsym (symbolP)->flags |= flag; 15591 15592 c = *input_line_pointer; 15593 if (c == ',') 15594 { 15595 input_line_pointer++; 15596 SKIP_WHITESPACE (); 15597 if (is_end_of_line[(unsigned char) *input_line_pointer]) 15598 c = '\n'; 15599 } 15600 } 15601 while (c == ','); 15602 15603 demand_empty_rest_of_line (); 15604 } 15605 15606 static void 15607 s_option (int x ATTRIBUTE_UNUSED) 15608 { 15609 char *opt; 15610 char c; 15611 15612 opt = input_line_pointer; 15613 c = get_symbol_end (); 15614 15615 if (*opt == 'O') 15616 { 15617 /* FIXME: What does this mean? */ 15618 } 15619 else if (strncmp (opt, "pic", 3) == 0) 15620 { 15621 int i; 15622 15623 i = atoi (opt + 3); 15624 if (i == 0) 15625 mips_pic = NO_PIC; 15626 else if (i == 2) 15627 { 15628 mips_pic = SVR4_PIC; 15629 mips_abicalls = TRUE; 15630 } 15631 else 15632 as_bad (_(".option pic%d not supported"), i); 15633 15634 if (mips_pic == SVR4_PIC) 15635 { 15636 if (g_switch_seen && g_switch_value != 0) 15637 as_warn (_("-G may not be used with SVR4 PIC code")); 15638 g_switch_value = 0; 15639 bfd_set_gp_size (stdoutput, 0); 15640 } 15641 } 15642 else 15643 as_warn (_("unrecognized option \"%s\""), opt); 15644 15645 *input_line_pointer = c; 15646 demand_empty_rest_of_line (); 15647 } 15648 15649 /* This structure is used to hold a stack of .set values. */ 15650 15651 struct mips_option_stack 15652 { 15653 struct mips_option_stack *next; 15654 struct mips_set_options options; 15655 }; 15656 15657 static struct mips_option_stack *mips_opts_stack; 15658 15659 static bfd_boolean 15660 parse_code_option (char * name) 15661 { 15662 const struct mips_ase *ase; 15663 if (strncmp (name, "at=", 3) == 0) 15664 { 15665 char *s = name + 3; 15666 15667 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) 15668 as_bad (_("unrecognized register name `%s'"), s); 15669 } 15670 else if (strcmp (name, "at") == 0) 15671 mips_opts.at = ATREG; 15672 else if (strcmp (name, "noat") == 0) 15673 mips_opts.at = ZERO; 15674 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) 15675 mips_opts.nomove = 0; 15676 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) 15677 mips_opts.nomove = 1; 15678 else if (strcmp (name, "bopt") == 0) 15679 mips_opts.nobopt = 0; 15680 else if (strcmp (name, "nobopt") == 0) 15681 mips_opts.nobopt = 1; 15682 else if (strcmp (name, "gp=32") == 0) 15683 mips_opts.gp = 32; 15684 else if (strcmp (name, "gp=64") == 0) 15685 mips_opts.gp = 64; 15686 else if (strcmp (name, "fp=32") == 0) 15687 mips_opts.fp = 32; 15688 else if (strcmp (name, "fp=xx") == 0) 15689 mips_opts.fp = 0; 15690 else if (strcmp (name, "fp=64") == 0) 15691 mips_opts.fp = 64; 15692 else if (strcmp (name, "softfloat") == 0) 15693 mips_opts.soft_float = 1; 15694 else if (strcmp (name, "hardfloat") == 0) 15695 mips_opts.soft_float = 0; 15696 else if (strcmp (name, "singlefloat") == 0) 15697 mips_opts.single_float = 1; 15698 else if (strcmp (name, "doublefloat") == 0) 15699 mips_opts.single_float = 0; 15700 else if (strcmp (name, "nooddspreg") == 0) 15701 mips_opts.oddspreg = 0; 15702 else if (strcmp (name, "oddspreg") == 0) 15703 mips_opts.oddspreg = 1; 15704 else if (strcmp (name, "mips16") == 0 15705 || strcmp (name, "MIPS-16") == 0) 15706 mips_opts.mips16 = 1; 15707 else if (strcmp (name, "nomips16") == 0 15708 || strcmp (name, "noMIPS-16") == 0) 15709 mips_opts.mips16 = 0; 15710 else if (strcmp (name, "micromips") == 0) 15711 mips_opts.micromips = 1; 15712 else if (strcmp (name, "nomicromips") == 0) 15713 mips_opts.micromips = 0; 15714 else if (name[0] == 'n' 15715 && name[1] == 'o' 15716 && (ase = mips_lookup_ase (name + 2))) 15717 mips_set_ase (ase, &mips_opts, FALSE); 15718 else if ((ase = mips_lookup_ase (name))) 15719 mips_set_ase (ase, &mips_opts, TRUE); 15720 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) 15721 { 15722 /* Permit the user to change the ISA and architecture on the fly. 15723 Needless to say, misuse can cause serious problems. */ 15724 if (strncmp (name, "arch=", 5) == 0) 15725 { 15726 const struct mips_cpu_info *p; 15727 15728 p = mips_parse_cpu ("internal use", name + 5); 15729 if (!p) 15730 as_bad (_("unknown architecture %s"), name + 5); 15731 else 15732 { 15733 mips_opts.arch = p->cpu; 15734 mips_opts.isa = p->isa; 15735 } 15736 } 15737 else if (strncmp (name, "mips", 4) == 0) 15738 { 15739 const struct mips_cpu_info *p; 15740 15741 p = mips_parse_cpu ("internal use", name); 15742 if (!p) 15743 as_bad (_("unknown ISA level %s"), name + 4); 15744 else 15745 { 15746 mips_opts.arch = p->cpu; 15747 mips_opts.isa = p->isa; 15748 } 15749 } 15750 else 15751 as_bad (_("unknown ISA or architecture %s"), name); 15752 } 15753 else if (strcmp (name, "autoextend") == 0) 15754 mips_opts.noautoextend = 0; 15755 else if (strcmp (name, "noautoextend") == 0) 15756 mips_opts.noautoextend = 1; 15757 else if (strcmp (name, "insn32") == 0) 15758 mips_opts.insn32 = TRUE; 15759 else if (strcmp (name, "noinsn32") == 0) 15760 mips_opts.insn32 = FALSE; 15761 else if (strcmp (name, "sym32") == 0) 15762 mips_opts.sym32 = TRUE; 15763 else if (strcmp (name, "nosym32") == 0) 15764 mips_opts.sym32 = FALSE; 15765 else 15766 return FALSE; 15767 return TRUE; 15768 } 15769 15770 /* Handle the .set pseudo-op. */ 15771 15772 static void 15773 s_mipsset (int x ATTRIBUTE_UNUSED) 15774 { 15775 char *name = input_line_pointer, ch; 15776 int prev_isa = mips_opts.isa; 15777 15778 file_mips_check_options (); 15779 15780 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 15781 ++input_line_pointer; 15782 ch = *input_line_pointer; 15783 *input_line_pointer = '\0'; 15784 15785 if (strchr (name, ',')) 15786 { 15787 /* Generic ".set" directive; use the generic handler. */ 15788 *input_line_pointer = ch; 15789 input_line_pointer = name; 15790 s_set (0); 15791 return; 15792 } 15793 15794 if (strcmp (name, "reorder") == 0) 15795 { 15796 if (mips_opts.noreorder) 15797 end_noreorder (); 15798 } 15799 else if (strcmp (name, "noreorder") == 0) 15800 { 15801 if (!mips_opts.noreorder) 15802 start_noreorder (); 15803 } 15804 else if (strcmp (name, "macro") == 0) 15805 mips_opts.warn_about_macros = 0; 15806 else if (strcmp (name, "nomacro") == 0) 15807 { 15808 if (mips_opts.noreorder == 0) 15809 as_bad (_("`noreorder' must be set before `nomacro'")); 15810 mips_opts.warn_about_macros = 1; 15811 } 15812 else if (strcmp (name, "gp=default") == 0) 15813 mips_opts.gp = file_mips_opts.gp; 15814 else if (strcmp (name, "fp=default") == 0) 15815 mips_opts.fp = file_mips_opts.fp; 15816 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) 15817 { 15818 mips_opts.isa = file_mips_opts.isa; 15819 mips_opts.arch = file_mips_opts.arch; 15820 mips_opts.gp = file_mips_opts.gp; 15821 mips_opts.fp = file_mips_opts.fp; 15822 } 15823 else if (strcmp (name, "push") == 0) 15824 { 15825 struct mips_option_stack *s; 15826 15827 s = (struct mips_option_stack *) xmalloc (sizeof *s); 15828 s->next = mips_opts_stack; 15829 s->options = mips_opts; 15830 mips_opts_stack = s; 15831 } 15832 else if (strcmp (name, "pop") == 0) 15833 { 15834 struct mips_option_stack *s; 15835 15836 s = mips_opts_stack; 15837 if (s == NULL) 15838 as_bad (_(".set pop with no .set push")); 15839 else 15840 { 15841 /* If we're changing the reorder mode we need to handle 15842 delay slots correctly. */ 15843 if (s->options.noreorder && ! mips_opts.noreorder) 15844 start_noreorder (); 15845 else if (! s->options.noreorder && mips_opts.noreorder) 15846 end_noreorder (); 15847 15848 mips_opts = s->options; 15849 mips_opts_stack = s->next; 15850 free (s); 15851 } 15852 } 15853 else if (!parse_code_option (name)) 15854 as_warn (_("tried to set unrecognized symbol: %s\n"), name); 15855 15856 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp 15857 registers based on what is supported by the arch/cpu. */ 15858 if (mips_opts.isa != prev_isa) 15859 { 15860 switch (mips_opts.isa) 15861 { 15862 case 0: 15863 break; 15864 case ISA_MIPS1: 15865 /* MIPS I cannot support FPXX. */ 15866 mips_opts.fp = 32; 15867 /* fall-through. */ 15868 case ISA_MIPS2: 15869 case ISA_MIPS32: 15870 case ISA_MIPS32R2: 15871 case ISA_MIPS32R3: 15872 case ISA_MIPS32R5: 15873 mips_opts.gp = 32; 15874 if (mips_opts.fp != 0) 15875 mips_opts.fp = 32; 15876 break; 15877 case ISA_MIPS32R6: 15878 mips_opts.gp = 32; 15879 mips_opts.fp = 64; 15880 break; 15881 case ISA_MIPS3: 15882 case ISA_MIPS4: 15883 case ISA_MIPS5: 15884 case ISA_MIPS64: 15885 case ISA_MIPS64R2: 15886 case ISA_MIPS64R3: 15887 case ISA_MIPS64R5: 15888 case ISA_MIPS64R6: 15889 mips_opts.gp = 64; 15890 if (mips_opts.fp != 0) 15891 { 15892 if (mips_opts.arch == CPU_R5900) 15893 mips_opts.fp = 32; 15894 else 15895 mips_opts.fp = 64; 15896 } 15897 break; 15898 default: 15899 as_bad (_("unknown ISA level %s"), name + 4); 15900 break; 15901 } 15902 } 15903 15904 mips_check_options (&mips_opts, FALSE); 15905 15906 mips_check_isa_supports_ases (); 15907 *input_line_pointer = ch; 15908 demand_empty_rest_of_line (); 15909 } 15910 15911 /* Handle the .module pseudo-op. */ 15912 15913 static void 15914 s_module (int ignore ATTRIBUTE_UNUSED) 15915 { 15916 char *name = input_line_pointer, ch; 15917 15918 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 15919 ++input_line_pointer; 15920 ch = *input_line_pointer; 15921 *input_line_pointer = '\0'; 15922 15923 if (!file_mips_opts_checked) 15924 { 15925 if (!parse_code_option (name)) 15926 as_bad (_(".module used with unrecognized symbol: %s\n"), name); 15927 15928 /* Update module level settings from mips_opts. */ 15929 file_mips_opts = mips_opts; 15930 } 15931 else 15932 as_bad (_(".module is not permitted after generating code")); 15933 15934 *input_line_pointer = ch; 15935 demand_empty_rest_of_line (); 15936 } 15937 15938 /* Handle the .abicalls pseudo-op. I believe this is equivalent to 15939 .option pic2. It means to generate SVR4 PIC calls. */ 15940 15941 static void 15942 s_abicalls (int ignore ATTRIBUTE_UNUSED) 15943 { 15944 mips_pic = SVR4_PIC; 15945 mips_abicalls = TRUE; 15946 15947 if (g_switch_seen && g_switch_value != 0) 15948 as_warn (_("-G may not be used with SVR4 PIC code")); 15949 g_switch_value = 0; 15950 15951 bfd_set_gp_size (stdoutput, 0); 15952 demand_empty_rest_of_line (); 15953 } 15954 15955 /* Handle the .cpload pseudo-op. This is used when generating SVR4 15956 PIC code. It sets the $gp register for the function based on the 15957 function address, which is in the register named in the argument. 15958 This uses a relocation against _gp_disp, which is handled specially 15959 by the linker. The result is: 15960 lui $gp,%hi(_gp_disp) 15961 addiu $gp,$gp,%lo(_gp_disp) 15962 addu $gp,$gp,.cpload argument 15963 The .cpload argument is normally $25 == $t9. 15964 15965 The -mno-shared option changes this to: 15966 lui $gp,%hi(__gnu_local_gp) 15967 addiu $gp,$gp,%lo(__gnu_local_gp) 15968 and the argument is ignored. This saves an instruction, but the 15969 resulting code is not position independent; it uses an absolute 15970 address for __gnu_local_gp. Thus code assembled with -mno-shared 15971 can go into an ordinary executable, but not into a shared library. */ 15972 15973 static void 15974 s_cpload (int ignore ATTRIBUTE_UNUSED) 15975 { 15976 expressionS ex; 15977 int reg; 15978 int in_shared; 15979 15980 file_mips_check_options (); 15981 15982 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 15983 .cpload is ignored. */ 15984 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 15985 { 15986 s_ignore (0); 15987 return; 15988 } 15989 15990 if (mips_opts.mips16) 15991 { 15992 as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); 15993 ignore_rest_of_line (); 15994 return; 15995 } 15996 15997 /* .cpload should be in a .set noreorder section. */ 15998 if (mips_opts.noreorder == 0) 15999 as_warn (_(".cpload not in noreorder section")); 16000 16001 reg = tc_get_register (0); 16002 16003 /* If we need to produce a 64-bit address, we are better off using 16004 the default instruction sequence. */ 16005 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; 16006 16007 ex.X_op = O_symbol; 16008 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : 16009 "__gnu_local_gp"); 16010 ex.X_op_symbol = NULL; 16011 ex.X_add_number = 0; 16012 16013 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 16014 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 16015 16016 mips_mark_labels (); 16017 mips_assembling_insn = TRUE; 16018 16019 macro_start (); 16020 macro_build_lui (&ex, mips_gp_register); 16021 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 16022 mips_gp_register, BFD_RELOC_LO16); 16023 if (in_shared) 16024 macro_build (NULL, "addu", "d,v,t", mips_gp_register, 16025 mips_gp_register, reg); 16026 macro_end (); 16027 16028 mips_assembling_insn = FALSE; 16029 demand_empty_rest_of_line (); 16030 } 16031 16032 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: 16033 .cpsetup $reg1, offset|$reg2, label 16034 16035 If offset is given, this results in: 16036 sd $gp, offset($sp) 16037 lui $gp, %hi(%neg(%gp_rel(label))) 16038 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 16039 daddu $gp, $gp, $reg1 16040 16041 If $reg2 is given, this results in: 16042 daddu $reg2, $gp, $0 16043 lui $gp, %hi(%neg(%gp_rel(label))) 16044 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 16045 daddu $gp, $gp, $reg1 16046 $reg1 is normally $25 == $t9. 16047 16048 The -mno-shared option replaces the last three instructions with 16049 lui $gp,%hi(_gp) 16050 addiu $gp,$gp,%lo(_gp) */ 16051 16052 static void 16053 s_cpsetup (int ignore ATTRIBUTE_UNUSED) 16054 { 16055 expressionS ex_off; 16056 expressionS ex_sym; 16057 int reg1; 16058 16059 file_mips_check_options (); 16060 16061 /* If we are not generating SVR4 PIC code, .cpsetup is ignored. 16062 We also need NewABI support. */ 16063 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16064 { 16065 s_ignore (0); 16066 return; 16067 } 16068 16069 if (mips_opts.mips16) 16070 { 16071 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); 16072 ignore_rest_of_line (); 16073 return; 16074 } 16075 16076 reg1 = tc_get_register (0); 16077 SKIP_WHITESPACE (); 16078 if (*input_line_pointer != ',') 16079 { 16080 as_bad (_("missing argument separator ',' for .cpsetup")); 16081 return; 16082 } 16083 else 16084 ++input_line_pointer; 16085 SKIP_WHITESPACE (); 16086 if (*input_line_pointer == '$') 16087 { 16088 mips_cpreturn_register = tc_get_register (0); 16089 mips_cpreturn_offset = -1; 16090 } 16091 else 16092 { 16093 mips_cpreturn_offset = get_absolute_expression (); 16094 mips_cpreturn_register = -1; 16095 } 16096 SKIP_WHITESPACE (); 16097 if (*input_line_pointer != ',') 16098 { 16099 as_bad (_("missing argument separator ',' for .cpsetup")); 16100 return; 16101 } 16102 else 16103 ++input_line_pointer; 16104 SKIP_WHITESPACE (); 16105 expression (&ex_sym); 16106 16107 mips_mark_labels (); 16108 mips_assembling_insn = TRUE; 16109 16110 macro_start (); 16111 if (mips_cpreturn_register == -1) 16112 { 16113 ex_off.X_op = O_constant; 16114 ex_off.X_add_symbol = NULL; 16115 ex_off.X_op_symbol = NULL; 16116 ex_off.X_add_number = mips_cpreturn_offset; 16117 16118 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, 16119 BFD_RELOC_LO16, SP); 16120 } 16121 else 16122 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, 16123 mips_gp_register, 0); 16124 16125 if (mips_in_shared || HAVE_64BIT_SYMBOLS) 16126 { 16127 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, 16128 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, 16129 BFD_RELOC_HI16_S); 16130 16131 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, 16132 mips_gp_register, -1, BFD_RELOC_GPREL16, 16133 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); 16134 16135 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, 16136 mips_gp_register, reg1); 16137 } 16138 else 16139 { 16140 expressionS ex; 16141 16142 ex.X_op = O_symbol; 16143 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); 16144 ex.X_op_symbol = NULL; 16145 ex.X_add_number = 0; 16146 16147 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 16148 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 16149 16150 macro_build_lui (&ex, mips_gp_register); 16151 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 16152 mips_gp_register, BFD_RELOC_LO16); 16153 } 16154 16155 macro_end (); 16156 16157 mips_assembling_insn = FALSE; 16158 demand_empty_rest_of_line (); 16159 } 16160 16161 static void 16162 s_cplocal (int ignore ATTRIBUTE_UNUSED) 16163 { 16164 file_mips_check_options (); 16165 16166 /* If we are not generating SVR4 PIC code, or if this is not NewABI code, 16167 .cplocal is ignored. */ 16168 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16169 { 16170 s_ignore (0); 16171 return; 16172 } 16173 16174 if (mips_opts.mips16) 16175 { 16176 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); 16177 ignore_rest_of_line (); 16178 return; 16179 } 16180 16181 mips_gp_register = tc_get_register (0); 16182 demand_empty_rest_of_line (); 16183 } 16184 16185 /* Handle the .cprestore pseudo-op. This stores $gp into a given 16186 offset from $sp. The offset is remembered, and after making a PIC 16187 call $gp is restored from that location. */ 16188 16189 static void 16190 s_cprestore (int ignore ATTRIBUTE_UNUSED) 16191 { 16192 expressionS ex; 16193 16194 file_mips_check_options (); 16195 16196 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 16197 .cprestore is ignored. */ 16198 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 16199 { 16200 s_ignore (0); 16201 return; 16202 } 16203 16204 if (mips_opts.mips16) 16205 { 16206 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); 16207 ignore_rest_of_line (); 16208 return; 16209 } 16210 16211 mips_cprestore_offset = get_absolute_expression (); 16212 mips_cprestore_valid = 1; 16213 16214 ex.X_op = O_constant; 16215 ex.X_add_symbol = NULL; 16216 ex.X_op_symbol = NULL; 16217 ex.X_add_number = mips_cprestore_offset; 16218 16219 mips_mark_labels (); 16220 mips_assembling_insn = TRUE; 16221 16222 macro_start (); 16223 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, 16224 SP, HAVE_64BIT_ADDRESSES); 16225 macro_end (); 16226 16227 mips_assembling_insn = FALSE; 16228 demand_empty_rest_of_line (); 16229 } 16230 16231 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset 16232 was given in the preceding .cpsetup, it results in: 16233 ld $gp, offset($sp) 16234 16235 If a register $reg2 was given there, it results in: 16236 daddu $gp, $reg2, $0 */ 16237 16238 static void 16239 s_cpreturn (int ignore ATTRIBUTE_UNUSED) 16240 { 16241 expressionS ex; 16242 16243 file_mips_check_options (); 16244 16245 /* If we are not generating SVR4 PIC code, .cpreturn is ignored. 16246 We also need NewABI support. */ 16247 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16248 { 16249 s_ignore (0); 16250 return; 16251 } 16252 16253 if (mips_opts.mips16) 16254 { 16255 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); 16256 ignore_rest_of_line (); 16257 return; 16258 } 16259 16260 mips_mark_labels (); 16261 mips_assembling_insn = TRUE; 16262 16263 macro_start (); 16264 if (mips_cpreturn_register == -1) 16265 { 16266 ex.X_op = O_constant; 16267 ex.X_add_symbol = NULL; 16268 ex.X_op_symbol = NULL; 16269 ex.X_add_number = mips_cpreturn_offset; 16270 16271 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); 16272 } 16273 else 16274 macro_build (NULL, "daddu", "d,v,t", mips_gp_register, 16275 mips_cpreturn_register, 0); 16276 macro_end (); 16277 16278 mips_assembling_insn = FALSE; 16279 demand_empty_rest_of_line (); 16280 } 16281 16282 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword 16283 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size 16284 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF 16285 debug information or MIPS16 TLS. */ 16286 16287 static void 16288 s_tls_rel_directive (const size_t bytes, const char *dirstr, 16289 bfd_reloc_code_real_type rtype) 16290 { 16291 expressionS ex; 16292 char *p; 16293 16294 expression (&ex); 16295 16296 if (ex.X_op != O_symbol) 16297 { 16298 as_bad (_("unsupported use of %s"), dirstr); 16299 ignore_rest_of_line (); 16300 } 16301 16302 p = frag_more (bytes); 16303 md_number_to_chars (p, 0, bytes); 16304 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); 16305 demand_empty_rest_of_line (); 16306 mips_clear_insn_labels (); 16307 } 16308 16309 /* Handle .dtprelword. */ 16310 16311 static void 16312 s_dtprelword (int ignore ATTRIBUTE_UNUSED) 16313 { 16314 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); 16315 } 16316 16317 /* Handle .dtpreldword. */ 16318 16319 static void 16320 s_dtpreldword (int ignore ATTRIBUTE_UNUSED) 16321 { 16322 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); 16323 } 16324 16325 /* Handle .tprelword. */ 16326 16327 static void 16328 s_tprelword (int ignore ATTRIBUTE_UNUSED) 16329 { 16330 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); 16331 } 16332 16333 /* Handle .tpreldword. */ 16334 16335 static void 16336 s_tpreldword (int ignore ATTRIBUTE_UNUSED) 16337 { 16338 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); 16339 } 16340 16341 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC 16342 code. It sets the offset to use in gp_rel relocations. */ 16343 16344 static void 16345 s_gpvalue (int ignore ATTRIBUTE_UNUSED) 16346 { 16347 /* If we are not generating SVR4 PIC code, .gpvalue is ignored. 16348 We also need NewABI support. */ 16349 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 16350 { 16351 s_ignore (0); 16352 return; 16353 } 16354 16355 mips_gprel_offset = get_absolute_expression (); 16356 16357 demand_empty_rest_of_line (); 16358 } 16359 16360 /* Handle the .gpword pseudo-op. This is used when generating PIC 16361 code. It generates a 32 bit GP relative reloc. */ 16362 16363 static void 16364 s_gpword (int ignore ATTRIBUTE_UNUSED) 16365 { 16366 segment_info_type *si; 16367 struct insn_label_list *l; 16368 expressionS ex; 16369 char *p; 16370 16371 /* When not generating PIC code, this is treated as .word. */ 16372 if (mips_pic != SVR4_PIC) 16373 { 16374 s_cons (2); 16375 return; 16376 } 16377 16378 si = seg_info (now_seg); 16379 l = si->label_list; 16380 mips_emit_delays (); 16381 if (auto_align) 16382 mips_align (2, 0, l); 16383 16384 expression (&ex); 16385 mips_clear_insn_labels (); 16386 16387 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16388 { 16389 as_bad (_("unsupported use of .gpword")); 16390 ignore_rest_of_line (); 16391 } 16392 16393 p = frag_more (4); 16394 md_number_to_chars (p, 0, 4); 16395 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16396 BFD_RELOC_GPREL32); 16397 16398 demand_empty_rest_of_line (); 16399 } 16400 16401 static void 16402 s_gpdword (int ignore ATTRIBUTE_UNUSED) 16403 { 16404 segment_info_type *si; 16405 struct insn_label_list *l; 16406 expressionS ex; 16407 char *p; 16408 16409 /* When not generating PIC code, this is treated as .dword. */ 16410 if (mips_pic != SVR4_PIC) 16411 { 16412 s_cons (3); 16413 return; 16414 } 16415 16416 si = seg_info (now_seg); 16417 l = si->label_list; 16418 mips_emit_delays (); 16419 if (auto_align) 16420 mips_align (3, 0, l); 16421 16422 expression (&ex); 16423 mips_clear_insn_labels (); 16424 16425 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16426 { 16427 as_bad (_("unsupported use of .gpdword")); 16428 ignore_rest_of_line (); 16429 } 16430 16431 p = frag_more (8); 16432 md_number_to_chars (p, 0, 8); 16433 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16434 BFD_RELOC_GPREL32)->fx_tcbit = 1; 16435 16436 /* GPREL32 composed with 64 gives a 64-bit GP offset. */ 16437 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, 16438 FALSE, BFD_RELOC_64)->fx_tcbit = 1; 16439 16440 demand_empty_rest_of_line (); 16441 } 16442 16443 /* Handle the .ehword pseudo-op. This is used when generating unwinding 16444 tables. It generates a R_MIPS_EH reloc. */ 16445 16446 static void 16447 s_ehword (int ignore ATTRIBUTE_UNUSED) 16448 { 16449 expressionS ex; 16450 char *p; 16451 16452 mips_emit_delays (); 16453 16454 expression (&ex); 16455 mips_clear_insn_labels (); 16456 16457 if (ex.X_op != O_symbol || ex.X_add_number != 0) 16458 { 16459 as_bad (_("unsupported use of .ehword")); 16460 ignore_rest_of_line (); 16461 } 16462 16463 p = frag_more (4); 16464 md_number_to_chars (p, 0, 4); 16465 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 16466 BFD_RELOC_MIPS_EH); 16467 16468 demand_empty_rest_of_line (); 16469 } 16470 16471 /* Handle the .cpadd pseudo-op. This is used when dealing with switch 16472 tables in SVR4 PIC code. */ 16473 16474 static void 16475 s_cpadd (int ignore ATTRIBUTE_UNUSED) 16476 { 16477 int reg; 16478 16479 file_mips_check_options (); 16480 16481 /* This is ignored when not generating SVR4 PIC code. */ 16482 if (mips_pic != SVR4_PIC) 16483 { 16484 s_ignore (0); 16485 return; 16486 } 16487 16488 mips_mark_labels (); 16489 mips_assembling_insn = TRUE; 16490 16491 /* Add $gp to the register named as an argument. */ 16492 macro_start (); 16493 reg = tc_get_register (0); 16494 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); 16495 macro_end (); 16496 16497 mips_assembling_insn = FALSE; 16498 demand_empty_rest_of_line (); 16499 } 16500 16501 /* Handle the .insn pseudo-op. This marks instruction labels in 16502 mips16/micromips mode. This permits the linker to handle them specially, 16503 such as generating jalx instructions when needed. We also make 16504 them odd for the duration of the assembly, in order to generate the 16505 right sort of code. We will make them even in the adjust_symtab 16506 routine, while leaving them marked. This is convenient for the 16507 debugger and the disassembler. The linker knows to make them odd 16508 again. */ 16509 16510 static void 16511 s_insn (int ignore ATTRIBUTE_UNUSED) 16512 { 16513 file_mips_check_options (); 16514 file_ase_mips16 |= mips_opts.mips16; 16515 file_ase_micromips |= mips_opts.micromips; 16516 16517 mips_mark_labels (); 16518 16519 demand_empty_rest_of_line (); 16520 } 16521 16522 /* Handle the .nan pseudo-op. */ 16523 16524 static void 16525 s_nan (int ignore ATTRIBUTE_UNUSED) 16526 { 16527 static const char str_legacy[] = "legacy"; 16528 static const char str_2008[] = "2008"; 16529 size_t i; 16530 16531 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); 16532 16533 if (i == sizeof (str_2008) - 1 16534 && memcmp (input_line_pointer, str_2008, i) == 0) 16535 mips_nan2008 = 1; 16536 else if (i == sizeof (str_legacy) - 1 16537 && memcmp (input_line_pointer, str_legacy, i) == 0) 16538 { 16539 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) 16540 mips_nan2008 = 0; 16541 else 16542 as_bad (_("`%s' does not support legacy NaN"), 16543 mips_cpu_info_from_isa (file_mips_opts.isa)->name); 16544 } 16545 else 16546 as_bad (_("bad .nan directive")); 16547 16548 input_line_pointer += i; 16549 demand_empty_rest_of_line (); 16550 } 16551 16552 /* Handle a .stab[snd] directive. Ideally these directives would be 16553 implemented in a transparent way, so that removing them would not 16554 have any effect on the generated instructions. However, s_stab 16555 internally changes the section, so in practice we need to decide 16556 now whether the preceding label marks compressed code. We do not 16557 support changing the compression mode of a label after a .stab* 16558 directive, such as in: 16559 16560 foo: 16561 .stabs ... 16562 .set mips16 16563 16564 so the current mode wins. */ 16565 16566 static void 16567 s_mips_stab (int type) 16568 { 16569 mips_mark_labels (); 16570 s_stab (type); 16571 } 16572 16573 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ 16574 16575 static void 16576 s_mips_weakext (int ignore ATTRIBUTE_UNUSED) 16577 { 16578 char *name; 16579 int c; 16580 symbolS *symbolP; 16581 expressionS exp; 16582 16583 name = input_line_pointer; 16584 c = get_symbol_end (); 16585 symbolP = symbol_find_or_make (name); 16586 S_SET_WEAK (symbolP); 16587 *input_line_pointer = c; 16588 16589 SKIP_WHITESPACE (); 16590 16591 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 16592 { 16593 if (S_IS_DEFINED (symbolP)) 16594 { 16595 as_bad (_("ignoring attempt to redefine symbol %s"), 16596 S_GET_NAME (symbolP)); 16597 ignore_rest_of_line (); 16598 return; 16599 } 16600 16601 if (*input_line_pointer == ',') 16602 { 16603 ++input_line_pointer; 16604 SKIP_WHITESPACE (); 16605 } 16606 16607 expression (&exp); 16608 if (exp.X_op != O_symbol) 16609 { 16610 as_bad (_("bad .weakext directive")); 16611 ignore_rest_of_line (); 16612 return; 16613 } 16614 symbol_set_value_expression (symbolP, &exp); 16615 } 16616 16617 demand_empty_rest_of_line (); 16618 } 16619 16620 /* Parse a register string into a number. Called from the ECOFF code 16621 to parse .frame. The argument is non-zero if this is the frame 16622 register, so that we can record it in mips_frame_reg. */ 16623 16624 int 16625 tc_get_register (int frame) 16626 { 16627 unsigned int reg; 16628 16629 SKIP_WHITESPACE (); 16630 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) 16631 reg = 0; 16632 if (frame) 16633 { 16634 mips_frame_reg = reg != 0 ? reg : SP; 16635 mips_frame_reg_valid = 1; 16636 mips_cprestore_valid = 0; 16637 } 16638 return reg; 16639 } 16640 16641 valueT 16642 md_section_align (asection *seg, valueT addr) 16643 { 16644 int align = bfd_get_section_alignment (stdoutput, seg); 16645 16646 /* We don't need to align ELF sections to the full alignment. 16647 However, Irix 5 may prefer that we align them at least to a 16 16648 byte boundary. We don't bother to align the sections if we 16649 are targeted for an embedded system. */ 16650 if (strncmp (TARGET_OS, "elf", 3) == 0) 16651 return addr; 16652 if (align > 4) 16653 align = 4; 16654 16655 return ((addr + (1 << align) - 1) & (-1 << align)); 16656 } 16657 16658 /* Utility routine, called from above as well. If called while the 16659 input file is still being read, it's only an approximation. (For 16660 example, a symbol may later become defined which appeared to be 16661 undefined earlier.) */ 16662 16663 static int 16664 nopic_need_relax (symbolS *sym, int before_relaxing) 16665 { 16666 if (sym == 0) 16667 return 0; 16668 16669 if (g_switch_value > 0) 16670 { 16671 const char *symname; 16672 int change; 16673 16674 /* Find out whether this symbol can be referenced off the $gp 16675 register. It can be if it is smaller than the -G size or if 16676 it is in the .sdata or .sbss section. Certain symbols can 16677 not be referenced off the $gp, although it appears as though 16678 they can. */ 16679 symname = S_GET_NAME (sym); 16680 if (symname != (const char *) NULL 16681 && (strcmp (symname, "eprol") == 0 16682 || strcmp (symname, "etext") == 0 16683 || strcmp (symname, "_gp") == 0 16684 || strcmp (symname, "edata") == 0 16685 || strcmp (symname, "_fbss") == 0 16686 || strcmp (symname, "_fdata") == 0 16687 || strcmp (symname, "_ftext") == 0 16688 || strcmp (symname, "end") == 0 16689 || strcmp (symname, "_gp_disp") == 0)) 16690 change = 1; 16691 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) 16692 && (0 16693 #ifndef NO_ECOFF_DEBUGGING 16694 || (symbol_get_obj (sym)->ecoff_extern_size != 0 16695 && (symbol_get_obj (sym)->ecoff_extern_size 16696 <= g_switch_value)) 16697 #endif 16698 /* We must defer this decision until after the whole 16699 file has been read, since there might be a .extern 16700 after the first use of this symbol. */ 16701 || (before_relaxing 16702 #ifndef NO_ECOFF_DEBUGGING 16703 && symbol_get_obj (sym)->ecoff_extern_size == 0 16704 #endif 16705 && S_GET_VALUE (sym) == 0) 16706 || (S_GET_VALUE (sym) != 0 16707 && S_GET_VALUE (sym) <= g_switch_value))) 16708 change = 0; 16709 else 16710 { 16711 const char *segname; 16712 16713 segname = segment_name (S_GET_SEGMENT (sym)); 16714 gas_assert (strcmp (segname, ".lit8") != 0 16715 && strcmp (segname, ".lit4") != 0); 16716 change = (strcmp (segname, ".sdata") != 0 16717 && strcmp (segname, ".sbss") != 0 16718 && strncmp (segname, ".sdata.", 7) != 0 16719 && strncmp (segname, ".sbss.", 6) != 0 16720 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 16721 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); 16722 } 16723 return change; 16724 } 16725 else 16726 /* We are not optimizing for the $gp register. */ 16727 return 1; 16728 } 16729 16730 16731 /* Return true if the given symbol should be considered local for SVR4 PIC. */ 16732 16733 static bfd_boolean 16734 pic_need_relax (symbolS *sym, asection *segtype) 16735 { 16736 asection *symsec; 16737 16738 /* Handle the case of a symbol equated to another symbol. */ 16739 while (symbol_equated_reloc_p (sym)) 16740 { 16741 symbolS *n; 16742 16743 /* It's possible to get a loop here in a badly written program. */ 16744 n = symbol_get_value_expression (sym)->X_add_symbol; 16745 if (n == sym) 16746 break; 16747 sym = n; 16748 } 16749 16750 if (symbol_section_p (sym)) 16751 return TRUE; 16752 16753 symsec = S_GET_SEGMENT (sym); 16754 16755 /* This must duplicate the test in adjust_reloc_syms. */ 16756 return (!bfd_is_und_section (symsec) 16757 && !bfd_is_abs_section (symsec) 16758 && !bfd_is_com_section (symsec) 16759 && !s_is_linkonce (sym, segtype) 16760 /* A global or weak symbol is treated as external. */ 16761 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); 16762 } 16763 16764 16765 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an 16766 extended opcode. SEC is the section the frag is in. */ 16767 16768 static int 16769 mips16_extended_frag (fragS *fragp, asection *sec, long stretch) 16770 { 16771 int type; 16772 const struct mips_int_operand *operand; 16773 offsetT val; 16774 segT symsec; 16775 fragS *sym_frag; 16776 16777 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 16778 return 0; 16779 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 16780 return 1; 16781 16782 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 16783 operand = mips16_immed_operand (type, FALSE); 16784 16785 sym_frag = symbol_get_frag (fragp->fr_symbol); 16786 val = S_GET_VALUE (fragp->fr_symbol); 16787 symsec = S_GET_SEGMENT (fragp->fr_symbol); 16788 16789 if (operand->root.type == OP_PCREL) 16790 { 16791 const struct mips_pcrel_operand *pcrel_op; 16792 addressT addr; 16793 offsetT maxtiny; 16794 16795 /* We won't have the section when we are called from 16796 mips_relax_frag. However, we will always have been called 16797 from md_estimate_size_before_relax first. If this is a 16798 branch to a different section, we mark it as such. If SEC is 16799 NULL, and the frag is not marked, then it must be a branch to 16800 the same section. */ 16801 pcrel_op = (const struct mips_pcrel_operand *) operand; 16802 if (sec == NULL) 16803 { 16804 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) 16805 return 1; 16806 } 16807 else 16808 { 16809 /* Must have been called from md_estimate_size_before_relax. */ 16810 if (symsec != sec) 16811 { 16812 fragp->fr_subtype = 16813 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 16814 16815 /* FIXME: We should support this, and let the linker 16816 catch branches and loads that are out of range. */ 16817 as_bad_where (fragp->fr_file, fragp->fr_line, 16818 _("unsupported PC relative reference to different section")); 16819 16820 return 1; 16821 } 16822 if (fragp != sym_frag && sym_frag->fr_address == 0) 16823 /* Assume non-extended on the first relaxation pass. 16824 The address we have calculated will be bogus if this is 16825 a forward branch to another frag, as the forward frag 16826 will have fr_address == 0. */ 16827 return 0; 16828 } 16829 16830 /* In this case, we know for sure that the symbol fragment is in 16831 the same section. If the relax_marker of the symbol fragment 16832 differs from the relax_marker of this fragment, we have not 16833 yet adjusted the symbol fragment fr_address. We want to add 16834 in STRETCH in order to get a better estimate of the address. 16835 This particularly matters because of the shift bits. */ 16836 if (stretch != 0 16837 && sym_frag->relax_marker != fragp->relax_marker) 16838 { 16839 fragS *f; 16840 16841 /* Adjust stretch for any alignment frag. Note that if have 16842 been expanding the earlier code, the symbol may be 16843 defined in what appears to be an earlier frag. FIXME: 16844 This doesn't handle the fr_subtype field, which specifies 16845 a maximum number of bytes to skip when doing an 16846 alignment. */ 16847 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 16848 { 16849 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 16850 { 16851 if (stretch < 0) 16852 stretch = - ((- stretch) 16853 & ~ ((1 << (int) f->fr_offset) - 1)); 16854 else 16855 stretch &= ~ ((1 << (int) f->fr_offset) - 1); 16856 if (stretch == 0) 16857 break; 16858 } 16859 } 16860 if (f != NULL) 16861 val += stretch; 16862 } 16863 16864 addr = fragp->fr_address + fragp->fr_fix; 16865 16866 /* The base address rules are complicated. The base address of 16867 a branch is the following instruction. The base address of a 16868 PC relative load or add is the instruction itself, but if it 16869 is in a delay slot (in which case it can not be extended) use 16870 the address of the instruction whose delay slot it is in. */ 16871 if (pcrel_op->include_isa_bit) 16872 { 16873 addr += 2; 16874 16875 /* If we are currently assuming that this frag should be 16876 extended, then, the current address is two bytes 16877 higher. */ 16878 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 16879 addr += 2; 16880 16881 /* Ignore the low bit in the target, since it will be set 16882 for a text label. */ 16883 val &= -2; 16884 } 16885 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 16886 addr -= 4; 16887 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 16888 addr -= 2; 16889 16890 val -= addr & -(1 << pcrel_op->align_log2); 16891 16892 /* If any of the shifted bits are set, we must use an extended 16893 opcode. If the address depends on the size of this 16894 instruction, this can lead to a loop, so we arrange to always 16895 use an extended opcode. We only check this when we are in 16896 the main relaxation loop, when SEC is NULL. */ 16897 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL) 16898 { 16899 fragp->fr_subtype = 16900 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 16901 return 1; 16902 } 16903 16904 /* If we are about to mark a frag as extended because the value 16905 is precisely the next value above maxtiny, then there is a 16906 chance of an infinite loop as in the following code: 16907 la $4,foo 16908 .skip 1020 16909 .align 2 16910 foo: 16911 In this case when the la is extended, foo is 0x3fc bytes 16912 away, so the la can be shrunk, but then foo is 0x400 away, so 16913 the la must be extended. To avoid this loop, we mark the 16914 frag as extended if it was small, and is about to become 16915 extended with the next value above maxtiny. */ 16916 maxtiny = mips_int_operand_max (operand); 16917 if (val == maxtiny + (1 << operand->shift) 16918 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) 16919 && sec == NULL) 16920 { 16921 fragp->fr_subtype = 16922 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 16923 return 1; 16924 } 16925 } 16926 else if (symsec != absolute_section && sec != NULL) 16927 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); 16928 16929 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); 16930 } 16931 16932 /* Compute the length of a branch sequence, and adjust the 16933 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 16934 worst-case length is computed, with UPDATE being used to indicate 16935 whether an unconditional (-1), branch-likely (+1) or regular (0) 16936 branch is to be computed. */ 16937 static int 16938 relaxed_branch_length (fragS *fragp, asection *sec, int update) 16939 { 16940 bfd_boolean toofar; 16941 int length; 16942 16943 if (fragp 16944 && S_IS_DEFINED (fragp->fr_symbol) 16945 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 16946 { 16947 addressT addr; 16948 offsetT val; 16949 16950 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 16951 16952 addr = fragp->fr_address + fragp->fr_fix + 4; 16953 16954 val -= addr; 16955 16956 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); 16957 } 16958 else if (fragp) 16959 /* If the symbol is not defined or it's in a different segment, 16960 assume the user knows what's going on and emit a short 16961 branch. */ 16962 toofar = FALSE; 16963 else 16964 toofar = TRUE; 16965 16966 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 16967 fragp->fr_subtype 16968 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), 16969 RELAX_BRANCH_UNCOND (fragp->fr_subtype), 16970 RELAX_BRANCH_LIKELY (fragp->fr_subtype), 16971 RELAX_BRANCH_LINK (fragp->fr_subtype), 16972 toofar); 16973 16974 length = 4; 16975 if (toofar) 16976 { 16977 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) 16978 length += 8; 16979 16980 if (mips_pic != NO_PIC) 16981 { 16982 /* Additional space for PIC loading of target address. */ 16983 length += 8; 16984 if (mips_opts.isa == ISA_MIPS1) 16985 /* Additional space for $at-stabilizing nop. */ 16986 length += 4; 16987 } 16988 16989 /* If branch is conditional. */ 16990 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) 16991 length += 8; 16992 } 16993 16994 return length; 16995 } 16996 16997 /* Compute the length of a branch sequence, and adjust the 16998 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the 16999 worst-case length is computed, with UPDATE being used to indicate 17000 whether an unconditional (-1), or regular (0) branch is to be 17001 computed. */ 17002 17003 static int 17004 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) 17005 { 17006 bfd_boolean toofar; 17007 int length; 17008 17009 if (fragp 17010 && S_IS_DEFINED (fragp->fr_symbol) 17011 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 17012 { 17013 addressT addr; 17014 offsetT val; 17015 17016 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17017 /* Ignore the low bit in the target, since it will be set 17018 for a text label. */ 17019 if ((val & 1) != 0) 17020 --val; 17021 17022 addr = fragp->fr_address + fragp->fr_fix + 4; 17023 17024 val -= addr; 17025 17026 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); 17027 } 17028 else if (fragp) 17029 /* If the symbol is not defined or it's in a different segment, 17030 assume the user knows what's going on and emit a short 17031 branch. */ 17032 toofar = FALSE; 17033 else 17034 toofar = TRUE; 17035 17036 if (fragp && update 17037 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 17038 fragp->fr_subtype = (toofar 17039 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) 17040 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); 17041 17042 length = 4; 17043 if (toofar) 17044 { 17045 bfd_boolean compact_known = fragp != NULL; 17046 bfd_boolean compact = FALSE; 17047 bfd_boolean uncond; 17048 17049 if (compact_known) 17050 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 17051 if (fragp) 17052 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); 17053 else 17054 uncond = update < 0; 17055 17056 /* If label is out of range, we turn branch <br>: 17057 17058 <br> label # 4 bytes 17059 0: 17060 17061 into: 17062 17063 j label # 4 bytes 17064 nop # 2 bytes if compact && !PIC 17065 0: 17066 */ 17067 if (mips_pic == NO_PIC && (!compact_known || compact)) 17068 length += 2; 17069 17070 /* If assembling PIC code, we further turn: 17071 17072 j label # 4 bytes 17073 17074 into: 17075 17076 lw/ld at, %got(label)(gp) # 4 bytes 17077 d/addiu at, %lo(label) # 4 bytes 17078 jr/c at # 2 bytes 17079 */ 17080 if (mips_pic != NO_PIC) 17081 length += 6; 17082 17083 /* If branch <br> is conditional, we prepend negated branch <brneg>: 17084 17085 <brneg> 0f # 4 bytes 17086 nop # 2 bytes if !compact 17087 */ 17088 if (!uncond) 17089 length += (compact_known && compact) ? 4 : 6; 17090 } 17091 17092 return length; 17093 } 17094 17095 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 17096 bit accordingly. */ 17097 17098 static int 17099 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) 17100 { 17101 bfd_boolean toofar; 17102 17103 if (fragp 17104 && S_IS_DEFINED (fragp->fr_symbol) 17105 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 17106 { 17107 addressT addr; 17108 offsetT val; 17109 int type; 17110 17111 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17112 /* Ignore the low bit in the target, since it will be set 17113 for a text label. */ 17114 if ((val & 1) != 0) 17115 --val; 17116 17117 /* Assume this is a 2-byte branch. */ 17118 addr = fragp->fr_address + fragp->fr_fix + 2; 17119 17120 /* We try to avoid the infinite loop by not adding 2 more bytes for 17121 long branches. */ 17122 17123 val -= addr; 17124 17125 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 17126 if (type == 'D') 17127 toofar = val < - (0x200 << 1) || val >= (0x200 << 1); 17128 else if (type == 'E') 17129 toofar = val < - (0x40 << 1) || val >= (0x40 << 1); 17130 else 17131 abort (); 17132 } 17133 else 17134 /* If the symbol is not defined or it's in a different segment, 17135 we emit a normal 32-bit branch. */ 17136 toofar = TRUE; 17137 17138 if (fragp && update 17139 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 17140 fragp->fr_subtype 17141 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) 17142 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); 17143 17144 if (toofar) 17145 return 4; 17146 17147 return 2; 17148 } 17149 17150 /* Estimate the size of a frag before relaxing. Unless this is the 17151 mips16, we are not really relaxing here, and the final size is 17152 encoded in the subtype information. For the mips16, we have to 17153 decide whether we are using an extended opcode or not. */ 17154 17155 int 17156 md_estimate_size_before_relax (fragS *fragp, asection *segtype) 17157 { 17158 int change; 17159 17160 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17161 { 17162 17163 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); 17164 17165 return fragp->fr_var; 17166 } 17167 17168 if (RELAX_MIPS16_P (fragp->fr_subtype)) 17169 /* We don't want to modify the EXTENDED bit here; it might get us 17170 into infinite loops. We change it only in mips_relax_frag(). */ 17171 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); 17172 17173 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17174 { 17175 int length = 4; 17176 17177 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 17178 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); 17179 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 17180 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); 17181 fragp->fr_var = length; 17182 17183 return length; 17184 } 17185 17186 if (mips_pic == NO_PIC) 17187 change = nopic_need_relax (fragp->fr_symbol, 0); 17188 else if (mips_pic == SVR4_PIC) 17189 change = pic_need_relax (fragp->fr_symbol, segtype); 17190 else if (mips_pic == VXWORKS_PIC) 17191 /* For vxworks, GOT16 relocations never have a corresponding LO16. */ 17192 change = 0; 17193 else 17194 abort (); 17195 17196 if (change) 17197 { 17198 fragp->fr_subtype |= RELAX_USE_SECOND; 17199 return -RELAX_FIRST (fragp->fr_subtype); 17200 } 17201 else 17202 return -RELAX_SECOND (fragp->fr_subtype); 17203 } 17204 17205 /* This is called to see whether a reloc against a defined symbol 17206 should be converted into a reloc against a section. */ 17207 17208 int 17209 mips_fix_adjustable (fixS *fixp) 17210 { 17211 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 17212 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 17213 return 0; 17214 17215 if (fixp->fx_addsy == NULL) 17216 return 1; 17217 17218 /* If symbol SYM is in a mergeable section, relocations of the form 17219 SYM + 0 can usually be made section-relative. The mergeable data 17220 is then identified by the section offset rather than by the symbol. 17221 17222 However, if we're generating REL LO16 relocations, the offset is split 17223 between the LO16 and parterning high part relocation. The linker will 17224 need to recalculate the complete offset in order to correctly identify 17225 the merge data. 17226 17227 The linker has traditionally not looked for the parterning high part 17228 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be 17229 placed anywhere. Rather than break backwards compatibility by changing 17230 this, it seems better not to force the issue, and instead keep the 17231 original symbol. This will work with either linker behavior. */ 17232 if ((lo16_reloc_p (fixp->fx_r_type) 17233 || reloc_needs_lo_p (fixp->fx_r_type)) 17234 && HAVE_IN_PLACE_ADDENDS 17235 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) 17236 return 0; 17237 17238 /* There is no place to store an in-place offset for JALR relocations. 17239 Likewise an in-range offset of limited PC-relative relocations may 17240 overflow the in-place relocatable field if recalculated against the 17241 start address of the symbol's containing section. 17242 17243 Also, PC relative relocations for MIPS R6 need to be symbol rather than 17244 section relative to allow linker relaxations to be performed later on. */ 17245 if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa)) 17246 && (limited_pcrel_reloc_p (fixp->fx_r_type) 17247 || jalr_reloc_p (fixp->fx_r_type))) 17248 return 0; 17249 17250 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve 17251 to a floating-point stub. The same is true for non-R_MIPS16_26 17252 relocations against MIPS16 functions; in this case, the stub becomes 17253 the function's canonical address. 17254 17255 Floating-point stubs are stored in unique .mips16.call.* or 17256 .mips16.fn.* sections. If a stub T for function F is in section S, 17257 the first relocation in section S must be against F; this is how the 17258 linker determines the target function. All relocations that might 17259 resolve to T must also be against F. We therefore have the following 17260 restrictions, which are given in an intentionally-redundant way: 17261 17262 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 17263 symbols. 17264 17265 2. We cannot reduce a stub's relocations against non-MIPS16 symbols 17266 if that stub might be used. 17267 17268 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 17269 symbols. 17270 17271 4. We cannot reduce a stub's relocations against MIPS16 symbols if 17272 that stub might be used. 17273 17274 There is a further restriction: 17275 17276 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or 17277 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on 17278 targets with in-place addends; the relocation field cannot 17279 encode the low bit. 17280 17281 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation 17282 against a MIPS16 symbol. We deal with (5) by by not reducing any 17283 such relocations on REL targets. 17284 17285 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 17286 relocation against some symbol R, no relocation against R may be 17287 reduced. (Note that this deals with (2) as well as (1) because 17288 relocations against global symbols will never be reduced on ELF 17289 targets.) This approach is a little simpler than trying to detect 17290 stub sections, and gives the "all or nothing" per-symbol consistency 17291 that we have for MIPS16 symbols. */ 17292 if (fixp->fx_subsy == NULL 17293 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) 17294 || *symbol_get_tc (fixp->fx_addsy) 17295 || (HAVE_IN_PLACE_ADDENDS 17296 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) 17297 && jmp_reloc_p (fixp->fx_r_type)))) 17298 return 0; 17299 17300 return 1; 17301 } 17302 17303 /* Translate internal representation of relocation info to BFD target 17304 format. */ 17305 17306 arelent ** 17307 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 17308 { 17309 static arelent *retval[4]; 17310 arelent *reloc; 17311 bfd_reloc_code_real_type code; 17312 17313 memset (retval, 0, sizeof(retval)); 17314 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); 17315 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 17316 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 17317 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 17318 17319 if (fixp->fx_pcrel) 17320 { 17321 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 17322 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 17323 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 17324 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 17325 || fixp->fx_r_type == BFD_RELOC_32_PCREL 17326 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 17327 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 17328 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 17329 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 17330 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 17331 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); 17332 17333 /* At this point, fx_addnumber is "symbol offset - pcrel address". 17334 Relocations want only the symbol offset. */ 17335 reloc->addend = fixp->fx_addnumber + reloc->address; 17336 } 17337 else 17338 reloc->addend = fixp->fx_addnumber; 17339 17340 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable 17341 entry to be used in the relocation's section offset. */ 17342 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 17343 { 17344 reloc->address = reloc->addend; 17345 reloc->addend = 0; 17346 } 17347 17348 code = fixp->fx_r_type; 17349 17350 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 17351 if (reloc->howto == NULL) 17352 { 17353 as_bad_where (fixp->fx_file, fixp->fx_line, 17354 _("cannot represent %s relocation in this object file" 17355 " format"), 17356 bfd_get_reloc_code_name (code)); 17357 retval[0] = NULL; 17358 } 17359 17360 return retval; 17361 } 17362 17363 /* Relax a machine dependent frag. This returns the amount by which 17364 the current size of the frag should change. */ 17365 17366 int 17367 mips_relax_frag (asection *sec, fragS *fragp, long stretch) 17368 { 17369 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17370 { 17371 offsetT old_var = fragp->fr_var; 17372 17373 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 17374 17375 return fragp->fr_var - old_var; 17376 } 17377 17378 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17379 { 17380 offsetT old_var = fragp->fr_var; 17381 offsetT new_var = 4; 17382 17383 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 17384 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); 17385 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 17386 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); 17387 fragp->fr_var = new_var; 17388 17389 return new_var - old_var; 17390 } 17391 17392 if (! RELAX_MIPS16_P (fragp->fr_subtype)) 17393 return 0; 17394 17395 if (mips16_extended_frag (fragp, NULL, stretch)) 17396 { 17397 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17398 return 0; 17399 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 17400 return 2; 17401 } 17402 else 17403 { 17404 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17405 return 0; 17406 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 17407 return -2; 17408 } 17409 17410 return 0; 17411 } 17412 17413 /* Convert a machine dependent frag. */ 17414 17415 void 17416 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) 17417 { 17418 if (RELAX_BRANCH_P (fragp->fr_subtype)) 17419 { 17420 char *buf; 17421 unsigned long insn; 17422 expressionS exp; 17423 fixS *fixp; 17424 17425 buf = fragp->fr_literal + fragp->fr_fix; 17426 insn = read_insn (buf); 17427 17428 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 17429 { 17430 /* We generate a fixup instead of applying it right now 17431 because, if there are linker relaxations, we're going to 17432 need the relocations. */ 17433 exp.X_op = O_symbol; 17434 exp.X_add_symbol = fragp->fr_symbol; 17435 exp.X_add_number = fragp->fr_offset; 17436 17437 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, 17438 BFD_RELOC_16_PCREL_S2); 17439 fixp->fx_file = fragp->fr_file; 17440 fixp->fx_line = fragp->fr_line; 17441 17442 buf = write_insn (buf, insn); 17443 } 17444 else 17445 { 17446 int i; 17447 17448 as_warn_where (fragp->fr_file, fragp->fr_line, 17449 _("relaxed out-of-range branch into a jump")); 17450 17451 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) 17452 goto uncond; 17453 17454 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17455 { 17456 /* Reverse the branch. */ 17457 switch ((insn >> 28) & 0xf) 17458 { 17459 case 4: 17460 if ((insn & 0xff000000) == 0x47000000 17461 || (insn & 0xff600000) == 0x45600000) 17462 { 17463 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition 17464 reversed by tweaking bit 23. */ 17465 insn ^= 0x00800000; 17466 } 17467 else 17468 { 17469 /* bc[0-3][tf]l? instructions can have the condition 17470 reversed by tweaking a single TF bit, and their 17471 opcodes all have 0x4???????. */ 17472 gas_assert ((insn & 0xf3e00000) == 0x41000000); 17473 insn ^= 0x00010000; 17474 } 17475 break; 17476 17477 case 0: 17478 /* bltz 0x04000000 bgez 0x04010000 17479 bltzal 0x04100000 bgezal 0x04110000 */ 17480 gas_assert ((insn & 0xfc0e0000) == 0x04000000); 17481 insn ^= 0x00010000; 17482 break; 17483 17484 case 1: 17485 /* beq 0x10000000 bne 0x14000000 17486 blez 0x18000000 bgtz 0x1c000000 */ 17487 insn ^= 0x04000000; 17488 break; 17489 17490 default: 17491 abort (); 17492 } 17493 } 17494 17495 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 17496 { 17497 /* Clear the and-link bit. */ 17498 gas_assert ((insn & 0xfc1c0000) == 0x04100000); 17499 17500 /* bltzal 0x04100000 bgezal 0x04110000 17501 bltzall 0x04120000 bgezall 0x04130000 */ 17502 insn &= ~0x00100000; 17503 } 17504 17505 /* Branch over the branch (if the branch was likely) or the 17506 full jump (not likely case). Compute the offset from the 17507 current instruction to branch to. */ 17508 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17509 i = 16; 17510 else 17511 { 17512 /* How many bytes in instructions we've already emitted? */ 17513 i = buf - fragp->fr_literal - fragp->fr_fix; 17514 /* How many bytes in instructions from here to the end? */ 17515 i = fragp->fr_var - i; 17516 } 17517 /* Convert to instruction count. */ 17518 i >>= 2; 17519 /* Branch counts from the next instruction. */ 17520 i--; 17521 insn |= i; 17522 /* Branch over the jump. */ 17523 buf = write_insn (buf, insn); 17524 17525 /* nop */ 17526 buf = write_insn (buf, 0); 17527 17528 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 17529 { 17530 /* beql $0, $0, 2f */ 17531 insn = 0x50000000; 17532 /* Compute the PC offset from the current instruction to 17533 the end of the variable frag. */ 17534 /* How many bytes in instructions we've already emitted? */ 17535 i = buf - fragp->fr_literal - fragp->fr_fix; 17536 /* How many bytes in instructions from here to the end? */ 17537 i = fragp->fr_var - i; 17538 /* Convert to instruction count. */ 17539 i >>= 2; 17540 /* Don't decrement i, because we want to branch over the 17541 delay slot. */ 17542 insn |= i; 17543 17544 buf = write_insn (buf, insn); 17545 buf = write_insn (buf, 0); 17546 } 17547 17548 uncond: 17549 if (mips_pic == NO_PIC) 17550 { 17551 /* j or jal. */ 17552 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) 17553 ? 0x0c000000 : 0x08000000); 17554 exp.X_op = O_symbol; 17555 exp.X_add_symbol = fragp->fr_symbol; 17556 exp.X_add_number = fragp->fr_offset; 17557 17558 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 17559 FALSE, BFD_RELOC_MIPS_JMP); 17560 fixp->fx_file = fragp->fr_file; 17561 fixp->fx_line = fragp->fr_line; 17562 17563 buf = write_insn (buf, insn); 17564 } 17565 else 17566 { 17567 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); 17568 17569 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ 17570 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; 17571 insn |= at << OP_SH_RT; 17572 exp.X_op = O_symbol; 17573 exp.X_add_symbol = fragp->fr_symbol; 17574 exp.X_add_number = fragp->fr_offset; 17575 17576 if (fragp->fr_offset) 17577 { 17578 exp.X_add_symbol = make_expr_symbol (&exp); 17579 exp.X_add_number = 0; 17580 } 17581 17582 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 17583 FALSE, BFD_RELOC_MIPS_GOT16); 17584 fixp->fx_file = fragp->fr_file; 17585 fixp->fx_line = fragp->fr_line; 17586 17587 buf = write_insn (buf, insn); 17588 17589 if (mips_opts.isa == ISA_MIPS1) 17590 /* nop */ 17591 buf = write_insn (buf, 0); 17592 17593 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ 17594 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; 17595 insn |= at << OP_SH_RS | at << OP_SH_RT; 17596 17597 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, 17598 FALSE, BFD_RELOC_LO16); 17599 fixp->fx_file = fragp->fr_file; 17600 fixp->fx_line = fragp->fr_line; 17601 17602 buf = write_insn (buf, insn); 17603 17604 /* j(al)r $at. */ 17605 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 17606 insn = 0x0000f809; 17607 else 17608 insn = 0x00000008; 17609 insn |= at << OP_SH_RS; 17610 17611 buf = write_insn (buf, insn); 17612 } 17613 } 17614 17615 fragp->fr_fix += fragp->fr_var; 17616 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 17617 return; 17618 } 17619 17620 /* Relax microMIPS branches. */ 17621 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 17622 { 17623 char *buf = fragp->fr_literal + fragp->fr_fix; 17624 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 17625 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); 17626 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 17627 bfd_boolean short_ds; 17628 unsigned long insn; 17629 expressionS exp; 17630 fixS *fixp; 17631 17632 exp.X_op = O_symbol; 17633 exp.X_add_symbol = fragp->fr_symbol; 17634 exp.X_add_number = fragp->fr_offset; 17635 17636 fragp->fr_fix += fragp->fr_var; 17637 17638 /* Handle 16-bit branches that fit or are forced to fit. */ 17639 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 17640 { 17641 /* We generate a fixup instead of applying it right now, 17642 because if there is linker relaxation, we're going to 17643 need the relocations. */ 17644 if (type == 'D') 17645 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, 17646 BFD_RELOC_MICROMIPS_10_PCREL_S1); 17647 else if (type == 'E') 17648 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, 17649 BFD_RELOC_MICROMIPS_7_PCREL_S1); 17650 else 17651 abort (); 17652 17653 fixp->fx_file = fragp->fr_file; 17654 fixp->fx_line = fragp->fr_line; 17655 17656 /* These relocations can have an addend that won't fit in 17657 2 octets. */ 17658 fixp->fx_no_overflow = 1; 17659 17660 return; 17661 } 17662 17663 /* Handle 32-bit branches that fit or are forced to fit. */ 17664 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 17665 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 17666 { 17667 /* We generate a fixup instead of applying it right now, 17668 because if there is linker relaxation, we're going to 17669 need the relocations. */ 17670 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, 17671 BFD_RELOC_MICROMIPS_16_PCREL_S1); 17672 fixp->fx_file = fragp->fr_file; 17673 fixp->fx_line = fragp->fr_line; 17674 17675 if (type == 0) 17676 return; 17677 } 17678 17679 /* Relax 16-bit branches to 32-bit branches. */ 17680 if (type != 0) 17681 { 17682 insn = read_compressed_insn (buf, 2); 17683 17684 if ((insn & 0xfc00) == 0xcc00) /* b16 */ 17685 insn = 0x94000000; /* beq */ 17686 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ 17687 { 17688 unsigned long regno; 17689 17690 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; 17691 regno = micromips_to_32_reg_d_map [regno]; 17692 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ 17693 insn |= regno << MICROMIPSOP_SH_RS; 17694 } 17695 else 17696 abort (); 17697 17698 /* Nothing else to do, just write it out. */ 17699 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 17700 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 17701 { 17702 buf = write_compressed_insn (buf, insn, 4); 17703 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 17704 return; 17705 } 17706 } 17707 else 17708 insn = read_compressed_insn (buf, 4); 17709 17710 /* Relax 32-bit branches to a sequence of instructions. */ 17711 as_warn_where (fragp->fr_file, fragp->fr_line, 17712 _("relaxed out-of-range branch into a jump")); 17713 17714 /* Set the short-delay-slot bit. */ 17715 short_ds = al && (insn & 0x02000000) != 0; 17716 17717 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) 17718 { 17719 symbolS *l; 17720 17721 /* Reverse the branch. */ 17722 if ((insn & 0xfc000000) == 0x94000000 /* beq */ 17723 || (insn & 0xfc000000) == 0xb4000000) /* bne */ 17724 insn ^= 0x20000000; 17725 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ 17726 || (insn & 0xffe00000) == 0x40400000 /* bgez */ 17727 || (insn & 0xffe00000) == 0x40800000 /* blez */ 17728 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ 17729 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ 17730 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ 17731 || (insn & 0xffe00000) == 0x40200000 /* bltzal */ 17732 || (insn & 0xffe00000) == 0x40600000 /* bgezal */ 17733 || (insn & 0xffe00000) == 0x42200000 /* bltzals */ 17734 || (insn & 0xffe00000) == 0x42600000) /* bgezals */ 17735 insn ^= 0x00400000; 17736 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ 17737 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ 17738 || (insn & 0xffe30000) == 0x42800000 /* bc2f */ 17739 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ 17740 insn ^= 0x00200000; 17741 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df 17742 BNZ.df */ 17743 || (insn & 0xff600000) == 0x81600000) /* BZ.V 17744 BNZ.V */ 17745 insn ^= 0x00800000; 17746 else 17747 abort (); 17748 17749 if (al) 17750 { 17751 /* Clear the and-link and short-delay-slot bits. */ 17752 gas_assert ((insn & 0xfda00000) == 0x40200000); 17753 17754 /* bltzal 0x40200000 bgezal 0x40600000 */ 17755 /* bltzals 0x42200000 bgezals 0x42600000 */ 17756 insn &= ~0x02200000; 17757 } 17758 17759 /* Make a label at the end for use with the branch. */ 17760 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); 17761 micromips_label_inc (); 17762 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); 17763 17764 /* Refer to it. */ 17765 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, 17766 BFD_RELOC_MICROMIPS_16_PCREL_S1); 17767 fixp->fx_file = fragp->fr_file; 17768 fixp->fx_line = fragp->fr_line; 17769 17770 /* Branch over the jump. */ 17771 buf = write_compressed_insn (buf, insn, 4); 17772 if (!compact) 17773 /* nop */ 17774 buf = write_compressed_insn (buf, 0x0c00, 2); 17775 } 17776 17777 if (mips_pic == NO_PIC) 17778 { 17779 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ 17780 17781 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ 17782 insn = al ? jal : 0xd4000000; 17783 17784 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 17785 BFD_RELOC_MICROMIPS_JMP); 17786 fixp->fx_file = fragp->fr_file; 17787 fixp->fx_line = fragp->fr_line; 17788 17789 buf = write_compressed_insn (buf, insn, 4); 17790 if (compact) 17791 /* nop */ 17792 buf = write_compressed_insn (buf, 0x0c00, 2); 17793 } 17794 else 17795 { 17796 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); 17797 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ 17798 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ 17799 17800 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ 17801 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; 17802 insn |= at << MICROMIPSOP_SH_RT; 17803 17804 if (exp.X_add_number) 17805 { 17806 exp.X_add_symbol = make_expr_symbol (&exp); 17807 exp.X_add_number = 0; 17808 } 17809 17810 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 17811 BFD_RELOC_MICROMIPS_GOT16); 17812 fixp->fx_file = fragp->fr_file; 17813 fixp->fx_line = fragp->fr_line; 17814 17815 buf = write_compressed_insn (buf, insn, 4); 17816 17817 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ 17818 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; 17819 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; 17820 17821 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, 17822 BFD_RELOC_MICROMIPS_LO16); 17823 fixp->fx_file = fragp->fr_file; 17824 fixp->fx_line = fragp->fr_line; 17825 17826 buf = write_compressed_insn (buf, insn, 4); 17827 17828 /* jr/jrc/jalr/jalrs $at */ 17829 insn = al ? jalr : jr; 17830 insn |= at << MICROMIPSOP_SH_MJ; 17831 17832 buf = write_compressed_insn (buf, insn, 2); 17833 } 17834 17835 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 17836 return; 17837 } 17838 17839 if (RELAX_MIPS16_P (fragp->fr_subtype)) 17840 { 17841 int type; 17842 const struct mips_int_operand *operand; 17843 offsetT val; 17844 char *buf; 17845 unsigned int user_length, length; 17846 unsigned long insn; 17847 bfd_boolean ext; 17848 17849 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 17850 operand = mips16_immed_operand (type, FALSE); 17851 17852 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); 17853 val = resolve_symbol_value (fragp->fr_symbol); 17854 if (operand->root.type == OP_PCREL) 17855 { 17856 const struct mips_pcrel_operand *pcrel_op; 17857 addressT addr; 17858 17859 pcrel_op = (const struct mips_pcrel_operand *) operand; 17860 addr = fragp->fr_address + fragp->fr_fix; 17861 17862 /* The rules for the base address of a PC relative reloc are 17863 complicated; see mips16_extended_frag. */ 17864 if (pcrel_op->include_isa_bit) 17865 { 17866 addr += 2; 17867 if (ext) 17868 addr += 2; 17869 /* Ignore the low bit in the target, since it will be 17870 set for a text label. */ 17871 val &= -2; 17872 } 17873 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 17874 addr -= 4; 17875 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 17876 addr -= 2; 17877 17878 addr &= -(1 << pcrel_op->align_log2); 17879 val -= addr; 17880 17881 /* Make sure the section winds up with the alignment we have 17882 assumed. */ 17883 if (operand->shift > 0) 17884 record_alignment (asec, operand->shift); 17885 } 17886 17887 if (ext 17888 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) 17889 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) 17890 as_warn_where (fragp->fr_file, fragp->fr_line, 17891 _("extended instruction in delay slot")); 17892 17893 buf = fragp->fr_literal + fragp->fr_fix; 17894 17895 insn = read_compressed_insn (buf, 2); 17896 if (ext) 17897 insn |= MIPS16_EXTEND; 17898 17899 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 17900 user_length = 4; 17901 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 17902 user_length = 2; 17903 else 17904 user_length = 0; 17905 17906 mips16_immed (fragp->fr_file, fragp->fr_line, type, 17907 BFD_RELOC_UNUSED, val, user_length, &insn); 17908 17909 length = (ext ? 4 : 2); 17910 gas_assert (mips16_opcode_length (insn) == length); 17911 write_compressed_insn (buf, insn, length); 17912 fragp->fr_fix += length; 17913 } 17914 else 17915 { 17916 relax_substateT subtype = fragp->fr_subtype; 17917 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; 17918 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; 17919 int first, second; 17920 fixS *fixp; 17921 17922 first = RELAX_FIRST (subtype); 17923 second = RELAX_SECOND (subtype); 17924 fixp = (fixS *) fragp->fr_opcode; 17925 17926 /* If the delay slot chosen does not match the size of the instruction, 17927 then emit a warning. */ 17928 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) 17929 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) 17930 { 17931 relax_substateT s; 17932 const char *msg; 17933 17934 s = subtype & (RELAX_DELAY_SLOT_16BIT 17935 | RELAX_DELAY_SLOT_SIZE_FIRST 17936 | RELAX_DELAY_SLOT_SIZE_SECOND); 17937 msg = macro_warning (s); 17938 if (msg != NULL) 17939 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 17940 subtype &= ~s; 17941 } 17942 17943 /* Possibly emit a warning if we've chosen the longer option. */ 17944 if (use_second == second_longer) 17945 { 17946 relax_substateT s; 17947 const char *msg; 17948 17949 s = (subtype 17950 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); 17951 msg = macro_warning (s); 17952 if (msg != NULL) 17953 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 17954 subtype &= ~s; 17955 } 17956 17957 /* Go through all the fixups for the first sequence. Disable them 17958 (by marking them as done) if we're going to use the second 17959 sequence instead. */ 17960 while (fixp 17961 && fixp->fx_frag == fragp 17962 && fixp->fx_where < fragp->fr_fix - second) 17963 { 17964 if (subtype & RELAX_USE_SECOND) 17965 fixp->fx_done = 1; 17966 fixp = fixp->fx_next; 17967 } 17968 17969 /* Go through the fixups for the second sequence. Disable them if 17970 we're going to use the first sequence, otherwise adjust their 17971 addresses to account for the relaxation. */ 17972 while (fixp && fixp->fx_frag == fragp) 17973 { 17974 if (subtype & RELAX_USE_SECOND) 17975 fixp->fx_where -= first; 17976 else 17977 fixp->fx_done = 1; 17978 fixp = fixp->fx_next; 17979 } 17980 17981 /* Now modify the frag contents. */ 17982 if (subtype & RELAX_USE_SECOND) 17983 { 17984 char *start; 17985 17986 start = fragp->fr_literal + fragp->fr_fix - first - second; 17987 memmove (start, start + first, second); 17988 fragp->fr_fix -= first; 17989 } 17990 else 17991 fragp->fr_fix -= second; 17992 } 17993 } 17994 17995 /* This function is called after the relocs have been generated. 17996 We've been storing mips16 text labels as odd. Here we convert them 17997 back to even for the convenience of the debugger. */ 17998 17999 void 18000 mips_frob_file_after_relocs (void) 18001 { 18002 asymbol **syms; 18003 unsigned int count, i; 18004 18005 syms = bfd_get_outsymbols (stdoutput); 18006 count = bfd_get_symcount (stdoutput); 18007 for (i = 0; i < count; i++, syms++) 18008 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) 18009 && ((*syms)->value & 1) != 0) 18010 { 18011 (*syms)->value &= ~1; 18012 /* If the symbol has an odd size, it was probably computed 18013 incorrectly, so adjust that as well. */ 18014 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) 18015 ++elf_symbol (*syms)->internal_elf_sym.st_size; 18016 } 18017 } 18018 18019 /* This function is called whenever a label is defined, including fake 18020 labels instantiated off the dot special symbol. It is used when 18021 handling branch delays; if a branch has a label, we assume we cannot 18022 move it. This also bumps the value of the symbol by 1 in compressed 18023 code. */ 18024 18025 static void 18026 mips_record_label (symbolS *sym) 18027 { 18028 segment_info_type *si = seg_info (now_seg); 18029 struct insn_label_list *l; 18030 18031 if (free_insn_labels == NULL) 18032 l = (struct insn_label_list *) xmalloc (sizeof *l); 18033 else 18034 { 18035 l = free_insn_labels; 18036 free_insn_labels = l->next; 18037 } 18038 18039 l->label = sym; 18040 l->next = si->label_list; 18041 si->label_list = l; 18042 } 18043 18044 /* This function is called as tc_frob_label() whenever a label is defined 18045 and adds a DWARF-2 record we only want for true labels. */ 18046 18047 void 18048 mips_define_label (symbolS *sym) 18049 { 18050 mips_record_label (sym); 18051 dwarf2_emit_label (sym); 18052 } 18053 18054 /* This function is called by tc_new_dot_label whenever a new dot symbol 18055 is defined. */ 18056 18057 void 18058 mips_add_dot_label (symbolS *sym) 18059 { 18060 mips_record_label (sym); 18061 if (mips_assembling_insn && HAVE_CODE_COMPRESSION) 18062 mips_compressed_mark_label (sym); 18063 } 18064 18065 /* Converting ASE flags from internal to .MIPS.abiflags values. */ 18067 static unsigned int 18068 mips_convert_ase_flags (int ase) 18069 { 18070 unsigned int ext_ases = 0; 18071 18072 if (ase & ASE_DSP) 18073 ext_ases |= AFL_ASE_DSP; 18074 if (ase & ASE_DSPR2) 18075 ext_ases |= AFL_ASE_DSPR2; 18076 if (ase & ASE_DSPR6) 18077 ext_ases |= AFL_ASE_DSPR6; 18078 if (ase & ASE_EVA) 18079 ext_ases |= AFL_ASE_EVA; 18080 if (ase & ASE_MCU) 18081 ext_ases |= AFL_ASE_MCU; 18082 if (ase & ASE_MDMX) 18083 ext_ases |= AFL_ASE_MDMX; 18084 if (ase & ASE_MIPS3D) 18085 ext_ases |= AFL_ASE_MIPS3D; 18086 if (ase & ASE_MT) 18087 ext_ases |= AFL_ASE_MT; 18088 if (ase & ASE_SMARTMIPS) 18089 ext_ases |= AFL_ASE_SMARTMIPS; 18090 if (ase & ASE_VIRT) 18091 ext_ases |= AFL_ASE_VIRT; 18092 if (ase & ASE_MSA) 18093 ext_ases |= AFL_ASE_MSA; 18094 if (ase & ASE_XPA) 18095 ext_ases |= AFL_ASE_XPA; 18096 18097 return ext_ases; 18098 } 18099 /* Some special processing for a MIPS ELF file. */ 18100 18101 void 18102 mips_elf_final_processing (void) 18103 { 18104 int fpabi; 18105 Elf_Internal_ABIFlags_v0 flags; 18106 18107 flags.version = 0; 18108 flags.isa_rev = 0; 18109 switch (file_mips_opts.isa) 18110 { 18111 case INSN_ISA1: 18112 flags.isa_level = 1; 18113 break; 18114 case INSN_ISA2: 18115 flags.isa_level = 2; 18116 break; 18117 case INSN_ISA3: 18118 flags.isa_level = 3; 18119 break; 18120 case INSN_ISA4: 18121 flags.isa_level = 4; 18122 break; 18123 case INSN_ISA5: 18124 flags.isa_level = 5; 18125 break; 18126 case INSN_ISA32: 18127 flags.isa_level = 32; 18128 flags.isa_rev = 1; 18129 break; 18130 case INSN_ISA32R2: 18131 flags.isa_level = 32; 18132 flags.isa_rev = 2; 18133 break; 18134 case INSN_ISA32R3: 18135 flags.isa_level = 32; 18136 flags.isa_rev = 3; 18137 break; 18138 case INSN_ISA32R5: 18139 flags.isa_level = 32; 18140 flags.isa_rev = 5; 18141 break; 18142 case INSN_ISA32R6: 18143 flags.isa_level = 32; 18144 flags.isa_rev = 6; 18145 break; 18146 case INSN_ISA64: 18147 flags.isa_level = 64; 18148 flags.isa_rev = 1; 18149 break; 18150 case INSN_ISA64R2: 18151 flags.isa_level = 64; 18152 flags.isa_rev = 2; 18153 break; 18154 case INSN_ISA64R3: 18155 flags.isa_level = 64; 18156 flags.isa_rev = 3; 18157 break; 18158 case INSN_ISA64R5: 18159 flags.isa_level = 64; 18160 flags.isa_rev = 5; 18161 break; 18162 case INSN_ISA64R6: 18163 flags.isa_level = 64; 18164 flags.isa_rev = 6; 18165 break; 18166 } 18167 18168 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; 18169 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE 18170 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 18171 : (file_mips_opts.fp == 64) ? AFL_REG_64 18172 : AFL_REG_32; 18173 flags.cpr2_size = AFL_REG_NONE; 18174 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 18175 Tag_GNU_MIPS_ABI_FP); 18176 flags.isa_ext = bfd_mips_isa_ext (stdoutput); 18177 flags.ases = mips_convert_ase_flags (file_mips_opts.ase); 18178 if (file_ase_mips16) 18179 flags.ases |= AFL_ASE_MIPS16; 18180 if (file_ase_micromips) 18181 flags.ases |= AFL_ASE_MICROMIPS; 18182 flags.flags1 = 0; 18183 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) 18184 || file_mips_opts.fp == 64) 18185 && file_mips_opts.oddspreg) 18186 flags.flags1 |= AFL_FLAGS1_ODDSPREG; 18187 flags.flags2 = 0; 18188 18189 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, 18190 ((Elf_External_ABIFlags_v0 *) 18191 mips_flags_frag)); 18192 18193 /* Write out the register information. */ 18194 if (mips_abi != N64_ABI) 18195 { 18196 Elf32_RegInfo s; 18197 18198 s.ri_gprmask = mips_gprmask; 18199 s.ri_cprmask[0] = mips_cprmask[0]; 18200 s.ri_cprmask[1] = mips_cprmask[1]; 18201 s.ri_cprmask[2] = mips_cprmask[2]; 18202 s.ri_cprmask[3] = mips_cprmask[3]; 18203 /* The gp_value field is set by the MIPS ELF backend. */ 18204 18205 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, 18206 ((Elf32_External_RegInfo *) 18207 mips_regmask_frag)); 18208 } 18209 else 18210 { 18211 Elf64_Internal_RegInfo s; 18212 18213 s.ri_gprmask = mips_gprmask; 18214 s.ri_pad = 0; 18215 s.ri_cprmask[0] = mips_cprmask[0]; 18216 s.ri_cprmask[1] = mips_cprmask[1]; 18217 s.ri_cprmask[2] = mips_cprmask[2]; 18218 s.ri_cprmask[3] = mips_cprmask[3]; 18219 /* The gp_value field is set by the MIPS ELF backend. */ 18220 18221 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, 18222 ((Elf64_External_RegInfo *) 18223 mips_regmask_frag)); 18224 } 18225 18226 /* Set the MIPS ELF flag bits. FIXME: There should probably be some 18227 sort of BFD interface for this. */ 18228 if (mips_any_noreorder) 18229 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; 18230 if (mips_pic != NO_PIC) 18231 { 18232 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; 18233 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 18234 } 18235 if (mips_abicalls) 18236 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 18237 18238 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags 18239 defined at present; this might need to change in future. */ 18240 if (file_ase_mips16) 18241 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; 18242 if (file_ase_micromips) 18243 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; 18244 if (file_mips_opts.ase & ASE_MDMX) 18245 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; 18246 18247 /* Set the MIPS ELF ABI flags. */ 18248 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) 18249 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; 18250 else if (mips_abi == O64_ABI) 18251 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; 18252 else if (mips_abi == EABI_ABI) 18253 { 18254 if (file_mips_opts.gp == 64) 18255 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; 18256 else 18257 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; 18258 } 18259 else if (mips_abi == N32_ABI) 18260 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; 18261 18262 /* Nothing to do for N64_ABI. */ 18263 18264 if (mips_32bitmode) 18265 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; 18266 18267 if (mips_nan2008 == 1) 18268 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; 18269 18270 /* 32 bit code with 64 bit FP registers. */ 18271 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 18272 Tag_GNU_MIPS_ABI_FP); 18273 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) 18274 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; 18275 } 18276 18277 typedef struct proc { 18279 symbolS *func_sym; 18280 symbolS *func_end_sym; 18281 unsigned long reg_mask; 18282 unsigned long reg_offset; 18283 unsigned long fpreg_mask; 18284 unsigned long fpreg_offset; 18285 unsigned long frame_offset; 18286 unsigned long frame_reg; 18287 unsigned long pc_reg; 18288 } procS; 18289 18290 static procS cur_proc; 18291 static procS *cur_proc_ptr; 18292 static int numprocs; 18293 18294 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop 18295 as "2", and a normal nop as "0". */ 18296 18297 #define NOP_OPCODE_MIPS 0 18298 #define NOP_OPCODE_MIPS16 1 18299 #define NOP_OPCODE_MICROMIPS 2 18300 18301 char 18302 mips_nop_opcode (void) 18303 { 18304 if (seg_info (now_seg)->tc_segment_info_data.micromips) 18305 return NOP_OPCODE_MICROMIPS; 18306 else if (seg_info (now_seg)->tc_segment_info_data.mips16) 18307 return NOP_OPCODE_MIPS16; 18308 else 18309 return NOP_OPCODE_MIPS; 18310 } 18311 18312 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use 18313 32-bit microMIPS NOPs here (if applicable). */ 18314 18315 void 18316 mips_handle_align (fragS *fragp) 18317 { 18318 char nop_opcode; 18319 char *p; 18320 int bytes, size, excess; 18321 valueT opcode; 18322 18323 if (fragp->fr_type != rs_align_code) 18324 return; 18325 18326 p = fragp->fr_literal + fragp->fr_fix; 18327 nop_opcode = *p; 18328 switch (nop_opcode) 18329 { 18330 case NOP_OPCODE_MICROMIPS: 18331 opcode = micromips_nop32_insn.insn_opcode; 18332 size = 4; 18333 break; 18334 case NOP_OPCODE_MIPS16: 18335 opcode = mips16_nop_insn.insn_opcode; 18336 size = 2; 18337 break; 18338 case NOP_OPCODE_MIPS: 18339 default: 18340 opcode = nop_insn.insn_opcode; 18341 size = 4; 18342 break; 18343 } 18344 18345 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 18346 excess = bytes % size; 18347 18348 /* Handle the leading part if we're not inserting a whole number of 18349 instructions, and make it the end of the fixed part of the frag. 18350 Try to fit in a short microMIPS NOP if applicable and possible, 18351 and use zeroes otherwise. */ 18352 gas_assert (excess < 4); 18353 fragp->fr_fix += excess; 18354 switch (excess) 18355 { 18356 case 3: 18357 *p++ = '\0'; 18358 /* Fall through. */ 18359 case 2: 18360 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) 18361 { 18362 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); 18363 break; 18364 } 18365 *p++ = '\0'; 18366 /* Fall through. */ 18367 case 1: 18368 *p++ = '\0'; 18369 /* Fall through. */ 18370 case 0: 18371 break; 18372 } 18373 18374 md_number_to_chars (p, opcode, size); 18375 fragp->fr_var = size; 18376 } 18377 18378 static long 18379 get_number (void) 18380 { 18381 int negative = 0; 18382 long val = 0; 18383 18384 if (*input_line_pointer == '-') 18385 { 18386 ++input_line_pointer; 18387 negative = 1; 18388 } 18389 if (!ISDIGIT (*input_line_pointer)) 18390 as_bad (_("expected simple number")); 18391 if (input_line_pointer[0] == '0') 18392 { 18393 if (input_line_pointer[1] == 'x') 18394 { 18395 input_line_pointer += 2; 18396 while (ISXDIGIT (*input_line_pointer)) 18397 { 18398 val <<= 4; 18399 val |= hex_value (*input_line_pointer++); 18400 } 18401 return negative ? -val : val; 18402 } 18403 else 18404 { 18405 ++input_line_pointer; 18406 while (ISDIGIT (*input_line_pointer)) 18407 { 18408 val <<= 3; 18409 val |= *input_line_pointer++ - '0'; 18410 } 18411 return negative ? -val : val; 18412 } 18413 } 18414 if (!ISDIGIT (*input_line_pointer)) 18415 { 18416 printf (_(" *input_line_pointer == '%c' 0x%02x\n"), 18417 *input_line_pointer, *input_line_pointer); 18418 as_warn (_("invalid number")); 18419 return -1; 18420 } 18421 while (ISDIGIT (*input_line_pointer)) 18422 { 18423 val *= 10; 18424 val += *input_line_pointer++ - '0'; 18425 } 18426 return negative ? -val : val; 18427 } 18428 18429 /* The .file directive; just like the usual .file directive, but there 18430 is an initial number which is the ECOFF file index. In the non-ECOFF 18431 case .file implies DWARF-2. */ 18432 18433 static void 18434 s_mips_file (int x ATTRIBUTE_UNUSED) 18435 { 18436 static int first_file_directive = 0; 18437 18438 if (ECOFF_DEBUGGING) 18439 { 18440 get_number (); 18441 s_app_file (0); 18442 } 18443 else 18444 { 18445 char *filename; 18446 18447 filename = dwarf2_directive_file (0); 18448 18449 /* Versions of GCC up to 3.1 start files with a ".file" 18450 directive even for stabs output. Make sure that this 18451 ".file" is handled. Note that you need a version of GCC 18452 after 3.1 in order to support DWARF-2 on MIPS. */ 18453 if (filename != NULL && ! first_file_directive) 18454 { 18455 (void) new_logical_line (filename, -1); 18456 s_app_file_string (filename, 0); 18457 } 18458 first_file_directive = 1; 18459 } 18460 } 18461 18462 /* The .loc directive, implying DWARF-2. */ 18463 18464 static void 18465 s_mips_loc (int x ATTRIBUTE_UNUSED) 18466 { 18467 if (!ECOFF_DEBUGGING) 18468 dwarf2_directive_loc (0); 18469 } 18470 18471 /* The .end directive. */ 18472 18473 static void 18474 s_mips_end (int x ATTRIBUTE_UNUSED) 18475 { 18476 symbolS *p; 18477 18478 /* Following functions need their own .frame and .cprestore directives. */ 18479 mips_frame_reg_valid = 0; 18480 mips_cprestore_valid = 0; 18481 18482 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 18483 { 18484 p = get_symbol (); 18485 demand_empty_rest_of_line (); 18486 } 18487 else 18488 p = NULL; 18489 18490 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 18491 as_warn (_(".end not in text section")); 18492 18493 if (!cur_proc_ptr) 18494 { 18495 as_warn (_(".end directive without a preceding .ent directive")); 18496 demand_empty_rest_of_line (); 18497 return; 18498 } 18499 18500 if (p != NULL) 18501 { 18502 gas_assert (S_GET_NAME (p)); 18503 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) 18504 as_warn (_(".end symbol does not match .ent symbol")); 18505 18506 if (debug_type == DEBUG_STABS) 18507 stabs_generate_asm_endfunc (S_GET_NAME (p), 18508 S_GET_NAME (p)); 18509 } 18510 else 18511 as_warn (_(".end directive missing or unknown symbol")); 18512 18513 /* Create an expression to calculate the size of the function. */ 18514 if (p && cur_proc_ptr) 18515 { 18516 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); 18517 expressionS *exp = xmalloc (sizeof (expressionS)); 18518 18519 obj->size = exp; 18520 exp->X_op = O_subtract; 18521 exp->X_add_symbol = symbol_temp_new_now (); 18522 exp->X_op_symbol = p; 18523 exp->X_add_number = 0; 18524 18525 cur_proc_ptr->func_end_sym = exp->X_add_symbol; 18526 } 18527 18528 /* Generate a .pdr section. */ 18529 if (!ECOFF_DEBUGGING && mips_flag_pdr) 18530 { 18531 segT saved_seg = now_seg; 18532 subsegT saved_subseg = now_subseg; 18533 expressionS exp; 18534 char *fragp; 18535 18536 #ifdef md_flush_pending_output 18537 md_flush_pending_output (); 18538 #endif 18539 18540 gas_assert (pdr_seg); 18541 subseg_set (pdr_seg, 0); 18542 18543 /* Write the symbol. */ 18544 exp.X_op = O_symbol; 18545 exp.X_add_symbol = p; 18546 exp.X_add_number = 0; 18547 emit_expr (&exp, 4); 18548 18549 fragp = frag_more (7 * 4); 18550 18551 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); 18552 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); 18553 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); 18554 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); 18555 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); 18556 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); 18557 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); 18558 18559 subseg_set (saved_seg, saved_subseg); 18560 } 18561 18562 cur_proc_ptr = NULL; 18563 } 18564 18565 /* The .aent and .ent directives. */ 18566 18567 static void 18568 s_mips_ent (int aent) 18569 { 18570 symbolS *symbolP; 18571 18572 symbolP = get_symbol (); 18573 if (*input_line_pointer == ',') 18574 ++input_line_pointer; 18575 SKIP_WHITESPACE (); 18576 if (ISDIGIT (*input_line_pointer) 18577 || *input_line_pointer == '-') 18578 get_number (); 18579 18580 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 18581 as_warn (_(".ent or .aent not in text section")); 18582 18583 if (!aent && cur_proc_ptr) 18584 as_warn (_("missing .end")); 18585 18586 if (!aent) 18587 { 18588 /* This function needs its own .frame and .cprestore directives. */ 18589 mips_frame_reg_valid = 0; 18590 mips_cprestore_valid = 0; 18591 18592 cur_proc_ptr = &cur_proc; 18593 memset (cur_proc_ptr, '\0', sizeof (procS)); 18594 18595 cur_proc_ptr->func_sym = symbolP; 18596 18597 ++numprocs; 18598 18599 if (debug_type == DEBUG_STABS) 18600 stabs_generate_asm_func (S_GET_NAME (symbolP), 18601 S_GET_NAME (symbolP)); 18602 } 18603 18604 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 18605 18606 demand_empty_rest_of_line (); 18607 } 18608 18609 /* The .frame directive. If the mdebug section is present (IRIX 5 native) 18610 then ecoff.c (ecoff_directive_frame) is used. For embedded targets, 18611 s_mips_frame is used so that we can set the PDR information correctly. 18612 We can't use the ecoff routines because they make reference to the ecoff 18613 symbol table (in the mdebug section). */ 18614 18615 static void 18616 s_mips_frame (int ignore ATTRIBUTE_UNUSED) 18617 { 18618 if (ECOFF_DEBUGGING) 18619 s_ignore (ignore); 18620 else 18621 { 18622 long val; 18623 18624 if (cur_proc_ptr == (procS *) NULL) 18625 { 18626 as_warn (_(".frame outside of .ent")); 18627 demand_empty_rest_of_line (); 18628 return; 18629 } 18630 18631 cur_proc_ptr->frame_reg = tc_get_register (1); 18632 18633 SKIP_WHITESPACE (); 18634 if (*input_line_pointer++ != ',' 18635 || get_absolute_expression_and_terminator (&val) != ',') 18636 { 18637 as_warn (_("bad .frame directive")); 18638 --input_line_pointer; 18639 demand_empty_rest_of_line (); 18640 return; 18641 } 18642 18643 cur_proc_ptr->frame_offset = val; 18644 cur_proc_ptr->pc_reg = tc_get_register (0); 18645 18646 demand_empty_rest_of_line (); 18647 } 18648 } 18649 18650 /* The .fmask and .mask directives. If the mdebug section is present 18651 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For 18652 embedded targets, s_mips_mask is used so that we can set the PDR 18653 information correctly. We can't use the ecoff routines because they 18654 make reference to the ecoff symbol table (in the mdebug section). */ 18655 18656 static void 18657 s_mips_mask (int reg_type) 18658 { 18659 if (ECOFF_DEBUGGING) 18660 s_ignore (reg_type); 18661 else 18662 { 18663 long mask, off; 18664 18665 if (cur_proc_ptr == (procS *) NULL) 18666 { 18667 as_warn (_(".mask/.fmask outside of .ent")); 18668 demand_empty_rest_of_line (); 18669 return; 18670 } 18671 18672 if (get_absolute_expression_and_terminator (&mask) != ',') 18673 { 18674 as_warn (_("bad .mask/.fmask directive")); 18675 --input_line_pointer; 18676 demand_empty_rest_of_line (); 18677 return; 18678 } 18679 18680 off = get_absolute_expression (); 18681 18682 if (reg_type == 'F') 18683 { 18684 cur_proc_ptr->fpreg_mask = mask; 18685 cur_proc_ptr->fpreg_offset = off; 18686 } 18687 else 18688 { 18689 cur_proc_ptr->reg_mask = mask; 18690 cur_proc_ptr->reg_offset = off; 18691 } 18692 18693 demand_empty_rest_of_line (); 18694 } 18695 } 18696 18697 /* A table describing all the processors gas knows about. Names are 18698 matched in the order listed. 18699 18700 To ease comparison, please keep this table in the same order as 18701 gcc's mips_cpu_info_table[]. */ 18702 static const struct mips_cpu_info mips_cpu_info_table[] = 18703 { 18704 /* Entries for generic ISAs */ 18705 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, 18706 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, 18707 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, 18708 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, 18709 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, 18710 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, 18711 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18712 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, 18713 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, 18714 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, 18715 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, 18716 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, 18717 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, 18718 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, 18719 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, 18720 18721 /* MIPS I */ 18722 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, 18723 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, 18724 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, 18725 18726 /* MIPS II */ 18727 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, 18728 18729 /* MIPS III */ 18730 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, 18731 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, 18732 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, 18733 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, 18734 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, 18735 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, 18736 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, 18737 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, 18738 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, 18739 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, 18740 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, 18741 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, 18742 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, 18743 /* ST Microelectronics Loongson 2E and 2F cores */ 18744 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, 18745 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, 18746 18747 /* MIPS IV */ 18748 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, 18749 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, 18750 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, 18751 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, 18752 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, 18753 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, 18754 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, 18755 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, 18756 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, 18757 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, 18758 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, 18759 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, 18760 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, 18761 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, 18762 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, 18763 18764 /* MIPS 32 */ 18765 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 18766 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 18767 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 18768 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, 18769 18770 /* MIPS 32 Release 2 */ 18771 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18772 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18773 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18774 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, 18775 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18776 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18777 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 18778 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 18779 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 18780 ISA_MIPS32R2, CPU_MIPS32R2 }, 18781 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 18782 ISA_MIPS32R2, CPU_MIPS32R2 }, 18783 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18784 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18785 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18786 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18787 /* Deprecated forms of the above. */ 18788 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18789 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 18790 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ 18791 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18792 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18793 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18794 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18795 /* Deprecated forms of the above. */ 18796 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18797 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 18798 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ 18799 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18800 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18801 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18802 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18803 /* Deprecated forms of the above. */ 18804 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18805 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18806 /* 34Kn is a 34kc without DSP. */ 18807 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18808 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ 18809 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18810 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18811 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18812 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18813 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18814 /* Deprecated forms of the above. */ 18815 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18816 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 18817 /* 1004K cores are multiprocessor versions of the 34K. */ 18818 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18819 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18820 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18821 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 18822 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ 18823 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, 18824 18825 /* MIPS 64 */ 18826 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 18827 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 18828 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 18829 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 18830 18831 /* Broadcom SB-1 CPU core */ 18832 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 18833 /* Broadcom SB-1A CPU core */ 18834 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 18835 18836 { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, 18837 18838 /* MIPS 64 Release 2 */ 18839 18840 /* Cavium Networks Octeon CPU core */ 18841 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, 18842 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, 18843 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, 18844 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, 18845 18846 /* RMI Xlr */ 18847 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, 18848 18849 /* Broadcom XLP. 18850 XLP is mostly like XLR, with the prominent exception that it is 18851 MIPS64R2 rather than MIPS64. */ 18852 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, 18853 18854 /* i6400. */ 18855 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 18856 18857 /* End marker */ 18858 { NULL, 0, 0, 0, 0 } 18859 }; 18860 18861 18862 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 18863 with a final "000" replaced by "k". Ignore case. 18864 18865 Note: this function is shared between GCC and GAS. */ 18866 18867 static bfd_boolean 18868 mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 18869 { 18870 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 18871 given++, canonical++; 18872 18873 return ((*given == 0 && *canonical == 0) 18874 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 18875 } 18876 18877 18878 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 18879 CPU name. We've traditionally allowed a lot of variation here. 18880 18881 Note: this function is shared between GCC and GAS. */ 18882 18883 static bfd_boolean 18884 mips_matching_cpu_name_p (const char *canonical, const char *given) 18885 { 18886 /* First see if the name matches exactly, or with a final "000" 18887 turned into "k". */ 18888 if (mips_strict_matching_cpu_name_p (canonical, given)) 18889 return TRUE; 18890 18891 /* If not, try comparing based on numerical designation alone. 18892 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 18893 if (TOLOWER (*given) == 'r') 18894 given++; 18895 if (!ISDIGIT (*given)) 18896 return FALSE; 18897 18898 /* Skip over some well-known prefixes in the canonical name, 18899 hoping to find a number there too. */ 18900 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 18901 canonical += 2; 18902 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 18903 canonical += 2; 18904 else if (TOLOWER (canonical[0]) == 'r') 18905 canonical += 1; 18906 18907 return mips_strict_matching_cpu_name_p (canonical, given); 18908 } 18909 18910 18911 /* Parse an option that takes the name of a processor as its argument. 18912 OPTION is the name of the option and CPU_STRING is the argument. 18913 Return the corresponding processor enumeration if the CPU_STRING is 18914 recognized, otherwise report an error and return null. 18915 18916 A similar function exists in GCC. */ 18917 18918 static const struct mips_cpu_info * 18919 mips_parse_cpu (const char *option, const char *cpu_string) 18920 { 18921 const struct mips_cpu_info *p; 18922 18923 /* 'from-abi' selects the most compatible architecture for the given 18924 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 18925 EABIs, we have to decide whether we're using the 32-bit or 64-bit 18926 version. Look first at the -mgp options, if given, otherwise base 18927 the choice on MIPS_DEFAULT_64BIT. 18928 18929 Treat NO_ABI like the EABIs. One reason to do this is that the 18930 plain 'mips' and 'mips64' configs have 'from-abi' as their default 18931 architecture. This code picks MIPS I for 'mips' and MIPS III for 18932 'mips64', just as we did in the days before 'from-abi'. */ 18933 if (strcasecmp (cpu_string, "from-abi") == 0) 18934 { 18935 if (ABI_NEEDS_32BIT_REGS (mips_abi)) 18936 return mips_cpu_info_from_isa (ISA_MIPS1); 18937 18938 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 18939 return mips_cpu_info_from_isa (ISA_MIPS3); 18940 18941 if (file_mips_opts.gp >= 0) 18942 return mips_cpu_info_from_isa (file_mips_opts.gp == 32 18943 ? ISA_MIPS1 : ISA_MIPS3); 18944 18945 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT 18946 ? ISA_MIPS3 18947 : ISA_MIPS1); 18948 } 18949 18950 /* 'default' has traditionally been a no-op. Probably not very useful. */ 18951 if (strcasecmp (cpu_string, "default") == 0) 18952 return 0; 18953 18954 for (p = mips_cpu_info_table; p->name != 0; p++) 18955 if (mips_matching_cpu_name_p (p->name, cpu_string)) 18956 return p; 18957 18958 as_bad (_("bad value (%s) for %s"), cpu_string, option); 18959 return 0; 18960 } 18961 18962 /* Return the canonical processor information for ISA (a member of the 18963 ISA_MIPS* enumeration). */ 18964 18965 static const struct mips_cpu_info * 18966 mips_cpu_info_from_isa (int isa) 18967 { 18968 int i; 18969 18970 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 18971 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) 18972 && isa == mips_cpu_info_table[i].isa) 18973 return (&mips_cpu_info_table[i]); 18974 18975 return NULL; 18976 } 18977 18978 static const struct mips_cpu_info * 18979 mips_cpu_info_from_arch (int arch) 18980 { 18981 int i; 18982 18983 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 18984 if (arch == mips_cpu_info_table[i].cpu) 18985 return (&mips_cpu_info_table[i]); 18986 18987 return NULL; 18988 } 18989 18990 static void 18992 show (FILE *stream, const char *string, int *col_p, int *first_p) 18993 { 18994 if (*first_p) 18995 { 18996 fprintf (stream, "%24s", ""); 18997 *col_p = 24; 18998 } 18999 else 19000 { 19001 fprintf (stream, ", "); 19002 *col_p += 2; 19003 } 19004 19005 if (*col_p + strlen (string) > 72) 19006 { 19007 fprintf (stream, "\n%24s", ""); 19008 *col_p = 24; 19009 } 19010 19011 fprintf (stream, "%s", string); 19012 *col_p += strlen (string); 19013 19014 *first_p = 0; 19015 } 19016 19017 void 19018 md_show_usage (FILE *stream) 19019 { 19020 int column, first; 19021 size_t i; 19022 19023 fprintf (stream, _("\ 19024 MIPS options:\n\ 19025 -EB generate big endian output\n\ 19026 -EL generate little endian output\n\ 19027 -g, -g2 do not remove unneeded NOPs or swap branches\n\ 19028 -G NUM allow referencing objects up to NUM bytes\n\ 19029 implicitly with the gp register [default 8]\n")); 19030 fprintf (stream, _("\ 19031 -mips1 generate MIPS ISA I instructions\n\ 19032 -mips2 generate MIPS ISA II instructions\n\ 19033 -mips3 generate MIPS ISA III instructions\n\ 19034 -mips4 generate MIPS ISA IV instructions\n\ 19035 -mips5 generate MIPS ISA V instructions\n\ 19036 -mips32 generate MIPS32 ISA instructions\n\ 19037 -mips32r2 generate MIPS32 release 2 ISA instructions\n\ 19038 -mips32r3 generate MIPS32 release 3 ISA instructions\n\ 19039 -mips32r5 generate MIPS32 release 5 ISA instructions\n\ 19040 -mips32r6 generate MIPS32 release 6 ISA instructions\n\ 19041 -mips64 generate MIPS64 ISA instructions\n\ 19042 -mips64r2 generate MIPS64 release 2 ISA instructions\n\ 19043 -mips64r3 generate MIPS64 release 3 ISA instructions\n\ 19044 -mips64r5 generate MIPS64 release 5 ISA instructions\n\ 19045 -mips64r6 generate MIPS64 release 6 ISA instructions\n\ 19046 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); 19047 19048 first = 1; 19049 19050 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 19051 show (stream, mips_cpu_info_table[i].name, &column, &first); 19052 show (stream, "from-abi", &column, &first); 19053 fputc ('\n', stream); 19054 19055 fprintf (stream, _("\ 19056 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ 19057 -no-mCPU don't generate code specific to CPU.\n\ 19058 For -mCPU and -no-mCPU, CPU must be one of:\n")); 19059 19060 first = 1; 19061 19062 show (stream, "3900", &column, &first); 19063 show (stream, "4010", &column, &first); 19064 show (stream, "4100", &column, &first); 19065 show (stream, "4650", &column, &first); 19066 fputc ('\n', stream); 19067 19068 fprintf (stream, _("\ 19069 -mips16 generate mips16 instructions\n\ 19070 -no-mips16 do not generate mips16 instructions\n")); 19071 fprintf (stream, _("\ 19072 -mmicromips generate microMIPS instructions\n\ 19073 -mno-micromips do not generate microMIPS instructions\n")); 19074 fprintf (stream, _("\ 19075 -msmartmips generate smartmips instructions\n\ 19076 -mno-smartmips do not generate smartmips instructions\n")); 19077 fprintf (stream, _("\ 19078 -mdsp generate DSP instructions\n\ 19079 -mno-dsp do not generate DSP instructions\n")); 19080 fprintf (stream, _("\ 19081 -mdspr2 generate DSP R2 instructions\n\ 19082 -mno-dspr2 do not generate DSP R2 instructions\n")); 19083 fprintf (stream, _("\ 19084 -mmt generate MT instructions\n\ 19085 -mno-mt do not generate MT instructions\n")); 19086 fprintf (stream, _("\ 19087 -mmcu generate MCU instructions\n\ 19088 -mno-mcu do not generate MCU instructions\n")); 19089 fprintf (stream, _("\ 19090 -mmsa generate MSA instructions\n\ 19091 -mno-msa do not generate MSA instructions\n")); 19092 fprintf (stream, _("\ 19093 -mxpa generate eXtended Physical Address (XPA) instructions\n\ 19094 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); 19095 fprintf (stream, _("\ 19096 -mmxu generate MXU instructions\n\ 19097 -mno-mxu do not generate MXU instructions\n")); 19098 fprintf (stream, _("\ 19099 -mvirt generate Virtualization instructions\n\ 19100 -mno-virt do not generate Virtualization instructions\n")); 19101 fprintf (stream, _("\ 19102 -minsn32 only generate 32-bit microMIPS instructions\n\ 19103 -mno-insn32 generate all microMIPS instructions\n")); 19104 fprintf (stream, _("\ 19105 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ 19106 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ 19107 -mfix-vr4120 work around certain VR4120 errata\n\ 19108 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ 19109 -mfix-24k insert a nop after ERET and DERET instructions\n\ 19110 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ 19111 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ 19112 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ 19113 -msym32 assume all symbols have 32-bit values\n\ 19114 -O0 remove unneeded NOPs, do not swap branches\n\ 19115 -O remove unneeded NOPs and swap branches\n\ 19116 --trap, --no-break trap exception on div by 0 and mult overflow\n\ 19117 --break, --no-trap break exception on div by 0 and mult overflow\n")); 19118 fprintf (stream, _("\ 19119 -mhard-float allow floating-point instructions\n\ 19120 -msoft-float do not allow floating-point instructions\n\ 19121 -msingle-float only allow 32-bit floating-point operations\n\ 19122 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ 19123 --[no-]construct-floats [dis]allow floating point values to be constructed\n\ 19124 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ 19125 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); 19126 19127 first = 1; 19128 19129 show (stream, "legacy", &column, &first); 19130 show (stream, "2008", &column, &first); 19131 19132 fputc ('\n', stream); 19133 19134 fprintf (stream, _("\ 19135 -KPIC, -call_shared generate SVR4 position independent code\n\ 19136 -call_nonpic generate non-PIC code that can operate with DSOs\n\ 19137 -mvxworks-pic generate VxWorks position independent code\n\ 19138 -non_shared do not generate code that can operate with DSOs\n\ 19139 -xgot assume a 32 bit GOT\n\ 19140 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ 19141 -mshared, -mno-shared disable/enable .cpload optimization for\n\ 19142 position dependent (non shared) code\n\ 19143 -mabi=ABI create ABI conformant object file for:\n")); 19144 19145 first = 1; 19146 19147 show (stream, "32", &column, &first); 19148 show (stream, "o64", &column, &first); 19149 show (stream, "n32", &column, &first); 19150 show (stream, "64", &column, &first); 19151 show (stream, "eabi", &column, &first); 19152 19153 fputc ('\n', stream); 19154 19155 fprintf (stream, _("\ 19156 -32 create o32 ABI object file (default)\n\ 19157 -n32 create n32 ABI object file\n\ 19158 -64 create 64 ABI object file\n")); 19159 } 19160 19161 #ifdef TE_IRIX 19162 enum dwarf2_format 19163 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) 19164 { 19165 if (HAVE_64BIT_SYMBOLS) 19166 return dwarf2_format_64bit_irix; 19167 else 19168 return dwarf2_format_32bit; 19169 } 19170 #endif 19171 19172 int 19173 mips_dwarf2_addr_size (void) 19174 { 19175 if (HAVE_64BIT_OBJECTS) 19176 return 8; 19177 else 19178 return 4; 19179 } 19180 19181 /* Standard calling conventions leave the CFA at SP on entry. */ 19182 void 19183 mips_cfi_frame_initial_instructions (void) 19184 { 19185 cfi_add_CFA_def_cfa_register (SP); 19186 } 19187 19188 int 19189 tc_mips_regname_to_dw2regnum (char *regname) 19190 { 19191 unsigned int regnum = -1; 19192 unsigned int reg; 19193 19194 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) 19195 regnum = reg; 19196 19197 return regnum; 19198 } 19199 19200 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. 19201 Given a symbolic attribute NAME, return the proper integer value. 19202 Returns -1 if the attribute is not known. */ 19203 19204 int 19205 mips_convert_symbolic_attribute (const char *name) 19206 { 19207 static const struct 19208 { 19209 const char * name; 19210 const int tag; 19211 } 19212 attribute_table[] = 19213 { 19214 #define T(tag) {#tag, tag} 19215 T (Tag_GNU_MIPS_ABI_FP), 19216 T (Tag_GNU_MIPS_ABI_MSA), 19217 #undef T 19218 }; 19219 unsigned int i; 19220 19221 if (name == NULL) 19222 return -1; 19223 19224 for (i = 0; i < ARRAY_SIZE (attribute_table); i++) 19225 if (streq (name, attribute_table[i].name)) 19226 return attribute_table[i].tag; 19227 19228 return -1; 19229 } 19230 19231 void 19232 md_mips_end (void) 19233 { 19234 int fpabi = Val_GNU_MIPS_ABI_FP_ANY; 19235 19236 mips_emit_delays (); 19237 if (cur_proc_ptr) 19238 as_warn (_("missing .end at end of assembly")); 19239 19240 /* Just in case no code was emitted, do the consistency check. */ 19241 file_mips_check_options (); 19242 19243 /* Set a floating-point ABI if the user did not. */ 19244 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) 19245 { 19246 /* Perform consistency checks on the floating-point ABI. */ 19247 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19248 Tag_GNU_MIPS_ABI_FP); 19249 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) 19250 check_fpabi (fpabi); 19251 } 19252 else 19253 { 19254 /* Soft-float gets precedence over single-float, the two options should 19255 not be used together so this should not matter. */ 19256 if (file_mips_opts.soft_float == 1) 19257 fpabi = Val_GNU_MIPS_ABI_FP_SOFT; 19258 /* Single-float gets precedence over all double_float cases. */ 19259 else if (file_mips_opts.single_float == 1) 19260 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; 19261 else 19262 { 19263 switch (file_mips_opts.fp) 19264 { 19265 case 32: 19266 if (file_mips_opts.gp == 32) 19267 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 19268 break; 19269 case 0: 19270 fpabi = Val_GNU_MIPS_ABI_FP_XX; 19271 break; 19272 case 64: 19273 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) 19274 fpabi = Val_GNU_MIPS_ABI_FP_64A; 19275 else if (file_mips_opts.gp == 32) 19276 fpabi = Val_GNU_MIPS_ABI_FP_64; 19277 else 19278 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 19279 break; 19280 } 19281 } 19282 19283 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19284 Tag_GNU_MIPS_ABI_FP, fpabi); 19285 } 19286 } 19287
