1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 * 24 */ 25 26 #include "util/u_format.h" 27 #include "util/u_math.h" 28 #include "util/u_half.h" 29 30 #include "nv_object.xml.h" 31 #include "nv30/nv30-40_3d.xml.h" 32 #include "nv30/nv30_context.h" 33 #include "nv30/nv30_format.h" 34 35 static void 36 nv30_validate_fb(struct nv30_context *nv30) 37 { 38 struct pipe_screen *pscreen = &nv30->screen->base.base; 39 struct pipe_framebuffer_state *fb = &nv30->framebuffer; 40 struct nouveau_pushbuf *push = nv30->base.pushbuf; 41 struct nouveau_object *eng3d = nv30->screen->eng3d; 42 uint32_t rt_format; 43 int h = fb->height; 44 int w = fb->width; 45 int x = 0; 46 int y = 0; 47 48 nv30->state.rt_enable = (NV30_3D_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1; 49 if (nv30->state.rt_enable > 1) 50 nv30->state.rt_enable |= NV30_3D_RT_ENABLE_MRT; 51 52 rt_format = 0; 53 if (fb->nr_cbufs > 0) { 54 struct nv30_miptree *mt = nv30_miptree(fb->cbufs[0]->texture); 55 rt_format |= nv30_format(pscreen, fb->cbufs[0]->format)->hw; 56 rt_format |= mt->ms_mode; 57 if (mt->swizzled) 58 rt_format |= NV30_3D_RT_FORMAT_TYPE_SWIZZLED; 59 else 60 rt_format |= NV30_3D_RT_FORMAT_TYPE_LINEAR; 61 } else { 62 if (fb->zsbuf && util_format_get_blocksize(fb->zsbuf->format) > 2) 63 rt_format |= NV30_3D_RT_FORMAT_COLOR_A8R8G8B8; 64 else 65 rt_format |= NV30_3D_RT_FORMAT_COLOR_R5G6B5; 66 } 67 68 if (fb->zsbuf) { 69 rt_format |= nv30_format(pscreen, fb->zsbuf->format)->hw; 70 if (nv30_miptree(fb->zsbuf->texture)->swizzled) 71 rt_format |= NV30_3D_RT_FORMAT_TYPE_SWIZZLED; 72 else 73 rt_format |= NV30_3D_RT_FORMAT_TYPE_LINEAR; 74 } else { 75 if (fb->nr_cbufs && util_format_get_blocksize(fb->cbufs[0]->format) > 2) 76 rt_format |= NV30_3D_RT_FORMAT_ZETA_Z24S8; 77 else 78 rt_format |= NV30_3D_RT_FORMAT_ZETA_Z16; 79 } 80 81 /* hardware rounds down render target offset to 64 bytes, but surfaces 82 * with a size of 2x2 pixel (16bpp) or 1x1 pixel (32bpp) have an 83 * unaligned start aaddress. For these two important square formats 84 * we can hack around this limitation by adjusting the viewport origin 85 */ 86 if (nv30->state.rt_enable) { 87 int off = nv30_surface(fb->cbufs[0])->offset & 63; 88 if (off) { 89 x += off / (util_format_get_blocksize(fb->cbufs[0]->format) * 2); 90 w = 16; 91 h = 2; 92 } 93 } 94 95 if (rt_format & NV30_3D_RT_FORMAT_TYPE_SWIZZLED) { 96 rt_format |= util_logbase2(w) << 16; 97 rt_format |= util_logbase2(h) << 24; 98 } 99 100 if (!PUSH_SPACE(push, 64)) 101 return; 102 PUSH_RESET(push, BUFCTX_FB); 103 104 BEGIN_NV04(push, SUBC_3D(0x1da4), 1); 105 PUSH_DATA (push, 0); 106 BEGIN_NV04(push, NV30_3D(RT_HORIZ), 3); 107 PUSH_DATA (push, w << 16); 108 PUSH_DATA (push, h << 16); 109 PUSH_DATA (push, rt_format); 110 BEGIN_NV04(push, NV30_3D(VIEWPORT_TX_ORIGIN), 4); 111 PUSH_DATA (push, (y << 16) | x); 112 PUSH_DATA (push, 0); 113 PUSH_DATA (push, ((w - 1) << 16) | 0); 114 PUSH_DATA (push, ((h - 1) << 16) | 0); 115 116 if ((nv30->state.rt_enable & NV30_3D_RT_ENABLE_COLOR0) || fb->zsbuf) { 117 struct nv30_surface *rsf = nv30_surface(fb->cbufs[0]); 118 struct nv30_surface *zsf = nv30_surface(fb->zsbuf); 119 struct nouveau_bo *rbo, *zbo; 120 121 if (!rsf) rsf = zsf; 122 else if (!zsf) zsf = rsf; 123 rbo = nv30_miptree(rsf->base.texture)->base.bo; 124 zbo = nv30_miptree(zsf->base.texture)->base.bo; 125 126 if (eng3d->oclass >= NV40_3D_CLASS) { 127 BEGIN_NV04(push, NV40_3D(ZETA_PITCH), 1); 128 PUSH_DATA (push, zsf->pitch); 129 BEGIN_NV04(push, NV40_3D(COLOR0_PITCH), 3); 130 PUSH_DATA (push, rsf->pitch); 131 } else { 132 BEGIN_NV04(push, NV30_3D(COLOR0_PITCH), 3); 133 PUSH_DATA (push, (zsf->pitch << 16) | rsf->pitch); 134 } 135 PUSH_MTHDl(push, NV30_3D(COLOR0_OFFSET), BUFCTX_FB, rbo, rsf->offset & ~63, 136 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 137 PUSH_MTHDl(push, NV30_3D(ZETA_OFFSET), BUFCTX_FB, zbo, zsf->offset & ~63, 138 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 139 } 140 141 if (nv30->state.rt_enable & NV30_3D_RT_ENABLE_COLOR1) { 142 struct nv30_surface *sf = nv30_surface(fb->cbufs[1]); 143 struct nouveau_bo *bo = nv30_miptree(sf->base.texture)->base.bo; 144 145 BEGIN_NV04(push, NV30_3D(COLOR1_OFFSET), 2); 146 PUSH_MTHDl(push, NV30_3D(COLOR1_OFFSET), BUFCTX_FB, bo, sf->offset, 147 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 148 PUSH_DATA (push, sf->pitch); 149 } 150 151 if (nv30->state.rt_enable & NV40_3D_RT_ENABLE_COLOR2) { 152 struct nv30_surface *sf = nv30_surface(fb->cbufs[2]); 153 struct nouveau_bo *bo = nv30_miptree(sf->base.texture)->base.bo; 154 155 BEGIN_NV04(push, NV40_3D(COLOR2_OFFSET), 1); 156 PUSH_MTHDl(push, NV40_3D(COLOR2_OFFSET), BUFCTX_FB, bo, sf->offset, 157 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 158 BEGIN_NV04(push, NV40_3D(COLOR2_PITCH), 1); 159 PUSH_DATA (push, sf->pitch); 160 } 161 162 if (nv30->state.rt_enable & NV40_3D_RT_ENABLE_COLOR3) { 163 struct nv30_surface *sf = nv30_surface(fb->cbufs[3]); 164 struct nouveau_bo *bo = nv30_miptree(sf->base.texture)->base.bo; 165 166 BEGIN_NV04(push, NV40_3D(COLOR3_OFFSET), 1); 167 PUSH_MTHDl(push, NV40_3D(COLOR3_OFFSET), BUFCTX_FB, bo, sf->offset, 168 NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); 169 BEGIN_NV04(push, NV40_3D(COLOR3_PITCH), 1); 170 PUSH_DATA (push, sf->pitch); 171 } 172 } 173 174 static void 175 nv30_validate_blend_colour(struct nv30_context *nv30) 176 { 177 struct nouveau_pushbuf *push = nv30->base.pushbuf; 178 float *rgba = nv30->blend_colour.color; 179 180 if (nv30->framebuffer.nr_cbufs) { 181 switch (nv30->framebuffer.cbufs[0]->format) { 182 case PIPE_FORMAT_R16G16B16A16_FLOAT: 183 case PIPE_FORMAT_R32G32B32A32_FLOAT: 184 BEGIN_NV04(push, NV30_3D(BLEND_COLOR), 1); 185 PUSH_DATA (push, (util_float_to_half(rgba[0]) << 0) | 186 (util_float_to_half(rgba[1]) << 16)); 187 BEGIN_NV04(push, SUBC_3D(0x037c), 1); 188 PUSH_DATA (push, (util_float_to_half(rgba[2]) << 0) | 189 (util_float_to_half(rgba[3]) << 16)); 190 break; 191 default: 192 break; 193 } 194 } 195 196 BEGIN_NV04(push, NV30_3D(BLEND_COLOR), 1); 197 PUSH_DATA (push, (float_to_ubyte(rgba[3]) << 24) | 198 (float_to_ubyte(rgba[0]) << 16) | 199 (float_to_ubyte(rgba[1]) << 8) | 200 (float_to_ubyte(rgba[2]) << 0)); 201 } 202 203 static void 204 nv30_validate_stencil_ref(struct nv30_context *nv30) 205 { 206 struct nouveau_pushbuf *push = nv30->base.pushbuf; 207 208 BEGIN_NV04(push, NV30_3D(STENCIL_FUNC_REF(0)), 1); 209 PUSH_DATA (push, nv30->stencil_ref.ref_value[0]); 210 BEGIN_NV04(push, NV30_3D(STENCIL_FUNC_REF(1)), 1); 211 PUSH_DATA (push, nv30->stencil_ref.ref_value[1]); 212 } 213 214 static void 215 nv30_validate_stipple(struct nv30_context *nv30) 216 { 217 struct nouveau_pushbuf *push = nv30->base.pushbuf; 218 219 BEGIN_NV04(push, NV30_3D(POLYGON_STIPPLE_PATTERN(0)), 32); 220 PUSH_DATAp(push, nv30->stipple.stipple, 32); 221 } 222 223 static void 224 nv30_validate_scissor(struct nv30_context *nv30) 225 { 226 struct nouveau_pushbuf *push = nv30->base.pushbuf; 227 struct pipe_scissor_state *s = &nv30->scissor; 228 229 if (!(nv30->dirty & NV30_NEW_SCISSOR) && 230 nv30->rast->pipe.scissor != nv30->state.scissor_off) 231 return; 232 nv30->state.scissor_off = !nv30->rast->pipe.scissor; 233 234 BEGIN_NV04(push, NV30_3D(SCISSOR_HORIZ), 2); 235 if (nv30->rast->pipe.scissor) { 236 PUSH_DATA (push, ((s->maxx - s->minx) << 16) | s->minx); 237 PUSH_DATA (push, ((s->maxy - s->miny) << 16) | s->miny); 238 } else { 239 PUSH_DATA (push, 0x10000000); 240 PUSH_DATA (push, 0x10000000); 241 } 242 } 243 244 static void 245 nv30_validate_viewport(struct nv30_context *nv30) 246 { 247 struct nouveau_pushbuf *push = nv30->base.pushbuf; 248 struct pipe_viewport_state *vp = &nv30->viewport; 249 250 unsigned x = CLAMP(vp->translate[0] - fabsf(vp->scale[0]), 0, 4095); 251 unsigned y = CLAMP(vp->translate[1] - fabsf(vp->scale[1]), 0, 4095); 252 unsigned w = CLAMP(2.0f * fabsf(vp->scale[0]), 0, 4096); 253 unsigned h = CLAMP(2.0f * fabsf(vp->scale[1]), 0, 4096); 254 255 BEGIN_NV04(push, NV30_3D(VIEWPORT_TRANSLATE_X), 8); 256 PUSH_DATAf(push, vp->translate[0]); 257 PUSH_DATAf(push, vp->translate[1]); 258 PUSH_DATAf(push, vp->translate[2]); 259 PUSH_DATAf(push, 0.0f); 260 PUSH_DATAf(push, vp->scale[0]); 261 PUSH_DATAf(push, vp->scale[1]); 262 PUSH_DATAf(push, vp->scale[2]); 263 PUSH_DATAf(push, 0.0f); 264 BEGIN_NV04(push, NV30_3D(DEPTH_RANGE_NEAR), 2); 265 PUSH_DATAf(push, vp->translate[2] - fabsf(vp->scale[2])); 266 PUSH_DATAf(push, vp->translate[2] + fabsf(vp->scale[2])); 267 268 BEGIN_NV04(push, NV30_3D(VIEWPORT_HORIZ), 2); 269 PUSH_DATA (push, (w << 16) | x); 270 PUSH_DATA (push, (h << 16) | y); 271 } 272 273 static void 274 nv30_validate_clip(struct nv30_context *nv30) 275 { 276 struct nouveau_pushbuf *push = nv30->base.pushbuf; 277 unsigned i; 278 uint32_t clpd_enable = 0; 279 280 for (i = 0; i < 6; i++) { 281 if (nv30->dirty & NV30_NEW_CLIP) { 282 BEGIN_NV04(push, NV30_3D(VP_UPLOAD_CONST_ID), 5); 283 PUSH_DATA (push, i); 284 PUSH_DATAp(push, nv30->clip.ucp[i], 4); 285 } 286 if (nv30->rast->pipe.clip_plane_enable & (1 << i)) 287 clpd_enable |= 2 << (4*i); 288 } 289 290 BEGIN_NV04(push, NV30_3D(VP_CLIP_PLANES_ENABLE), 1); 291 PUSH_DATA (push, clpd_enable); 292 } 293 294 static void 295 nv30_validate_blend(struct nv30_context *nv30) 296 { 297 struct nouveau_pushbuf *push = nv30->base.pushbuf; 298 299 PUSH_SPACE(push, nv30->blend->size); 300 PUSH_DATAp(push, nv30->blend->data, nv30->blend->size); 301 } 302 303 static void 304 nv30_validate_zsa(struct nv30_context *nv30) 305 { 306 struct nouveau_pushbuf *push = nv30->base.pushbuf; 307 308 PUSH_SPACE(push, nv30->zsa->size); 309 PUSH_DATAp(push, nv30->zsa->data, nv30->zsa->size); 310 } 311 312 static void 313 nv30_validate_rasterizer(struct nv30_context *nv30) 314 { 315 struct nouveau_pushbuf *push = nv30->base.pushbuf; 316 317 PUSH_SPACE(push, nv30->rast->size); 318 PUSH_DATAp(push, nv30->rast->data, nv30->rast->size); 319 } 320 321 static void 322 nv30_validate_multisample(struct nv30_context *nv30) 323 { 324 struct pipe_rasterizer_state *rasterizer = &nv30->rast->pipe; 325 struct pipe_blend_state *blend = &nv30->blend->pipe; 326 struct nouveau_pushbuf *push = nv30->base.pushbuf; 327 uint32_t ctrl = nv30->sample_mask << 16; 328 329 if (blend->alpha_to_one) 330 ctrl |= 0x00000100; 331 if (blend->alpha_to_coverage) 332 ctrl |= 0x00000010; 333 if (rasterizer->multisample) 334 ctrl |= 0x00000001; 335 336 BEGIN_NV04(push, NV30_3D(MULTISAMPLE_CONTROL), 1); 337 PUSH_DATA (push, ctrl); 338 } 339 340 static void 341 nv30_validate_fragment(struct nv30_context *nv30) 342 { 343 struct nouveau_pushbuf *push = nv30->base.pushbuf; 344 struct nv30_fragprog *fp = nv30->fragprog.program; 345 346 BEGIN_NV04(push, NV30_3D(RT_ENABLE), 1); 347 PUSH_DATA (push, nv30->state.rt_enable & ~fp->rt_enable); 348 BEGIN_NV04(push, NV30_3D(COORD_CONVENTIONS), 1); 349 PUSH_DATA (push, fp->coord_conventions | nv30->framebuffer.height); 350 } 351 352 static void 353 nv30_validate_point_coord(struct nv30_context *nv30) 354 { 355 struct pipe_rasterizer_state *rasterizer = &nv30->rast->pipe; 356 struct nouveau_pushbuf *push = nv30->base.pushbuf; 357 struct nv30_fragprog *fp = nv30->fragprog.program; 358 uint32_t hw = 0x00000000; 359 360 if (rasterizer) { 361 hw |= (nv30->rast->pipe.sprite_coord_enable & 0xff) << 8; 362 if (fp) 363 hw |= fp->point_sprite_control; 364 365 if (rasterizer->sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT) { 366 if (hw) 367 nv30->draw_flags |= NV30_NEW_RASTERIZER; 368 } else 369 if (rasterizer->point_quad_rasterization) { 370 hw |= NV30_3D_POINT_SPRITE_ENABLE; 371 } 372 } 373 374 BEGIN_NV04(push, NV30_3D(POINT_SPRITE), 1); 375 PUSH_DATA (push, hw); 376 } 377 378 struct state_validate { 379 void (*func)(struct nv30_context *); 380 uint32_t mask; 381 }; 382 383 static struct state_validate hwtnl_validate_list[] = { 384 { nv30_validate_fb, NV30_NEW_FRAMEBUFFER }, 385 { nv30_validate_blend, NV30_NEW_BLEND }, 386 { nv30_validate_zsa, NV30_NEW_ZSA }, 387 { nv30_validate_rasterizer, NV30_NEW_RASTERIZER }, 388 { nv30_validate_multisample, NV30_NEW_SAMPLE_MASK | NV30_NEW_BLEND | 389 NV30_NEW_RASTERIZER }, 390 { nv30_validate_blend_colour, NV30_NEW_BLEND_COLOUR | 391 NV30_NEW_FRAMEBUFFER }, 392 { nv30_validate_stencil_ref, NV30_NEW_STENCIL_REF }, 393 { nv30_validate_stipple, NV30_NEW_STIPPLE }, 394 { nv30_validate_scissor, NV30_NEW_SCISSOR | NV30_NEW_RASTERIZER }, 395 { nv30_validate_viewport, NV30_NEW_VIEWPORT }, 396 { nv30_validate_clip, NV30_NEW_CLIP | NV30_NEW_RASTERIZER }, 397 { nv30_fragprog_validate, NV30_NEW_FRAGPROG | NV30_NEW_FRAGCONST }, 398 { nv30_vertprog_validate, NV30_NEW_VERTPROG | NV30_NEW_VERTCONST | 399 NV30_NEW_FRAGPROG | NV30_NEW_RASTERIZER }, 400 { nv30_validate_fragment, NV30_NEW_FRAMEBUFFER | NV30_NEW_FRAGPROG }, 401 { nv30_validate_point_coord, NV30_NEW_RASTERIZER | NV30_NEW_FRAGPROG }, 402 { nv30_fragtex_validate, NV30_NEW_FRAGTEX }, 403 { nv40_verttex_validate, NV30_NEW_VERTTEX }, 404 { nv30_vbo_validate, NV30_NEW_VERTEX | NV30_NEW_ARRAYS }, 405 {} 406 }; 407 408 #define NV30_SWTNL_MASK (NV30_NEW_VIEWPORT | \ 409 NV30_NEW_CLIP | \ 410 NV30_NEW_VERTPROG | \ 411 NV30_NEW_VERTCONST | \ 412 NV30_NEW_VERTTEX | \ 413 NV30_NEW_VERTEX | \ 414 NV30_NEW_ARRAYS) 415 416 static struct state_validate swtnl_validate_list[] = { 417 { nv30_validate_fb, NV30_NEW_FRAMEBUFFER }, 418 { nv30_validate_blend, NV30_NEW_BLEND }, 419 { nv30_validate_zsa, NV30_NEW_ZSA }, 420 { nv30_validate_rasterizer, NV30_NEW_RASTERIZER }, 421 { nv30_validate_multisample, NV30_NEW_SAMPLE_MASK | NV30_NEW_BLEND | 422 NV30_NEW_RASTERIZER }, 423 { nv30_validate_blend_colour, NV30_NEW_BLEND_COLOUR | 424 NV30_NEW_FRAMEBUFFER }, 425 { nv30_validate_stencil_ref, NV30_NEW_STENCIL_REF }, 426 { nv30_validate_stipple, NV30_NEW_STIPPLE }, 427 { nv30_validate_scissor, NV30_NEW_SCISSOR | NV30_NEW_RASTERIZER }, 428 { nv30_fragprog_validate, NV30_NEW_FRAGPROG | NV30_NEW_FRAGCONST }, 429 { nv30_validate_fragment, NV30_NEW_FRAMEBUFFER | NV30_NEW_FRAGPROG }, 430 { nv30_fragtex_validate, NV30_NEW_FRAGTEX }, 431 {} 432 }; 433 434 static void 435 nv30_state_context_switch(struct nv30_context *nv30) 436 { 437 struct nv30_context *prev = nv30->screen->cur_ctx; 438 439 if (prev) 440 nv30->state = prev->state; 441 nv30->dirty = NV30_NEW_ALL; 442 443 if (!nv30->vertex) 444 nv30->dirty &= ~(NV30_NEW_VERTEX | NV30_NEW_ARRAYS); 445 446 if (!nv30->vertprog.program) 447 nv30->dirty &= ~NV30_NEW_VERTPROG; 448 if (!nv30->fragprog.program) 449 nv30->dirty &= ~NV30_NEW_FRAGPROG; 450 451 if (!nv30->blend) 452 nv30->dirty &= ~NV30_NEW_BLEND; 453 if (!nv30->rast) 454 nv30->dirty &= ~NV30_NEW_RASTERIZER; 455 if (!nv30->zsa) 456 nv30->dirty &= ~NV30_NEW_ZSA; 457 458 nv30->screen->cur_ctx = nv30; 459 nv30->base.pushbuf->user_priv = &nv30->bufctx; 460 } 461 462 bool 463 nv30_state_validate(struct nv30_context *nv30, uint32_t mask, bool hwtnl) 464 { 465 struct nouveau_screen *screen = &nv30->screen->base; 466 struct nouveau_pushbuf *push = nv30->base.pushbuf; 467 struct nouveau_bufctx *bctx = nv30->bufctx; 468 struct nouveau_bufref *bref; 469 struct state_validate *validate; 470 471 if (nv30->screen->cur_ctx != nv30) 472 nv30_state_context_switch(nv30); 473 474 if (hwtnl) { 475 nv30->draw_dirty |= nv30->dirty; 476 if (nv30->draw_flags) { 477 nv30->draw_flags &= ~nv30->dirty; 478 if (!nv30->draw_flags) 479 nv30->dirty |= NV30_SWTNL_MASK; 480 } 481 } 482 483 if (!nv30->draw_flags) 484 validate = hwtnl_validate_list; 485 else 486 validate = swtnl_validate_list; 487 488 mask &= nv30->dirty; 489 490 if (mask) { 491 while (validate->func) { 492 if (mask & validate->mask) 493 validate->func(nv30); 494 validate++; 495 } 496 497 nv30->dirty &= ~mask; 498 } 499 500 nouveau_pushbuf_bufctx(push, bctx); 501 if (nouveau_pushbuf_validate(push)) { 502 nouveau_pushbuf_bufctx(push, NULL); 503 return false; 504 } 505 506 /*XXX*/ 507 BEGIN_NV04(push, NV30_3D(VTX_CACHE_INVALIDATE_1710), 1); 508 PUSH_DATA (push, 0); 509 if (nv30->screen->eng3d->oclass >= NV40_3D_CLASS) { 510 BEGIN_NV04(push, NV40_3D(TEX_CACHE_CTL), 1); 511 PUSH_DATA (push, 2); 512 BEGIN_NV04(push, NV40_3D(TEX_CACHE_CTL), 1); 513 PUSH_DATA (push, 1); 514 BEGIN_NV04(push, NV30_3D(R1718), 1); 515 PUSH_DATA (push, 0); 516 BEGIN_NV04(push, NV30_3D(R1718), 1); 517 PUSH_DATA (push, 0); 518 BEGIN_NV04(push, NV30_3D(R1718), 1); 519 PUSH_DATA (push, 0); 520 } 521 522 LIST_FOR_EACH_ENTRY(bref, &bctx->current, thead) { 523 struct nv04_resource *res = bref->priv; 524 if (res && res->mm) { 525 nouveau_fence_ref(screen->fence.current, &res->fence); 526 527 if (bref->flags & NOUVEAU_BO_RD) 528 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING; 529 530 if (bref->flags & NOUVEAU_BO_WR) { 531 nouveau_fence_ref(screen->fence.current, &res->fence_wr); 532 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; 533 } 534 } 535 } 536 537 return true; 538 } 539 540 void 541 nv30_state_release(struct nv30_context *nv30) 542 { 543 nouveau_pushbuf_bufctx(nv30->base.pushbuf, NULL); 544 } 545
