1 /* 2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __HI6220_REGS_ACPU_H__ 33 #define __HI6220_REGS_ACPU_H__ 34 35 #define ACPU_CTRL_BASE 0xF6504000 36 37 #define ACPU_SC_CPU_CTRL (ACPU_CTRL_BASE + 0x000) 38 #define ACPU_SC_CPU_STAT (ACPU_CTRL_BASE + 0x008) 39 #define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2 (1 << 0) 40 #define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2_SHIFT (0) 41 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI0 (1 << 1) 42 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI0_SHIFT (1) 43 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI1 (1 << 2) 44 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI1_SHIFT (2) 45 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI2 (1 << 3) 46 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI2_SHIFT (3) 47 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI3 (1 << 4) 48 #define ACPU_SC_CPU_STAT_SC_STANDBYWFI3_SHIFT (4) 49 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2 (1 << 8) 50 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2_SHIFT (8) 51 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI (1 << 9) 52 #define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI_SHIFT (9) 53 #define ACPU_SC_CPU_STAT_L2FLSHUDONE0 (1 << 16) 54 #define ACPU_SC_CPU_STAT_L2FLSHUDONE0_SHIFT (16) 55 #define ACPU_SC_CPU_STAT_L2FLSHUDONE1 (1 << 17) 56 #define ACPU_SC_CPU_STAT_L2FLSHUDONE1_SHIFT (17) 57 #define ACPU_SC_CPU_STAT_CCI400_ACTIVE (1 << 18) 58 #define ACPU_SC_CPU_STAT_CCI400_ACTIVE_SHIFT (18) 59 #define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD (1 << 20) 60 #define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD_SHIFT (20) 61 62 #define ACPU_SC_CLKEN (ACPU_CTRL_BASE + 0x00c) 63 #define HPM_L2_1_CLKEN (1 << 9) 64 #define G_CPU_1_CLKEN (1 << 8) 65 #define HPM_L2_CLKEN (1 << 1) 66 #define G_CPU_CLKEN (1 << 0) 67 68 #define ACPU_SC_CLKDIS (ACPU_CTRL_BASE + 0x010) 69 #define ACPU_SC_CLK_STAT (ACPU_CTRL_BASE + 0x014) 70 #define ACPU_SC_RSTEN (ACPU_CTRL_BASE + 0x018) 71 #define SRST_PRESET1_RSTEN (1 << 11) 72 #define SRST_PRESET0_RSTEN (1 << 10) 73 #define SRST_CLUSTER1_RSTEN (1 << 9) 74 #define SRST_CLUSTER0_RSTEN (1 << 8) 75 #define SRST_L2_HPM_1_RSTEN (1 << 5) 76 #define SRST_AARM_L2_1_RSTEN (1 << 4) 77 #define SRST_L2_HPM_0_RSTEN (1 << 3) 78 #define SRST_AARM_L2_0_RSTEN (1 << 1) 79 #define SRST_CLUSTER1 (SRST_PRESET1_RSTEN | \ 80 SRST_CLUSTER1_RSTEN | \ 81 SRST_L2_HPM_1_RSTEN | \ 82 SRST_AARM_L2_1_RSTEN) 83 #define SRST_CLUSTER0 (SRST_PRESET0_RSTEN | \ 84 SRST_CLUSTER0_RSTEN | \ 85 SRST_L2_HPM_0_RSTEN | \ 86 SRST_AARM_L2_0_RSTEN) 87 88 #define ACPU_SC_RSTDIS (ACPU_CTRL_BASE + 0x01c) 89 #define ACPU_SC_RST_STAT (ACPU_CTRL_BASE + 0x020) 90 #define ACPU_SC_PDBGUP_MBIST (ACPU_CTRL_BASE + 0x02c) 91 #define PDBGUP_CLUSTER1_SHIFT 8 92 93 #define ACPU_SC_VD_CTRL (ACPU_CTRL_BASE + 0x054) 94 #define ACPU_SC_VD_MASK_PATTERN_CTRL (ACPU_CTRL_BASE + 0x058) 95 #define ACPU_SC_VD_MASK_PATTERN_VAL (0xCCB << 12) 96 #define ACPU_SC_VD_MASK_PATTERN_MASK ((0x1 << 13) - 1) 97 98 #define ACPU_SC_VD_DLY_FIXED_CTRL (ACPU_CTRL_BASE + 0x05c) 99 #define ACPU_SC_VD_DLY_TABLE0_CTRL (ACPU_CTRL_BASE + 0x060) 100 #define ACPU_SC_VD_DLY_TABLE1_CTRL (ACPU_CTRL_BASE + 0x064) 101 #define ACPU_SC_VD_DLY_TABLE2_CTRL (ACPU_CTRL_BASE + 0x068) 102 #define ACPU_SC_VD_HPM_CTRL (ACPU_CTRL_BASE + 0x06c) 103 #define ACPU_SC_A53_CLUSTER_MTCMOS_EN (ACPU_CTRL_BASE + 0x088) 104 #define PW_MTCMOS_EN_A53_1_EN (1 << 1) 105 #define PW_MTCMOS_EN_A53_0_EN (1 << 0) 106 107 #define ACPU_SC_A53_CLUSTER_MTCMOS_STA (ACPU_CTRL_BASE + 0x090) 108 #define ACPU_SC_A53_CLUSTER_ISO_EN (ACPU_CTRL_BASE + 0x098) 109 #define PW_ISO_A53_1_EN (1 << 1) 110 #define PW_ISO_A53_0_EN (1 << 0) 111 112 #define ACPU_SC_A53_CLUSTER_ISO_DIS (ACPU_CTRL_BASE + 0x09c) 113 #define ACPU_SC_A53_CLUSTER_ISO_STA (ACPU_CTRL_BASE + 0x0a0) 114 #define ACPU_SC_A53_1_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0b4) 115 #define ACPU_SC_A53_0_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0bc) 116 #define ACPU_SC_A53_x_MTCMOS_TIMER(x) ((x) ? ACPU_SC_A53_1_MTCMOS_TIMER : ACPU_SC_A53_0_MTCMOS_TIMER) 117 118 #define ACPU_SC_CPU0_CTRL (ACPU_CTRL_BASE + 0x100) 119 #define CPU_CTRL_AARCH64_MODE (1 << 7) 120 121 #define ACPU_SC_CPU0_STAT (ACPU_CTRL_BASE + 0x104) 122 #define ACPU_SC_CPU0_CLKEN (ACPU_CTRL_BASE + 0x108) 123 #define CPU_CLKEN_HPM (1 << 1) 124 125 #define ACPU_SC_CPU0_CLK_STAT (ACPU_CTRL_BASE + 0x110) 126 127 #define ACPU_SC_CPU0_RSTEN (ACPU_CTRL_BASE + 0x114) 128 #define ACPU_SC_CPU0_RSTDIS (ACPU_CTRL_BASE + 0x118) 129 #define ACPU_SC_CPU0_MTCMOS_EN (ACPU_CTRL_BASE + 0x120) 130 #define CPU_MTCMOS_PW (1 << 0) 131 132 #define ACPU_SC_CPU0_PW_ISOEN (ACPU_CTRL_BASE + 0x130) 133 #define CPU_PW_ISO (1 << 0) 134 135 #define ACPU_SC_CPU0_PW_ISODIS (ACPU_CTRL_BASE + 0x134) 136 #define ACPU_SC_CPU0_PW_ISO_STAT (ACPU_CTRL_BASE + 0x138) 137 #define ACPU_SC_CPU0_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x154) 138 #define CPU_MTCMOS_TIMER_STA (1 << 0) 139 140 #define ACPU_SC_CPU0_RVBARADDR (ACPU_CTRL_BASE + 0x158) 141 #define ACPU_SC_CPU1_CTRL (ACPU_CTRL_BASE + 0x200) 142 #define ACPU_SC_CPU1_STAT (ACPU_CTRL_BASE + 0x204) 143 #define ACPU_SC_CPU1_CLKEN (ACPU_CTRL_BASE + 0x208) 144 #define ACPU_SC_CPU1_CLK_STAT (ACPU_CTRL_BASE + 0x210) 145 #define ACPU_SC_CPU1_RSTEN (ACPU_CTRL_BASE + 0x214) 146 #define ACPU_SC_CPU1_RSTDIS (ACPU_CTRL_BASE + 0x218) 147 #define ACPU_SC_CPU1_MTCMOS_EN (ACPU_CTRL_BASE + 0x220) 148 #define ACPU_SC_CPU1_PW_ISODIS (ACPU_CTRL_BASE + 0x234) 149 #define ACPU_SC_CPU1_PW_ISO_STAT (ACPU_CTRL_BASE + 0x238) 150 #define ACPU_SC_CPU1_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x254) 151 #define ACPU_SC_CPU1_RVBARADDR (ACPU_CTRL_BASE + 0x258) 152 #define ACPU_SC_CPU2_CTRL (ACPU_CTRL_BASE + 0x300) 153 #define ACPU_SC_CPU2_STAT (ACPU_CTRL_BASE + 0x304) 154 #define ACPU_SC_CPU2_CLKEN (ACPU_CTRL_BASE + 0x308) 155 #define ACPU_SC_CPU2_CLK_STAT (ACPU_CTRL_BASE + 0x310) 156 #define ACPU_SC_CPU2_RSTEN (ACPU_CTRL_BASE + 0x314) 157 #define ACPU_SC_CPU2_RSTDIS (ACPU_CTRL_BASE + 0x318) 158 #define ACPU_SC_CPU2_MTCMOS_EN (ACPU_CTRL_BASE + 0x320) 159 #define ACPU_SC_CPU2_PW_ISODIS (ACPU_CTRL_BASE + 0x334) 160 #define ACPU_SC_CPU2_PW_ISO_STAT (ACPU_CTRL_BASE + 0x338) 161 #define ACPU_SC_CPU2_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x354) 162 #define ACPU_SC_CPU2_RVBARADDR (ACPU_CTRL_BASE + 0x358) 163 #define ACPU_SC_CPU3_CTRL (ACPU_CTRL_BASE + 0x400) 164 #define ACPU_SC_CPU3_STAT (ACPU_CTRL_BASE + 0x404) 165 #define ACPU_SC_CPU3_CLKEN (ACPU_CTRL_BASE + 0x408) 166 #define ACPU_SC_CPU3_CLK_STAT (ACPU_CTRL_BASE + 0x410) 167 #define ACPU_SC_CPU3_RSTEN (ACPU_CTRL_BASE + 0x414) 168 #define ACPU_SC_CPU3_RSTDIS (ACPU_CTRL_BASE + 0x418) 169 #define ACPU_SC_CPU3_MTCMOS_EN (ACPU_CTRL_BASE + 0x420) 170 #define ACPU_SC_CPU3_PW_ISODIS (ACPU_CTRL_BASE + 0x434) 171 #define ACPU_SC_CPU3_PW_ISO_STAT (ACPU_CTRL_BASE + 0x438) 172 #define ACPU_SC_CPU3_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x454) 173 #define ACPU_SC_CPU3_RVBARADDR (ACPU_CTRL_BASE + 0x458) 174 #define ACPU_SC_CPU4_CTRL (ACPU_CTRL_BASE + 0x500) 175 #define ACPU_SC_CPU4_STAT (ACPU_CTRL_BASE + 0x504) 176 #define ACPU_SC_CPU4_CLKEN (ACPU_CTRL_BASE + 0x508) 177 #define ACPU_SC_CPU4_CLK_STAT (ACPU_CTRL_BASE + 0x510) 178 #define ACPU_SC_CPU4_RSTEN (ACPU_CTRL_BASE + 0x514) 179 #define ACPU_SC_CPU4_RSTDIS (ACPU_CTRL_BASE + 0x518) 180 #define ACPU_SC_CPU4_MTCMOS_EN (ACPU_CTRL_BASE + 0x520) 181 #define ACPU_SC_CPU4_PW_ISODIS (ACPU_CTRL_BASE + 0x534) 182 #define ACPU_SC_CPU4_PW_ISO_STAT (ACPU_CTRL_BASE + 0x538) 183 #define ACPU_SC_CPU4_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x554) 184 #define ACPU_SC_CPU4_RVBARADDR (ACPU_CTRL_BASE + 0x558) 185 #define ACPU_SC_CPU5_CTRL (ACPU_CTRL_BASE + 0x600) 186 #define ACPU_SC_CPU5_STAT (ACPU_CTRL_BASE + 0x604) 187 #define ACPU_SC_CPU5_CLKEN (ACPU_CTRL_BASE + 0x608) 188 #define ACPU_SC_CPU5_CLK_STAT (ACPU_CTRL_BASE + 0x610) 189 #define ACPU_SC_CPU5_RSTEN (ACPU_CTRL_BASE + 0x614) 190 #define ACPU_SC_CPU5_RSTDIS (ACPU_CTRL_BASE + 0x618) 191 #define ACPU_SC_CPU5_MTCMOS_EN (ACPU_CTRL_BASE + 0x620) 192 #define ACPU_SC_CPU5_PW_ISODIS (ACPU_CTRL_BASE + 0x634) 193 #define ACPU_SC_CPU5_PW_ISO_STAT (ACPU_CTRL_BASE + 0x638) 194 #define ACPU_SC_CPU5_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x654) 195 #define ACPU_SC_CPU5_RVBARADDR (ACPU_CTRL_BASE + 0x658) 196 #define ACPU_SC_CPU6_CTRL (ACPU_CTRL_BASE + 0x700) 197 #define ACPU_SC_CPU6_STAT (ACPU_CTRL_BASE + 0x704) 198 #define ACPU_SC_CPU6_CLKEN (ACPU_CTRL_BASE + 0x708) 199 #define ACPU_SC_CPU6_CLK_STAT (ACPU_CTRL_BASE + 0x710) 200 #define ACPU_SC_CPU6_RSTEN (ACPU_CTRL_BASE + 0x714) 201 #define ACPU_SC_CPU6_RSTDIS (ACPU_CTRL_BASE + 0x718) 202 #define ACPU_SC_CPU6_MTCMOS_EN (ACPU_CTRL_BASE + 0x720) 203 #define ACPU_SC_CPU6_PW_ISODIS (ACPU_CTRL_BASE + 0x734) 204 #define ACPU_SC_CPU6_PW_ISO_STAT (ACPU_CTRL_BASE + 0x738) 205 #define ACPU_SC_CPU6_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x754) 206 #define ACPU_SC_CPU6_RVBARADDR (ACPU_CTRL_BASE + 0x758) 207 #define ACPU_SC_CPU7_CTRL (ACPU_CTRL_BASE + 0x800) 208 #define ACPU_SC_CPU7_STAT (ACPU_CTRL_BASE + 0x804) 209 #define ACPU_SC_CPU7_CLKEN (ACPU_CTRL_BASE + 0x808) 210 #define ACPU_SC_CPU7_CLK_STAT (ACPU_CTRL_BASE + 0x810) 211 #define ACPU_SC_CPU7_RSTEN (ACPU_CTRL_BASE + 0x814) 212 #define ACPU_SC_CPU7_RSTDIS (ACPU_CTRL_BASE + 0x818) 213 #define ACPU_SC_CPU7_MTCMOS_EN (ACPU_CTRL_BASE + 0x820) 214 #define ACPU_SC_CPU7_PW_ISODIS (ACPU_CTRL_BASE + 0x834) 215 #define ACPU_SC_CPU7_PW_ISO_STAT (ACPU_CTRL_BASE + 0x838) 216 #define ACPU_SC_CPU7_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x854) 217 #define ACPU_SC_CPU7_RVBARADDR (ACPU_CTRL_BASE + 0x858) 218 #define ACPU_SC_CPUx_CTRL(x) ((x < 8) ? (ACPU_SC_CPU0_CTRL + 0x100 * x) : ACPU_SC_CPU0_CTRL) 219 #define ACPU_SC_CPUx_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_STAT + 0x100 * x) : ACPU_SC_CPU0_STAT) 220 #define ACPU_SC_CPUx_CLKEN(x) ((x < 8) ? (ACPU_SC_CPU0_CLKEN + 0x100 * x) : ACPU_SC_CPU0_CLKEN) 221 #define ACPU_SC_CPUx_CLK_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_CLK_STAT + 0x100 *x) : ACPU_SC_CPU0_CLK_STAT) 222 #define ACPU_SC_CPUx_RSTEN(x) ((x < 8) ? (ACPU_SC_CPU0_RSTEN + 0x100 * x) : ACPU_SC_CPU0_RSTEN) 223 #define ACPU_SC_CPUx_RSTDIS(x) ((x < 8) ? (ACPU_SC_CPU0_RSTDIS + 0x100 * x) : ACPU_SC_CPU0_RSTDIS) 224 #define ACPU_SC_CPUx_MTCMOS_EN(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_EN + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_EN) 225 #define ACPU_SC_CPUx_PW_ISODIS(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISODIS + 0x100 * x) : ACPU_SC_CPU0_PW_ISODIS) 226 #define ACPU_SC_CPUx_PW_ISO_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISO_STAT + 0x100 * x) : ACPU_SC_CPU0_PW_ISO_STAT) 227 #define ACPU_SC_CPUx_MTCMOS_TIMER_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_TIMER_STAT + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_TIMER_STAT) 228 #define ACPU_SC_CPUx_RVBARADDR(x) ((x < 8) ? (ACPU_SC_CPU0_RVBARADDR + 0x100 * x) : ACPU_SC_CPU0_RVBARADDR) 229 230 #define ACPU_SC_CPU_STAT_CLKDIV_VD_MASK (3 << 20) 231 232 #define ACPU_SC_VD_CTRL_TUNE_EN_DIF (1 << 0) 233 #define ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT (0) 234 #define ACPU_SC_VD_CTRL_TUNE (1 << 1) 235 #define ACPU_SC_VD_CTRL_TUNE_SHIFT (1) 236 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF (1 << 7) 237 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT (7) 238 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI (1 << 8) 239 #define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT (8) 240 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR (1 << 9) 241 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR_SHIFT (9) 242 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN (1 << 10) 243 #define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT (10) 244 #define ACPU_SC_VD_CTRL_TUNE_EN_INT (1 << 11) 245 #define ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT (11) 246 #define ACPU_SC_VD_CTRL_SHIFT_TABLE0 (1 << 12) 247 #define ACPU_SC_VD_CTRL_SHIFT_TABLE0_MASK (0xf << 12) 248 #define ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT (12) 249 #define ACPU_SC_VD_CTRL_SHIFT_TABLE1 (1 << 16) 250 #define ACPU_SC_VD_CTRL_SHIFT_TABLE1_MASK (0xf << 16) 251 #define ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT (16) 252 #define ACPU_SC_VD_CTRL_SHIFT_TABLE2 (1 << 20) 253 #define ACPU_SC_VD_CTRL_SHIFT_TABLE2_MASK (0xf << 20) 254 #define ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT (20) 255 #define ACPU_SC_VD_CTRL_SHIFT_TABLE3 (1 << 24) 256 #define ACPU_SC_VD_CTRL_SHIFT_TABLE3_MASK (0xf << 24) 257 #define ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT (24) 258 #define ACPU_SC_VD_CTRL_FORCE_CLK_EN (1 << 28) 259 #define ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT (28) 260 #define ACPU_SC_VD_CTRL_DIV_EN_DIF (1 << 29) 261 #define ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT (29) 262 263 #define ACPU_SC_VD_SHIFT_TABLE_TUNE_VAL \ 264 ((0x1 << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \ 265 (0x3 << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \ 266 (0x5 << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \ 267 (0x6 << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \ 268 (0x7 << ACPU_SC_VD_CTRL_TUNE_SHIFT)) 269 270 #define ACPU_SC_VD_SHIFT_TABLE_TUNE_MASK \ 271 ((0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \ 272 (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \ 273 (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \ 274 (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \ 275 (0x3F << ACPU_SC_VD_CTRL_TUNE_SHIFT)) 276 277 #define ACPU_SC_VD_HPM_CTRL_OSC_DIV (1 << 0) 278 #define ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT (0) 279 #define ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK (0x000000FF) 280 #define ACPU_SC_VD_HPM_CTRL_DLY_EXP (1 << 8) 281 #define ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT (8) 282 #define ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK (0x001FFF00) 283 284 #define HPM_OSC_DIV_VAL \ 285 (0x56 << ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT) 286 #define HPM_OSC_DIV_MASK \ 287 (ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK) 288 289 #define HPM_DLY_EXP_VAL \ 290 (0xC7A << ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT) 291 #define HPM_DLY_EXP_MASK \ 292 (ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK) 293 294 #define ACPU_SC_VD_EN_ASIC_VAL \ 295 ((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ 296 (0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ 297 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ 298 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ 299 (0X0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ 300 (0X0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ 301 (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) 302 303 #define ACPU_SC_VD_EN_SFT_VAL \ 304 ((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ 305 (0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ 306 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ 307 (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ 308 (0x0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ 309 (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ 310 (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) 311 312 #define ACPU_SC_VD_EN_MASK \ 313 ((0x1 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ 314 (0x1 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ 315 (0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ 316 (0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ 317 (0x1 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ 318 (0x1 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ 319 (0x1 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) 320 321 #endif /* __HI6220_REGS_ACPU_H__ */ 322
