/external/pcre/dist2/src/sljit/ |
sljitNativePPC_64.c | 52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); 70 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 87 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 93 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 103 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); 220 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); 234 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)));
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sljitNativePPC_32.c | 32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); 101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); 114 FAIL_IF(push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)));
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sljitNativeARM_64.c | 67 #define ADDI 0x91000000 565 return push_inst(compiler, ((op == SLJIT_ADD ? ADDI : SUBI) ^ inv_bits) | RD(dst) | RN(reg)); 569 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | (imm << 10)); 578 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22)); 585 FAIL_IF(push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22))); 586 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(dst) | ((imm & 0xfff) << 10)); 813 return push_inst(compiler, ADDI | RD(dst) | RN(reg) | (value << 10)); 815 return push_inst(compiler, ADDI | (1 << 22) | RD(dst) | RN(reg) | (value >> 2)); 931 FAIL_IF(push_inst(compiler, ADDI | RD(other_r) | RN(other_r) | ((argw & 0xfff) << 10))); 933 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(other_r) | RN(other_r) | ((argw >> 12) << 10))) [all...] |
sljitNativePPC_common.c | 139 #define ADDI (HI(14)) 611 FAIL_IF(push_inst(compiler, ADDI | D(TMP_ZERO) | A(0) | 0)); 665 FAIL_IF(push_inst(compiler, ADDI | D(SLJIT_SP) | A(SLJIT_SP) | IMM(compiler->local_size))); 941 FAIL_IF(push_inst(compiler, ADDI | D(TMP_REG3) | A(TMP_REG3) | (imm & 0x3))); \ [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 83 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 290 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 335 /// addi R0, SP, \#frameSize ; get the address of the previous frame 337 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 367 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 382 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 431 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 436 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 612 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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PPCFrameLowering.cpp | 585 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 600 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 665 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; [all...] |
PPCInstrInfo.cpp | 453 // R0 = ADDI FI# 457 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 582 // R0 = ADDI FI# 586 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
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PPCISelDAGToDAG.cpp | 671 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, 827 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; [all...] |
/toolchain/binutils/binutils-2.25/include/opcode/ |
nios2r1.h | 265 #define MATCH_R1_ADDI MATCH_R1_OP (ADDI) 393 #define MATCH_R1_MOVI MATCH_R1_OP (ADDI) | SET_IW_I_A (0) 457 #define MATCH_R1_SUBI MATCH_R1_OP (ADDI)
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/external/valgrind/none/tests/mips64/ |
arithmetic_instruction.c | 6 ADD=0, ADDI, ADDIU, ADDU, 35 case ADDI: 39 TEST2("addi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 40 TEST2("addi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 41 TEST2("addi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 42 TEST2("addi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 343 /// addi R0, SP, \#frameSize ; get the address of the previous frame 345 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 378 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 386 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 451 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) [all...] |
PPCAsmPrinter.cpp | 249 // addi vs add, etc. [all...] |
PPCFastISel.cpp | 414 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will [all...] |
PPCFrameLowering.cpp | [all...] |
PPCISelDAGToDAG.cpp | 460 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; [all...] |
/external/v8/src/mips/ |
constants-mips.h | 352 ADDI = ((1U << 3) + 0) << kOpcodeShift, 403 POP10 = ADDI, // beqzalc, bovc, beqc 906 OpcodeToBitNumber(BGTZ) | OpcodeToBitNumber(ADDI) | [all...] |
assembler-mips.cc | [all...] |
/external/v8/src/mips64/ |
constants-mips64.h | 323 ADDI = ((1U << 3) + 0) << kOpcodeShift, 386 POP10 = ADDI, // beqzalc, bovc, beqc 938 OpcodeToBitNumber(BGTZ) | OpcodeToBitNumber(ADDI) | [all...] |
assembler-mips64.cc | [all...] |
/prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
plan9.go | 155 ADDI: "ADD",
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/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/ |
plan9.go | 155 ADDI: "ADD",
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
MBlazeDisassembler.cpp | 43 MBlaze::ADDI, MBlaze::RSUBI, MBlaze::ADDIC, MBlaze::RSUBIC, //08,09,0A,0B
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/external/v8/src/ppc/ |
assembler-ppc.cc | 304 return ((instr & kOpcodeMask) == ADDI) && GetRA(instr).is(r0); 880 addi(dst, src, Operand(-(imm.imm_))); 965 void Assembler::addi(Register dst, Register src, const Operand& imm) { function in class:v8::internal::Assembler 967 d_form(ADDI, dst, src, imm.imm_, true); 1126 d_form(ADDI, dst, r0, imm.imm_, true); [all...] |
/toolchain/binutils/binutils-2.25/bfd/ |
elf32-nds32.c | [all...] |
/external/llvm/lib/Target/PowerPC/AsmParser/ |
PPCAsmParser.cpp | 888 TmpInst.setOpcode(PPC::ADDI); [all...] |