| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 115 {{vc, r8, r11, ASR, 13}, false, al, "vc r8 r11 ASR 13", "vc_r8_r11_ASR_13"},
116 {{al, r9, r12, ASR, 1}, false, al, "al r9 r12 ASR 1", "al_r9_r12_ASR_1"},
117 {{vs, r10, r3, ASR, 31}, false, al, "vs r10 r3 ASR 31", "vs_r10_r3_ASR_31"},
118 {{pl, r2, r11, ASR, 14}, false, al, "pl r2 r11 ASR 14", "pl_r2_r11_ASR_14"},
125 {{vc, r6, r2, ASR, 9}, false, al, "vc r6 r2 ASR 9", "vc_r6_r2_ASR_9"}
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc | 101 {{eq, r7, r2, ASR, 14}, true, eq, "eq r7 r2 ASR 14", "eq_r7_r2_ASR_14"},
104 {{ge, r5, r0, ASR, 23}, true, ge, "ge r5 r0 ASR 23", "ge_r5_r0_ASR_23"},
108 {{pl, r6, r1, ASR, 12}, true, pl, "pl r6 r1 ASR 12", "pl_r6_r1_ASR_12"},
109 {{hi, r7, r1, ASR, 30}, true, hi, "hi r7 r1 ASR 30", "hi_r7_r1_ASR_30"},
110 {{mi, r7, r6, ASR, 20}, true, mi, "mi r7 r6 ASR 20", "mi_r7_r6_ASR_20"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 116 const TestData kTests[] = {{{al, r11, r13, r10, ASR, 9},
119 "al r11 r13 r10 ASR 9",
121 {{al, r7, r5, r2, ASR, 2},
124 "al r7 r5 r2 ASR 2",
156 {{al, r10, r12, r4, ASR, 2},
159 "al r10 r12 r4 ASR 2",
166 {{al, r12, r11, r4, ASR, 7},
169 "al r12 r11 r4 ASR 7",
171 {{al, r9, r4, r8, ASR, 27},
174 "al r9 r4 r8 ASR 27"
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 116 const TestData kTests[] = {{{eq, r13, r6, r7, ASR, 5},
119 "eq r13 r6 r7 ASR 5",
121 {{mi, r8, r11, r8, ASR, 32},
124 "mi r8 r11 r8 ASR 32",
126 {{hi, r2, r3, r10, ASR, 18},
129 "hi r2 r3 r10 ASR 18",
136 {{cc, r8, r9, r2, ASR, 3},
139 "cc r8 r9 r2 ASR 3",
146 {{pl, r8, r6, r1, ASR, 31},
149 "pl r8 r6 r1 ASR 31"
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 105 {{al, r0, r3, ASR, 30}, false, al, "al r0 r3 ASR 30", "al_r0_r3_ASR_30"},
106 {{al, r10, r5, ASR, 31}, false, al, "al r10 r5 ASR 31", "al_r10_r5_ASR_31"},
107 {{al, r12, r9, ASR, 16}, false, al, "al r12 r9 ASR 16", "al_r12_r9_ASR_16"},
108 {{al, r5, r3, ASR, 31}, false, al, "al r5 r3 ASR 31", "al_r5_r3_ASR_31"},
109 {{al, r10, r8, ASR, 10}, false, al, "al r10 r8 ASR 10", "al_r10_r8_ASR_10"}
[all...] |
| test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 335 {{al, r1, r0, plus, r5, ASR, 24, Offset},
336 "al r1 r0 plus r5 ASR 24 Offset",
345 {{al, r12, r10, plus, r0, ASR, 16, Offset},
346 "al r12 r10 plus r0 ASR 16 Offset",
350 {{al, r4, r10, plus, r9, ASR, 19, Offset},
351 "al r4 r10 plus r9 ASR 19 Offset",
365 {{al, r1, r4, plus, r9, ASR, 25, Offset},
366 "al r1 r4 plus r9 ASR 25 Offset",
380 {{al, r0, r10, plus, r14, ASR, 11, Offset},
381 "al r0 r10 plus r14 ASR 11 Offset"
[all...] |
| test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 617 {{al, r0, r14, minus, r1, ASR, 1, Offset},
620 "al r0 r14 minus r1 ASR 1 Offset",
622 {{al, r0, r4, plus, r8, ASR, 4, Offset},
625 "al r0 r4 plus r8 ASR 4 Offset",
627 {{al, r0, r9, minus, r1, ASR, 26, Offset},
630 "al r0 r9 minus r1 ASR 26 Offset",
637 {{al, r0, r0, plus, r13, ASR, 13, Offset},
640 "al r0 r0 plus r13 ASR 13 Offset",
642 {{al, r0, r9, minus, r7, ASR, 23, Offset},
645 "al r0 r9 minus r7 ASR 23 Offset"
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 98 {{al, r11, r2, ASR, r10},
101 "al r11 r2 ASR r10",
103 {{al, r7, r8, ASR, r12}, false, al, "al r7 r8 ASR r12", "al_r7_r8_ASR_r12"},
104 {{al, r10, r8, ASR, r4}, false, al, "al r10 r8 ASR r4", "al_r10_r8_ASR_r4"},
110 {{al, r13, r4, ASR, r5}, false, al, "al r13 r4 ASR r5", "al_r13_r4_ASR_r5"},
112 {{al, r6, r11, ASR, r8}, false, al, "al r6 r11 ASR r8", "al_r6_r11_ASR_r8"}
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc | 103 {{le, r6, r6, ASR, r6}, true, le, "le r6 r6 ASR r6", "le_r6_r6_ASR_r6"},
105 {{le, r3, r3, ASR, r6}, true, le, "le r3 r3 ASR r6", "le_r3_r3_ASR_r6"},
107 {{pl, r3, r3, ASR, r2}, true, pl, "pl r3 r3 ASR r2", "pl_r3_r3_ASR_r2"},
110 {{cs, r0, r0, ASR, r6}, true, cs, "cs r0 r0 ASR r6", "cs_r0_r0_ASR_r6"},
114 {{pl, r2, r2, ASR, r7}, true, pl, "pl r2 r2 ASR r7", "pl_r2_r2_ASR_r7"}
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc | 112 {{al, r0, r0, ASR, r0}, false, al, "al r0 r0 ASR r0", "al_r0_r0_ASR_r0"},
113 {{al, r0, r0, ASR, r1}, false, al, "al r0 r0 ASR r1", "al_r0_r0_ASR_r1"},
114 {{al, r0, r0, ASR, r2}, false, al, "al r0 r0 ASR r2", "al_r0_r0_ASR_r2"},
115 {{al, r0, r0, ASR, r3}, false, al, "al r0 r0 ASR r3", "al_r0_r0_ASR_r3"},
116 {{al, r0, r0, ASR, r4}, false, al, "al r0 r0 ASR r4", "al_r0_r0_ASR_r4"}
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 146 {{mi, r12, r3, r13, ASR, r3},
149 "mi r12 r3 r13 ASR r3",
166 {{vc, r0, r5, r14, ASR, r12},
169 "vc r0 r5 r14 ASR r12",
176 {{le, r14, r6, r7, ASR, r1},
179 "le r14 r6 r7 ASR r1",
241 {{cs, r12, r3, r3, ASR, r2},
244 "cs r12 r3 r3 ASR r2",
251 {{vs, r9, r10, r2, ASR, r9},
254 "vs r9 r10 r2 ASR r9"
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-a32.cc | 115 {{hi, r9, r8, ASR, r10}, false, al, "hi r9 r8 ASR r10", "hi_r9_r8_ASR_r10"},
118 {{vc, r4, r6, ASR, r11}, false, al, "vc r4 r6 ASR r11", "vc_r4_r6_ASR_r11"},
150 {{lt, r7, r12, ASR, r7}, false, al, "lt r7 r12 ASR r7", "lt_r7_r12_ASR_r7"},
157 {{lt, r5, r0, ASR, r2}, false, al, "lt r5 r0 ASR r2", "lt_r5_r0_ASR_r2"},
166 {{le, r7, r1, ASR, r0}, false, al, "le r7 r1 ASR r0", "le_r7_r1_ASR_r0"}
[all...] |
| /external/aac/libSBRdec/src/arm/ |
| env_calc_arm.cpp | 118 MOVS r3, r3, ASR #1
126 EOR r4, r4, r4, ASR #31
127 EOR r5, r5, r5, ASR #31
134 EOR r4, r4, r4, ASR #31
135 EOR r5, r5, r5, ASR #31
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| scale_sig_opt.s | 46 TEQ r5, r12, ASR r10
47 EORNE r12, r8, r5, ASR #31
50 MOV r12, r11, ASR #16
59 MOV r5, r6, ASR r7 @L_tmp >>= exp
61 MOV r12, r11, ASR #16
|
| cor_h_vec_opt.s | 69 MOV r5, r9, ASR #16
70 MOV r6, r10, ASR #16
77 MOV r5, r12, ASR #15
78 MOV r6, r14, ASR #15
116 MOV r5, r9, ASR #16
117 MOV r6, r10, ASR #16
124 MOV r5, r12, ASR #15
125 MOV r6, r14, ASR #15
|
| Deemph_32_opt.s | 45 MOV r8, r5, ASR #1 @fac = mu >> 1
55 MOV r14, r10, ASR #16 @y[0] = round(L_tmp)
66 MOV r14, r10, ASR #16 @y[1] = round(L_tmp)
81 MOV r14, r10, ASR #16
93 MOV r14, r10, ASR #16
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| addthumb2err.s | 11 add sp, sp, r0, ASR #3
16 adds sp, sp, r0, ASR #3
21 sub sp, sp, r0, ASR #3
26 subs sp, sp, r0, ASR #3
|
| addthumb2err.l | 4 [^:]*:11: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ASR#3'
9 [^:]*:16: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ASR#3'
14 [^:]*:21: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ASR#3'
19 [^:]*:26: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ASR#3'
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_TransformResidual4x4_s.s | 185 PKHTB trRow10,in10,in00,ASR #16 ;// [5 4] = [f5:f1]
195 PKHTB trRow30,in12,in02,ASR #16 ;// [13 12] = [7 3]
205 PKHTB trRow12,in30,in20,ASR #16 ;// [7 6] = [f13:f9]
216 PKHTB trRow32,in32,in22,ASR #16 ;// [15 14] = [15 11]
265 PKHTB trCol10,rowOp10,rowOp00,ASR #16 ;// [5 4] = [f5:f1]
275 PKHTB trCol30,rowOp12,rowOp02,ASR #16 ;// [13 12] = [7 3]
285 PKHTB trCol12,rowOp30,rowOp20,ASR #16 ;// [7 6] = [f13:f9]
296 PKHTB trCol32,rowOp32,rowOp22,ASR #16 ;// [15 14] = [15 11]
356 AND colOp00, mask, colOp00, ASR #6
357 AND colOp02, mask, colOp02, ASR #
[all...] |
| omxVCM4P10_TransformDequantLumaDCFromPair_s.s | 195 PKHTB trRow10,in10,in00,ASR #16 ;// [5 4] = [f5:f1]
205 PKHTB trRow30,in12,in02,ASR #16 ;// [13 12] = [7 3]
215 PKHTB trRow12,in30,in20,ASR #16 ;// [7 6] = [f13:f9]
226 PKHTB trRow32,in32,in22,ASR #16 ;// [15 14] = [15 11]
272 PKHTB trCol10,rowOp10,rowOp00,ASR #16 ;// [5 4] = [f5:f1]
282 PKHTB trCol30,rowOp12,rowOp02,ASR #16 ;// [13 12] = [7 3]
292 PKHTB trCol12,rowOp30,rowOp20,ASR #16 ;// [7 6] = [f13:f9]
303 PKHTB trCol32,rowOp32,rowOp22,ASR #16 ;// [15 14] = [15 11]
370 ASR temp1, temp1, #2 ;// Temp1 = Temp1 >> 2
371 ASR temp3, temp3, #2 ;// Temp3 = Temp3 >>
[all...] |
| /external/tremolo/Tremolo/ |
| mdctLARM.s | 63 MOV r5, r5, ASR #9 @ r5 = (*--r)>>9
64 MOV r6, r6, ASR #9 @ r6 = (*--r)>>9
65 MOV r7, r7, ASR #9 @ r7 = (*--r)>>9
66 MOV r12,r12,ASR #9 @ r12= (*--r)>>9
68 MOV r14,r12,ASR #15
69 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
70 EORNE r12,r4, r14,ASR #31
73 MOV r14,r7, ASR #15
74 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
75 EORNE r7, r4, r14,ASR #3
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| cor_h_vec_neon.s | 70 MOV r5, r9, ASR #16
71 MOV r6, r10, ASR #16
78 MOV r5, r12, ASR #15
79 MOV r6, r14, ASR #15
117 MOV r5, r9, ASR #16
118 MOV r6, r10, ASR #16
125 MOV r5, r12, ASR #15
126 MOV r6, r14, ASR #15
|
| Deemph_32_neon.s | 45 MOV r8, r5, ASR #1 @fac = mu >> 1
55 MOV r14, r10, ASR #16 @y[0] = round(L_tmp)
66 MOV r14, r10, ASR #16 @y[1] = round(L_tmp)
81 MOV r14, r10, ASR #16
93 MOV r14, r10, ASR #16
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| vector2.s | 22 //Dreg = VIT_MAX ( Dreg , Dreg ) (ASR) ; /* shift history bits right (b) */
25 //Dreg_lo = VIT_MAX ( Dreg ) (ASR) ; /* shift history bits right (b) */
27 r7 = vit_max (r1, r0) (asr) ; /* shift right, dual operation */
30 r3 = vit_max (r4, r5) (asr) ; /* shift right, dual operation */
32 r1 = vit_max (r2, r3) (asr) ; /* shift right, dual operation */
34 r7 = vit_max (r0, r1) (asr) ; /* shift right, dual operation */
36 r5 = vit_max (r6, r7) (asr) ; /* shift right, dual operation */
40 r3.l = vit_max (r1)(asr) ; /* shift right, single operation */
43 r2.l = vit_max (r3)(asr) ; /* shift right, single operation */
45 r6.l = vit_max (r7)(asr) ; /* shift right, single operation *
[all...] |
| bit.d | 34 2a: 08 c6 08 00 BITMUX \(R1, R0, A0\) \(ASR\);
35 2e: 08 c6 13 00 BITMUX \(R2, R3, A0\) \(ASR\);
|
