1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // ----------------------------------------------------------------------------- 29 // This file is auto generated from the 30 // test/aarch32/config/template-assembler-aarch32.cc.in template file using 31 // tools/generate_tests.py. 32 // 33 // PLEASE DO NOT EDIT. 34 // ----------------------------------------------------------------------------- 35 36 37 #include "test-runner.h" 38 39 #include "test-utils.h" 40 #include "test-utils-aarch32.h" 41 42 #include "aarch32/assembler-aarch32.h" 43 #include "aarch32/macro-assembler-aarch32.h" 44 45 #define BUF_SIZE (4096) 46 47 namespace vixl { 48 namespace aarch32 { 49 50 // List of instruction mnemonics. 51 #define FOREACH_INSTRUCTION(M) \ 52 M(cmn) \ 53 M(cmp) \ 54 M(mov) \ 55 M(movs) \ 56 M(mvn) \ 57 M(mvns) \ 58 M(teq) \ 59 M(tst) 60 61 62 // The following definitions are defined again in each generated test, therefore 63 // we need to place them in an anomymous namespace. It expresses that they are 64 // local to this file only, and the compiler is not allowed to share these types 65 // across test files during template instantiation. Specifically, `Operands` has 66 // various layouts across generated tests so it absolutely cannot be shared. 67 68 #ifdef VIXL_INCLUDE_TARGET_A32 69 namespace { 70 71 // Values to be passed to the assembler to produce the instruction under test. 72 struct Operands { 73 Condition cond; 74 Register rd; 75 Register rn; 76 ShiftType shift; 77 uint32_t amount; 78 }; 79 80 // This structure contains all data needed to test one specific 81 // instruction. 82 struct TestData { 83 // The `operands` field represents what to pass to the assembler to 84 // produce the instruction. 85 Operands operands; 86 // True if we need to generate an IT instruction for this test to be valid. 87 bool in_it_block; 88 // The condition to give the IT instruction, this will be set to "al" by 89 // default. 90 Condition it_condition; 91 // Description of the operands, used for error reporting. 92 const char* operands_description; 93 // Unique identifier, used for generating traces. 94 const char* identifier; 95 }; 96 97 struct TestResult { 98 size_t size; 99 const byte* encoding; 100 }; 101 102 // Each element of this array produce one instruction encoding. 103 const TestData kTests[] = { 104 {{eq, r10, r13, LSR, 23}, 105 false, 106 al, 107 "eq r10 r13 LSR 23", 108 "eq_r10_r13_LSR_23"}, 109 {{eq, r12, r13, LSR, 13}, 110 false, 111 al, 112 "eq r12 r13 LSR 13", 113 "eq_r12_r13_LSR_13"}, 114 {{pl, r13, r5, LSR, 12}, false, al, "pl r13 r5 LSR 12", "pl_r13_r5_LSR_12"}, 115 {{vc, r8, r11, ASR, 13}, false, al, "vc r8 r11 ASR 13", "vc_r8_r11_ASR_13"}, 116 {{al, r9, r12, ASR, 1}, false, al, "al r9 r12 ASR 1", "al_r9_r12_ASR_1"}, 117 {{vs, r10, r3, ASR, 31}, false, al, "vs r10 r3 ASR 31", "vs_r10_r3_ASR_31"}, 118 {{pl, r2, r11, ASR, 14}, false, al, "pl r2 r11 ASR 14", "pl_r2_r11_ASR_14"}, 119 {{al, r11, r10, LSR, 27}, 120 false, 121 al, 122 "al r11 r10 LSR 27", 123 "al_r11_r10_LSR_27"}, 124 {{le, r10, r8, LSR, 19}, false, al, "le r10 r8 LSR 19", "le_r10_r8_LSR_19"}, 125 {{vc, r6, r2, ASR, 9}, false, al, "vc r6 r2 ASR 9", "vc_r6_r2_ASR_9"}, 126 {{al, r10, r10, ASR, 7}, false, al, "al r10 r10 ASR 7", "al_r10_r10_ASR_7"}, 127 {{pl, r4, r6, LSR, 3}, false, al, "pl r4 r6 LSR 3", "pl_r4_r6_LSR_3"}, 128 {{vs, r0, r6, ASR, 19}, false, al, "vs r0 r6 ASR 19", "vs_r0_r6_ASR_19"}, 129 {{vc, r5, r8, LSR, 5}, false, al, "vc r5 r8 LSR 5", "vc_r5_r8_LSR_5"}, 130 {{ne, r2, r9, LSR, 26}, false, al, "ne r2 r9 LSR 26", "ne_r2_r9_LSR_26"}, 131 {{lt, r14, r0, LSR, 12}, false, al, "lt r14 r0 LSR 12", "lt_r14_r0_LSR_12"}, 132 {{hi, r8, r1, ASR, 15}, false, al, "hi r8 r1 ASR 15", "hi_r8_r1_ASR_15"}, 133 {{vc, r9, r13, LSR, 16}, false, al, "vc r9 r13 LSR 16", "vc_r9_r13_LSR_16"}, 134 {{lt, r4, r11, LSR, 26}, false, al, "lt r4 r11 LSR 26", "lt_r4_r11_LSR_26"}, 135 {{vs, r2, r2, ASR, 7}, false, al, "vs r2 r2 ASR 7", "vs_r2_r2_ASR_7"}, 136 {{pl, r8, r8, ASR, 4}, false, al, "pl r8 r8 ASR 4", "pl_r8_r8_ASR_4"}, 137 {{al, r10, r11, ASR, 31}, 138 false, 139 al, 140 "al r10 r11 ASR 31", 141 "al_r10_r11_ASR_31"}, 142 {{cs, r14, r11, ASR, 3}, false, al, "cs r14 r11 ASR 3", "cs_r14_r11_ASR_3"}, 143 {{vs, r0, r11, LSR, 30}, false, al, "vs r0 r11 LSR 30", "vs_r0_r11_LSR_30"}, 144 {{pl, r6, r13, LSR, 18}, false, al, "pl r6 r13 LSR 18", "pl_r6_r13_LSR_18"}, 145 {{pl, r14, r2, ASR, 32}, false, al, "pl r14 r2 ASR 32", "pl_r14_r2_ASR_32"}, 146 {{ls, r11, r6, ASR, 23}, false, al, "ls r11 r6 ASR 23", "ls_r11_r6_ASR_23"}, 147 {{cc, r11, r2, ASR, 2}, false, al, "cc r11 r2 ASR 2", "cc_r11_r2_ASR_2"}, 148 {{le, r12, r5, ASR, 27}, false, al, "le r12 r5 ASR 27", "le_r12_r5_ASR_27"}, 149 {{ge, r2, r5, ASR, 31}, false, al, "ge r2 r5 ASR 31", "ge_r2_r5_ASR_31"}, 150 {{le, r0, r5, ASR, 7}, false, al, "le r0 r5 ASR 7", "le_r0_r5_ASR_7"}, 151 {{ge, r1, r10, ASR, 28}, false, al, "ge r1 r10 ASR 28", "ge_r1_r10_ASR_28"}, 152 {{vc, r6, r0, LSR, 13}, false, al, "vc r6 r0 LSR 13", "vc_r6_r0_LSR_13"}, 153 {{eq, r13, r2, ASR, 4}, false, al, "eq r13 r2 ASR 4", "eq_r13_r2_ASR_4"}, 154 {{pl, r10, r12, ASR, 20}, 155 false, 156 al, 157 "pl r10 r12 ASR 20", 158 "pl_r10_r12_ASR_20"}, 159 {{gt, r2, r0, ASR, 32}, false, al, "gt r2 r0 ASR 32", "gt_r2_r0_ASR_32"}, 160 {{hi, r10, r5, LSR, 9}, false, al, "hi r10 r5 LSR 9", "hi_r10_r5_LSR_9"}, 161 {{ge, r12, r1, ASR, 27}, false, al, "ge r12 r1 ASR 27", "ge_r12_r1_ASR_27"}, 162 {{eq, r5, r5, LSR, 17}, false, al, "eq r5 r5 LSR 17", "eq_r5_r5_LSR_17"}, 163 {{pl, r10, r0, LSR, 2}, false, al, "pl r10 r0 LSR 2", "pl_r10_r0_LSR_2"}, 164 {{mi, r6, r3, ASR, 24}, false, al, "mi r6 r3 ASR 24", "mi_r6_r3_ASR_24"}, 165 {{eq, r1, r7, LSR, 1}, false, al, "eq r1 r7 LSR 1", "eq_r1_r7_LSR_1"}, 166 {{eq, r13, r14, ASR, 24}, 167 false, 168 al, 169 "eq r13 r14 ASR 24", 170 "eq_r13_r14_ASR_24"}, 171 {{pl, r0, r5, ASR, 12}, false, al, "pl r0 r5 ASR 12", "pl_r0_r5_ASR_12"}, 172 {{gt, r2, r14, ASR, 17}, false, al, "gt r2 r14 ASR 17", "gt_r2_r14_ASR_17"}, 173 {{cs, r14, r0, LSR, 15}, false, al, "cs r14 r0 LSR 15", "cs_r14_r0_LSR_15"}, 174 {{ls, r14, r3, LSR, 18}, false, al, "ls r14 r3 LSR 18", "ls_r14_r3_LSR_18"}, 175 {{le, r0, r13, ASR, 29}, false, al, "le r0 r13 ASR 29", "le_r0_r13_ASR_29"}, 176 {{ge, r5, r14, ASR, 17}, false, al, "ge r5 r14 ASR 17", "ge_r5_r14_ASR_17"}, 177 {{vc, r7, r1, ASR, 12}, false, al, "vc r7 r1 ASR 12", "vc_r7_r1_ASR_12"}, 178 {{ne, r1, r5, ASR, 23}, false, al, "ne r1 r5 ASR 23", "ne_r1_r5_ASR_23"}, 179 {{ls, r5, r2, LSR, 15}, false, al, "ls r5 r2 LSR 15", "ls_r5_r2_LSR_15"}, 180 {{le, r12, r7, ASR, 18}, false, al, "le r12 r7 ASR 18", "le_r12_r7_ASR_18"}, 181 {{hi, r11, r8, ASR, 8}, false, al, "hi r11 r8 ASR 8", "hi_r11_r8_ASR_8"}, 182 {{pl, r9, r0, LSR, 16}, false, al, "pl r9 r0 LSR 16", "pl_r9_r0_LSR_16"}, 183 {{ls, r13, r4, LSR, 18}, false, al, "ls r13 r4 LSR 18", "ls_r13_r4_LSR_18"}, 184 {{ls, r4, r6, ASR, 7}, false, al, "ls r4 r6 ASR 7", "ls_r4_r6_ASR_7"}, 185 {{gt, r1, r7, LSR, 1}, false, al, "gt r1 r7 LSR 1", "gt_r1_r7_LSR_1"}, 186 {{eq, r7, r11, LSR, 24}, false, al, "eq r7 r11 LSR 24", "eq_r7_r11_LSR_24"}, 187 {{al, r8, r10, LSR, 7}, false, al, "al r8 r10 LSR 7", "al_r8_r10_LSR_7"}, 188 {{pl, r8, r14, LSR, 32}, false, al, "pl r8 r14 LSR 32", "pl_r8_r14_LSR_32"}, 189 {{ne, r12, r10, LSR, 9}, false, al, "ne r12 r10 LSR 9", "ne_r12_r10_LSR_9"}, 190 {{vc, r2, r4, LSR, 23}, false, al, "vc r2 r4 LSR 23", "vc_r2_r4_LSR_23"}, 191 {{ne, r1, r3, ASR, 22}, false, al, "ne r1 r3 ASR 22", "ne_r1_r3_ASR_22"}, 192 {{eq, r7, r1, ASR, 32}, false, al, "eq r7 r1 ASR 32", "eq_r7_r1_ASR_32"}, 193 {{ge, r7, r12, LSR, 29}, false, al, "ge r7 r12 LSR 29", "ge_r7_r12_LSR_29"}, 194 {{hi, r4, r6, LSR, 2}, false, al, "hi r4 r6 LSR 2", "hi_r4_r6_LSR_2"}, 195 {{hi, r12, r8, LSR, 3}, false, al, "hi r12 r8 LSR 3", "hi_r12_r8_LSR_3"}, 196 {{vs, r3, r9, ASR, 11}, false, al, "vs r3 r9 ASR 11", "vs_r3_r9_ASR_11"}, 197 {{cs, r4, r9, ASR, 2}, false, al, "cs r4 r9 ASR 2", "cs_r4_r9_ASR_2"}, 198 {{cs, r7, r6, ASR, 23}, false, al, "cs r7 r6 ASR 23", "cs_r7_r6_ASR_23"}, 199 {{lt, r5, r8, LSR, 17}, false, al, "lt r5 r8 LSR 17", "lt_r5_r8_LSR_17"}, 200 {{eq, r8, r2, LSR, 11}, false, al, "eq r8 r2 LSR 11", "eq_r8_r2_LSR_11"}, 201 {{ls, r12, r9, LSR, 5}, false, al, "ls r12 r9 LSR 5", "ls_r12_r9_LSR_5"}, 202 {{cc, r14, r14, ASR, 15}, 203 false, 204 al, 205 "cc r14 r14 ASR 15", 206 "cc_r14_r14_ASR_15"}, 207 {{mi, r2, r14, LSR, 10}, false, al, "mi r2 r14 LSR 10", "mi_r2_r14_LSR_10"}, 208 {{vs, r5, r11, ASR, 29}, false, al, "vs r5 r11 ASR 29", "vs_r5_r11_ASR_29"}, 209 {{gt, r12, r9, LSR, 27}, false, al, "gt r12 r9 LSR 27", "gt_r12_r9_LSR_27"}, 210 {{hi, r12, r5, LSR, 11}, false, al, "hi r12 r5 LSR 11", "hi_r12_r5_LSR_11"}, 211 {{cc, r12, r10, ASR, 10}, 212 false, 213 al, 214 "cc r12 r10 ASR 10", 215 "cc_r12_r10_ASR_10"}, 216 {{lt, r11, r1, LSR, 20}, false, al, "lt r11 r1 LSR 20", "lt_r11_r1_LSR_20"}, 217 {{lt, r0, r0, ASR, 25}, false, al, "lt r0 r0 ASR 25", "lt_r0_r0_ASR_25"}, 218 {{le, r10, r1, LSR, 19}, false, al, "le r10 r1 LSR 19", "le_r10_r1_LSR_19"}, 219 {{le, r5, r1, LSR, 28}, false, al, "le r5 r1 LSR 28", "le_r5_r1_LSR_28"}, 220 {{cs, r6, r11, LSR, 32}, false, al, "cs r6 r11 LSR 32", "cs_r6_r11_LSR_32"}, 221 {{vs, r10, r13, LSR, 8}, false, al, "vs r10 r13 LSR 8", "vs_r10_r13_LSR_8"}, 222 {{eq, r3, r4, ASR, 5}, false, al, "eq r3 r4 ASR 5", "eq_r3_r4_ASR_5"}, 223 {{pl, r3, r13, LSR, 17}, false, al, "pl r3 r13 LSR 17", "pl_r3_r13_LSR_17"}, 224 {{vs, r3, r6, ASR, 5}, false, al, "vs r3 r6 ASR 5", "vs_r3_r6_ASR_5"}, 225 {{al, r7, r8, ASR, 3}, false, al, "al r7 r8 ASR 3", "al_r7_r8_ASR_3"}, 226 {{hi, r9, r8, ASR, 16}, false, al, "hi r9 r8 ASR 16", "hi_r9_r8_ASR_16"}, 227 {{le, r12, r5, ASR, 16}, false, al, "le r12 r5 ASR 16", "le_r12_r5_ASR_16"}, 228 {{al, r12, r10, ASR, 8}, false, al, "al r12 r10 ASR 8", "al_r12_r10_ASR_8"}, 229 {{lt, r9, r9, LSR, 3}, false, al, "lt r9 r9 LSR 3", "lt_r9_r9_LSR_3"}, 230 {{ge, r2, r11, ASR, 26}, false, al, "ge r2 r11 ASR 26", "ge_r2_r11_ASR_26"}, 231 {{cs, r13, r12, ASR, 12}, 232 false, 233 al, 234 "cs r13 r12 ASR 12", 235 "cs_r13_r12_ASR_12"}, 236 {{hi, r14, r2, ASR, 9}, false, al, "hi r14 r2 ASR 9", "hi_r14_r2_ASR_9"}, 237 {{lt, r0, r3, ASR, 23}, false, al, "lt r0 r3 ASR 23", "lt_r0_r3_ASR_23"}, 238 {{eq, r6, r4, LSR, 16}, false, al, "eq r6 r4 LSR 16", "eq_r6_r4_LSR_16"}, 239 {{mi, r11, r8, LSR, 20}, false, al, "mi r11 r8 LSR 20", "mi_r11_r8_LSR_20"}, 240 {{vc, r0, r9, ASR, 23}, false, al, "vc r0 r9 ASR 23", "vc_r0_r9_ASR_23"}, 241 {{pl, r11, r0, LSR, 8}, false, al, "pl r11 r0 LSR 8", "pl_r11_r0_LSR_8"}, 242 {{pl, r14, r9, LSR, 11}, false, al, "pl r14 r9 LSR 11", "pl_r14_r9_LSR_11"}, 243 {{pl, r10, r12, LSR, 2}, false, al, "pl r10 r12 LSR 2", "pl_r10_r12_LSR_2"}, 244 {{mi, r0, r9, ASR, 23}, false, al, "mi r0 r9 ASR 23", "mi_r0_r9_ASR_23"}, 245 {{ge, r12, r0, ASR, 9}, false, al, "ge r12 r0 ASR 9", "ge_r12_r0_ASR_9"}, 246 {{eq, r4, r9, LSR, 1}, false, al, "eq r4 r9 LSR 1", "eq_r4_r9_LSR_1"}, 247 {{eq, r14, r11, ASR, 4}, false, al, "eq r14 r11 ASR 4", "eq_r14_r11_ASR_4"}, 248 {{ge, r1, r1, ASR, 23}, false, al, "ge r1 r1 ASR 23", "ge_r1_r1_ASR_23"}, 249 {{ge, r14, r2, LSR, 3}, false, al, "ge r14 r2 LSR 3", "ge_r14_r2_LSR_3"}, 250 {{pl, r1, r5, ASR, 16}, false, al, "pl r1 r5 ASR 16", "pl_r1_r5_ASR_16"}, 251 {{vc, r9, r14, ASR, 28}, false, al, "vc r9 r14 ASR 28", "vc_r9_r14_ASR_28"}, 252 {{cs, r6, r3, LSR, 9}, false, al, "cs r6 r3 LSR 9", "cs_r6_r3_LSR_9"}, 253 {{pl, r6, r12, ASR, 32}, false, al, "pl r6 r12 ASR 32", "pl_r6_r12_ASR_32"}, 254 {{ne, r4, r4, ASR, 32}, false, al, "ne r4 r4 ASR 32", "ne_r4_r4_ASR_32"}, 255 {{cs, r14, r6, ASR, 14}, false, al, "cs r14 r6 ASR 14", "cs_r14_r6_ASR_14"}, 256 {{al, r2, r5, LSR, 1}, false, al, "al r2 r5 LSR 1", "al_r2_r5_LSR_1"}, 257 {{ge, r0, r1, LSR, 20}, false, al, "ge r0 r1 LSR 20", "ge_r0_r1_LSR_20"}, 258 {{vs, r2, r5, LSR, 11}, false, al, "vs r2 r5 LSR 11", "vs_r2_r5_LSR_11"}, 259 {{vs, r1, r10, LSR, 17}, false, al, "vs r1 r10 LSR 17", "vs_r1_r10_LSR_17"}, 260 {{hi, r0, r2, LSR, 13}, false, al, "hi r0 r2 LSR 13", "hi_r0_r2_LSR_13"}, 261 {{hi, r11, r14, LSR, 9}, false, al, "hi r11 r14 LSR 9", "hi_r11_r14_LSR_9"}, 262 {{le, r11, r9, ASR, 3}, false, al, "le r11 r9 ASR 3", "le_r11_r9_ASR_3"}, 263 {{le, r14, r13, LSR, 9}, false, al, "le r14 r13 LSR 9", "le_r14_r13_LSR_9"}, 264 {{cc, r7, r4, ASR, 24}, false, al, "cc r7 r4 ASR 24", "cc_r7_r4_ASR_24"}, 265 {{lt, r1, r3, LSR, 17}, false, al, "lt r1 r3 LSR 17", "lt_r1_r3_LSR_17"}, 266 {{mi, r10, r12, LSR, 16}, 267 false, 268 al, 269 "mi r10 r12 LSR 16", 270 "mi_r10_r12_LSR_16"}, 271 {{vc, r7, r14, LSR, 11}, false, al, "vc r7 r14 LSR 11", "vc_r7_r14_LSR_11"}, 272 {{gt, r7, r3, ASR, 29}, false, al, "gt r7 r3 ASR 29", "gt_r7_r3_ASR_29"}, 273 {{mi, r7, r13, ASR, 27}, false, al, "mi r7 r13 ASR 27", "mi_r7_r13_ASR_27"}, 274 {{cs, r4, r10, ASR, 21}, false, al, "cs r4 r10 ASR 21", "cs_r4_r10_ASR_21"}, 275 {{cc, r8, r9, ASR, 16}, false, al, "cc r8 r9 ASR 16", "cc_r8_r9_ASR_16"}, 276 {{gt, r1, r1, LSR, 29}, false, al, "gt r1 r1 LSR 29", "gt_r1_r1_LSR_29"}, 277 {{lt, r11, r8, LSR, 8}, false, al, "lt r11 r8 LSR 8", "lt_r11_r8_LSR_8"}, 278 {{eq, r9, r3, ASR, 24}, false, al, "eq r9 r3 ASR 24", "eq_r9_r3_ASR_24"}, 279 {{mi, r0, r14, LSR, 13}, false, al, "mi r0 r14 LSR 13", "mi_r0_r14_LSR_13"}, 280 {{hi, r5, r9, LSR, 31}, false, al, "hi r5 r9 LSR 31", "hi_r5_r9_LSR_31"}, 281 {{vc, r8, r3, LSR, 25}, false, al, "vc r8 r3 LSR 25", "vc_r8_r3_LSR_25"}, 282 {{le, r6, r5, ASR, 28}, false, al, "le r6 r5 ASR 28", "le_r6_r5_ASR_28"}, 283 {{ne, r11, r6, ASR, 24}, false, al, "ne r11 r6 ASR 24", "ne_r11_r6_ASR_24"}, 284 {{vc, r11, r10, LSR, 9}, false, al, "vc r11 r10 LSR 9", "vc_r11_r10_LSR_9"}, 285 {{cc, r9, r4, LSR, 31}, false, al, "cc r9 r4 LSR 31", "cc_r9_r4_LSR_31"}, 286 {{vs, r14, r3, ASR, 32}, false, al, "vs r14 r3 ASR 32", "vs_r14_r3_ASR_32"}, 287 {{cs, r5, r3, ASR, 27}, false, al, "cs r5 r3 ASR 27", "cs_r5_r3_ASR_27"}, 288 {{gt, r2, r8, ASR, 18}, false, al, "gt r2 r8 ASR 18", "gt_r2_r8_ASR_18"}, 289 {{lt, r11, r7, LSR, 4}, false, al, "lt r11 r7 LSR 4", "lt_r11_r7_LSR_4"}, 290 {{eq, r11, r3, LSR, 17}, false, al, "eq r11 r3 LSR 17", "eq_r11_r3_LSR_17"}, 291 {{cc, r2, r12, LSR, 10}, false, al, "cc r2 r12 LSR 10", "cc_r2_r12_LSR_10"}, 292 {{ne, r10, r12, ASR, 31}, 293 false, 294 al, 295 "ne r10 r12 ASR 31", 296 "ne_r10_r12_ASR_31"}, 297 {{lt, r11, r5, LSR, 4}, false, al, "lt r11 r5 LSR 4", "lt_r11_r5_LSR_4"}, 298 {{gt, r3, r10, ASR, 3}, false, al, "gt r3 r10 ASR 3", "gt_r3_r10_ASR_3"}, 299 {{ge, r7, r0, ASR, 17}, false, al, "ge r7 r0 ASR 17", "ge_r7_r0_ASR_17"}, 300 {{hi, r7, r14, ASR, 23}, false, al, "hi r7 r14 ASR 23", "hi_r7_r14_ASR_23"}, 301 {{mi, r10, r14, LSR, 28}, 302 false, 303 al, 304 "mi r10 r14 LSR 28", 305 "mi_r10_r14_LSR_28"}, 306 {{al, r14, r11, LSR, 12}, 307 false, 308 al, 309 "al r14 r11 LSR 12", 310 "al_r14_r11_LSR_12"}, 311 {{cc, r13, r6, ASR, 23}, false, al, "cc r13 r6 ASR 23", "cc_r13_r6_ASR_23"}, 312 {{ge, r4, r0, ASR, 3}, false, al, "ge r4 r0 ASR 3", "ge_r4_r0_ASR_3"}, 313 {{vc, r8, r2, LSR, 16}, false, al, "vc r8 r2 LSR 16", "vc_r8_r2_LSR_16"}, 314 {{vc, r9, r8, ASR, 26}, false, al, "vc r9 r8 ASR 26", "vc_r9_r8_ASR_26"}, 315 {{pl, r3, r4, ASR, 16}, false, al, "pl r3 r4 ASR 16", "pl_r3_r4_ASR_16"}, 316 {{vc, r12, r13, ASR, 29}, 317 false, 318 al, 319 "vc r12 r13 ASR 29", 320 "vc_r12_r13_ASR_29"}, 321 {{hi, r0, r7, LSR, 13}, false, al, "hi r0 r7 LSR 13", "hi_r0_r7_LSR_13"}, 322 {{vc, r2, r2, ASR, 1}, false, al, "vc r2 r2 ASR 1", "vc_r2_r2_ASR_1"}, 323 {{eq, r13, r6, ASR, 2}, false, al, "eq r13 r6 ASR 2", "eq_r13_r6_ASR_2"}, 324 {{ge, r14, r3, LSR, 5}, false, al, "ge r14 r3 LSR 5", "ge_r14_r3_LSR_5"}, 325 {{cc, r2, r11, ASR, 19}, false, al, "cc r2 r11 ASR 19", "cc_r2_r11_ASR_19"}, 326 {{eq, r14, r6, LSR, 17}, false, al, "eq r14 r6 LSR 17", "eq_r14_r6_LSR_17"}, 327 {{mi, r11, r2, LSR, 1}, false, al, "mi r11 r2 LSR 1", "mi_r11_r2_LSR_1"}, 328 {{pl, r6, r14, ASR, 31}, false, al, "pl r6 r14 ASR 31", "pl_r6_r14_ASR_31"}, 329 {{le, r10, r11, LSR, 30}, 330 false, 331 al, 332 "le r10 r11 LSR 30", 333 "le_r10_r11_LSR_30"}, 334 {{lt, r4, r5, ASR, 30}, false, al, "lt r4 r5 ASR 30", "lt_r4_r5_ASR_30"}, 335 {{ge, r11, r0, LSR, 15}, false, al, "ge r11 r0 LSR 15", "ge_r11_r0_LSR_15"}, 336 {{cc, r0, r1, ASR, 14}, false, al, "cc r0 r1 ASR 14", "cc_r0_r1_ASR_14"}, 337 {{le, r10, r12, LSR, 30}, 338 false, 339 al, 340 "le r10 r12 LSR 30", 341 "le_r10_r12_LSR_30"}, 342 {{le, r8, r2, ASR, 11}, false, al, "le r8 r2 ASR 11", "le_r8_r2_ASR_11"}, 343 {{ls, r12, r7, ASR, 23}, false, al, "ls r12 r7 ASR 23", "ls_r12_r7_ASR_23"}, 344 {{hi, r14, r9, ASR, 31}, false, al, "hi r14 r9 ASR 31", "hi_r14_r9_ASR_31"}, 345 {{lt, r12, r4, LSR, 20}, false, al, "lt r12 r4 LSR 20", "lt_r12_r4_LSR_20"}, 346 {{lt, r6, r4, ASR, 12}, false, al, "lt r6 r4 ASR 12", "lt_r6_r4_ASR_12"}, 347 {{pl, r0, r0, ASR, 21}, false, al, "pl r0 r0 ASR 21", "pl_r0_r0_ASR_21"}, 348 {{ls, r2, r3, LSR, 9}, false, al, "ls r2 r3 LSR 9", "ls_r2_r3_LSR_9"}, 349 {{le, r4, r11, LSR, 22}, false, al, "le r4 r11 LSR 22", "le_r4_r11_LSR_22"}, 350 {{gt, r9, r6, LSR, 28}, false, al, "gt r9 r6 LSR 28", "gt_r9_r6_LSR_28"}, 351 {{lt, r7, r6, ASR, 25}, false, al, "lt r7 r6 ASR 25", "lt_r7_r6_ASR_25"}, 352 {{ne, r10, r3, LSR, 25}, false, al, "ne r10 r3 LSR 25", "ne_r10_r3_LSR_25"}, 353 {{hi, r14, r11, ASR, 16}, 354 false, 355 al, 356 "hi r14 r11 ASR 16", 357 "hi_r14_r11_ASR_16"}, 358 {{cc, r0, r8, ASR, 26}, false, al, "cc r0 r8 ASR 26", "cc_r0_r8_ASR_26"}, 359 {{pl, r5, r0, LSR, 29}, false, al, "pl r5 r0 LSR 29", "pl_r5_r0_LSR_29"}, 360 {{lt, r5, r6, ASR, 9}, false, al, "lt r5 r6 ASR 9", "lt_r5_r6_ASR_9"}, 361 {{vc, r11, r7, ASR, 20}, false, al, "vc r11 r7 ASR 20", "vc_r11_r7_ASR_20"}, 362 {{vc, r14, r13, ASR, 20}, 363 false, 364 al, 365 "vc r14 r13 ASR 20", 366 "vc_r14_r13_ASR_20"}, 367 {{le, r3, r0, ASR, 31}, false, al, "le r3 r0 ASR 31", "le_r3_r0_ASR_31"}, 368 {{eq, r5, r12, LSR, 18}, false, al, "eq r5 r12 LSR 18", "eq_r5_r12_LSR_18"}, 369 {{cs, r2, r14, ASR, 3}, false, al, "cs r2 r14 ASR 3", "cs_r2_r14_ASR_3"}, 370 {{ge, r1, r4, ASR, 15}, false, al, "ge r1 r4 ASR 15", "ge_r1_r4_ASR_15"}, 371 {{mi, r8, r5, ASR, 9}, false, al, "mi r8 r5 ASR 9", "mi_r8_r5_ASR_9"}, 372 {{vc, r7, r11, LSR, 9}, false, al, "vc r7 r11 LSR 9", "vc_r7_r11_LSR_9"}, 373 {{pl, r4, r7, ASR, 10}, false, al, "pl r4 r7 ASR 10", "pl_r4_r7_ASR_10"}, 374 {{hi, r4, r13, ASR, 32}, false, al, "hi r4 r13 ASR 32", "hi_r4_r13_ASR_32"}, 375 {{lt, r4, r10, ASR, 22}, false, al, "lt r4 r10 ASR 22", "lt_r4_r10_ASR_22"}, 376 {{ne, r2, r4, LSR, 23}, false, al, "ne r2 r4 LSR 23", "ne_r2_r4_LSR_23"}, 377 {{lt, r12, r12, ASR, 18}, 378 false, 379 al, 380 "lt r12 r12 ASR 18", 381 "lt_r12_r12_ASR_18"}, 382 {{lt, r6, r13, LSR, 28}, false, al, "lt r6 r13 LSR 28", "lt_r6_r13_LSR_28"}, 383 {{vc, r8, r8, ASR, 32}, false, al, "vc r8 r8 ASR 32", "vc_r8_r8_ASR_32"}, 384 {{vs, r4, r1, LSR, 24}, false, al, "vs r4 r1 LSR 24", "vs_r4_r1_LSR_24"}, 385 {{al, r7, r7, ASR, 24}, false, al, "al r7 r7 ASR 24", "al_r7_r7_ASR_24"}, 386 {{mi, r9, r2, LSR, 2}, false, al, "mi r9 r2 LSR 2", "mi_r9_r2_LSR_2"}, 387 {{lt, r4, r6, ASR, 5}, false, al, "lt r4 r6 ASR 5", "lt_r4_r6_ASR_5"}, 388 {{vs, r14, r11, LSR, 18}, 389 false, 390 al, 391 "vs r14 r11 LSR 18", 392 "vs_r14_r11_LSR_18"}, 393 {{cc, r9, r7, LSR, 12}, false, al, "cc r9 r7 LSR 12", "cc_r9_r7_LSR_12"}, 394 {{mi, r0, r6, LSR, 12}, false, al, "mi r0 r6 LSR 12", "mi_r0_r6_LSR_12"}, 395 {{vs, r5, r0, LSR, 11}, false, al, "vs r5 r0 LSR 11", "vs_r5_r0_LSR_11"}, 396 {{hi, r0, r14, LSR, 13}, false, al, "hi r0 r14 LSR 13", "hi_r0_r14_LSR_13"}, 397 {{vc, r1, r5, LSR, 30}, false, al, "vc r1 r5 LSR 30", "vc_r1_r5_LSR_30"}, 398 {{vc, r14, r7, LSR, 19}, false, al, "vc r14 r7 LSR 19", "vc_r14_r7_LSR_19"}, 399 {{eq, r2, r14, LSR, 28}, false, al, "eq r2 r14 LSR 28", "eq_r2_r14_LSR_28"}, 400 {{ls, r5, r1, LSR, 14}, false, al, "ls r5 r1 LSR 14", "ls_r5_r1_LSR_14"}, 401 {{mi, r6, r12, LSR, 14}, false, al, "mi r6 r12 LSR 14", "mi_r6_r12_LSR_14"}, 402 {{ne, r1, r0, LSR, 11}, false, al, "ne r1 r0 LSR 11", "ne_r1_r0_LSR_11"}, 403 {{al, r14, r12, LSR, 2}, false, al, "al r14 r12 LSR 2", "al_r14_r12_LSR_2"}, 404 {{eq, r10, r10, LSR, 20}, 405 false, 406 al, 407 "eq r10 r10 LSR 20", 408 "eq_r10_r10_LSR_20"}, 409 {{vc, r2, r14, ASR, 29}, false, al, "vc r2 r14 ASR 29", "vc_r2_r14_ASR_29"}, 410 {{vc, r3, r1, ASR, 22}, false, al, "vc r3 r1 ASR 22", "vc_r3_r1_ASR_22"}, 411 {{vs, r6, r5, ASR, 2}, false, al, "vs r6 r5 ASR 2", "vs_r6_r5_ASR_2"}, 412 {{gt, r2, r5, ASR, 19}, false, al, "gt r2 r5 ASR 19", "gt_r2_r5_ASR_19"}, 413 {{eq, r12, r13, LSR, 16}, 414 false, 415 al, 416 "eq r12 r13 LSR 16", 417 "eq_r12_r13_LSR_16"}, 418 {{ls, r7, r7, ASR, 14}, false, al, "ls r7 r7 ASR 14", "ls_r7_r7_ASR_14"}, 419 {{ge, r5, r7, ASR, 15}, false, al, "ge r5 r7 ASR 15", "ge_r5_r7_ASR_15"}, 420 {{al, r10, r1, ASR, 29}, false, al, "al r10 r1 ASR 29", "al_r10_r1_ASR_29"}, 421 {{pl, r4, r11, LSR, 14}, false, al, "pl r4 r11 LSR 14", "pl_r4_r11_LSR_14"}, 422 {{cc, r9, r13, LSR, 5}, false, al, "cc r9 r13 LSR 5", "cc_r9_r13_LSR_5"}, 423 {{ls, r10, r12, ASR, 13}, 424 false, 425 al, 426 "ls r10 r12 ASR 13", 427 "ls_r10_r12_ASR_13"}, 428 {{gt, r5, r11, LSR, 25}, false, al, "gt r5 r11 LSR 25", "gt_r5_r11_LSR_25"}, 429 {{vc, r1, r13, ASR, 18}, false, al, "vc r1 r13 ASR 18", "vc_r1_r13_ASR_18"}, 430 {{le, r0, r4, LSR, 30}, false, al, "le r0 r4 LSR 30", "le_r0_r4_LSR_30"}, 431 {{eq, r6, r1, ASR, 15}, false, al, "eq r6 r1 ASR 15", "eq_r6_r1_ASR_15"}, 432 {{eq, r11, r6, LSR, 19}, false, al, "eq r11 r6 LSR 19", "eq_r11_r6_LSR_19"}, 433 {{vc, r3, r7, ASR, 2}, false, al, "vc r3 r7 ASR 2", "vc_r3_r7_ASR_2"}, 434 {{cs, r9, r13, ASR, 11}, false, al, "cs r9 r13 ASR 11", "cs_r9_r13_ASR_11"}, 435 {{lt, r12, r3, ASR, 1}, false, al, "lt r12 r3 ASR 1", "lt_r12_r3_ASR_1"}, 436 {{le, r0, r11, LSR, 26}, false, al, "le r0 r11 LSR 26", "le_r0_r11_LSR_26"}, 437 {{lt, r9, r10, LSR, 23}, false, al, "lt r9 r10 LSR 23", "lt_r9_r10_LSR_23"}, 438 {{ls, r10, r13, LSR, 25}, 439 false, 440 al, 441 "ls r10 r13 LSR 25", 442 "ls_r10_r13_LSR_25"}, 443 {{eq, r5, r9, ASR, 32}, false, al, "eq r5 r9 ASR 32", "eq_r5_r9_ASR_32"}, 444 {{vc, r9, r12, LSR, 11}, false, al, "vc r9 r12 LSR 11", "vc_r9_r12_LSR_11"}, 445 {{lt, r12, r0, LSR, 5}, false, al, "lt r12 r0 LSR 5", "lt_r12_r0_LSR_5"}, 446 {{mi, r13, r5, LSR, 23}, false, al, "mi r13 r5 LSR 23", "mi_r13_r5_LSR_23"}, 447 {{ge, r13, r14, ASR, 3}, false, al, "ge r13 r14 ASR 3", "ge_r13_r14_ASR_3"}, 448 {{cc, r7, r6, LSR, 2}, false, al, "cc r7 r6 LSR 2", "cc_r7_r6_LSR_2"}, 449 {{ge, r11, r7, LSR, 26}, false, al, "ge r11 r7 LSR 26", "ge_r11_r7_LSR_26"}, 450 {{vs, r7, r5, LSR, 3}, false, al, "vs r7 r5 LSR 3", "vs_r7_r5_LSR_3"}, 451 {{cs, r2, r2, ASR, 23}, false, al, "cs r2 r2 ASR 23", "cs_r2_r2_ASR_23"}, 452 {{hi, r11, r11, ASR, 15}, 453 false, 454 al, 455 "hi r11 r11 ASR 15", 456 "hi_r11_r11_ASR_15"}, 457 {{ge, r14, r13, LSR, 1}, false, al, "ge r14 r13 LSR 1", "ge_r14_r13_LSR_1"}, 458 {{vs, r6, r13, ASR, 29}, false, al, "vs r6 r13 ASR 29", "vs_r6_r13_ASR_29"}, 459 {{lt, r1, r9, LSR, 3}, false, al, "lt r1 r9 LSR 3", "lt_r1_r9_LSR_3"}, 460 {{vs, r8, r7, ASR, 4}, false, al, "vs r8 r7 ASR 4", "vs_r8_r7_ASR_4"}, 461 {{ls, r14, r14, ASR, 31}, 462 false, 463 al, 464 "ls r14 r14 ASR 31", 465 "ls_r14_r14_ASR_31"}, 466 {{pl, r2, r7, ASR, 2}, false, al, "pl r2 r7 ASR 2", "pl_r2_r7_ASR_2"}, 467 {{al, r1, r2, LSR, 14}, false, al, "al r1 r2 LSR 14", "al_r1_r2_LSR_14"}, 468 {{ge, r7, r9, ASR, 17}, false, al, "ge r7 r9 ASR 17", "ge_r7_r9_ASR_17"}, 469 {{le, r2, r9, ASR, 1}, false, al, "le r2 r9 ASR 1", "le_r2_r9_ASR_1"}, 470 {{cs, r7, r2, ASR, 26}, false, al, "cs r7 r2 ASR 26", "cs_r7_r2_ASR_26"}, 471 {{eq, r6, r0, LSR, 26}, false, al, "eq r6 r0 LSR 26", "eq_r6_r0_LSR_26"}, 472 {{gt, r10, r12, ASR, 10}, 473 false, 474 al, 475 "gt r10 r12 ASR 10", 476 "gt_r10_r12_ASR_10"}, 477 {{ge, r2, r2, ASR, 7}, false, al, "ge r2 r2 ASR 7", "ge_r2_r2_ASR_7"}, 478 {{vc, r1, r1, ASR, 5}, false, al, "vc r1 r1 ASR 5", "vc_r1_r1_ASR_5"}, 479 {{cs, r1, r7, ASR, 7}, false, al, "cs r1 r7 ASR 7", "cs_r1_r7_ASR_7"}, 480 {{eq, r0, r5, LSR, 21}, false, al, "eq r0 r5 LSR 21", "eq_r0_r5_LSR_21"}, 481 {{lt, r13, r1, LSR, 22}, false, al, "lt r13 r1 LSR 22", "lt_r13_r1_LSR_22"}, 482 {{cs, r11, r3, ASR, 26}, false, al, "cs r11 r3 ASR 26", "cs_r11_r3_ASR_26"}, 483 {{cs, r2, r14, LSR, 13}, false, al, "cs r2 r14 LSR 13", "cs_r2_r14_LSR_13"}, 484 {{cs, r11, r0, LSR, 9}, false, al, "cs r11 r0 LSR 9", "cs_r11_r0_LSR_9"}, 485 {{lt, r11, r12, LSR, 29}, 486 false, 487 al, 488 "lt r11 r12 LSR 29", 489 "lt_r11_r12_LSR_29"}, 490 {{vc, r9, r0, ASR, 7}, false, al, "vc r9 r0 ASR 7", "vc_r9_r0_ASR_7"}, 491 {{eq, r8, r12, ASR, 13}, false, al, "eq r8 r12 ASR 13", "eq_r8_r12_ASR_13"}, 492 {{vc, r0, r8, ASR, 22}, false, al, "vc r0 r8 ASR 22", "vc_r0_r8_ASR_22"}, 493 {{lt, r6, r4, ASR, 25}, false, al, "lt r6 r4 ASR 25", "lt_r6_r4_ASR_25"}, 494 {{cs, r11, r9, ASR, 2}, false, al, "cs r11 r9 ASR 2", "cs_r11_r9_ASR_2"}, 495 {{cs, r8, r1, ASR, 1}, false, al, "cs r8 r1 ASR 1", "cs_r8_r1_ASR_1"}, 496 {{hi, r9, r7, ASR, 26}, false, al, "hi r9 r7 ASR 26", "hi_r9_r7_ASR_26"}, 497 {{pl, r8, r10, ASR, 6}, false, al, "pl r8 r10 ASR 6", "pl_r8_r10_ASR_6"}, 498 {{al, r6, r11, ASR, 1}, false, al, "al r6 r11 ASR 1", "al_r6_r11_ASR_1"}, 499 {{al, r2, r8, ASR, 28}, false, al, "al r2 r8 ASR 28", "al_r2_r8_ASR_28"}, 500 {{eq, r6, r10, LSR, 8}, false, al, "eq r6 r10 LSR 8", "eq_r6_r10_LSR_8"}, 501 {{pl, r6, r6, ASR, 10}, false, al, "pl r6 r6 ASR 10", "pl_r6_r6_ASR_10"}, 502 {{ls, r10, r6, LSR, 8}, false, al, "ls r10 r6 LSR 8", "ls_r10_r6_LSR_8"}, 503 {{ge, r7, r4, LSR, 10}, false, al, "ge r7 r4 LSR 10", "ge_r7_r4_LSR_10"}, 504 {{pl, r3, r2, ASR, 29}, false, al, "pl r3 r2 ASR 29", "pl_r3_r2_ASR_29"}, 505 {{vc, r12, r4, LSR, 1}, false, al, "vc r12 r4 LSR 1", "vc_r12_r4_LSR_1"}, 506 {{hi, r8, r8, ASR, 24}, false, al, "hi r8 r8 ASR 24", "hi_r8_r8_ASR_24"}, 507 {{vs, r0, r12, ASR, 8}, false, al, "vs r0 r12 ASR 8", "vs_r0_r12_ASR_8"}, 508 {{ge, r1, r0, ASR, 6}, false, al, "ge r1 r0 ASR 6", "ge_r1_r0_ASR_6"}, 509 {{gt, r13, r3, ASR, 3}, false, al, "gt r13 r3 ASR 3", "gt_r13_r3_ASR_3"}, 510 {{cc, r0, r8, LSR, 26}, false, al, "cc r0 r8 LSR 26", "cc_r0_r8_LSR_26"}, 511 {{eq, r8, r9, ASR, 19}, false, al, "eq r8 r9 ASR 19", "eq_r8_r9_ASR_19"}, 512 {{eq, r3, r6, LSR, 10}, false, al, "eq r3 r6 LSR 10", "eq_r3_r6_LSR_10"}, 513 {{gt, r4, r3, ASR, 24}, false, al, "gt r4 r3 ASR 24", "gt_r4_r3_ASR_24"}, 514 {{pl, r12, r14, ASR, 5}, false, al, "pl r12 r14 ASR 5", "pl_r12_r14_ASR_5"}, 515 {{cs, r7, r5, ASR, 8}, false, al, "cs r7 r5 ASR 8", "cs_r7_r5_ASR_8"}, 516 {{cc, r3, r8, LSR, 21}, false, al, "cc r3 r8 LSR 21", "cc_r3_r8_LSR_21"}, 517 {{ge, r5, r12, ASR, 9}, false, al, "ge r5 r12 ASR 9", "ge_r5_r12_ASR_9"}, 518 {{lt, r2, r4, ASR, 21}, false, al, "lt r2 r4 ASR 21", "lt_r2_r4_ASR_21"}, 519 {{ne, r5, r10, LSR, 24}, false, al, "ne r5 r10 LSR 24", "ne_r5_r10_LSR_24"}, 520 {{eq, r10, r13, LSR, 6}, false, al, "eq r10 r13 LSR 6", "eq_r10_r13_LSR_6"}, 521 {{le, r2, r12, ASR, 25}, false, al, "le r2 r12 ASR 25", "le_r2_r12_ASR_25"}, 522 {{lt, r6, r1, ASR, 7}, false, al, "lt r6 r1 ASR 7", "lt_r6_r1_ASR_7"}, 523 {{vs, r12, r10, ASR, 28}, 524 false, 525 al, 526 "vs r12 r10 ASR 28", 527 "vs_r12_r10_ASR_28"}, 528 {{ls, r10, r4, ASR, 17}, false, al, "ls r10 r4 ASR 17", "ls_r10_r4_ASR_17"}, 529 {{le, r3, r4, ASR, 8}, false, al, "le r3 r4 ASR 8", "le_r3_r4_ASR_8"}, 530 {{hi, r14, r0, LSR, 31}, false, al, "hi r14 r0 LSR 31", "hi_r14_r0_LSR_31"}, 531 {{ge, r13, r2, ASR, 19}, false, al, "ge r13 r2 ASR 19", "ge_r13_r2_ASR_19"}, 532 {{pl, r13, r3, ASR, 10}, false, al, "pl r13 r3 ASR 10", "pl_r13_r3_ASR_10"}, 533 {{cc, r7, r8, ASR, 32}, false, al, "cc r7 r8 ASR 32", "cc_r7_r8_ASR_32"}, 534 {{cc, r8, r3, ASR, 20}, false, al, "cc r8 r3 ASR 20", "cc_r8_r3_ASR_20"}, 535 {{vc, r5, r10, LSR, 25}, false, al, "vc r5 r10 LSR 25", "vc_r5_r10_LSR_25"}, 536 {{le, r3, r14, ASR, 24}, false, al, "le r3 r14 ASR 24", "le_r3_r14_ASR_24"}, 537 {{pl, r1, r12, LSR, 12}, false, al, "pl r1 r12 LSR 12", "pl_r1_r12_LSR_12"}, 538 {{vs, r11, r0, ASR, 11}, false, al, "vs r11 r0 ASR 11", "vs_r11_r0_ASR_11"}, 539 {{eq, r14, r1, LSR, 2}, false, al, "eq r14 r1 LSR 2", "eq_r14_r1_LSR_2"}, 540 {{ne, r2, r1, LSR, 18}, false, al, "ne r2 r1 LSR 18", "ne_r2_r1_LSR_18"}, 541 {{al, r7, r13, LSR, 2}, false, al, "al r7 r13 LSR 2", "al_r7_r13_LSR_2"}, 542 {{vc, r5, r8, LSR, 18}, false, al, "vc r5 r8 LSR 18", "vc_r5_r8_LSR_18"}, 543 {{le, r1, r12, ASR, 5}, false, al, "le r1 r12 ASR 5", "le_r1_r12_ASR_5"}, 544 {{pl, r6, r2, LSR, 11}, false, al, "pl r6 r2 LSR 11", "pl_r6_r2_LSR_11"}, 545 {{cc, r7, r12, LSR, 3}, false, al, "cc r7 r12 LSR 3", "cc_r7_r12_LSR_3"}, 546 {{al, r10, r0, LSR, 9}, false, al, "al r10 r0 LSR 9", "al_r10_r0_LSR_9"}, 547 {{hi, r2, r1, LSR, 29}, false, al, "hi r2 r1 LSR 29", "hi_r2_r1_LSR_29"}, 548 {{lt, r3, r13, LSR, 13}, false, al, "lt r3 r13 LSR 13", "lt_r3_r13_LSR_13"}, 549 {{mi, r13, r14, ASR, 23}, 550 false, 551 al, 552 "mi r13 r14 ASR 23", 553 "mi_r13_r14_ASR_23"}, 554 {{lt, r14, r14, LSR, 16}, 555 false, 556 al, 557 "lt r14 r14 LSR 16", 558 "lt_r14_r14_LSR_16"}, 559 {{hi, r11, r14, ASR, 8}, false, al, "hi r11 r14 ASR 8", "hi_r11_r14_ASR_8"}, 560 {{eq, r4, r1, LSR, 1}, false, al, "eq r4 r1 LSR 1", "eq_r4_r1_LSR_1"}, 561 {{ls, r14, r0, LSR, 30}, false, al, "ls r14 r0 LSR 30", "ls_r14_r0_LSR_30"}, 562 {{le, r1, r9, LSR, 29}, false, al, "le r1 r9 LSR 29", "le_r1_r9_LSR_29"}, 563 {{vc, r4, r2, ASR, 27}, false, al, "vc r4 r2 ASR 27", "vc_r4_r2_ASR_27"}, 564 {{cc, r11, r2, LSR, 27}, false, al, "cc r11 r2 LSR 27", "cc_r11_r2_LSR_27"}, 565 {{lt, r13, r7, ASR, 3}, false, al, "lt r13 r7 ASR 3", "lt_r13_r7_ASR_3"}, 566 {{hi, r12, r12, ASR, 1}, false, al, "hi r12 r12 ASR 1", "hi_r12_r12_ASR_1"}, 567 {{ne, r14, r13, LSR, 25}, 568 false, 569 al, 570 "ne r14 r13 LSR 25", 571 "ne_r14_r13_LSR_25"}, 572 {{mi, r8, r11, ASR, 6}, false, al, "mi r8 r11 ASR 6", "mi_r8_r11_ASR_6"}, 573 {{pl, r7, r5, ASR, 31}, false, al, "pl r7 r5 ASR 31", "pl_r7_r5_ASR_31"}, 574 {{gt, r14, r6, LSR, 9}, false, al, "gt r14 r6 LSR 9", "gt_r14_r6_LSR_9"}, 575 {{cc, r1, r9, LSR, 7}, false, al, "cc r1 r9 LSR 7", "cc_r1_r9_LSR_7"}, 576 {{ge, r11, r14, LSR, 10}, 577 false, 578 al, 579 "ge r11 r14 LSR 10", 580 "ge_r11_r14_LSR_10"}, 581 {{le, r7, r9, ASR, 25}, false, al, "le r7 r9 ASR 25", "le_r7_r9_ASR_25"}, 582 {{gt, r0, r14, LSR, 14}, false, al, "gt r0 r14 LSR 14", "gt_r0_r14_LSR_14"}, 583 {{ne, r11, r4, ASR, 6}, false, al, "ne r11 r4 ASR 6", "ne_r11_r4_ASR_6"}, 584 {{ls, r10, r9, LSR, 12}, false, al, "ls r10 r9 LSR 12", "ls_r10_r9_LSR_12"}, 585 {{al, r8, r0, ASR, 27}, false, al, "al r8 r0 ASR 27", "al_r8_r0_ASR_27"}, 586 {{le, r4, r7, ASR, 21}, false, al, "le r4 r7 ASR 21", "le_r4_r7_ASR_21"}, 587 {{cc, r8, r5, ASR, 18}, false, al, "cc r8 r5 ASR 18", "cc_r8_r5_ASR_18"}, 588 {{al, r4, r10, LSR, 21}, false, al, "al r4 r10 LSR 21", "al_r4_r10_LSR_21"}, 589 {{hi, r8, r5, LSR, 25}, false, al, "hi r8 r5 LSR 25", "hi_r8_r5_LSR_25"}, 590 {{gt, r4, r2, LSR, 29}, false, al, "gt r4 r2 LSR 29", "gt_r4_r2_LSR_29"}, 591 {{al, r10, r0, ASR, 1}, false, al, "al r10 r0 ASR 1", "al_r10_r0_ASR_1"}, 592 {{ls, r1, r12, LSR, 26}, false, al, "ls r1 r12 LSR 26", "ls_r1_r12_LSR_26"}, 593 {{vs, r13, r6, ASR, 8}, false, al, "vs r13 r6 ASR 8", "vs_r13_r6_ASR_8"}, 594 {{eq, r13, r12, ASR, 1}, false, al, "eq r13 r12 ASR 1", "eq_r13_r12_ASR_1"}, 595 {{eq, r9, r11, ASR, 5}, false, al, "eq r9 r11 ASR 5", "eq_r9_r11_ASR_5"}, 596 {{le, r11, r2, LSR, 18}, false, al, "le r11 r2 LSR 18", "le_r11_r2_LSR_18"}, 597 {{hi, r11, r0, LSR, 32}, false, al, "hi r11 r0 LSR 32", "hi_r11_r0_LSR_32"}, 598 {{eq, r8, r5, LSR, 31}, false, al, "eq r8 r5 LSR 31", "eq_r8_r5_LSR_31"}, 599 {{ne, r7, r13, ASR, 4}, false, al, "ne r7 r13 ASR 4", "ne_r7_r13_ASR_4"}, 600 {{cs, r7, r7, LSR, 32}, false, al, "cs r7 r7 LSR 32", "cs_r7_r7_LSR_32"}, 601 {{pl, r13, r5, ASR, 2}, false, al, "pl r13 r5 ASR 2", "pl_r13_r5_ASR_2"}, 602 {{vc, r9, r2, ASR, 11}, false, al, "vc r9 r2 ASR 11", "vc_r9_r2_ASR_11"}, 603 {{mi, r7, r7, ASR, 16}, false, al, "mi r7 r7 ASR 16", "mi_r7_r7_ASR_16"}, 604 {{vs, r2, r3, ASR, 8}, false, al, "vs r2 r3 ASR 8", "vs_r2_r3_ASR_8"}, 605 {{lt, r5, r3, LSR, 19}, false, al, "lt r5 r3 LSR 19", "lt_r5_r3_LSR_19"}, 606 {{al, r3, r14, ASR, 20}, false, al, "al r3 r14 ASR 20", "al_r3_r14_ASR_20"}, 607 {{ge, r10, r11, LSR, 7}, false, al, "ge r10 r11 LSR 7", "ge_r10_r11_LSR_7"}, 608 {{mi, r2, r14, LSR, 11}, false, al, "mi r2 r14 LSR 11", "mi_r2_r14_LSR_11"}, 609 {{mi, r3, r1, ASR, 24}, false, al, "mi r3 r1 ASR 24", "mi_r3_r1_ASR_24"}, 610 {{lt, r7, r14, ASR, 23}, false, al, "lt r7 r14 ASR 23", "lt_r7_r14_ASR_23"}, 611 {{ge, r14, r3, LSR, 8}, false, al, "ge r14 r3 LSR 8", "ge_r14_r3_LSR_8"}, 612 {{al, r3, r3, ASR, 16}, false, al, "al r3 r3 ASR 16", "al_r3_r3_ASR_16"}, 613 {{cs, r12, r6, LSR, 8}, false, al, "cs r12 r6 LSR 8", "cs_r12_r6_LSR_8"}, 614 {{ge, r9, r1, LSR, 1}, false, al, "ge r9 r1 LSR 1", "ge_r9_r1_LSR_1"}, 615 {{hi, r0, r2, LSR, 15}, false, al, "hi r0 r2 LSR 15", "hi_r0_r2_LSR_15"}, 616 {{pl, r4, r3, LSR, 22}, false, al, "pl r4 r3 LSR 22", "pl_r4_r3_LSR_22"}, 617 {{mi, r14, r1, ASR, 3}, false, al, "mi r14 r1 ASR 3", "mi_r14_r1_ASR_3"}, 618 {{vc, r7, r6, LSR, 5}, false, al, "vc r7 r6 LSR 5", "vc_r7_r6_LSR_5"}, 619 {{lt, r7, r3, LSR, 19}, false, al, "lt r7 r3 LSR 19", "lt_r7_r3_LSR_19"}, 620 {{vc, r9, r3, LSR, 4}, false, al, "vc r9 r3 LSR 4", "vc_r9_r3_LSR_4"}, 621 {{ls, r2, r1, ASR, 15}, false, al, "ls r2 r1 ASR 15", "ls_r2_r1_ASR_15"}, 622 {{ls, r1, r10, ASR, 31}, false, al, "ls r1 r10 ASR 31", "ls_r1_r10_ASR_31"}, 623 {{mi, r5, r9, ASR, 7}, false, al, "mi r5 r9 ASR 7", "mi_r5_r9_ASR_7"}, 624 {{ne, r7, r2, ASR, 31}, false, al, "ne r7 r2 ASR 31", "ne_r7_r2_ASR_31"}, 625 {{vc, r0, r1, LSR, 20}, false, al, "vc r0 r1 LSR 20", "vc_r0_r1_LSR_20"}, 626 {{ge, r7, r11, ASR, 9}, false, al, "ge r7 r11 ASR 9", "ge_r7_r11_ASR_9"}, 627 {{vc, r8, r13, ASR, 19}, false, al, "vc r8 r13 ASR 19", "vc_r8_r13_ASR_19"}, 628 {{hi, r7, r5, LSR, 17}, false, al, "hi r7 r5 LSR 17", "hi_r7_r5_LSR_17"}, 629 {{mi, r11, r2, LSR, 23}, false, al, "mi r11 r2 LSR 23", "mi_r11_r2_LSR_23"}, 630 {{pl, r13, r13, LSR, 5}, false, al, "pl r13 r13 LSR 5", "pl_r13_r13_LSR_5"}, 631 {{ls, r1, r3, LSR, 17}, false, al, "ls r1 r3 LSR 17", "ls_r1_r3_LSR_17"}, 632 {{vc, r6, r5, LSR, 10}, false, al, "vc r6 r5 LSR 10", "vc_r6_r5_LSR_10"}, 633 {{cs, r6, r6, ASR, 9}, false, al, "cs r6 r6 ASR 9", "cs_r6_r6_ASR_9"}, 634 {{ls, r3, r8, LSR, 21}, false, al, "ls r3 r8 LSR 21", "ls_r3_r8_LSR_21"}, 635 {{cs, r2, r0, ASR, 23}, false, al, "cs r2 r0 ASR 23", "cs_r2_r0_ASR_23"}, 636 {{ge, r0, r13, LSR, 29}, false, al, "ge r0 r13 LSR 29", "ge_r0_r13_LSR_29"}, 637 {{lt, r13, r12, ASR, 10}, 638 false, 639 al, 640 "lt r13 r12 ASR 10", 641 "lt_r13_r12_ASR_10"}, 642 {{vs, r4, r2, ASR, 15}, false, al, "vs r4 r2 ASR 15", "vs_r4_r2_ASR_15"}, 643 {{mi, r6, r14, ASR, 6}, false, al, "mi r6 r14 ASR 6", "mi_r6_r14_ASR_6"}, 644 {{ge, r10, r12, ASR, 22}, 645 false, 646 al, 647 "ge r10 r12 ASR 22", 648 "ge_r10_r12_ASR_22"}, 649 {{cs, r4, r5, ASR, 2}, false, al, "cs r4 r5 ASR 2", "cs_r4_r5_ASR_2"}, 650 {{cc, r5, r4, ASR, 4}, false, al, "cc r5 r4 ASR 4", "cc_r5_r4_ASR_4"}, 651 {{ge, r13, r13, LSR, 30}, 652 false, 653 al, 654 "ge r13 r13 LSR 30", 655 "ge_r13_r13_LSR_30"}, 656 {{gt, r1, r11, ASR, 20}, false, al, "gt r1 r11 ASR 20", "gt_r1_r11_ASR_20"}, 657 {{cs, r2, r12, ASR, 15}, false, al, "cs r2 r12 ASR 15", "cs_r2_r12_ASR_15"}, 658 {{le, r11, r0, ASR, 32}, false, al, "le r11 r0 ASR 32", "le_r11_r0_ASR_32"}, 659 {{hi, r0, r3, ASR, 9}, false, al, "hi r0 r3 ASR 9", "hi_r0_r3_ASR_9"}, 660 {{mi, r9, r8, LSR, 10}, false, al, "mi r9 r8 LSR 10", "mi_r9_r8_LSR_10"}, 661 {{lt, r12, r3, ASR, 2}, false, al, "lt r12 r3 ASR 2", "lt_r12_r3_ASR_2"}, 662 {{ne, r11, r2, LSR, 32}, false, al, "ne r11 r2 LSR 32", "ne_r11_r2_LSR_32"}, 663 {{al, r1, r5, ASR, 6}, false, al, "al r1 r5 ASR 6", "al_r1_r5_ASR_6"}, 664 {{eq, r0, r3, LSR, 21}, false, al, "eq r0 r3 LSR 21", "eq_r0_r3_LSR_21"}, 665 {{lt, r7, r11, ASR, 23}, false, al, "lt r7 r11 ASR 23", "lt_r7_r11_ASR_23"}, 666 {{hi, r8, r13, LSR, 19}, false, al, "hi r8 r13 LSR 19", "hi_r8_r13_LSR_19"}, 667 {{ne, r9, r10, LSR, 18}, false, al, "ne r9 r10 LSR 18", "ne_r9_r10_LSR_18"}, 668 {{hi, r9, r8, ASR, 24}, false, al, "hi r9 r8 ASR 24", "hi_r9_r8_ASR_24"}, 669 {{ls, r14, r8, ASR, 9}, false, al, "ls r14 r8 ASR 9", "ls_r14_r8_ASR_9"}, 670 {{al, r0, r6, LSR, 1}, false, al, "al r0 r6 LSR 1", "al_r0_r6_LSR_1"}, 671 {{al, r9, r12, ASR, 32}, false, al, "al r9 r12 ASR 32", "al_r9_r12_ASR_32"}, 672 {{gt, r8, r14, ASR, 5}, false, al, "gt r8 r14 ASR 5", "gt_r8_r14_ASR_5"}, 673 {{cc, r6, r13, ASR, 31}, false, al, "cc r6 r13 ASR 31", "cc_r6_r13_ASR_31"}, 674 {{ne, r2, r14, ASR, 10}, false, al, "ne r2 r14 ASR 10", "ne_r2_r14_ASR_10"}, 675 {{mi, r0, r11, ASR, 22}, false, al, "mi r0 r11 ASR 22", "mi_r0_r11_ASR_22"}, 676 {{mi, r1, r5, LSR, 22}, false, al, "mi r1 r5 LSR 22", "mi_r1_r5_LSR_22"}, 677 {{pl, r5, r1, ASR, 2}, false, al, "pl r5 r1 ASR 2", "pl_r5_r1_ASR_2"}, 678 {{cs, r6, r13, LSR, 9}, false, al, "cs r6 r13 LSR 9", "cs_r6_r13_LSR_9"}, 679 {{al, r12, r5, LSR, 12}, false, al, "al r12 r5 LSR 12", "al_r12_r5_LSR_12"}, 680 {{gt, r6, r12, ASR, 2}, false, al, "gt r6 r12 ASR 2", "gt_r6_r12_ASR_2"}, 681 {{eq, r4, r0, LSR, 24}, false, al, "eq r4 r0 LSR 24", "eq_r4_r0_LSR_24"}, 682 {{ls, r5, r6, LSR, 32}, false, al, "ls r5 r6 LSR 32", "ls_r5_r6_LSR_32"}, 683 {{mi, r13, r7, ASR, 24}, false, al, "mi r13 r7 ASR 24", "mi_r13_r7_ASR_24"}, 684 {{ge, r8, r6, ASR, 26}, false, al, "ge r8 r6 ASR 26", "ge_r8_r6_ASR_26"}, 685 {{eq, r5, r1, ASR, 24}, false, al, "eq r5 r1 ASR 24", "eq_r5_r1_ASR_24"}, 686 {{al, r13, r2, ASR, 6}, false, al, "al r13 r2 ASR 6", "al_r13_r2_ASR_6"}, 687 {{mi, r0, r2, ASR, 15}, false, al, "mi r0 r2 ASR 15", "mi_r0_r2_ASR_15"}, 688 {{lt, r7, r13, ASR, 8}, false, al, "lt r7 r13 ASR 8", "lt_r7_r13_ASR_8"}, 689 {{cs, r7, r12, ASR, 27}, false, al, "cs r7 r12 ASR 27", "cs_r7_r12_ASR_27"}, 690 {{ls, r9, r1, ASR, 27}, false, al, "ls r9 r1 ASR 27", "ls_r9_r1_ASR_27"}, 691 {{ne, r14, r7, ASR, 18}, false, al, "ne r14 r7 ASR 18", "ne_r14_r7_ASR_18"}, 692 {{cc, r5, r14, LSR, 28}, false, al, "cc r5 r14 LSR 28", "cc_r5_r14_LSR_28"}, 693 {{vs, r0, r8, ASR, 14}, false, al, "vs r0 r8 ASR 14", "vs_r0_r8_ASR_14"}, 694 {{gt, r3, r7, ASR, 1}, false, al, "gt r3 r7 ASR 1", "gt_r3_r7_ASR_1"}, 695 {{pl, r8, r6, ASR, 18}, false, al, "pl r8 r6 ASR 18", "pl_r8_r6_ASR_18"}, 696 {{vc, r14, r5, ASR, 4}, false, al, "vc r14 r5 ASR 4", "vc_r14_r5_ASR_4"}, 697 {{vc, r7, r5, LSR, 9}, false, al, "vc r7 r5 LSR 9", "vc_r7_r5_LSR_9"}, 698 {{vs, r8, r1, LSR, 15}, false, al, "vs r8 r1 LSR 15", "vs_r8_r1_LSR_15"}, 699 {{ge, r12, r13, ASR, 21}, 700 false, 701 al, 702 "ge r12 r13 ASR 21", 703 "ge_r12_r13_ASR_21"}, 704 {{vs, r8, r3, ASR, 8}, false, al, "vs r8 r3 ASR 8", "vs_r8_r3_ASR_8"}, 705 {{al, r0, r3, ASR, 8}, false, al, "al r0 r3 ASR 8", "al_r0_r3_ASR_8"}, 706 {{vs, r9, r7, LSR, 13}, false, al, "vs r9 r7 LSR 13", "vs_r9_r7_LSR_13"}, 707 {{al, r7, r6, LSR, 31}, false, al, "al r7 r6 LSR 31", "al_r7_r6_LSR_31"}, 708 {{lt, r8, r1, ASR, 14}, false, al, "lt r8 r1 ASR 14", "lt_r8_r1_ASR_14"}, 709 {{ne, r10, r13, ASR, 10}, 710 false, 711 al, 712 "ne r10 r13 ASR 10", 713 "ne_r10_r13_ASR_10"}, 714 {{ls, r7, r14, ASR, 22}, false, al, "ls r7 r14 ASR 22", "ls_r7_r14_ASR_22"}, 715 {{vs, r10, r4, LSR, 9}, false, al, "vs r10 r4 LSR 9", "vs_r10_r4_LSR_9"}, 716 {{eq, r0, r5, ASR, 6}, false, al, "eq r0 r5 ASR 6", "eq_r0_r5_ASR_6"}, 717 {{vc, r1, r13, LSR, 27}, false, al, "vc r1 r13 LSR 27", "vc_r1_r13_LSR_27"}, 718 {{vc, r1, r13, ASR, 19}, false, al, "vc r1 r13 ASR 19", "vc_r1_r13_ASR_19"}, 719 {{mi, r11, r7, ASR, 27}, false, al, "mi r11 r7 ASR 27", "mi_r11_r7_ASR_27"}, 720 {{hi, r6, r0, ASR, 18}, false, al, "hi r6 r0 ASR 18", "hi_r6_r0_ASR_18"}, 721 {{vs, r12, r13, ASR, 22}, 722 false, 723 al, 724 "vs r12 r13 ASR 22", 725 "vs_r12_r13_ASR_22"}, 726 {{vc, r0, r14, LSR, 23}, false, al, "vc r0 r14 LSR 23", "vc_r0_r14_LSR_23"}, 727 {{mi, r14, r8, LSR, 24}, false, al, "mi r14 r8 LSR 24", "mi_r14_r8_LSR_24"}, 728 {{mi, r2, r10, LSR, 13}, false, al, "mi r2 r10 LSR 13", "mi_r2_r10_LSR_13"}, 729 {{ne, r13, r9, LSR, 17}, false, al, "ne r13 r9 LSR 17", "ne_r13_r9_LSR_17"}, 730 {{cs, r1, r1, ASR, 28}, false, al, "cs r1 r1 ASR 28", "cs_r1_r1_ASR_28"}, 731 {{eq, r14, r1, LSR, 9}, false, al, "eq r14 r1 LSR 9", "eq_r14_r1_LSR_9"}, 732 {{gt, r7, r11, LSR, 5}, false, al, "gt r7 r11 LSR 5", "gt_r7_r11_LSR_5"}, 733 {{le, r4, r13, ASR, 25}, false, al, "le r4 r13 ASR 25", "le_r4_r13_ASR_25"}, 734 {{eq, r5, r11, LSR, 15}, false, al, "eq r5 r11 LSR 15", "eq_r5_r11_LSR_15"}, 735 {{mi, r10, r13, ASR, 13}, 736 false, 737 al, 738 "mi r10 r13 ASR 13", 739 "mi_r10_r13_ASR_13"}, 740 {{gt, r10, r7, ASR, 32}, false, al, "gt r10 r7 ASR 32", "gt_r10_r7_ASR_32"}, 741 {{mi, r2, r12, ASR, 31}, false, al, "mi r2 r12 ASR 31", "mi_r2_r12_ASR_31"}, 742 {{gt, r8, r14, ASR, 31}, false, al, "gt r8 r14 ASR 31", "gt_r8_r14_ASR_31"}, 743 {{hi, r6, r8, ASR, 4}, false, al, "hi r6 r8 ASR 4", "hi_r6_r8_ASR_4"}, 744 {{ne, r5, r12, ASR, 23}, false, al, "ne r5 r12 ASR 23", "ne_r5_r12_ASR_23"}, 745 {{eq, r4, r10, ASR, 13}, false, al, "eq r4 r10 ASR 13", "eq_r4_r10_ASR_13"}, 746 {{ls, r11, r12, LSR, 21}, 747 false, 748 al, 749 "ls r11 r12 LSR 21", 750 "ls_r11_r12_LSR_21"}, 751 {{mi, r8, r3, ASR, 29}, false, al, "mi r8 r3 ASR 29", "mi_r8_r3_ASR_29"}, 752 {{ls, r0, r13, LSR, 16}, false, al, "ls r0 r13 LSR 16", "ls_r0_r13_LSR_16"}, 753 {{mi, r12, r7, LSR, 22}, false, al, "mi r12 r7 LSR 22", "mi_r12_r7_LSR_22"}, 754 {{eq, r4, r14, LSR, 19}, false, al, "eq r4 r14 LSR 19", "eq_r4_r14_LSR_19"}, 755 {{ge, r3, r7, LSR, 4}, false, al, "ge r3 r7 LSR 4", "ge_r3_r7_LSR_4"}, 756 {{ge, r10, r10, LSR, 5}, false, al, "ge r10 r10 LSR 5", "ge_r10_r10_LSR_5"}, 757 {{vc, r13, r8, LSR, 30}, false, al, "vc r13 r8 LSR 30", "vc_r13_r8_LSR_30"}, 758 {{mi, r2, r14, LSR, 8}, false, al, "mi r2 r14 LSR 8", "mi_r2_r14_LSR_8"}, 759 {{hi, r14, r11, ASR, 20}, 760 false, 761 al, 762 "hi r14 r11 ASR 20", 763 "hi_r14_r11_ASR_20"}, 764 {{ge, r13, r6, LSR, 16}, false, al, "ge r13 r6 LSR 16", "ge_r13_r6_LSR_16"}, 765 {{vs, r5, r0, LSR, 16}, false, al, "vs r5 r0 LSR 16", "vs_r5_r0_LSR_16"}, 766 {{cc, r6, r1, LSR, 23}, false, al, "cc r6 r1 LSR 23", "cc_r6_r1_LSR_23"}, 767 {{mi, r14, r12, LSR, 16}, 768 false, 769 al, 770 "mi r14 r12 LSR 16", 771 "mi_r14_r12_LSR_16"}, 772 {{vs, r1, r9, ASR, 24}, false, al, "vs r1 r9 ASR 24", "vs_r1_r9_ASR_24"}, 773 {{vs, r9, r4, LSR, 28}, false, al, "vs r9 r4 LSR 28", "vs_r9_r4_LSR_28"}, 774 {{cc, r12, r10, ASR, 25}, 775 false, 776 al, 777 "cc r12 r10 ASR 25", 778 "cc_r12_r10_ASR_25"}, 779 {{lt, r8, r7, LSR, 1}, false, al, "lt r8 r7 LSR 1", "lt_r8_r7_LSR_1"}}; 780 781 // These headers each contain an array of `TestResult` with the reference output 782 // values. The reference arrays are names `kReference{mnemonic}`. 783 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmn.h" 784 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-cmp.h" 785 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mov.h" 786 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-movs.h" 787 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvn.h" 788 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-mvns.h" 789 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-teq.h" 790 #include "aarch32/traces/assembler-cond-rd-operand-rn-shift-amount-1to32-a32-tst.h" 791 792 793 // The maximum number of errors to report in detail for each test. 794 const unsigned kErrorReportLimit = 8; 795 796 typedef void (MacroAssembler::*Fn)(Condition cond, 797 Register rd, 798 const Operand& op); 799 800 void TestHelper(Fn instruction, 801 const char* mnemonic, 802 const TestResult reference[]) { 803 unsigned total_error_count = 0; 804 MacroAssembler masm(BUF_SIZE); 805 806 masm.UseA32(); 807 808 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 809 // Values to pass to the macro-assembler. 810 Condition cond = kTests[i].operands.cond; 811 Register rd = kTests[i].operands.rd; 812 Register rn = kTests[i].operands.rn; 813 ShiftType shift = kTests[i].operands.shift; 814 uint32_t amount = kTests[i].operands.amount; 815 Operand op(rn, shift, amount); 816 817 int32_t start = masm.GetCursorOffset(); 818 { 819 // We never generate more that 4 bytes, as IT instructions are only 820 // allowed for narrow encodings. 821 ExactAssemblyScope scope(&masm, 4, ExactAssemblyScope::kMaximumSize); 822 if (kTests[i].in_it_block) { 823 masm.it(kTests[i].it_condition); 824 } 825 (masm.*instruction)(cond, rd, op); 826 } 827 int32_t end = masm.GetCursorOffset(); 828 829 const byte* result_ptr = 830 masm.GetBuffer()->GetOffsetAddress<const byte*>(start); 831 VIXL_ASSERT(start < end); 832 uint32_t result_size = end - start; 833 834 if (Test::generate_test_trace()) { 835 // Print the result bytes. 836 printf("const byte kInstruction_%s_%s[] = {\n", 837 mnemonic, 838 kTests[i].identifier); 839 for (uint32_t j = 0; j < result_size; j++) { 840 if (j == 0) { 841 printf(" 0x%02" PRIx8, result_ptr[j]); 842 } else { 843 printf(", 0x%02" PRIx8, result_ptr[j]); 844 } 845 } 846 // This comment is meant to be used by external tools to validate 847 // the encoding. We can parse the comment to figure out what 848 // instruction this corresponds to. 849 if (kTests[i].in_it_block) { 850 printf(" // It %s; %s %s\n};\n", 851 kTests[i].it_condition.GetName(), 852 mnemonic, 853 kTests[i].operands_description); 854 } else { 855 printf(" // %s %s\n};\n", mnemonic, kTests[i].operands_description); 856 } 857 } else { 858 // Check we've emitted the exact same encoding as present in the 859 // trace file. Only print up to `kErrorReportLimit` errors. 860 if (((result_size != reference[i].size) || 861 (memcmp(result_ptr, reference[i].encoding, reference[i].size) != 862 0)) && 863 (++total_error_count <= kErrorReportLimit)) { 864 printf("Error when testing \"%s\" with operands \"%s\":\n", 865 mnemonic, 866 kTests[i].operands_description); 867 printf(" Expected: "); 868 for (uint32_t j = 0; j < reference[i].size; j++) { 869 if (j == 0) { 870 printf("0x%02" PRIx8, reference[i].encoding[j]); 871 } else { 872 printf(", 0x%02" PRIx8, reference[i].encoding[j]); 873 } 874 } 875 printf("\n"); 876 printf(" Found: "); 877 for (uint32_t j = 0; j < result_size; j++) { 878 if (j == 0) { 879 printf("0x%02" PRIx8, result_ptr[j]); 880 } else { 881 printf(", 0x%02" PRIx8, result_ptr[j]); 882 } 883 } 884 printf("\n"); 885 } 886 } 887 } 888 889 masm.FinalizeCode(); 890 891 if (Test::generate_test_trace()) { 892 // Finalize the trace file by writing the final `TestResult` array 893 // which links all generated instruction encodings. 894 printf("const TestResult kReference%s[] = {\n", mnemonic); 895 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 896 printf(" {\n"); 897 printf(" ARRAY_SIZE(kInstruction_%s_%s),\n", 898 mnemonic, 899 kTests[i].identifier); 900 printf(" kInstruction_%s_%s,\n", mnemonic, kTests[i].identifier); 901 printf(" },\n"); 902 } 903 printf("};\n"); 904 } else { 905 if (total_error_count > kErrorReportLimit) { 906 printf("%u other errors follow.\n", 907 total_error_count - kErrorReportLimit); 908 } 909 // Crash if the test failed. 910 VIXL_CHECK(total_error_count == 0); 911 } 912 } 913 914 // Instantiate tests for each instruction in the list. 915 #define TEST(mnemonic) \ 916 void Test_##mnemonic() { \ 917 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 918 } \ 919 Test test_##mnemonic( \ 920 "AARCH32_ASSEMBLER_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" \ 921 "A32_" #mnemonic, \ 922 &Test_##mnemonic); 923 FOREACH_INSTRUCTION(TEST) 924 #undef TEST 925 926 } // namespace 927 #endif 928 929 } // namespace aarch32 930 } // namespace vixl 931
