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Searched
refs:BIT6
(Results
1 - 25
of
156
) sorted by null
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/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h
30
#define CTRL4_PICO_SIDDQ
BIT6
41
#define CTRL5_PICOPHY_CHRGSEL
BIT6
58
#define RST0_USBOTG
BIT6
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
Fdc.h
46
#define MSR_DIO
BIT6
// Data Input/Output
81
#define CMD_MFM
BIT6
97
#define STS0_IC (BIT7 |
BIT6
) // Interrupt Code
112
//
BIT6
is unused
128
#define STS2_CM
BIT6
// Control Mark
143
#define STS3_WP
BIT6
// Write Protected
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
55
#define USBPORTSC_RD
BIT6
// Resume Detect
76
#define USBCMD_CF
BIT6
// Config Flag (sw only)
90
#define USBTD_STALLED
BIT6
// TD is stalled
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
SP804Timer.h
40
#define SP804_TIMER_CTRL_PERIODIC
BIT6
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
I2cRegs.h
53
#define B_I2C_REG_TAR (BIT9+BIT8+BIT7+
BIT6
+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
67
#define I2C_REG_RAW_INTR_STAT_TX_ABRT (
BIT6
) // Raw Interrupt Status Register TX Abort status.
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530Dma.h
43
#define DMA4_CSDP_SRC_PACKED
BIT6
83
#define DMA4_CCR_READ_PRIORITY_HIGH
BIT6
115
#define DMA4_CSR_SYNC
BIT6
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h
48
#define ISP1761_DC_INTERRUPT_DMA
BIT6
75
#define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 |
BIT6
96
#define ISP1761_OTG_CTRL_VBUS_CHRG
BIT6
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Dma.h
43
#define DMA4_CSDP_SRC_PACKED
BIT6
83
#define DMA4_CCR_READ_PRIORITY_HIGH
BIT6
115
#define DMA4_CSR_SYNC
BIT6
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsSmbus.h
58
#define B_PCH_SMBUS_PCICMD_PER
BIT6
// Parity Error - reserved as '0'
79
#define B_PCH_SMBUS_IUS
BIT6
// In Use Status
90
#define B_PCH_SMBUS_START
BIT6
// Start
PchRegsPcu.h
79
#define B_PCH_LPC_COMMAND_PER
BIT6
// Parity Error Response Enable
204
#define B_PCH_LPC_FWH_BIOS_DEC_LEE
BIT6
// Legacy E Segment Enable
373
#define B_PCH_ILB_DXXIR_IBR_MASK (
BIT6
| BIT5 | BIT4) // INTB Mask
378
#define V_PCH_ILB_DXXIR_IBR_PIRQE
BIT6
// INTB Mapping to IRQ E
379
#define V_PCH_ILB_DXXIR_IBR_PIRQF (
BIT6
| BIT4) // INTB Mapping to IRQ F
380
#define V_PCH_ILB_DXXIR_IBR_PIRQG (
BIT6
| BIT5) // INTB Mapping to IRQ G
381
#define V_PCH_ILB_DXXIR_IBR_PIRQH (
BIT6
| BIT5 | BIT4) // INTB Mapping to IRQ H
413
#define B_PCH_ILB_RTCC_RTCB4
BIT6
// RTC Bias Resistor 4, Adds 480 Kohm
428
#define B_PCH_ILB_DEF1_ECWS
BIT6
// 8254 Early CW Select
438
#define B_PCH_ILB_GNMI_NMI2SMIEN
BIT6
// NMI to SMI Enable
[
all
...]
PchRegsSata.h
71
#define B_PCH_SATA_COMMAND_PER
BIT6
// Parity Error Response Enable
178
#define B_PCH_SATA_MAP_SMS_MASK (BIT7 |
BIT6
) // SATA Mode Select
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
29
#define B_IC_SLAVE_DISABLE
BIT6
60
#define I2C_INTR_TX_ABRT
BIT6
// Set on NACK
120
#define I2C_INTR_TX_ABRT
BIT6
// Set on NACK
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 |
BIT6
| BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
/device/linaro/bootloader/edk2/SecurityPkg/Include/Library/
Tcg2PhysicalPresenceLib.h
32
#define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_EPS
BIT6
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
23
#undef
BIT6
59
#define
BIT6
0x00000040U
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h
75
#define MCI_POWER_OPENDRAIN
BIT6
89
#define MCI_STATUS_CMD_RESPEND
BIT6
142
#define MCI_CPSM_WAIT_RESPONSE
BIT6
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
I2CLib.h
40
#define B_IC_SLAVE_DISABLE
BIT6
71
#define I2C_INTR_TX_ABRT
BIT6
// Set on NACK
133
#define I2C_INTR_TX_ABRT
BIT6
// Set on NACK
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
96
#define EPHSR_LTX_BRD
BIT6
122
#define RPCR_LS1A
BIT6
141
#define CTR_CR_ENABLE
BIT6
271
#define PHYANA_10BASETFD
BIT6
// Advertise 10BASET Full duplex capability
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h
67
#define RXSTATUS_LCOLL
BIT6
// Late collision detected
106
#define INSTS_RXDF_INT
BIT6
// Rx Frame dropped
141
#define MPTCTRL_PME_TYPE
BIT6
// PME Buffer type (Open Drain or Push-Pull)
173
#define PHYANA_10BASETFD
BIT6
// Advertise 10BASET Full duplex capability
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
42
#define MCH_ESMRAMC_E_SMERR
BIT6
VirtioBlk.h
55
#define VIRTIO_BLK_F_BLK_SIZE
BIT6
// treated as "logical block size" in
VirtioNet.h
47
#define VIRTIO_NET_F_GSO
BIT6
// deprecated
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
I2CLibPei.h
26
#define B_PCH_PMC_FUNC_DIS_LPSS_FUNC6
BIT6
// LPSS HSUART #2 Disable
82
#define B_IC_SLAVE_DISABLE
BIT6
113
#define I2C_INTR_TX_ABRT
BIT6
// Set on NACK
177
#define I2C_INTR_TX_ABRT
BIT6
// Set on NACK
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/
IsaFloppy.h
242
#define MSR_DIO
BIT6
313
#define CMD_MFM
BIT6
333
#define STS0_IC (BIT7 |
BIT6
)
377
//
BIT6
is unused
412
#define STS2_CM
BIT6
438
#define STS3_WP
BIT6
/device/linaro/bootloader/edk2/ShellPkg/Include/Library/
HandleParsingLib.h
148
#define HR_DRIVER_DIAGNOSTICS_HANDLE
BIT6
154
#define HR_VALID_MASK (BIT1|BIT2|BIT3|BIT4|BIT5|
BIT6
|BIT7|BIT8|BIT9|BIT10|BIT11)
Completed in 333 milliseconds
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