1 #ifndef GEN_EU_MESSAGE_XML 2 #define GEN_EU_MESSAGE_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 https://github.com/olvaffe/envytools/ 8 git clone https://github.com/olvaffe/envytools.git 9 10 Copyright (C) 2014-2015 by the following authors: 11 - Chia-I Wu <olvaffe (at) gmail.com> (olv) 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice (including the 22 next paragraph) shall be included in all copies or substantial 23 portions of the Software. 24 25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 35 enum gen_eu_urb_op { 36 GEN6_MSG_URB_WRITE = 0x0, 37 GEN6_MSG_URB_FF_SYNC = 0x1, 38 GEN7_MSG_URB_WRITE_HWORD = 0x0, 39 GEN7_MSG_URB_WRITE_OWORD = 0x1, 40 GEN7_MSG_URB_READ_HWORD = 0x2, 41 GEN7_MSG_URB_READ_OWORD = 0x3, 42 GEN7_MSG_URB_ATOMIC_MOV = 0x4, 43 GEN7_MSG_URB_ATOMIC_INC = 0x5, 44 GEN75_MSG_URB_ATOMIC_ADD = 0x6, 45 GEN8_MSG_URB_SIMD8_WRITE = 0x7, 46 GEN8_MSG_URB_SIMD8_READ = 0x8, 47 }; 48 49 enum gen_eu_pi_simd { 50 GEN7_MSG_PI_SIMD8 = 0x0, 51 GEN7_MSG_PI_SIMD16 = 0x1, 52 }; 53 54 enum gen_eu_pi_op { 55 GEN7_MSG_PI_EVAL_SNAPPED_IMM = 0x0, 56 GEN7_MSG_PI_EVAL_SINDEX = 0x1, 57 GEN7_MSG_PI_EVAL_CENTROID = 0x2, 58 GEN7_MSG_PI_EVAL_SNAPPED = 0x3, 59 }; 60 61 enum gen_eu_sampler_simd { 62 GEN6_MSG_SAMPLER_SIMD4X2 = 0x0, 63 GEN9_MSG_SAMPLER_SIMD8D = 0x0, 64 GEN6_MSG_SAMPLER_SIMD8 = 0x1, 65 GEN6_MSG_SAMPLER_SIMD16 = 0x2, 66 GEN6_MSG_SAMPLER_SIMD32_64 = 0x3, 67 }; 68 69 enum gen_eu_sampler_op { 70 GEN6_MSG_SAMPLER_SAMPLE = 0x0, 71 GEN6_MSG_SAMPLER_SAMPLE_B = 0x1, 72 GEN6_MSG_SAMPLER_SAMPLE_L = 0x2, 73 GEN6_MSG_SAMPLER_SAMPLE_C = 0x3, 74 GEN6_MSG_SAMPLER_SAMPLE_D = 0x4, 75 GEN6_MSG_SAMPLER_SAMPLE_B_C = 0x5, 76 GEN6_MSG_SAMPLER_SAMPLE_L_C = 0x6, 77 GEN6_MSG_SAMPLER_LD = 0x7, 78 GEN6_MSG_SAMPLER_GATHER4 = 0x8, 79 GEN6_MSG_SAMPLER_LOD = 0x9, 80 GEN6_MSG_SAMPLER_RESINFO = 0xa, 81 GEN6_MSG_SAMPLER_SAMPLEINFO = 0xb, 82 GEN7_MSG_SAMPLER_GATHER4_C = 0x10, 83 GEN7_MSG_SAMPLER_GATHER4_PO = 0x11, 84 GEN7_MSG_SAMPLER_GATHER4_PO_C = 0x12, 85 GEN7_MSG_SAMPLER_SAMPLE_D_C = 0x14, 86 GEN7_MSG_SAMPLER_SAMPLE_LZ = 0x18, 87 GEN7_MSG_SAMPLER_SAMPLE_C_LC = 0x19, 88 GEN7_MSG_SAMPLER_LD_LZ = 0x1a, 89 GEN7_MSG_SAMPLER_LD_MCS = 0x1d, 90 GEN7_MSG_SAMPLER_LD2DMS = 0x1e, 91 GEN7_MSG_SAMPLER_LD2DSS = 0x1f, 92 }; 93 94 enum gen_eu_dp_op { 95 GEN6_MSG_DP_OWORD_BLOCK_READ = 0x0, 96 GEN6_MSG_DP_RT_UNORM_READ = 0x1, 97 GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ = 0x2, 98 GEN6_MSG_DP_MEDIA_BLOCK_READ = 0x4, 99 GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_READ = 0x5, 100 GEN6_MSG_DP_DWORD_SCATTERED_READ = 0x6, 101 GEN6_MSG_DP_DWORD_ATOMIC_WRITE = 0x7, 102 GEN6_MSG_DP_OWORD_BLOCK_WRITE = 0x8, 103 GEN6_MSG_DP_OWORD_DUAL_BLOCK_WRITE = 0x9, 104 GEN6_MSG_DP_MEDIA_BLOCK_WRITE = 0xa, 105 GEN6_MSG_DP_DWORD_SCATTERED_WRITE = 0xb, 106 GEN6_MSG_DP_RT_WRITE = 0xc, 107 GEN6_MSG_DP_SVB_WRITE = 0xd, 108 GEN6_MSG_DP_RT_UNORM_WRITE = 0xe, 109 GEN7_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ = 0x1, 110 GEN7_MSG_DP_SAMPLER_MEDIA_BLOCK_READ = 0x4, 111 GEN7_MSG_DP_RC_MEDIA_BLOCK_READ = 0x4, 112 GEN7_MSG_DP_RC_TYPED_SURFACE_READ = 0x5, 113 GEN7_MSG_DP_RC_TYPED_ATOMIC_OP = 0x6, 114 GEN7_MSG_DP_RC_MEMORY_FENCE = 0x7, 115 GEN7_MSG_DP_RC_MEDIA_BLOCK_WRITE = 0xa, 116 GEN7_MSG_DP_RC_RT_WRITE = 0xc, 117 GEN7_MSG_DP_RC_TYPED_SURFACE_WRITE = 0xd, 118 GEN7_MSG_DP_CC_OWORD_BLOCK_READ = 0x0, 119 GEN7_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ = 0x1, 120 GEN7_MSG_DP_CC_OWORD_DUAL_BLOCK_READ = 0x2, 121 GEN7_MSG_DP_CC_DWORD_SCATTERED_READ = 0x3, 122 GEN7_MSG_DP_DC0_OWORD_BLOCK_READ = 0x0, 123 GEN7_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ = 0x1, 124 GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ = 0x2, 125 GEN7_MSG_DP_DC0_DWORD_SCATTERED_READ = 0x3, 126 GEN7_MSG_DP_DC0_BYTE_SCATTERED_READ = 0x4, 127 GEN7_MSG_DP_DC0_UNTYPED_SURFACE_READ = 0x5, 128 GEN7_MSG_DP_DC0_UNTYPED_ATOMIC_OP = 0x6, 129 GEN7_MSG_DP_DC0_MEMORY_FENCE = 0x7, 130 GEN7_MSG_DP_DC0_OWORD_BLOCK_WRITE = 0x8, 131 GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE = 0xa, 132 GEN7_MSG_DP_DC0_DWORD_SCATTERED_WRITE = 0xb, 133 GEN7_MSG_DP_DC0_BYTE_SCATTERED_WRITE = 0xc, 134 GEN7_MSG_DP_DC0_UNTYPED_SURFACE_WRITE = 0xd, 135 GEN75_MSG_DP_SAMPLER_READ_SURFACE_INFO = 0x0, 136 GEN75_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ = 0x1, 137 GEN75_MSG_DP_SAMPLER_MEDIA_BLOCK_READ = 0x4, 138 GEN75_MSG_DP_RC_MEDIA_BLOCK_READ = 0x4, 139 GEN75_MSG_DP_RC_MEMORY_FENCE = 0x7, 140 GEN75_MSG_DP_RC_MEDIA_BLOCK_WRITE = 0xa, 141 GEN75_MSG_DP_RC_RT_WRITE = 0xc, 142 GEN8_MSG_DP_RC_RT_READ = 0xd, 143 GEN75_MSG_DP_CC_OWORD_BLOCK_READ = 0x0, 144 GEN75_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ = 0x1, 145 GEN75_MSG_DP_CC_OWORD_DUAL_BLOCK_READ = 0x2, 146 GEN75_MSG_DP_CC_DWORD_SCATTERED_READ = 0x3, 147 GEN75_MSG_DP_DC0_OWORD_BLOCK_READ = 0x0, 148 GEN75_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ = 0x1, 149 GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ = 0x2, 150 GEN75_MSG_DP_DC0_DWORD_SCATTERED_READ = 0x3, 151 GEN75_MSG_DP_DC0_BYTE_SCATTERED_READ = 0x4, 152 GEN75_MSG_DP_DC0_MEMORY_FENCE = 0x7, 153 GEN75_MSG_DP_DC0_OWORD_BLOCK_WRITE = 0x8, 154 GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE = 0xa, 155 GEN75_MSG_DP_DC0_DWORD_SCATTERED_WRITE = 0xb, 156 GEN75_MSG_DP_DC0_BYTE_SCATTERED_WRITE = 0xc, 157 GEN75_MSG_DP_DC1_UNTYPED_SURFACE_READ = 0x1, 158 GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP = 0x2, 159 GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP_SIMD4X2 = 0x3, 160 GEN75_MSG_DP_DC1_MEDIA_BLOCK_READ = 0x4, 161 GEN75_MSG_DP_DC1_TYPED_SURFACE_READ = 0x5, 162 GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP = 0x6, 163 GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP_SIMD4X2 = 0x7, 164 GEN75_MSG_DP_DC1_UNTYPED_SURFACE_WRITE = 0x9, 165 GEN75_MSG_DP_DC1_MEDIA_BLOCK_WRITE = 0xa, 166 GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP = 0xb, 167 GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP_SIMD4X2 = 0xc, 168 GEN75_MSG_DP_DC1_TYPED_SURFACE_WRITE = 0xd, 169 }; 170 171 enum gen_eu_dp_aop { 172 GEN7_MSG_DP_AOP_CMPWR8B = 0x0, 173 GEN7_MSG_DP_AOP_AND = 0x1, 174 GEN7_MSG_DP_AOP_OR = 0x2, 175 GEN7_MSG_DP_AOP_XOR = 0x3, 176 GEN7_MSG_DP_AOP_MOV = 0x4, 177 GEN7_MSG_DP_AOP_INC = 0x5, 178 GEN7_MSG_DP_AOP_DEC = 0x6, 179 GEN7_MSG_DP_AOP_ADD = 0x7, 180 GEN7_MSG_DP_AOP_SUB = 0x8, 181 GEN7_MSG_DP_AOP_REVSUB = 0x9, 182 GEN7_MSG_DP_AOP_IMAX = 0xa, 183 GEN7_MSG_DP_AOP_IMIN = 0xb, 184 GEN7_MSG_DP_AOP_UMAX = 0xc, 185 GEN7_MSG_DP_AOP_UMIN = 0xd, 186 GEN7_MSG_DP_AOP_CMPWR = 0xe, 187 GEN7_MSG_DP_AOP_PREDEC = 0xf, 188 }; 189 190 #define GEN6_MSG_EOT (0x1 << 31) 191 #define GEN6_MSG_MLEN__MASK 0x1e000000 192 #define GEN6_MSG_MLEN__SHIFT 25 193 #define GEN6_MSG_RLEN__MASK 0x01f00000 194 #define GEN6_MSG_RLEN__SHIFT 20 195 #define GEN6_MSG_HEADER_PRESENT (0x1 << 19) 196 #define GEN6_MSG_FUNCTION_CONTROL__MASK 0x0007ffff 197 #define GEN6_MSG_FUNCTION_CONTROL__SHIFT 0 198 #define GEN6_MSG_URB_COMPLETE (0x1 << 15) 199 #define GEN6_MSG_URB_USED (0x1 << 14) 200 #define GEN6_MSG_URB_ALLOCATE (0x1 << 13) 201 #define GEN6_MSG_URB_INTERLEAVED (0x1 << 10) 202 #define GEN6_MSG_URB_OFFSET__MASK 0x000003f0 203 #define GEN6_MSG_URB_OFFSET__SHIFT 4 204 #define GEN6_MSG_URB_OP__MASK 0x0000000f 205 #define GEN6_MSG_URB_OP__SHIFT 0 206 #define GEN7_MSG_URB_PER_SLOT_OFFSET (0x1 << 16) 207 #define GEN7_MSG_URB_COMPLETE (0x1 << 15) 208 #define GEN7_MSG_URB_INTERLEAVED (0x1 << 14) 209 #define GEN7_MSG_URB_GLOBAL_OFFSET__MASK 0x00003ff8 210 #define GEN7_MSG_URB_GLOBAL_OFFSET__SHIFT 3 211 #define GEN7_MSG_URB_OP__MASK 0x00000007 212 #define GEN7_MSG_URB_OP__SHIFT 0 213 #define GEN8_MSG_URB_PER_SLOT_OFFSET (0x1 << 17) 214 #define GEN8_MSG_URB_INTERLEAVED (0x1 << 15) 215 #define GEN8_MSG_URB_GLOBAL_OFFSET__MASK 0x00007ff0 216 #define GEN8_MSG_URB_GLOBAL_OFFSET__SHIFT 4 217 #define GEN8_MSG_URB_OP__MASK 0x0000000f 218 #define GEN8_MSG_URB_OP__SHIFT 0 219 #define GEN7_MSG_PI_SIMD__MASK 0x00010000 220 #define GEN7_MSG_PI_SIMD__SHIFT 16 221 #define GEN7_MSG_PI_LINEAR_INTERP (0x1 << 14) 222 #define GEN7_MSG_PI_OP__MASK 0x00003000 223 #define GEN7_MSG_PI_OP__SHIFT 12 224 #define GEN7_MSG_PI_SLOTGRP_HI (0x1 << 11) 225 #define GEN7_MSG_PI_OFFSET_Y__MASK 0x000000f0 226 #define GEN7_MSG_PI_OFFSET_Y__SHIFT 4 227 #define GEN7_MSG_PI_OFFSET_X__MASK 0x0000000f 228 #define GEN7_MSG_PI_OFFSET_X__SHIFT 0 229 #define GEN7_MSG_PI_SAMPLE_INDEX__MASK 0x000000f0 230 #define GEN7_MSG_PI_SAMPLE_INDEX__SHIFT 4 231 #define GEN6_MSG_SAMPLER_SIMD__MASK 0x00030000 232 #define GEN6_MSG_SAMPLER_SIMD__SHIFT 16 233 #define GEN6_MSG_SAMPLER_OP__MASK 0x0000f000 234 #define GEN6_MSG_SAMPLER_OP__SHIFT 12 235 #define GEN7_MSG_SAMPLER_SIMD__MASK 0x00060000 236 #define GEN7_MSG_SAMPLER_SIMD__SHIFT 17 237 #define GEN7_MSG_SAMPLER_OP__MASK 0x0001f000 238 #define GEN7_MSG_SAMPLER_OP__SHIFT 12 239 #define GEN6_MSG_SAMPLER_INDEX__MASK 0x00000f00 240 #define GEN6_MSG_SAMPLER_INDEX__SHIFT 8 241 #define GEN6_MSG_SAMPLER_SURFACE__MASK 0x000000ff 242 #define GEN6_MSG_SAMPLER_SURFACE__SHIFT 0 243 #define GEN6_MSG_DP_SEND_WRITE_COMMIT (0x1 << 17) 244 #define GEN6_MSG_DP_OP__MASK 0x0001e000 245 #define GEN6_MSG_DP_OP__SHIFT 13 246 #define GEN6_MSG_DP_CTRL__MASK 0x00001f00 247 #define GEN6_MSG_DP_CTRL__SHIFT 8 248 #define GEN7_MSG_DP_CATEGORY (0x1 << 18) 249 #define GEN7_MSG_DP_OP__MASK 0x0003c000 250 #define GEN7_MSG_DP_OP__SHIFT 14 251 #define GEN7_MSG_DP_CTRL__MASK 0x00003f00 252 #define GEN7_MSG_DP_CTRL__SHIFT 8 253 #define GEN7_MSG_DP_OWORD_BLOCK_READ_INVALIDATE (0x1 << 13) 254 #define GEN6_MSG_DP_OWORD_BLOCK_SIZE__MASK 0x00000700 255 #define GEN6_MSG_DP_OWORD_BLOCK_SIZE__SHIFT 8 256 #define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_LO (0x0 << 8) 257 #define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_HI (0x1 << 8) 258 #define GEN6_MSG_DP_OWORD_BLOCK_SIZE_2 (0x2 << 8) 259 #define GEN6_MSG_DP_OWORD_BLOCK_SIZE_4 (0x3 << 8) 260 #define GEN6_MSG_DP_OWORD_BLOCK_SIZE_8 (0x4 << 8) 261 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__MASK 0x00000700 262 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__SHIFT 8 263 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_LO (0x0 << 8) 264 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_HI (0x1 << 8) 265 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_2 (0x2 << 8) 266 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_4 (0x3 << 8) 267 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_8 (0x4 << 8) 268 #define GEN7_MSG_DP_OWORD_DUAL_BLOCK_READ_INVALIDATE (0x1 << 13) 269 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__MASK 0x00000300 270 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__SHIFT 8 271 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1 (0x0 << 8) 272 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_4 (0x2 << 8) 273 #define GEN7_MSG_DP_DWORD_SCATTERED_READ_INVALIDATE (0x1 << 13) 274 #define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE__MASK 0x00000300 275 #define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE__SHIFT 8 276 #define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE_8 (0x2 << 8) 277 #define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE_16 (0x3 << 8) 278 #define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE__MASK 0x00000600 279 #define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE__SHIFT 9 280 #define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_1 (0x0 << 9) 281 #define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_2 (0x1 << 9) 282 #define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_4 (0x2 << 9) 283 #define GEN6_MSG_DP_BYTE_SCATTERED_MODE__MASK 0x00000100 284 #define GEN6_MSG_DP_BYTE_SCATTERED_MODE__SHIFT 8 285 #define GEN6_MSG_DP_BYTE_SCATTERED_MODE_SIMD8 (0x0 << 8) 286 #define GEN6_MSG_DP_BYTE_SCATTERED_MODE_SIMD16 (0x1 << 8) 287 #define GEN6_MSG_DP_RT_LAST (0x1 << 12) 288 #define GEN6_MSG_DP_RT_SLOTGRP_HI (0x1 << 11) 289 #define GEN6_MSG_DP_RT_MODE__MASK 0x00000700 290 #define GEN6_MSG_DP_RT_MODE__SHIFT 8 291 #define GEN6_MSG_DP_RT_MODE_SIMD16 (0x0 << 8) 292 #define GEN6_MSG_DP_RT_MODE_SIMD16_REPDATA (0x1 << 8) 293 #define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_LO (0x2 << 8) 294 #define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI (0x3 << 8) 295 #define GEN6_MSG_DP_RT_MODE_SIMD8_LO (0x4 << 8) 296 #define GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR (0x5 << 8) 297 #define GEN7_MSG_DP_TYPED_SLOTGRP_HI (0x1 << 13) 298 #define GEN7_MSG_DP_TYPED_MASK__MASK 0x00000f00 299 #define GEN7_MSG_DP_TYPED_MASK__SHIFT 8 300 #define GEN7_MSG_DP_UNTYPED_MODE__MASK 0x00003000 301 #define GEN7_MSG_DP_UNTYPED_MODE__SHIFT 12 302 #define GEN7_MSG_DP_UNTYPED_MODE_SIMD4X2 (0x0 << 12) 303 #define GEN7_MSG_DP_UNTYPED_MODE_SIMD16 (0x1 << 12) 304 #define GEN7_MSG_DP_UNTYPED_MODE_SIMD8 (0x2 << 12) 305 #define GEN7_MSG_DP_UNTYPED_MASK__MASK 0x00000f00 306 #define GEN7_MSG_DP_UNTYPED_MASK__SHIFT 8 307 #define GEN7_MSG_DP_ATOMIC_RETURN_DATA_ENABLE (0x1 << 13) 308 #define GEN7_MSG_DP_ATOMIC_TYPED_SLOTGRP_HI (0x1 << 12) 309 #define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE__MASK 0x00001000 310 #define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE__SHIFT 12 311 #define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE_SIMD16 (0x0 << 12) 312 #define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE_SIMD8 (0x1 << 12) 313 #define GEN7_MSG_DP_ATOMIC_OP__MASK 0x00000f00 314 #define GEN7_MSG_DP_ATOMIC_OP__SHIFT 8 315 #define GEN6_MSG_DP_SURFACE__MASK 0x000000ff 316 #define GEN6_MSG_DP_SURFACE__SHIFT 0 317 #define GEN6_MSG_TS_RESOURCE_SELECT__MASK 0x00000010 318 #define GEN6_MSG_TS_RESOURCE_SELECT__SHIFT 4 319 #define GEN6_MSG_TS_RESOURCE_SELECT_CHILD (0x0 << 4) 320 #define GEN6_MSG_TS_RESOURCE_SELECT_ROOT (0x1 << 4) 321 #define GEN6_MSG_TS_RESOURCE_SELECT_DEREF (0x0 << 4) 322 #define GEN6_MSG_TS_RESOURCE_SELECT_NO_DEREF (0x1 << 4) 323 #define GEN6_MSG_TS_REQUESTER_TYPE__MASK 0x00000002 324 #define GEN6_MSG_TS_REQUESTER_TYPE__SHIFT 1 325 #define GEN6_MSG_TS_REQUESTER_TYPE_ROOT (0x0 << 1) 326 #define GEN6_MSG_TS_REQUESTER_TYPE_CHILD (0x1 << 1) 327 #define GEN6_MSG_TS_OPCODE__MASK 0x00000001 328 #define GEN6_MSG_TS_OPCODE__SHIFT 0 329 #define GEN6_MSG_TS_OPCODE_DEREF 0x0 330 #define GEN6_MSG_TS_OPCODE_SPAWN 0x1 331 332 #endif /* GEN_EU_MESSAGE_XML */ 333
