| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 61 const MCOperand &MO1 = MI->getOperand(1);
70 << ", " << getRegisterName(MO1.getReg());
81 const MCOperand &MO1 = MI->getOperand(1);
89 << ", " << getRegisterName(MO1.getReg());
226 const MCOperand &MO1 = MI->getOperand(OpNum);
227 if (MO1.isExpr())
228 O << *MO1.getExpr();
229 else if (MO1.isImm())
230 O << "[pc, #" << MO1.getImm() << "]";
242 const MCOperand &MO1 = MI->getOperand(OpNum)
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 81 const MCOperand &MO1 = MI->getOperand(1);
92 printRegName(O, MO1.getReg());
104 const MCOperand &MO1 = MI->getOperand(1);
114 printRegName(O, MO1.getReg());
315 const MCOperand &MO1 = MI->getOperand(OpNum);
316 if (MO1.isExpr()) {
317 MO1.getExpr()->print(O, &MAI);
323 int32_t OffImm = (int32_t)MO1.getImm();
345 const MCOperand &MO1 = MI->getOperand(OpNum);
349 printRegName(O, MO1.getReg())
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 55 static inline bool isIdenticalOp(const MachineOperand &MO1,
60 static bool isSimilarDispOp(const MachineOperand &MO1,
181 static inline bool isIdenticalOp(const MachineOperand &MO1,
183 return MO1.isIdenticalTo(MO2) &&
184 (!MO1.isReg() ||
185 !TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
195 static bool isSimilarDispOp(const MachineOperand &MO1,
197 assert(isValidDispOp(MO1) && isValidDispOp(MO2) &&
199 return (MO1.isImm() && MO2.isImm()) ||
200 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) |
[all...] |
| X86FloatingPoint.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 434 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
438 int32_t SImm = MO1.getImm();
690 const MCOperand &MO1 = MI.getOperand(OpIdx);
692 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
823 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
825 unsigned Imm8 = MO1.getImm();
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86CodeEmitter.cpp | 826 const MachineOperand &MO1 = MI.getOperand(CurOp++);
828 if (MO1.isImm()) {
829 emitConstant(MO1.getImm(), Size);
840 if (MO1.isGlobal()) {
841 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
842 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
844 } else if (MO1.isSymbol())
845 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
846 else if (MO1.isCPI()
[all...] |
| X86FloatingPoint.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 555 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
559 int32_t SImm = MO1.getImm();
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 837 const MachineOperand &MO1 = MI.getOperand(1);
838 unsigned Flags = MO1.getTargetFlags();
846 if (MO1.isGlobal()) {
847 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE);
848 MIB2.addGlobalAddress(MO1.getGlobal(), 0,
850 } else if (MO1.isSymbol()) {
851 MIB1.addExternalSymbol(MO1.getSymbolName(), Flags | AArch64II::MO_PAGE);
852 MIB2.addExternalSymbol(MO1.getSymbolName(),
855 assert(MO1.isCPI() &&
857 MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 250 const MachineOperand &MO1 = MI.getOperand(Op + 1);
256 int32_t Imm12 = MO1.getImm();
292 const MachineOperand &MO1 = MI.getOperand(Op + 1);
298 int32_t Imm12 = MO1.getImm();
686 const MachineOperand &MO1 = MI.getOperand(1);
691 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
704 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
722 const MachineOperand &MO1 = MI.getOperand(1);
723 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &
[all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ProcessImplicitDefs.cpp | 66 MachineOperand &MO1 = MI->getOperand(1);
67 if (MO1.getReg() != Reg)
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 249 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
250 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
252 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 412 MCOperand &MO1 = MappedInst.getOperand(1);
413 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg);
414 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg);
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
