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      1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the pass that transforms the X86 machine instructions into
     11 // relocatable machine code.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #define DEBUG_TYPE "x86-emitter"
     16 #include "X86InstrInfo.h"
     17 #include "X86JITInfo.h"
     18 #include "X86Subtarget.h"
     19 #include "X86TargetMachine.h"
     20 #include "X86Relocations.h"
     21 #include "X86.h"
     22 #include "llvm/LLVMContext.h"
     23 #include "llvm/PassManager.h"
     24 #include "llvm/CodeGen/JITCodeEmitter.h"
     25 #include "llvm/CodeGen/MachineFunctionPass.h"
     26 #include "llvm/CodeGen/MachineInstr.h"
     27 #include "llvm/CodeGen/MachineModuleInfo.h"
     28 #include "llvm/CodeGen/Passes.h"
     29 #include "llvm/Function.h"
     30 #include "llvm/ADT/Statistic.h"
     31 #include "llvm/MC/MCCodeEmitter.h"
     32 #include "llvm/MC/MCExpr.h"
     33 #include "llvm/MC/MCInst.h"
     34 #include "llvm/Support/Debug.h"
     35 #include "llvm/Support/ErrorHandling.h"
     36 #include "llvm/Support/raw_ostream.h"
     37 #include "llvm/Target/TargetOptions.h"
     38 using namespace llvm;
     39 
     40 STATISTIC(NumEmitted, "Number of machine instructions emitted");
     41 
     42 namespace {
     43   template<class CodeEmitter>
     44   class Emitter : public MachineFunctionPass {
     45     const X86InstrInfo  *II;
     46     const TargetData    *TD;
     47     X86TargetMachine    &TM;
     48     CodeEmitter         &MCE;
     49     MachineModuleInfo   *MMI;
     50     intptr_t PICBaseOffset;
     51     bool Is64BitMode;
     52     bool IsPIC;
     53   public:
     54     static char ID;
     55     explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
     56       : MachineFunctionPass(ID), II(0), TD(0), TM(tm),
     57       MCE(mce), PICBaseOffset(0), Is64BitMode(false),
     58       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
     59     Emitter(X86TargetMachine &tm, CodeEmitter &mce,
     60             const X86InstrInfo &ii, const TargetData &td, bool is64)
     61       : MachineFunctionPass(ID), II(&ii), TD(&td), TM(tm),
     62       MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
     63       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
     64 
     65     bool runOnMachineFunction(MachineFunction &MF);
     66 
     67     virtual const char *getPassName() const {
     68       return "X86 Machine Code Emitter";
     69     }
     70 
     71     void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
     72 
     73     void getAnalysisUsage(AnalysisUsage &AU) const {
     74       AU.setPreservesAll();
     75       AU.addRequired<MachineModuleInfo>();
     76       MachineFunctionPass::getAnalysisUsage(AU);
     77     }
     78 
     79   private:
     80     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
     81     void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
     82                            intptr_t Disp = 0, intptr_t PCAdj = 0,
     83                            bool Indirect = false);
     84     void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
     85     void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
     86                               intptr_t PCAdj = 0);
     87     void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
     88                               intptr_t PCAdj = 0);
     89 
     90     void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
     91                                intptr_t Adj = 0, bool IsPCRel = true);
     92 
     93     void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
     94     void emitRegModRMByte(unsigned RegOpcodeField);
     95     void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
     96     void emitConstant(uint64_t Val, unsigned Size);
     97 
     98     void emitMemModRMByte(const MachineInstr &MI,
     99                           unsigned Op, unsigned RegOpcodeField,
    100                           intptr_t PCAdj = 0);
    101   };
    102 
    103 template<class CodeEmitter>
    104   char Emitter<CodeEmitter>::ID = 0;
    105 } // end anonymous namespace.
    106 
    107 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
    108 /// to the specified templated MachineCodeEmitter object.
    109 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
    110                                                 JITCodeEmitter &JCE) {
    111   return new Emitter<JITCodeEmitter>(TM, JCE);
    112 }
    113 
    114 template<class CodeEmitter>
    115 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
    116   MMI = &getAnalysis<MachineModuleInfo>();
    117   MCE.setModuleInfo(MMI);
    118 
    119   II = TM.getInstrInfo();
    120   TD = TM.getTargetData();
    121   Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
    122   IsPIC = TM.getRelocationModel() == Reloc::PIC_;
    123 
    124   do {
    125     DEBUG(dbgs() << "JITTing function '"
    126           << MF.getFunction()->getName() << "'\n");
    127     MCE.startFunction(MF);
    128     for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
    129          MBB != E; ++MBB) {
    130       MCE.StartMachineBasicBlock(MBB);
    131       for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
    132            I != E; ++I) {
    133         const MCInstrDesc &Desc = I->getDesc();
    134         emitInstruction(*I, &Desc);
    135         // MOVPC32r is basically a call plus a pop instruction.
    136         if (Desc.getOpcode() == X86::MOVPC32r)
    137           emitInstruction(*I, &II->get(X86::POP32r));
    138         ++NumEmitted;  // Keep track of the # of mi's emitted
    139       }
    140     }
    141   } while (MCE.finishFunction(MF));
    142 
    143   return false;
    144 }
    145 
    146 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
    147 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
    148 /// size, and 3) use of X86-64 extended registers.
    149 static unsigned determineREX(const MachineInstr &MI) {
    150   unsigned REX = 0;
    151   const MCInstrDesc &Desc = MI.getDesc();
    152 
    153   // Pseudo instructions do not need REX prefix byte.
    154   if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
    155     return 0;
    156   if (Desc.TSFlags & X86II::REX_W)
    157     REX |= 1 << 3;
    158 
    159   unsigned NumOps = Desc.getNumOperands();
    160   if (NumOps) {
    161     bool isTwoAddr = NumOps > 1 &&
    162     Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
    163 
    164     // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
    165     unsigned i = isTwoAddr ? 1 : 0;
    166     for (unsigned e = NumOps; i != e; ++i) {
    167       const MachineOperand& MO = MI.getOperand(i);
    168       if (MO.isReg()) {
    169         unsigned Reg = MO.getReg();
    170         if (X86II::isX86_64NonExtLowByteReg(Reg))
    171           REX |= 0x40;
    172       }
    173     }
    174 
    175     switch (Desc.TSFlags & X86II::FormMask) {
    176       case X86II::MRMInitReg:
    177         if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
    178           REX |= (1 << 0) | (1 << 2);
    179         break;
    180       case X86II::MRMSrcReg: {
    181         if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
    182           REX |= 1 << 2;
    183         i = isTwoAddr ? 2 : 1;
    184         for (unsigned e = NumOps; i != e; ++i) {
    185           const MachineOperand& MO = MI.getOperand(i);
    186           if (X86InstrInfo::isX86_64ExtendedReg(MO))
    187             REX |= 1 << 0;
    188         }
    189         break;
    190       }
    191       case X86II::MRMSrcMem: {
    192         if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
    193           REX |= 1 << 2;
    194         unsigned Bit = 0;
    195         i = isTwoAddr ? 2 : 1;
    196         for (; i != NumOps; ++i) {
    197           const MachineOperand& MO = MI.getOperand(i);
    198           if (MO.isReg()) {
    199             if (X86InstrInfo::isX86_64ExtendedReg(MO))
    200               REX |= 1 << Bit;
    201             Bit++;
    202           }
    203         }
    204         break;
    205       }
    206       case X86II::MRM0m: case X86II::MRM1m:
    207       case X86II::MRM2m: case X86II::MRM3m:
    208       case X86II::MRM4m: case X86II::MRM5m:
    209       case X86II::MRM6m: case X86II::MRM7m:
    210       case X86II::MRMDestMem: {
    211         unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
    212         i = isTwoAddr ? 1 : 0;
    213         if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
    214           REX |= 1 << 2;
    215         unsigned Bit = 0;
    216         for (; i != e; ++i) {
    217           const MachineOperand& MO = MI.getOperand(i);
    218           if (MO.isReg()) {
    219             if (X86InstrInfo::isX86_64ExtendedReg(MO))
    220               REX |= 1 << Bit;
    221             Bit++;
    222           }
    223         }
    224         break;
    225       }
    226       default: {
    227         if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
    228           REX |= 1 << 0;
    229         i = isTwoAddr ? 2 : 1;
    230         for (unsigned e = NumOps; i != e; ++i) {
    231           const MachineOperand& MO = MI.getOperand(i);
    232           if (X86InstrInfo::isX86_64ExtendedReg(MO))
    233             REX |= 1 << 2;
    234         }
    235         break;
    236       }
    237     }
    238   }
    239   return REX;
    240 }
    241 
    242 
    243 /// emitPCRelativeBlockAddress - This method keeps track of the information
    244 /// necessary to resolve the address of this block later and emits a dummy
    245 /// value.
    246 ///
    247 template<class CodeEmitter>
    248 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
    249   // Remember where this reference was and where it is to so we can
    250   // deal with it later.
    251   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
    252                                              X86::reloc_pcrel_word, MBB));
    253   MCE.emitWordLE(0);
    254 }
    255 
    256 /// emitGlobalAddress - Emit the specified address to the code stream assuming
    257 /// this is part of a "take the address of a global" instruction.
    258 ///
    259 template<class CodeEmitter>
    260 void Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV,
    261                                 unsigned Reloc,
    262                                 intptr_t Disp /* = 0 */,
    263                                 intptr_t PCAdj /* = 0 */,
    264                                 bool Indirect /* = false */) {
    265   intptr_t RelocCST = Disp;
    266   if (Reloc == X86::reloc_picrel_word)
    267     RelocCST = PICBaseOffset;
    268   else if (Reloc == X86::reloc_pcrel_word)
    269     RelocCST = PCAdj;
    270   MachineRelocation MR = Indirect
    271     ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
    272                                            const_cast<GlobalValue *>(GV),
    273                                            RelocCST, false)
    274     : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
    275                                const_cast<GlobalValue *>(GV), RelocCST, false);
    276   MCE.addRelocation(MR);
    277   // The relocated value will be added to the displacement
    278   if (Reloc == X86::reloc_absolute_dword)
    279     MCE.emitDWordLE(Disp);
    280   else
    281     MCE.emitWordLE((int32_t)Disp);
    282 }
    283 
    284 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
    285 /// be emitted to the current location in the function, and allow it to be PC
    286 /// relative.
    287 template<class CodeEmitter>
    288 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
    289                                                      unsigned Reloc) {
    290   intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
    291 
    292   // X86 never needs stubs because instruction selection will always pick
    293   // an instruction sequence that is large enough to hold any address
    294   // to a symbol.
    295   // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall)
    296   bool NeedStub = false;
    297   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
    298                                                  Reloc, ES, RelocCST,
    299                                                  0, NeedStub));
    300   if (Reloc == X86::reloc_absolute_dword)
    301     MCE.emitDWordLE(0);
    302   else
    303     MCE.emitWordLE(0);
    304 }
    305 
    306 /// emitConstPoolAddress - Arrange for the address of an constant pool
    307 /// to be emitted to the current location in the function, and allow it to be PC
    308 /// relative.
    309 template<class CodeEmitter>
    310 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
    311                                    intptr_t Disp /* = 0 */,
    312                                    intptr_t PCAdj /* = 0 */) {
    313   intptr_t RelocCST = 0;
    314   if (Reloc == X86::reloc_picrel_word)
    315     RelocCST = PICBaseOffset;
    316   else if (Reloc == X86::reloc_pcrel_word)
    317     RelocCST = PCAdj;
    318   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
    319                                                     Reloc, CPI, RelocCST));
    320   // The relocated value will be added to the displacement
    321   if (Reloc == X86::reloc_absolute_dword)
    322     MCE.emitDWordLE(Disp);
    323   else
    324     MCE.emitWordLE((int32_t)Disp);
    325 }
    326 
    327 /// emitJumpTableAddress - Arrange for the address of a jump table to
    328 /// be emitted to the current location in the function, and allow it to be PC
    329 /// relative.
    330 template<class CodeEmitter>
    331 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
    332                                    intptr_t PCAdj /* = 0 */) {
    333   intptr_t RelocCST = 0;
    334   if (Reloc == X86::reloc_picrel_word)
    335     RelocCST = PICBaseOffset;
    336   else if (Reloc == X86::reloc_pcrel_word)
    337     RelocCST = PCAdj;
    338   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
    339                                                     Reloc, JTI, RelocCST));
    340   // The relocated value will be added to the displacement
    341   if (Reloc == X86::reloc_absolute_dword)
    342     MCE.emitDWordLE(0);
    343   else
    344     MCE.emitWordLE(0);
    345 }
    346 
    347 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
    348                                       unsigned RM) {
    349   assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
    350   return RM | (RegOpcode << 3) | (Mod << 6);
    351 }
    352 
    353 template<class CodeEmitter>
    354 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
    355                                             unsigned RegOpcodeFld){
    356   MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg)));
    357 }
    358 
    359 template<class CodeEmitter>
    360 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
    361   MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
    362 }
    363 
    364 template<class CodeEmitter>
    365 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
    366                                        unsigned Index,
    367                                        unsigned Base) {
    368   // SIB byte is in the same format as the ModRMByte...
    369   MCE.emitByte(ModRMByte(SS, Index, Base));
    370 }
    371 
    372 template<class CodeEmitter>
    373 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
    374   // Output the constant in little endian byte order...
    375   for (unsigned i = 0; i != Size; ++i) {
    376     MCE.emitByte(Val & 255);
    377     Val >>= 8;
    378   }
    379 }
    380 
    381 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
    382 /// sign-extended field.
    383 static bool isDisp8(int Value) {
    384   return Value == (signed char)Value;
    385 }
    386 
    387 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
    388                               const TargetMachine &TM) {
    389   // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
    390   // mechanism as 32-bit mode.
    391   if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
    392       !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
    393     return false;
    394 
    395   // Return true if this is a reference to a stub containing the address of the
    396   // global, not the global itself.
    397   return isGlobalStubReference(GVOp.getTargetFlags());
    398 }
    399 
    400 template<class CodeEmitter>
    401 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
    402                                                  int DispVal,
    403                                                  intptr_t Adj /* = 0 */,
    404                                                  bool IsPCRel /* = true */) {
    405   // If this is a simple integer displacement that doesn't require a relocation,
    406   // emit it now.
    407   if (!RelocOp) {
    408     emitConstant(DispVal, 4);
    409     return;
    410   }
    411 
    412   // Otherwise, this is something that requires a relocation.  Emit it as such
    413   // now.
    414   unsigned RelocType = Is64BitMode ?
    415     (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
    416     : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
    417   if (RelocOp->isGlobal()) {
    418     // In 64-bit static small code model, we could potentially emit absolute.
    419     // But it's probably not beneficial. If the MCE supports using RIP directly
    420     // do it, otherwise fallback to absolute (this is determined by IsPCRel).
    421     //  89 05 00 00 00 00     mov    %eax,0(%rip)  # PC-relative
    422     //  89 04 25 00 00 00 00  mov    %eax,0x0      # Absolute
    423     bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
    424     emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
    425                       Adj, Indirect);
    426   } else if (RelocOp->isSymbol()) {
    427     emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
    428   } else if (RelocOp->isCPI()) {
    429     emitConstPoolAddress(RelocOp->getIndex(), RelocType,
    430                          RelocOp->getOffset(), Adj);
    431   } else {
    432     assert(RelocOp->isJTI() && "Unexpected machine operand!");
    433     emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
    434   }
    435 }
    436 
    437 template<class CodeEmitter>
    438 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
    439                                             unsigned Op,unsigned RegOpcodeField,
    440                                             intptr_t PCAdj) {
    441   const MachineOperand &Op3 = MI.getOperand(Op+3);
    442   int DispVal = 0;
    443   const MachineOperand *DispForReloc = 0;
    444 
    445   // Figure out what sort of displacement we have to handle here.
    446   if (Op3.isGlobal()) {
    447     DispForReloc = &Op3;
    448   } else if (Op3.isSymbol()) {
    449     DispForReloc = &Op3;
    450   } else if (Op3.isCPI()) {
    451     if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
    452       DispForReloc = &Op3;
    453     } else {
    454       DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
    455       DispVal += Op3.getOffset();
    456     }
    457   } else if (Op3.isJTI()) {
    458     if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
    459       DispForReloc = &Op3;
    460     } else {
    461       DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
    462     }
    463   } else {
    464     DispVal = Op3.getImm();
    465   }
    466 
    467   const MachineOperand &Base     = MI.getOperand(Op);
    468   const MachineOperand &Scale    = MI.getOperand(Op+1);
    469   const MachineOperand &IndexReg = MI.getOperand(Op+2);
    470 
    471   unsigned BaseReg = Base.getReg();
    472 
    473   // Handle %rip relative addressing.
    474   if (BaseReg == X86::RIP ||
    475       (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode
    476     assert(IndexReg.getReg() == 0 && Is64BitMode &&
    477            "Invalid rip-relative address");
    478     MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
    479     emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
    480     return;
    481   }
    482 
    483   // Indicate that the displacement will use an pcrel or absolute reference
    484   // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
    485   // while others, unless explicit asked to use RIP, use absolute references.
    486   bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
    487 
    488   // Is a SIB byte needed?
    489   // If no BaseReg, issue a RIP relative instruction only if the MCE can
    490   // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
    491   // 2-7) and absolute references.
    492   unsigned BaseRegNo = -1U;
    493   if (BaseReg != 0 && BaseReg != X86::RIP)
    494     BaseRegNo = X86_MC::getX86RegNum(BaseReg);
    495 
    496   if (// The SIB byte must be used if there is an index register.
    497       IndexReg.getReg() == 0 &&
    498       // The SIB byte must be used if the base is ESP/RSP/R12, all of which
    499       // encode to an R/M value of 4, which indicates that a SIB byte is
    500       // present.
    501       BaseRegNo != N86::ESP &&
    502       // If there is no base register and we're in 64-bit mode, we need a SIB
    503       // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
    504       (!Is64BitMode || BaseReg != 0)) {
    505     if (BaseReg == 0 ||          // [disp32]     in X86-32 mode
    506         BaseReg == X86::RIP) {   // [disp32+RIP] in X86-64 mode
    507       MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
    508       emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
    509       return;
    510     }
    511 
    512     // If the base is not EBP/ESP and there is no displacement, use simple
    513     // indirect register encoding, this handles addresses like [EAX].  The
    514     // encoding for [EBP] with no displacement means [disp32] so we handle it
    515     // by emitting a displacement of 0 below.
    516     if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
    517       MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
    518       return;
    519     }
    520 
    521     // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
    522     if (!DispForReloc && isDisp8(DispVal)) {
    523       MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
    524       emitConstant(DispVal, 1);
    525       return;
    526     }
    527 
    528     // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
    529     MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
    530     emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
    531     return;
    532   }
    533 
    534   // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first.
    535   assert(IndexReg.getReg() != X86::ESP &&
    536          IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
    537 
    538   bool ForceDisp32 = false;
    539   bool ForceDisp8  = false;
    540   if (BaseReg == 0) {
    541     // If there is no base register, we emit the special case SIB byte with
    542     // MOD=0, BASE=4, to JUST get the index, scale, and displacement.
    543     MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
    544     ForceDisp32 = true;
    545   } else if (DispForReloc) {
    546     // Emit the normal disp32 encoding.
    547     MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
    548     ForceDisp32 = true;
    549   } else if (DispVal == 0 && BaseRegNo != N86::EBP) {
    550     // Emit no displacement ModR/M byte
    551     MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
    552   } else if (isDisp8(DispVal)) {
    553     // Emit the disp8 encoding...
    554     MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
    555     ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
    556   } else {
    557     // Emit the normal disp32 encoding...
    558     MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
    559   }
    560 
    561   // Calculate what the SS field value should be...
    562   static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
    563   unsigned SS = SSTable[Scale.getImm()];
    564 
    565   if (BaseReg == 0) {
    566     // Handle the SIB byte for the case where there is no base, see Intel
    567     // Manual 2A, table 2-7. The displacement has already been output.
    568     unsigned IndexRegNo;
    569     if (IndexReg.getReg())
    570       IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
    571     else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
    572       IndexRegNo = 4;
    573     emitSIBByte(SS, IndexRegNo, 5);
    574   } else {
    575     unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg);
    576     unsigned IndexRegNo;
    577     if (IndexReg.getReg())
    578       IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
    579     else
    580       IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
    581     emitSIBByte(SS, IndexRegNo, BaseRegNo);
    582   }
    583 
    584   // Do we need to output a displacement?
    585   if (ForceDisp8) {
    586     emitConstant(DispVal, 1);
    587   } else if (DispVal != 0 || ForceDisp32) {
    588     emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
    589   }
    590 }
    591 
    592 static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II,
    593                                    unsigned Opcode) {
    594   const MCInstrDesc *Desc = &II->get(Opcode);
    595   MI.setDesc(*Desc);
    596   return Desc;
    597 }
    598 
    599 template<class CodeEmitter>
    600 void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
    601                                            const MCInstrDesc *Desc) {
    602   DEBUG(dbgs() << MI);
    603 
    604   // If this is a pseudo instruction, lower it.
    605   switch (Desc->getOpcode()) {
    606   case X86::ADD16rr_DB:      Desc = UpdateOp(MI, II, X86::OR16rr); break;
    607   case X86::ADD32rr_DB:      Desc = UpdateOp(MI, II, X86::OR32rr); break;
    608   case X86::ADD64rr_DB:      Desc = UpdateOp(MI, II, X86::OR64rr); break;
    609   case X86::ADD16ri_DB:      Desc = UpdateOp(MI, II, X86::OR16ri); break;
    610   case X86::ADD32ri_DB:      Desc = UpdateOp(MI, II, X86::OR32ri); break;
    611   case X86::ADD64ri32_DB:    Desc = UpdateOp(MI, II, X86::OR64ri32); break;
    612   case X86::ADD16ri8_DB:     Desc = UpdateOp(MI, II, X86::OR16ri8); break;
    613   case X86::ADD32ri8_DB:     Desc = UpdateOp(MI, II, X86::OR32ri8); break;
    614   case X86::ADD64ri8_DB:     Desc = UpdateOp(MI, II, X86::OR64ri8); break;
    615   case X86::ACQUIRE_MOV8rm:  Desc = UpdateOp(MI, II, X86::MOV8rm); break;
    616   case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break;
    617   case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break;
    618   case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break;
    619   case X86::RELEASE_MOV8mr:  Desc = UpdateOp(MI, II, X86::MOV8mr); break;
    620   case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break;
    621   case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
    622   case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
    623   }
    624 
    625 
    626   MCE.processDebugLoc(MI.getDebugLoc(), true);
    627 
    628   unsigned Opcode = Desc->Opcode;
    629 
    630   // Emit the lock opcode prefix as needed.
    631   if (Desc->TSFlags & X86II::LOCK)
    632     MCE.emitByte(0xF0);
    633 
    634   // Emit segment override opcode prefix as needed.
    635   switch (Desc->TSFlags & X86II::SegOvrMask) {
    636   case X86II::FS:
    637     MCE.emitByte(0x64);
    638     break;
    639   case X86II::GS:
    640     MCE.emitByte(0x65);
    641     break;
    642   default: llvm_unreachable("Invalid segment!");
    643   case 0: break;  // No segment override!
    644   }
    645 
    646   // Emit the repeat opcode prefix as needed.
    647   if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
    648     MCE.emitByte(0xF3);
    649 
    650   // Emit the operand size opcode prefix as needed.
    651   if (Desc->TSFlags & X86II::OpSize)
    652     MCE.emitByte(0x66);
    653 
    654   // Emit the address size opcode prefix as needed.
    655   if (Desc->TSFlags & X86II::AdSize)
    656     MCE.emitByte(0x67);
    657 
    658   bool Need0FPrefix = false;
    659   switch (Desc->TSFlags & X86II::Op0Mask) {
    660   case X86II::TB:  // Two-byte opcode prefix
    661   case X86II::T8:  // 0F 38
    662   case X86II::TA:  // 0F 3A
    663   case X86II::A6:  // 0F A6
    664   case X86II::A7:  // 0F A7
    665     Need0FPrefix = true;
    666     break;
    667   case X86II::TF: // F2 0F 38
    668     MCE.emitByte(0xF2);
    669     Need0FPrefix = true;
    670     break;
    671   case X86II::REP: break; // already handled.
    672   case X86II::XS:   // F3 0F
    673     MCE.emitByte(0xF3);
    674     Need0FPrefix = true;
    675     break;
    676   case X86II::XD:   // F2 0F
    677     MCE.emitByte(0xF2);
    678     Need0FPrefix = true;
    679     break;
    680   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
    681   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
    682     MCE.emitByte(0xD8+
    683                  (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
    684                                    >> X86II::Op0Shift));
    685     break; // Two-byte opcode prefix
    686   default: llvm_unreachable("Invalid prefix!");
    687   case 0: break;  // No prefix!
    688   }
    689 
    690   // Handle REX prefix.
    691   if (Is64BitMode) {
    692     if (unsigned REX = determineREX(MI))
    693       MCE.emitByte(0x40 | REX);
    694   }
    695 
    696   // 0x0F escape code must be emitted just before the opcode.
    697   if (Need0FPrefix)
    698     MCE.emitByte(0x0F);
    699 
    700   switch (Desc->TSFlags & X86II::Op0Mask) {
    701   case X86II::TF:    // F2 0F 38
    702   case X86II::T8:    // 0F 38
    703     MCE.emitByte(0x38);
    704     break;
    705   case X86II::TA:    // 0F 3A
    706     MCE.emitByte(0x3A);
    707     break;
    708   case X86II::A6:    // 0F A6
    709     MCE.emitByte(0xA6);
    710     break;
    711   case X86II::A7:    // 0F A7
    712     MCE.emitByte(0xA7);
    713     break;
    714   }
    715 
    716   // If this is a two-address instruction, skip one of the register operands.
    717   unsigned NumOps = Desc->getNumOperands();
    718   unsigned CurOp = 0;
    719   if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1)
    720     ++CurOp;
    721   else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1,MCOI::TIED_TO)== 0)
    722     // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
    723     --NumOps;
    724 
    725   unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags);
    726   switch (Desc->TSFlags & X86II::FormMask) {
    727   default:
    728     llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
    729   case X86II::Pseudo:
    730     // Remember the current PC offset, this is the PIC relocation
    731     // base address.
    732     switch (Opcode) {
    733     default:
    734       llvm_unreachable("pseudo instructions should be removed before code"
    735                        " emission");
    736       break;
    737     // Do nothing for Int_MemBarrier - it's just a comment.  Add a debug
    738     // to make it slightly easier to see.
    739     case X86::Int_MemBarrier:
    740       DEBUG(dbgs() << "#MEMBARRIER\n");
    741       break;
    742 
    743     case TargetOpcode::INLINEASM:
    744       // We allow inline assembler nodes with empty bodies - they can
    745       // implicitly define registers, which is ok for JIT.
    746       if (MI.getOperand(0).getSymbolName()[0])
    747         report_fatal_error("JIT does not support inline asm!");
    748       break;
    749     case TargetOpcode::PROLOG_LABEL:
    750     case TargetOpcode::GC_LABEL:
    751     case TargetOpcode::EH_LABEL:
    752       MCE.emitLabel(MI.getOperand(0).getMCSymbol());
    753       break;
    754 
    755     case TargetOpcode::IMPLICIT_DEF:
    756     case TargetOpcode::KILL:
    757       break;
    758     case X86::MOVPC32r: {
    759       // This emits the "call" portion of this pseudo instruction.
    760       MCE.emitByte(BaseOpcode);
    761       emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags));
    762       // Remember PIC base.
    763       PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
    764       X86JITInfo *JTI = TM.getJITInfo();
    765       JTI->setPICBase(MCE.getCurrentPCValue());
    766       break;
    767     }
    768     }
    769     CurOp = NumOps;
    770     break;
    771   case X86II::RawFrm: {
    772     MCE.emitByte(BaseOpcode);
    773 
    774     if (CurOp == NumOps)
    775       break;
    776 
    777     const MachineOperand &MO = MI.getOperand(CurOp++);
    778 
    779     DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
    780     DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
    781     DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
    782     DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
    783     DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
    784 
    785     if (MO.isMBB()) {
    786       emitPCRelativeBlockAddress(MO.getMBB());
    787       break;
    788     }
    789 
    790     if (MO.isGlobal()) {
    791       emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
    792                         MO.getOffset(), 0);
    793       break;
    794     }
    795 
    796     if (MO.isSymbol()) {
    797       emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
    798       break;
    799     }
    800 
    801     // FIXME: Only used by hackish MCCodeEmitter, remove when dead.
    802     if (MO.isJTI()) {
    803       emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word);
    804       break;
    805     }
    806 
    807     assert(MO.isImm() && "Unknown RawFrm operand!");
    808     if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32 ||
    809         Opcode == X86::WINCALL64pcrel32) {
    810       // Fix up immediate operand for pc relative calls.
    811       intptr_t Imm = (intptr_t)MO.getImm();
    812       Imm = Imm - MCE.getCurrentPCValue() - 4;
    813       emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags));
    814     } else
    815       emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags));
    816     break;
    817   }
    818 
    819   case X86II::AddRegFrm: {
    820     MCE.emitByte(BaseOpcode +
    821                  X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg()));
    822 
    823     if (CurOp == NumOps)
    824       break;
    825 
    826     const MachineOperand &MO1 = MI.getOperand(CurOp++);
    827     unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
    828     if (MO1.isImm()) {
    829       emitConstant(MO1.getImm(), Size);
    830       break;
    831     }
    832 
    833     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
    834       : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
    835     if (Opcode == X86::MOV64ri64i32)
    836       rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
    837     // This should not occur on Darwin for relocatable objects.
    838     if (Opcode == X86::MOV64ri)
    839       rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
    840     if (MO1.isGlobal()) {
    841       bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
    842       emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
    843                         Indirect);
    844     } else if (MO1.isSymbol())
    845       emitExternalSymbolAddress(MO1.getSymbolName(), rt);
    846     else if (MO1.isCPI())
    847       emitConstPoolAddress(MO1.getIndex(), rt);
    848     else if (MO1.isJTI())
    849       emitJumpTableAddress(MO1.getIndex(), rt);
    850     break;
    851   }
    852 
    853   case X86II::MRMDestReg: {
    854     MCE.emitByte(BaseOpcode);
    855     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
    856                      X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg()));
    857     CurOp += 2;
    858     if (CurOp != NumOps)
    859       emitConstant(MI.getOperand(CurOp++).getImm(),
    860                    X86II::getSizeOfImm(Desc->TSFlags));
    861     break;
    862   }
    863   case X86II::MRMDestMem: {
    864     MCE.emitByte(BaseOpcode);
    865     emitMemModRMByte(MI, CurOp,
    866                 X86_MC::getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)
    867                                   .getReg()));
    868     CurOp +=  X86::AddrNumOperands + 1;
    869     if (CurOp != NumOps)
    870       emitConstant(MI.getOperand(CurOp++).getImm(),
    871                    X86II::getSizeOfImm(Desc->TSFlags));
    872     break;
    873   }
    874 
    875   case X86II::MRMSrcReg:
    876     MCE.emitByte(BaseOpcode);
    877     emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
    878                      X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
    879     CurOp += 2;
    880     if (CurOp != NumOps)
    881       emitConstant(MI.getOperand(CurOp++).getImm(),
    882                    X86II::getSizeOfImm(Desc->TSFlags));
    883     break;
    884 
    885   case X86II::MRMSrcMem: {
    886     int AddrOperands = X86::AddrNumOperands;
    887 
    888     intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
    889       X86II::getSizeOfImm(Desc->TSFlags) : 0;
    890 
    891     MCE.emitByte(BaseOpcode);
    892     emitMemModRMByte(MI, CurOp+1,
    893                      X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
    894     CurOp += AddrOperands + 1;
    895     if (CurOp != NumOps)
    896       emitConstant(MI.getOperand(CurOp++).getImm(),
    897                    X86II::getSizeOfImm(Desc->TSFlags));
    898     break;
    899   }
    900 
    901   case X86II::MRM0r: case X86II::MRM1r:
    902   case X86II::MRM2r: case X86II::MRM3r:
    903   case X86II::MRM4r: case X86II::MRM5r:
    904   case X86II::MRM6r: case X86II::MRM7r: {
    905     MCE.emitByte(BaseOpcode);
    906     emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
    907                      (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
    908 
    909     if (CurOp == NumOps)
    910       break;
    911 
    912     const MachineOperand &MO1 = MI.getOperand(CurOp++);
    913     unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
    914     if (MO1.isImm()) {
    915       emitConstant(MO1.getImm(), Size);
    916       break;
    917     }
    918 
    919     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
    920       : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
    921     if (Opcode == X86::MOV64ri32)
    922       rt = X86::reloc_absolute_word_sext;  // FIXME: add X86II flag?
    923     if (MO1.isGlobal()) {
    924       bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
    925       emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
    926                         Indirect);
    927     } else if (MO1.isSymbol())
    928       emitExternalSymbolAddress(MO1.getSymbolName(), rt);
    929     else if (MO1.isCPI())
    930       emitConstPoolAddress(MO1.getIndex(), rt);
    931     else if (MO1.isJTI())
    932       emitJumpTableAddress(MO1.getIndex(), rt);
    933     break;
    934   }
    935 
    936   case X86II::MRM0m: case X86II::MRM1m:
    937   case X86II::MRM2m: case X86II::MRM3m:
    938   case X86II::MRM4m: case X86II::MRM5m:
    939   case X86II::MRM6m: case X86II::MRM7m: {
    940     intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ?
    941       (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ?
    942           X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
    943 
    944     MCE.emitByte(BaseOpcode);
    945     emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
    946                      PCAdj);
    947     CurOp += X86::AddrNumOperands;
    948 
    949     if (CurOp == NumOps)
    950       break;
    951 
    952     const MachineOperand &MO = MI.getOperand(CurOp++);
    953     unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
    954     if (MO.isImm()) {
    955       emitConstant(MO.getImm(), Size);
    956       break;
    957     }
    958 
    959     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
    960       : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
    961     if (Opcode == X86::MOV64mi32)
    962       rt = X86::reloc_absolute_word_sext;  // FIXME: add X86II flag?
    963     if (MO.isGlobal()) {
    964       bool Indirect = gvNeedsNonLazyPtr(MO, TM);
    965       emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
    966                         Indirect);
    967     } else if (MO.isSymbol())
    968       emitExternalSymbolAddress(MO.getSymbolName(), rt);
    969     else if (MO.isCPI())
    970       emitConstPoolAddress(MO.getIndex(), rt);
    971     else if (MO.isJTI())
    972       emitJumpTableAddress(MO.getIndex(), rt);
    973     break;
    974   }
    975 
    976   case X86II::MRMInitReg:
    977     MCE.emitByte(BaseOpcode);
    978     // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
    979     emitRegModRMByte(MI.getOperand(CurOp).getReg(),
    980                      X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
    981     ++CurOp;
    982     break;
    983 
    984   case X86II::MRM_C1:
    985     MCE.emitByte(BaseOpcode);
    986     MCE.emitByte(0xC1);
    987     break;
    988   case X86II::MRM_C8:
    989     MCE.emitByte(BaseOpcode);
    990     MCE.emitByte(0xC8);
    991     break;
    992   case X86II::MRM_C9:
    993     MCE.emitByte(BaseOpcode);
    994     MCE.emitByte(0xC9);
    995     break;
    996   case X86II::MRM_E8:
    997     MCE.emitByte(BaseOpcode);
    998     MCE.emitByte(0xE8);
    999     break;
   1000   case X86II::MRM_F0:
   1001     MCE.emitByte(BaseOpcode);
   1002     MCE.emitByte(0xF0);
   1003     break;
   1004   }
   1005 
   1006   if (!Desc->isVariadic() && CurOp != NumOps) {
   1007 #ifndef NDEBUG
   1008     dbgs() << "Cannot encode all operands of: " << MI << "\n";
   1009 #endif
   1010     llvm_unreachable(0);
   1011   }
   1012 
   1013   MCE.processDebugLoc(MI.getDebugLoc(), false);
   1014 }
   1015