/art/compiler/utils/arm/ |
assembler_arm_vixl.h | 105 WITH_FLAGS_DONT_CARE_RD_OP(Mvn);
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assembler_arm_vixl.cc | 88 ___ Mvn(rd, ~value); 112 case MVN:
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/external/vixl/test/aarch32/ |
test-disasm-a32.cc | 413 COMPARE_BOTH(Orn(r0, r1, 0), "mvn r0, #0\n"); 421 "mvn r0, #1\n" 425 "mvn ip, #1\n" 436 "mvn r0, ip\n" 448 "mvn r0, r2\n" 452 "mvn ip, r1\n" 456 "mvn r0, r0\n" 460 "mvn ip, r0\n" 468 "mvn r0, r2, lsl #1\n" 472 "mvn ip, r2, lsr #2\n [all...] |
test-simulator-cond-rd-operand-const-a32.cc | 122 M(Mvn) \ 470 #include "aarch32/traces/simulator-cond-rd-operand-const-a32-mvn.h"
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test-simulator-cond-rd-operand-const-t32.cc | 122 M(Mvn) \ 585 #include "aarch32/traces/simulator-cond-rd-operand-const-t32-mvn.h" [all...] |
test-simulator-cond-rd-operand-rn-a32.cc | 122 M(Mvn) \ 594 #include "aarch32/traces/simulator-cond-rd-operand-rn-a32-mvn.h" [all...] |
test-simulator-cond-rd-operand-rn-t32.cc | 122 M(Mvn) \ 594 #include "aarch32/traces/simulator-cond-rd-operand-rn-t32-mvn.h" [all...] |
test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 122 M(Mvn) \ [all...] |
test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 122 M(Mvn) \ [all...] |
test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 122 M(Mvn) \ [all...] |
test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 122 M(Mvn) \ [all...] |
test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 122 M(Mvn) \ [all...] |
/external/vixl/src/aarch64/ |
macro-assembler-aarch64.cc | 819 Mvn(rd, rn); 884 // could also be achieved using an orr instruction (like orn used by Mvn), 1077 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) { 1079 // The worst case for size is mvn immediate with up to 4 instructions. 1084 Mvn(rd, operand.GetImmediate()); [all...] |
macro-assembler-aarch64.h | 668 void Mvn(const Register& rd, uint64_t imm) { 671 void Mvn(const Register& rd, const Operand& operand); [all...] |
/external/swiftshader/third_party/subzero/src/ |
IceInstARM32.h | 407 Mvn, [all...] |
IceInstARM32.cpp | [all...] |
/external/v8/src/arm64/ |
macro-assembler-arm64.h | 258 inline void Mvn(const Register& rd, uint64_t imm); 259 void Mvn(const Register& rd, const Operand& operand); [all...] |
macro-assembler-arm64.cc | 112 Mvn(rd, rn); 260 // could also be achieved using an orr instruction (like orn used by Mvn), 296 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) { 301 mvn(rd, rd); 312 mvn(rd, rd); 315 mvn(rd, operand); [all...] |
macro-assembler-arm64-inl.h | 287 void MacroAssembler::Mvn(const Register& rd, uint64_t imm) { [all...] |
/external/v8/src/compiler/arm64/ |
code-generator-arm64.cc | [all...] |
/external/vixl/test/aarch64/ |
test-assembler-aarch64.cc | 311 TEST(mvn) { 315 __ Mvn(w0, 0xfff); 316 __ Mvn(x1, 0xfff); 317 __ Mvn(w2, Operand(w0, LSL, 1)); 318 __ Mvn(x3, Operand(x1, LSL, 2)); 319 __ Mvn(w4, Operand(w0, LSR, 3)); 320 __ Mvn(x5, Operand(x1, LSR, 4)); 321 __ Mvn(w6, Operand(w0, ASR, 11)); 322 __ Mvn(x7, Operand(x1, ASR, 12)); 323 __ Mvn(w8, Operand(w0, ROR, 13)) [all...] |
test-disasm-aarch64.cc | 196 COMPARE_MACRO(Mvn(w0, Operand(0x101)), "mov w0, #0xfffffefe"); 197 COMPARE_MACRO(Mvn(x1, Operand(0xfff1)), "mov x1, #0xffffffffffff000e"); 198 COMPARE_MACRO(Mvn(w2, Operand(w3)), "mvn w2, w3"); 199 COMPARE_MACRO(Mvn(x4, Operand(x5)), "mvn x4, x5"); 200 COMPARE_MACRO(Mvn(w6, Operand(w7, LSL, 12)), "mvn w6, w7, lsl #12"); 201 COMPARE_MACRO(Mvn(x8, Operand(x9, ASR, 63)), "mvn x8, x9, asr #63") [all...] |
/external/vixl/src/aarch32/ |
macro-assembler-aarch32.h | [all...] |
/art/compiler/optimizing/ |
code_generator_arm_vixl.cc | [all...] |
code_generator_arm64.cc | [all...] |