| /external/pcre/dist2/src/sljit/ |
| sljitNativeMIPS_64.c | 38 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
45 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
81 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 32), dst_ar));
89 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
114 FAIL_IF(push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(uimm >> 48), dst_ar));
118 return !(imm & 0xffff) ? SLJIT_SUCCESS : push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar);
234 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM((op & SLJIT_I32_OP) ? 32 : 64), UNMOVABLE_INS));
257 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
293 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
415 EMIT_LOGICAL(ORI, OR)
[all...] |
| sljitNativePPC_64.c | 55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
77 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp >> 32)));
89 return push_inst(compiler, ORI | S(reg) | A(reg) | tmp2);
96 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(tmp2)) : SLJIT_SUCCESS;
107 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | (tmp2 >> 48)));
113 FAIL_IF(push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm >> 32)));
116 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm));
312 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
320 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm)))
[all...] |
| sljitNativePPC_32.c | 35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm));
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS;
185 return push_inst(compiler, ORI | S(src1) | A(dst) | compiler->imm);
193 FAIL_IF(push_inst(compiler, ORI | S(src1) | A(dst) | IMM(compiler->imm)));
250 return push_inst(compiler, ORI | S(reg) | A(reg) | IMM(init_value));
|
| sljitNativeMIPS_32.c | 32 return push_inst(compiler, ORI | SA(0) | TA(dst_ar) | IMM(imm), dst_ar);
38 return (imm & 0xffff) ? push_inst(compiler, ORI | SA(dst_ar) | TA(dst_ar) | IMM(imm), dst_ar) : SLJIT_SUCCESS;
142 FAIL_IF(push_inst(compiler, ORI | SA(0) | T(dst) | IMM(32), UNMOVABLE_INS));
165 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(ULESS_FLAG) | IMM(src2), ULESS_FLAG));
201 FAIL_IF(push_inst(compiler, ORI | S(src1) | TA(OVERFLOW_FLAG) | IMM(src2), OVERFLOW_FLAG));
320 EMIT_LOGICAL(ORI, OR);
347 return push_inst(compiler, ORI | S(dst) | T(dst) | IMM(init_value), DR(dst));
|
| sljitNativeTILEGX_64.c | 424 #define ORI(dst, srca, imm) \
[all...] |
| /external/valgrind/none/tests/mips64/ |
| logical_instructions.c | 7 OR, ORI, XOR, XORI
68 case ORI:
70 TEST2("ori $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
71 TEST2("ori $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
72 TEST2("ori $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
73 TEST2("ori $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
74 TEST2("ori $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
75 TEST2("ori $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
76 TEST2("ori $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
77 TEST2("ori $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeAsmBackend.cpp | 74 case MBlaze::ORI: return MBlaze::ORI32;
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPS64Assembler.cpp | 369 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
465 mMips->ORI(Rd, Rn, src);
472 mMips->ORI(R_at, 0, src);
482 mMips->ORI(R_at, 0, src);
495 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
498 mMips->ORI(Rd, 0, amode.value);
522 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
525 mMips->ORI(Rd, 0, amode.value);
563 mMips->ORI(R_cmp2, R_zero, src);
[all...] |
| MIPSAssembler.cpp | 382 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
466 mMips->ORI(Rd, Rn, src);
473 mMips->ORI(R_at, 0, src);
483 mMips->ORI(R_at, 0, src);
496 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
499 mMips->ORI(Rd, 0, amode.value);
528 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
531 mMips->ORI(Rd, 0, amode.value);
574 mMips->ORI(R_cmp2, R_zero, src);
[all...] |
| MIPSAssembler.h | 308 void ORI(int Rt, int Rs, uint16_t imm);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| ulw-reloc.d | 61 [0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffc
65 # This one must use LUI/ORI
67 [0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffd
71 # This one must use LUI/ORI
73 [0-9a-f]+ <[^>]*> ori \$1,\$1,0x7fff
79 [0-9a-f]+ <[^>]*> ori \$1,\$1,0x8000
|
| ulh-reloc.d | 49 [0-9a-f]+ <[^>]*> ori \$1,\$1,0x7ffe
55 # This one must use LUI/ORI
57 [0-9a-f]+ <[^>]*> ori \$1,\$1,0x7fff
65 [0-9a-f]+ <[^>]*> ori \$1,\$1,0x8000
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 97 // transform this into the appropriate ORI instruction.
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
590 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
668 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
[all...] |
| PPCRegisterInfo.cpp | 293 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
605 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| nios2r1.h | 395 #define MATCH_R1_MOVUI MATCH_R1_OP (ORI) | SET_IW_I_A (0)
417 #define MATCH_R1_ORI MATCH_R1_OP (ORI)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 301 // transform this into the appropriate ORI instruction.
351 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
355 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
377 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
765 : PPC::ORI );
[all...] |
| PPCFastISel.cpp | [all...] |
| PPCRegisterInfo.cpp | [all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 357 ORI = ((1U << 3) + 5) << kOpcodeShift,
909 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) |
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.cc | 160 // specially coded on MIPS means that it is a lui/ori instruction, and that is
593 return opcode == ORI;
1774 void Assembler::ori(Register rt, Register rs, int32_t j) { function in class:v8::internal::Assembler
[all...] |
| constants-mips64.h | 328 ORI = ((1U << 3) + 5) << kOpcodeShift,
942 OpcodeToBitNumber(ORI) | OpcodeToBitNumber(XORI) |
[all...] |
| /external/v8/src/ppc/ |
| assembler-ppc.cc | 149 // coded. Being specially coded on PPC means that it is a lis/ori
311 bool Assembler::IsOri(Instr instr) { return (instr & kOpcodeMask) == ORI; }
332 // This code assumes a FIXED_SEQUENCE for 64bit loads (lis/ori)
337 // 618c0000 ori r12, r12, 0
340 // 618ccd40 ori r12, r12, 52544
346 // This code assumes a FIXED_SEQUENCE for 32bit loads (lis/ori)
350 // 618c5000 ori r12, r12, 20480
470 instr = ORI; // nop: ori, 0,0,0
483 instr = ORI; // nop: ori, 0,0,
1002 void Assembler::ori(Register ra, Register rs, const Operand& imm) { function in class:v8::internal::Assembler
[all...] |
| /external/icu/icu4c/source/common/ |
| ucnvisci.c | 94 ORI = 0x47,
147 { ORIYA, ORI_MASK, ORI },
275 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 53 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
|
| /external/icu/icu4j/main/classes/charset/src/com/ibm/icu/charset/ |
| CharsetISCII.java | 86 static final short ORI = 0x47;
165 new LookupDataStruct(UniLang.ORIYA, MaskEnum.ORI_MASK, ISCIILang.ORI),
176 * |DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML |
[all...] |
