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    Searched refs:Orders (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 702 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
719 Orders.push_back(std::make_pair(DVOrder, DbgMI));
733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
739 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
749 Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr));
753 Orders.push_back(std::make_pair(Order, &*std::prev(Emitter.getInsertPos())));
754 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
802 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
842 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
849 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
    [all...]
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 636 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
654 Orders.push_back(std::make_pair(DVOrder, DbgMI));
668 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
674 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
681 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
685 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
686 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
695 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
736 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
743 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
    [all...]
  /external/swiftshader/third_party/LLVM/utils/TableGen/
CodeGenRegisters.h 90 // Allocation orders. Order[0] always contains all registers in Members.
91 std::vector<SmallVector<Record*, 16> > Orders;
176 return Orders[No];
179 // Return the total number of allocation orders available.
180 unsigned getNumOrders() const { return Orders.size(); }
CodeGenRegisters.cpp 279 Orders.resize(1 + AltOrders->size());
283 Orders[0].push_back((*Elements)[i]);
287 // Alternative allocation orders may be subsets.
291 Orders[1 + i].append(Order.begin(), Order.end());
366 // Copy all allocation orders, filter out foreign registers from the larger
368 Orders.resize(Super.Orders.size());
369 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
370 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
371 if (contains(RegBank.getReg(Super.Orders[i][j]))
    [all...]
  /external/llvm/lib/CodeGen/
InlineSpiller.cpp 99 SmallVectorImpl<MachineDomTreeNode *> &Orders,
    [all...]
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 268 // Allocation orders. Order[0] always contains all registers in Members.
269 std::vector<SmallVector<Record*, 16> > Orders;
384 return Orders[No];
387 // Return the total number of allocation orders available.
388 unsigned getNumOrders() const { return Orders.size(); }
CodeGenRegisters.cpp 678 Orders.resize(1 + AltOrders->size());
682 Orders[0].push_back((*Elements)[i]);
689 // Alternative allocation orders may be subsets.
693 Orders[1 + i].append(Order.begin(), Order.end());
755 // Copy all allocation orders, filter out foreign registers from the larger
757 Orders.resize(Super.Orders.size());
758 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
759 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
760 if (contains(RegBank.getReg(Super.Orders[i][j]))
    [all...]
  /external/clang/lib/CodeGen/
CGBuiltin.cpp     [all...]

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